From b7b6160d0eb922c44d174f7e1199713e4285c54e Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Fri, 6 May 2022 19:29:41 +0300 Subject: fs/ntfs3: Refactoring of indx_find function This commit makes function a bit more readable Cc: Joe Perches Signed-off-by: Konstantin Komarov --- fs/ntfs3/index.c | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) diff --git a/fs/ntfs3/index.c b/fs/ntfs3/index.c index 6f81e3a49abf..8468cca5d54d 100644 --- a/fs/ntfs3/index.c +++ b/fs/ntfs3/index.c @@ -1042,19 +1042,16 @@ int indx_find(struct ntfs_index *indx, struct ntfs_inode *ni, { int err; struct NTFS_DE *e; - const struct INDEX_HDR *hdr; struct indx_node *node; if (!root) root = indx_get_root(&ni->dir, ni, NULL, NULL); if (!root) { - err = -EINVAL; - goto out; + /* Should not happen. */ + return -EINVAL; } - hdr = &root->ihdr; - /* Check cache. */ e = fnd->level ? fnd->de[fnd->level - 1] : fnd->root_de; if (e && !de_is_last(e) && @@ -1068,39 +1065,35 @@ int indx_find(struct ntfs_index *indx, struct ntfs_inode *ni, fnd_clear(fnd); /* Lookup entry that is <= to the search value. */ - e = hdr_find_e(indx, hdr, key, key_len, ctx, diff); + e = hdr_find_e(indx, &root->ihdr, key, key_len, ctx, diff); if (!e) return -EINVAL; fnd->root_de = e; - err = 0; for (;;) { node = NULL; - if (*diff >= 0 || !de_has_vcn_ex(e)) { - *entry = e; - goto out; - } + if (*diff >= 0 || !de_has_vcn_ex(e)) + break; /* Read next level. */ err = indx_read(indx, ni, de_get_vbn(e), &node); if (err) - goto out; + return err; /* Lookup entry that is <= to the search value. */ e = hdr_find_e(indx, &node->index->ihdr, key, key_len, ctx, diff); if (!e) { - err = -EINVAL; put_indx_node(node); - goto out; + return -EINVAL; } fnd_push(fnd, node, e); } -out: - return err; + *entry = e; + return 0; } int indx_find_sort(struct ntfs_index *indx, struct ntfs_inode *ni, -- cgit v1.2.3 From cd39981fb92adf0cc736112f87e3e61602baa415 Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Wed, 11 May 2022 19:58:36 +0300 Subject: fs/ntfs3: Fix double free on remount Pointer to options was freed twice on remount Fixes xfstest generic/361 Fixes: 82cae269cfa9 ("fs/ntfs3: Add initialization of super block") Signed-off-by: Konstantin Komarov --- fs/ntfs3/super.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/fs/ntfs3/super.c b/fs/ntfs3/super.c index 278dcf502410..4b0dad2ac598 100644 --- a/fs/ntfs3/super.c +++ b/fs/ntfs3/super.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -390,7 +391,7 @@ static int ntfs_fs_reconfigure(struct fs_context *fc) return -EINVAL; } - memcpy(sbi->options, new_opts, sizeof(*new_opts)); + swap(sbi->options, fc->fs_private); return 0; } @@ -897,6 +898,8 @@ static int ntfs_fill_super(struct super_block *sb, struct fs_context *fc) ref.high = 0; sbi->sb = sb; + sbi->options = fc->fs_private; + fc->fs_private = NULL; sb->s_flags |= SB_NODIRATIME; sb->s_magic = 0x7366746e; // "ntfs" sb->s_op = &ntfs_sops; @@ -1260,8 +1263,6 @@ load_root: goto put_inode_out; } - fc->fs_private = NULL; - return 0; put_inode_out: @@ -1414,7 +1415,6 @@ static int ntfs_init_fs_context(struct fs_context *fc) mutex_init(&sbi->compress.mtx_lzx); #endif - sbi->options = opts; fc->s_fs_info = sbi; ok: fc->fs_private = opts; -- cgit v1.2.3 From 19d1b7872d1ebf0658b5032b79f536a715303ee4 Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Thu, 12 May 2022 12:25:48 +0300 Subject: fs/ntfs3: Refactor ni_try_remove_attr_list function Now we save a copy of primary record for restoration. Also now we remove all attributes from subrecords. Signed-off-by: Konstantin Komarov --- fs/ntfs3/frecord.c | 49 +++++++++++++++++++++++++++++++++++++------------ fs/ntfs3/record.c | 5 ++--- 2 files changed, 39 insertions(+), 15 deletions(-) diff --git a/fs/ntfs3/frecord.c b/fs/ntfs3/frecord.c index 18842998c8fa..3576268ee0a1 100644 --- a/fs/ntfs3/frecord.c +++ b/fs/ntfs3/frecord.c @@ -7,6 +7,7 @@ #include #include +#include #include #include "debug.h" @@ -649,6 +650,7 @@ static int ni_try_remove_attr_list(struct ntfs_inode *ni) struct mft_inode *mi; u32 asize, free; struct MFT_REF ref; + struct MFT_REC *mrec; __le16 id; if (!ni->attr_list.dirty) @@ -692,11 +694,17 @@ static int ni_try_remove_attr_list(struct ntfs_inode *ni) free -= asize; } + /* Make a copy of primary record to restore if error. */ + mrec = kmemdup(ni->mi.mrec, sbi->record_size, GFP_NOFS); + if (!mrec) + return 0; /* Not critical. */ + /* It seems that attribute list can be removed from primary record. */ mi_remove_attr(NULL, &ni->mi, attr_list); /* - * Repeat the cycle above and move all attributes to primary record. + * Repeat the cycle above and copy all attributes to primary record. + * Do not remove original attributes from subrecords! * It should be success! */ le = NULL; @@ -707,14 +715,14 @@ static int ni_try_remove_attr_list(struct ntfs_inode *ni) mi = ni_find_mi(ni, ino_get(&le->ref)); if (!mi) { /* Should never happened, 'cause already checked. */ - goto bad; + goto out; } attr = mi_find_attr(mi, NULL, le->type, le_name(le), le->name_len, &le->id); if (!attr) { /* Should never happened, 'cause already checked. */ - goto bad; + goto out; } asize = le32_to_cpu(attr->size); @@ -724,18 +732,33 @@ static int ni_try_remove_attr_list(struct ntfs_inode *ni) le16_to_cpu(attr->name_off)); if (!attr_ins) { /* - * Internal error. - * Either no space in primary record (already checked). - * Either tried to insert another - * non indexed attribute (logic error). + * No space in primary record (already checked). */ - goto bad; + goto out; } /* Copy all except id. */ id = attr_ins->id; memcpy(attr_ins, attr, asize); attr_ins->id = id; + } + + /* + * Repeat the cycle above and remove all attributes from subrecords. + */ + le = NULL; + while ((le = al_enumerate(ni, le))) { + if (!memcmp(&le->ref, &ref, sizeof(ref))) + continue; + + mi = ni_find_mi(ni, ino_get(&le->ref)); + if (!mi) + continue; + + attr = mi_find_attr(mi, NULL, le->type, le_name(le), + le->name_len, &le->id); + if (!attr) + continue; /* Remove from original record. */ mi_remove_attr(NULL, mi, attr); @@ -748,11 +771,13 @@ static int ni_try_remove_attr_list(struct ntfs_inode *ni) ni->attr_list.le = NULL; ni->attr_list.dirty = false; + kfree(mrec); + return 0; +out: + /* Restore primary record. */ + swap(mrec, ni->mi.mrec); + kfree(mrec); return 0; -bad: - ntfs_inode_err(&ni->vfs_inode, "Internal error"); - make_bad_inode(&ni->vfs_inode); - return -EINVAL; } /* diff --git a/fs/ntfs3/record.c b/fs/ntfs3/record.c index 861e35791506..8fe0a876400a 100644 --- a/fs/ntfs3/record.c +++ b/fs/ntfs3/record.c @@ -445,12 +445,11 @@ struct ATTRIB *mi_insert_attr(struct mft_inode *mi, enum ATTR_TYPE type, attr = NULL; while ((attr = mi_enum_attr(mi, attr))) { diff = compare_attr(attr, type, name, name_len, upcase); - if (diff > 0) - break; + if (diff < 0) continue; - if (!is_attr_indexed(attr)) + if (!diff && !is_attr_indexed(attr)) return NULL; break; } -- cgit v1.2.3 From 37a530bfe56ca9a0d3129598803f2794c7428aae Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Thu, 26 May 2022 12:51:03 +0300 Subject: fs/ntfs3: Fix missing i_op in ntfs_read_mft There is null pointer dereference because i_op == NULL. The bug happens because we don't initialize i_op for records in $Extend. Fixes: 82cae269cfa9 ("fs/ntfs3: Add initialization of super block") Reported-by: Liangbin Lian Signed-off-by: Konstantin Komarov --- fs/ntfs3/inode.c | 1 + 1 file changed, 1 insertion(+) diff --git a/fs/ntfs3/inode.c b/fs/ntfs3/inode.c index 38045264a61b..6c78930be035 100644 --- a/fs/ntfs3/inode.c +++ b/fs/ntfs3/inode.c @@ -430,6 +430,7 @@ end_enum: } else if (fname && fname->home.low == cpu_to_le32(MFT_REC_EXTEND) && fname->home.seq == cpu_to_le16(MFT_REC_EXTEND)) { /* Records in $Extend are not a files or general directories. */ + inode->i_op = &ntfs_file_inode_operations; } else { err = -EINVAL; goto out; -- cgit v1.2.3 From 548744f84456946181ed6dc0ac6be8267f167d28 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Thu, 23 Dec 2021 15:20:00 +0300 Subject: fs/ntfs3: Remove a useless test 'new_free' has just been allocated by kmalloc() and is known to be not NULL. So this pointer can't be equal to a previous memory allocation. Signed-off-by: Christophe JAILLET Signed-off-by: Konstantin Komarov --- fs/ntfs3/bitmap.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/fs/ntfs3/bitmap.c b/fs/ntfs3/bitmap.c index aa184407520f..e3b5680fd516 100644 --- a/fs/ntfs3/bitmap.c +++ b/fs/ntfs3/bitmap.c @@ -1333,9 +1333,7 @@ int wnd_extend(struct wnd_bitmap *wnd, size_t new_bits) if (!new_free) return -ENOMEM; - if (new_free != wnd->free_bits) - memcpy(new_free, wnd->free_bits, - wnd->nwnd * sizeof(short)); + memcpy(new_free, wnd->free_bits, wnd->nwnd * sizeof(short)); memset(new_free + wnd->nwnd, 0, (new_wnd - wnd->nwnd) * sizeof(short)); kfree(wnd->free_bits); -- cgit v1.2.3 From 560e613352b4a65c5c397e689a997fb04bd5f928 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Thu, 30 Dec 2021 18:59:00 +0300 Subject: fs/ntfs3: Remove redundant assignment to variable frame Variable frame is assigned a value that is never read. The assignment is redundant and can be removed. Cleans up the clang-scan build warning: fs/ntfs3/file.c:995:3: warning: Value stored to 'frame' is never read [deadcode.DeadStores] frame = pos >> frame_bits; Signed-off-by: Colin Ian King Signed-off-by: Konstantin Komarov --- fs/ntfs3/file.c | 1 - 1 file changed, 1 deletion(-) diff --git a/fs/ntfs3/file.c b/fs/ntfs3/file.c index 3bae76930e68..27c32692513c 100644 --- a/fs/ntfs3/file.c +++ b/fs/ntfs3/file.c @@ -992,7 +992,6 @@ static ssize_t ntfs_compress_write(struct kiocb *iocb, struct iov_iter *from) if (bytes > count) bytes = count; - frame = pos >> frame_bits; frame_vbo = pos & ~(frame_size - 1); index = frame_vbo >> PAGE_SHIFT; -- cgit v1.2.3 From dc8965ab5e338abfd8dfd65d12a62ad5be65a776 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Mon, 18 Apr 2022 17:00:00 +0300 Subject: fs/ntfs3: Remove redundant assignment to variable vcn Variable vcn is being assigned a value that is never read, it is being re-assigned again in the initialization of a for-loop. The assignment is redundant and can be removed. Cleans up clang scan build warning: fs/ntfs3/attrib.c:1176:7: warning: Value stored to 'vcn' during its initialization is never read [deadcode.DeadStores] Signed-off-by: Colin Ian King Reviewed-by: Kari Argillander Signed-off-by: Konstantin Komarov --- fs/ntfs3/attrib.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/ntfs3/attrib.c b/fs/ntfs3/attrib.c index e8c00dda42ad..fc0623b029e6 100644 --- a/fs/ntfs3/attrib.c +++ b/fs/ntfs3/attrib.c @@ -1173,7 +1173,7 @@ int attr_load_runs_range(struct ntfs_inode *ni, enum ATTR_TYPE type, { struct ntfs_sb_info *sbi = ni->mi.sbi; u8 cluster_bits = sbi->cluster_bits; - CLST vcn = from >> cluster_bits; + CLST vcn; CLST vcn_last = (to - 1) >> cluster_bits; CLST lcn, clen; int err; -- cgit v1.2.3 From ae5a4e46916fc307288227b64c1d062352eb93b7 Mon Sep 17 00:00:00 2001 From: Yan Lei Date: Sun, 10 Apr 2022 09:09:00 +0300 Subject: fs/ntfs3: Fix using uninitialized value n when calling indx_read This value is checked in indx_read, so it must be initialized Fixes: 82cae269cfa9 ("fs/ntfs3: Add initialization of super block") Signed-off-by: Yan Lei Signed-off-by: Konstantin Komarov --- fs/ntfs3/index.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/ntfs3/index.c b/fs/ntfs3/index.c index 8468cca5d54d..84ccc1409874 100644 --- a/fs/ntfs3/index.c +++ b/fs/ntfs3/index.c @@ -1987,7 +1987,7 @@ static int indx_free_children(struct ntfs_index *indx, struct ntfs_inode *ni, const struct NTFS_DE *e, bool trim) { int err; - struct indx_node *n; + struct indx_node *n = NULL; struct INDEX_HDR *hdr; CLST vbn = de_get_vbn(e); size_t i; -- cgit v1.2.3 From 19e890ff3bedc36fe3cd1cb7d03bfb66c5fdf1db Mon Sep 17 00:00:00 2001 From: Yang Xu Date: Wed, 20 Apr 2022 11:48:00 +0300 Subject: fs/ntfs3: Use the same order for acl pointer check in ntfs_init_acl For the readability and unity of the code, adjust the order Signed-off-by: Yang Xu Reviewed-by: Kari Argillander Signed-off-by: Konstantin Komarov --- fs/ntfs3/xattr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/fs/ntfs3/xattr.c b/fs/ntfs3/xattr.c index 5e0e0280e70d..2d29afe4b40b 100644 --- a/fs/ntfs3/xattr.c +++ b/fs/ntfs3/xattr.c @@ -706,13 +706,13 @@ int ntfs_init_acl(struct user_namespace *mnt_userns, struct inode *inode, inode->i_default_acl = NULL; } - if (!acl) - inode->i_acl = NULL; - else { + if (acl) { if (!err) err = ntfs_set_acl_ex(mnt_userns, inode, acl, ACL_TYPE_ACCESS, true); posix_acl_release(acl); + } else { + inode->i_acl = NULL; } return err; -- cgit v1.2.3 From a6c487cd7e4aa1af83423003f05c87302325b87c Mon Sep 17 00:00:00 2001 From: Luca Ceresoli Date: Fri, 3 Jun 2022 17:57:26 +0200 Subject: power: supply: max77976: update Luca Ceresoli's e-mail address My Bootlin address is preferred from now on. Signed-off-by: Luca Ceresoli Signed-off-by: Luca Ceresoli Signed-off-by: Sebastian Reichel --- drivers/power/supply/max77976_charger.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/power/supply/max77976_charger.c b/drivers/power/supply/max77976_charger.c index 8b6c8cfa7503..4fed74511931 100644 --- a/drivers/power/supply/max77976_charger.c +++ b/drivers/power/supply/max77976_charger.c @@ -3,7 +3,7 @@ * max77976_charger.c - Driver for the Maxim MAX77976 battery charger * * Copyright (C) 2021 Luca Ceresoli - * Author: Luca Ceresoli + * Author: Luca Ceresoli */ #include @@ -504,6 +504,6 @@ static struct i2c_driver max77976_driver = { }; module_i2c_driver(max77976_driver); -MODULE_AUTHOR("Luca Ceresoli "); +MODULE_AUTHOR("Luca Ceresoli "); MODULE_DESCRIPTION("Maxim MAX77976 charger driver"); MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 576fc9e6f7663f140ebf5002e6568d9dc273bb7d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 1 Jun 2022 09:19:08 +0200 Subject: dt-bindings: power: supply: bq24190: use regulator schema for child node The 'usb-otg-vbus' child node is a regulator so reference the regulator schema for proper evaluation. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Sebastian Reichel --- Documentation/devicetree/bindings/power/supply/bq24190.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/power/supply/bq24190.yaml b/Documentation/devicetree/bindings/power/supply/bq24190.yaml index 0d7cbbdf808b..402d9d2ed2b9 100644 --- a/Documentation/devicetree/bindings/power/supply/bq24190.yaml +++ b/Documentation/devicetree/bindings/power/supply/bq24190.yaml @@ -28,7 +28,7 @@ properties: maxItems: 1 usb-otg-vbus: - type: object + $ref: /schemas/regulator/regulator.yaml# description: | Regulator that is used to control the VBUS voltage direction for either USB host mode or for charging on the OTG port -- cgit v1.2.3 From 2441ca62b78bd675afdc63872f1f663dcd116dd3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 1 Jun 2022 09:19:09 +0200 Subject: dt-bindings: power: supply: qcom,pm8941: use regulator schema for child node The 'usb-otg-vbus' child node is a regulator so reference the regulator schema for proper evaluation. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Sebastian Reichel --- Documentation/devicetree/bindings/power/supply/qcom,pm8941-charger.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/power/supply/qcom,pm8941-charger.yaml b/Documentation/devicetree/bindings/power/supply/qcom,pm8941-charger.yaml index caeff68c66d5..cd6364d65751 100644 --- a/Documentation/devicetree/bindings/power/supply/qcom,pm8941-charger.yaml +++ b/Documentation/devicetree/bindings/power/supply/qcom,pm8941-charger.yaml @@ -121,7 +121,7 @@ properties: description: Reference to the regulator supplying power to the USB_OTG_IN pin. otg-vbus: - type: object + $ref: /schemas/regulator/regulator.yaml# description: | This node defines a regulator used to control the direction of VBUS voltage. Specifically whether to supply voltage to VBUS for host mode operation of the OTG port, -- cgit v1.2.3 From 096a6223424e8f5f9d9dbc70c66cdfd63b34fc58 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 1 Jun 2022 09:19:10 +0200 Subject: dt-bindings: power: supply: qcom,pm8941: document usb-charge-current-limit Document already used (in DTS and by driver) 'usb-charge-current-limit' property: arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dtb: charger@1000: 'usb-charge-current-limit' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Sebastian Reichel --- .../devicetree/bindings/power/supply/qcom,pm8941-charger.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/power/supply/qcom,pm8941-charger.yaml b/Documentation/devicetree/bindings/power/supply/qcom,pm8941-charger.yaml index cd6364d65751..cbac55d3cb92 100644 --- a/Documentation/devicetree/bindings/power/supply/qcom,pm8941-charger.yaml +++ b/Documentation/devicetree/bindings/power/supply/qcom,pm8941-charger.yaml @@ -117,6 +117,13 @@ properties: be done externally to fully comply with the JEITA safety guidelines if this flag is set. + usb-charge-current-limit: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 100000 + maximum: 2500000 + description: | + Default USB charge current limit in uA. + usb-otg-in-supply: description: Reference to the regulator supplying power to the USB_OTG_IN pin. -- cgit v1.2.3 From 2a21fe017ce564d773a6a524ce3dcaa8cb850917 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 1 Jun 2022 09:19:11 +0200 Subject: dt-bindings: power: supply: summit,smb347: use absolute path to schema Reference regulator schema by absolute path, as expected by DT schema coding style. Signed-off-by: Krzysztof Kozlowski Reviewed-by: David Heidelberg Acked-by: Rob Herring Signed-off-by: Sebastian Reichel --- .../devicetree/bindings/power/supply/summit,smb347-charger.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml b/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml index 20862cdfc116..ce0bca4689f6 100644 --- a/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml +++ b/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml @@ -82,7 +82,7 @@ properties: - 1 # SMB3XX_SYSOK_INOK_ACTIVE_HIGH usb-vbus: - $ref: "../../regulator/regulator.yaml#" + $ref: /schemas/regulator/regulator.yaml# type: object properties: -- cgit v1.2.3 From d54087651efd06e804b92c485b7612307e3839d1 Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Sat, 21 May 2022 13:10:35 +0200 Subject: power: supply: lp8788: fix typo in comment Spelling mistake (triple letters) in comment. Detected with the help of Coccinelle. Signed-off-by: Julia Lawall Signed-off-by: Sebastian Reichel --- drivers/power/supply/lp8788-charger.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/supply/lp8788-charger.c b/drivers/power/supply/lp8788-charger.c index 397e5a03b7d9..56c57529c228 100644 --- a/drivers/power/supply/lp8788-charger.c +++ b/drivers/power/supply/lp8788-charger.c @@ -376,7 +376,7 @@ static int lp8788_update_charger_params(struct platform_device *pdev, return 0; } - /* settting charging parameters */ + /* setting charging parameters */ for (i = 0; i < pdata->num_chg_params; i++) { param = pdata->chg_params + i; -- cgit v1.2.3 From b770583ba6028e8cbd2d49dad9eff63cba3d6fef Mon Sep 17 00:00:00 2001 From: Yang Li Date: Wed, 4 May 2022 21:52:14 +0800 Subject: power: supply: Remove unnecessary print function dev_err() The print function dev_err() is redundant because platform_get_irq() already prints an error. Eliminate the follow coccicheck warning: ./drivers/power/supply/goldfish_battery.c:225:2-9: line 225 is redundant because platform_get_irq() already prints an error Reported-by: Abaci Robot Signed-off-by: Yang Li Signed-off-by: Sebastian Reichel --- drivers/power/supply/goldfish_battery.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/power/supply/goldfish_battery.c b/drivers/power/supply/goldfish_battery.c index bf1754355c9f..a58d713d75ce 100644 --- a/drivers/power/supply/goldfish_battery.c +++ b/drivers/power/supply/goldfish_battery.c @@ -221,10 +221,8 @@ static int goldfish_battery_probe(struct platform_device *pdev) } data->irq = platform_get_irq(pdev, 0); - if (data->irq < 0) { - dev_err(&pdev->dev, "platform_get_irq failed\n"); + if (data->irq < 0) return -ENODEV; - } ret = devm_request_irq(&pdev->dev, data->irq, goldfish_battery_interrupt, -- cgit v1.2.3 From f7ca2d8c1b6d280a480baf7289c053754f98b44b Mon Sep 17 00:00:00 2001 From: Xiang wangx Date: Sat, 4 Jun 2022 22:18:11 +0800 Subject: power: supply: bq24257: Fix syntax error in comments Delete the redundant word 'is'. Signed-off-by: Xiang wangx Signed-off-by: Sebastian Reichel --- drivers/power/supply/bq24257_charger.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/supply/bq24257_charger.c b/drivers/power/supply/bq24257_charger.c index 96cb3290bcaa..ecba9ab86faf 100644 --- a/drivers/power/supply/bq24257_charger.c +++ b/drivers/power/supply/bq24257_charger.c @@ -287,7 +287,7 @@ static int bq24257_set_input_current_limit(struct bq24257_device *bq, { /* * Address the case where the user manually sets an input current limit - * while the charger auto-detection mechanism is is active. In this + * while the charger auto-detection mechanism is active. In this * case we want to abort and go straight to the user-specified value. */ if (bq->iilimit_autoset_enable) -- cgit v1.2.3 From 23c46bab922b856b585a5f49413f74a9a7b2400d Mon Sep 17 00:00:00 2001 From: Xiaohui Zhang Date: Tue, 7 Jun 2022 23:03:44 +0800 Subject: power: supply: cros_peripheral: Use struct_size() helper in kzalloc() Similar to the handling of cros_usbpd_charger_ec_command in commit 441d38c60fbe ("power: supply: cros_usbpd: Use struct_size() helper in kzalloc()"), we thought a patch might be needed here as well. Make use of the struct_size() helper instead of an open-coded version, in order to avoid any potential type mistakes or integer overflows that, in the worst scenario, could lead to heap overflows. Signed-off-by: Xiaohui Zhang Signed-off-by: Sebastian Reichel --- drivers/power/supply/cros_peripheral_charger.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/supply/cros_peripheral_charger.c b/drivers/power/supply/cros_peripheral_charger.c index 9fe6d826148d..1379afd9698d 100644 --- a/drivers/power/supply/cros_peripheral_charger.c +++ b/drivers/power/supply/cros_peripheral_charger.c @@ -63,7 +63,7 @@ static int cros_pchg_ec_command(const struct charger_data *charger, struct cros_ec_command *msg; int ret; - msg = kzalloc(sizeof(*msg) + max(outsize, insize), GFP_KERNEL); + msg = kzalloc(struct_size(msg, data, max(outsize, insize)), GFP_KERNEL); if (!msg) return -ENOMEM; -- cgit v1.2.3 From 6aa35ab9db2c9ca141ba9d64a2ad95b73dbf90e3 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 15 Apr 2022 22:36:37 +0200 Subject: power: supply: ab8500: Respect charge_restart_voltage_uv The battery info contains a voltage indicating when the voltage is so low that it is time to restart the CC/CV charging. Make the AB8500 respect and prioritize this setting over the hardcoded 95% threshold. Break out the check into its own function and add some safeguards so we do not run into unpredictable side effects. Signed-off-by: Linus Walleij Reviewed-by: Matti Vaittinen Signed-off-by: Sebastian Reichel --- drivers/power/supply/ab8500_chargalg.c | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/power/supply/ab8500_chargalg.c b/drivers/power/supply/ab8500_chargalg.c index 431bbc352d1b..037ae9b4a7d0 100644 --- a/drivers/power/supply/ab8500_chargalg.c +++ b/drivers/power/supply/ab8500_chargalg.c @@ -1216,6 +1216,34 @@ static void ab8500_chargalg_external_power_changed(struct power_supply *psy) queue_work(di->chargalg_wq, &di->chargalg_work); } +/** + * ab8500_chargalg_time_to_restart() - time to restart CC/CV charging? + * @di: charging algorithm state + * + * This checks if the voltage or capacity of the battery has fallen so + * low that we need to restart the CC/CV charge cycle. + */ +static bool ab8500_chargalg_time_to_restart(struct ab8500_chargalg *di) +{ + struct power_supply_battery_info *bi = di->bm->bi; + + /* Sanity check - these need to have some reasonable values */ + if (!di->batt_data.volt_uv || !di->batt_data.percent) + return false; + + /* Some batteries tell us at which voltage we should restart charging */ + if (bi->charge_restart_voltage_uv > 0) { + if (di->batt_data.volt_uv <= bi->charge_restart_voltage_uv) + return true; + /* Else we restart as we reach a certain capacity */ + } else { + if (di->batt_data.percent <= AB8500_RECHARGE_CAP) + return true; + } + + return false; +} + /** * ab8500_chargalg_algorithm() - Main function for the algorithm * @di: pointer to the ab8500_chargalg structure @@ -1459,7 +1487,7 @@ static void ab8500_chargalg_algorithm(struct ab8500_chargalg *di) fallthrough; case STATE_WAIT_FOR_RECHARGE: - if (di->batt_data.percent <= AB8500_RECHARGE_CAP) + if (ab8500_chargalg_time_to_restart(di)) ab8500_chargalg_state_to(di, STATE_NORMAL_INIT); break; -- cgit v1.2.3 From e08f8a118514c94c8cf78aa1dcf5f26f7b6918ba Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 15 Apr 2022 22:36:38 +0200 Subject: power: supply: ab8500: Exit maintenance if too low voltage The maintenance charging is supposedly designed such that the maintenance current compensates for the battery discharge curve, and as the charging progress from CC/CV -> maintenance A -> maintenance B states, we end up on a reasonable voltage to restart ordinary CC/CV charging after the safety timer at the maintenance B state exits. However: old batteries discharge quicker, and in an old battery we might not get to the expiration of the maintenance B timer before the battery is completely depleted and the system powers off with an empty battery. This is hardly the desire of anyone leaving their phone in the charger for a few days! Introduce a second clause in both maintenance states such that we exit the state and return to ordinary CC/CV charging if the voltage drops below charge_restart_voltage_uv or 95% if this is not defined for the battery. Signed-off-by: Linus Walleij Reviewed-by: Matti Vaittinen Signed-off-by: Sebastian Reichel --- drivers/power/supply/ab8500_chargalg.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/power/supply/ab8500_chargalg.c b/drivers/power/supply/ab8500_chargalg.c index 037ae9b4a7d0..f4c017527de4 100644 --- a/drivers/power/supply/ab8500_chargalg.c +++ b/drivers/power/supply/ab8500_chargalg.c @@ -1514,6 +1514,14 @@ static void ab8500_chargalg_algorithm(struct ab8500_chargalg *di) ab8500_chargalg_stop_maintenance_timer(di); ab8500_chargalg_state_to(di, STATE_MAINTENANCE_B_INIT); } + /* + * This happens if the voltage drops too quickly during + * maintenance charging, especially in older batteries. + */ + if (ab8500_chargalg_time_to_restart(di)) { + ab8500_chargalg_state_to(di, STATE_NORMAL_INIT); + dev_info(di->dev, "restarted charging from maintenance state A - battery getting old?\n"); + } break; case STATE_MAINTENANCE_B_INIT: @@ -1538,6 +1546,14 @@ static void ab8500_chargalg_algorithm(struct ab8500_chargalg *di) ab8500_chargalg_stop_maintenance_timer(di); ab8500_chargalg_state_to(di, STATE_NORMAL_INIT); } + /* + * This happens if the voltage drops too quickly during + * maintenance charging, especially in older batteries. + */ + if (ab8500_chargalg_time_to_restart(di)) { + ab8500_chargalg_state_to(di, STATE_NORMAL_INIT); + dev_info(di->dev, "restarted charging from maintenance state B - battery getting old?\n"); + } break; case STATE_TEMP_LOWHIGH_INIT: -- cgit v1.2.3 From 926034353d3c67db1ffeab47dcb7f6bdac02a263 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 9 May 2022 12:03:00 +0300 Subject: fs/ntfs3: Don't clear upper bits accidentally in log_replay() The "vcn" variable is a 64 bit. The "log->clst_per_page" variable is a u32. This means that the mask accidentally clears out the high 32 bits when it was only supposed to clear some low bits. Fix this by adding a cast to u64. Fixes: b46acd6a6a62 ("fs/ntfs3: Add NTFS journal") Signed-off-by: Dan Carpenter Reviewed-by: Namjae Jeon Signed-off-by: Konstantin Komarov --- fs/ntfs3/fslog.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/ntfs3/fslog.c b/fs/ntfs3/fslog.c index 49b7df616778..614513460b8e 100644 --- a/fs/ntfs3/fslog.c +++ b/fs/ntfs3/fslog.c @@ -5057,7 +5057,7 @@ undo_action_next: goto add_allocated_vcns; vcn = le64_to_cpu(lrh->target_vcn); - vcn &= ~(log->clst_per_page - 1); + vcn &= ~(u64)(log->clst_per_page - 1); add_allocated_vcns: for (i = 0, vcn = le64_to_cpu(lrh->target_vcn), -- cgit v1.2.3 From a4c0094fcf7628f31bf82a7b25e7f51ee5a22324 Mon Sep 17 00:00:00 2001 From: Asmaa Mnebhi Date: Tue, 14 Jun 2022 10:19:11 -0400 Subject: power: reset: pwr-mlxbf: add BlueField SoC power control driver This driver supports handling 2 BlueField power states controlled by GPIO interrupts: 1) chip reset and 2) low power mode Signed-off-by: Asmaa Mnebhi Signed-off-by: Sebastian Reichel --- drivers/power/reset/Kconfig | 6 +++ drivers/power/reset/Makefile | 1 + drivers/power/reset/pwr-mlxbf.c | 97 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 104 insertions(+) create mode 100644 drivers/power/reset/pwr-mlxbf.c diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index 4b563db3ab3e..a8c46ba5878f 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -297,4 +297,10 @@ config NVMEM_REBOOT_MODE then the bootloader can read it and take different action according to the mode. +config POWER_MLXBF + tristate "Mellanox BlueField power handling driver" + depends on (GPIO_MLXBF2 && ACPI) + help + This driver supports reset or low power mode handling for Mellanox BlueField. + endif diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile index f606a2f60539..0a39424fc558 100644 --- a/drivers/power/reset/Makefile +++ b/drivers/power/reset/Makefile @@ -35,3 +35,4 @@ obj-$(CONFIG_REBOOT_MODE) += reboot-mode.o obj-$(CONFIG_SYSCON_REBOOT_MODE) += syscon-reboot-mode.o obj-$(CONFIG_POWER_RESET_SC27XX) += sc27xx-poweroff.o obj-$(CONFIG_NVMEM_REBOOT_MODE) += nvmem-reboot-mode.o +obj-$(CONFIG_POWER_MLXBF) += pwr-mlxbf.o diff --git a/drivers/power/reset/pwr-mlxbf.c b/drivers/power/reset/pwr-mlxbf.c new file mode 100644 index 000000000000..c1f9987834a2 --- /dev/null +++ b/drivers/power/reset/pwr-mlxbf.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0-only or BSD-3-Clause + +/* + * Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +const char *rst_pwr_hid = "MLNXBF24"; +const char *low_pwr_hid = "MLNXBF29"; + +struct pwr_mlxbf { + struct work_struct send_work; + const char *hid; +}; + +static void pwr_mlxbf_send_work(struct work_struct *work) +{ + acpi_bus_generate_netlink_event("button/power.*", "Power Button", 0x80, 1); +} + +static irqreturn_t pwr_mlxbf_irq(int irq, void *ptr) +{ + struct pwr_mlxbf *priv = ptr; + + if (!strncmp(priv->hid, rst_pwr_hid, 8)) + emergency_restart(); + + if (!strncmp(priv->hid, low_pwr_hid, 8)) + schedule_work(&priv->send_work); + + return IRQ_HANDLED; +} + +static int pwr_mlxbf_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct acpi_device *adev; + struct pwr_mlxbf *priv; + const char *hid; + int irq, err; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + adev = ACPI_COMPANION(dev); + if (!adev) + return -ENXIO; + + hid = acpi_device_hid(adev); + priv->hid = hid; + + irq = acpi_dev_gpio_irq_get(ACPI_COMPANION(dev), 0); + if (irq < 0) + return dev_err_probe(dev, irq, "Error getting %s irq.\n", priv->hid); + + err = devm_work_autocancel(dev, &priv->send_work, pwr_mlxbf_send_work); + if (err) + return err; + + err = devm_request_irq(dev, irq, pwr_mlxbf_irq, 0, hid, priv); + if (err) + dev_err(dev, "Failed request of %s irq\n", priv->hid); + + return err; +} + +static const struct acpi_device_id __maybe_unused pwr_mlxbf_acpi_match[] = { + { "MLNXBF24", 0 }, + { "MLNXBF29", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(acpi, pwr_mlxbf_acpi_match); + +static struct platform_driver pwr_mlxbf_driver = { + .driver = { + .name = "pwr_mlxbf", + .acpi_match_table = pwr_mlxbf_acpi_match, + }, + .probe = pwr_mlxbf_probe, +}; + +module_platform_driver(pwr_mlxbf_driver); + +MODULE_DESCRIPTION("Mellanox BlueField power driver"); +MODULE_AUTHOR("Asmaa Mnebhi "); +MODULE_LICENSE("Dual BSD/GPL"); -- cgit v1.2.3 From e9405be8f9c204ea7e103b37821efea8aba5a79a Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 10 Jun 2022 12:24:07 +0300 Subject: dt-bindings: reset: convert Atmel/Microchip reset controller to YAML Convert Atmel/Microchip reset controller to YAML. Signed-off-by: Claudiu Beznea Reviewed-by: Rob Herring Signed-off-by: Sebastian Reichel --- .../devicetree/bindings/arm/atmel-sysregs.txt | 15 ------- .../bindings/reset/atmel,at91sam9260-reset.yaml | 49 ++++++++++++++++++++++ 2 files changed, 49 insertions(+), 15 deletions(-) create mode 100644 Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 16eef600d599..ab1b352344ae 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -25,21 +25,6 @@ System Timer (ST) required properties: Its subnodes can be: - watchdog: compatible should be "atmel,at91rm9200-wdt" -RSTC Reset Controller required properties: -- compatible: Should be "atmel,-rstc". - can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7" - it also can be "microchip,sam9x60-rstc" -- reg: Should contain registers location and length -- clocks: phandle to input clock. - -Example: - - rstc@fffffd00 { - compatible = "atmel,at91sam9260-rstc"; - reg = <0xfffffd00 0x10>; - clocks = <&clk32k>; - }; - RAMC SDRAM/DDR Controller required properties: - compatible: Should be "atmel,at91rm9200-sdramc", "syscon" "atmel,at91sam9260-sdramc", diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml new file mode 100644 index 000000000000..34c40b875e20 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/atmel,at91sam9260-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel/Microchip System Reset Controller + +maintainers: + - Claudiu Beznea + +description: | + The system reset controller can be used to reset the CPU. + +properties: + compatible: + oneOf: + - items: + - enum: + - atmel,at91sam9260-rstc + - atmel,at91sam9g45-rstc + - atmel,sama5d3-rstc + - microchip,sam9x60-rstc + - items: + - const: atmel,sama5d3-rstc + - const: atmel,at91sam9g45-rstc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include + + reset-controller@fffffd00 { + compatible = "atmel,at91sam9260-rstc"; + reg = <0xfffffd00 0x10>; + clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; + }; -- cgit v1.2.3 From a261ba4138b55d4ccf98d7bd08062d134cbd02d8 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 10 Jun 2022 12:24:08 +0300 Subject: dt-bindings: reset: atmel,at91sam9260-reset: add sama7g5 bindings Add documentation for SAMA7G5 reset controller. Compared with previous versions of reset controllers this one contains support for resetting in SoC devices (e.g. USB PHYs). Signed-off-by: Claudiu Beznea Reviewed-by: Rob Herring Signed-off-by: Sebastian Reichel --- .../bindings/reset/atmel,at91sam9260-reset.yaml | 23 ++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml index 34c40b875e20..98465d26949e 100644 --- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml @@ -10,7 +10,8 @@ maintainers: - Claudiu Beznea description: | - The system reset controller can be used to reset the CPU. + The system reset controller can be used to reset the CPU. In case of + SAMA7G5 it can also reset some devices (e.g. USB PHYs). properties: compatible: @@ -21,21 +22,39 @@ properties: - atmel,at91sam9g45-rstc - atmel,sama5d3-rstc - microchip,sam9x60-rstc + - microchip,sama7g5-rstc - items: - const: atmel,sama5d3-rstc - const: atmel,at91sam9g45-rstc reg: - maxItems: 1 + minItems: 1 + items: + - description: base registers for system reset control + - description: registers for device specific reset control clocks: maxItems: 1 + "#reset-cells": + const: 1 + required: - compatible - reg - clocks +allOf: + - if: + properties: + compatible: + contains: + enum: + - microchip,sama7g5-rstc + then: + required: + - "#reset-cells" + additionalProperties: false examples: -- cgit v1.2.3 From 5994f58977e0123d5cb77617b3cc4676325028dd Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 10 Jun 2022 12:24:09 +0300 Subject: dt-bindings: reset: add sama7g5 definitions Add reset bindings for SAMA7G5. At the moment only USB PHYs are included. Signed-off-by: Claudiu Beznea Acked-by: Philipp Zabel Acked-by: Rob Herring Signed-off-by: Sebastian Reichel --- include/dt-bindings/reset/sama7g5-reset.h | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 include/dt-bindings/reset/sama7g5-reset.h diff --git a/include/dt-bindings/reset/sama7g5-reset.h b/include/dt-bindings/reset/sama7g5-reset.h new file mode 100644 index 000000000000..2116f41d04e0 --- /dev/null +++ b/include/dt-bindings/reset/sama7g5-reset.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef __DT_BINDINGS_RESET_SAMA7G5_H +#define __DT_BINDINGS_RESET_SAMA7G5_H + +#define SAMA7G5_RESET_USB_PHY1 4 +#define SAMA7G5_RESET_USB_PHY2 5 +#define SAMA7G5_RESET_USB_PHY3 6 + +#endif /* __DT_BINDINGS_RESET_SAMA7G5_H */ -- cgit v1.2.3 From cd4ed0ab802b5aa171015dae40ac2418e1f7f720 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 10 Jun 2022 12:24:10 +0300 Subject: power: reset: at91-reset: document structures and enums Document structures and enums. Signed-off-by: Claudiu Beznea Signed-off-by: Sebastian Reichel --- drivers/power/reset/at91-reset.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c index 64def79d557a..e62798750b6b 100644 --- a/drivers/power/reset/at91-reset.c +++ b/drivers/power/reset/at91-reset.c @@ -39,6 +39,17 @@ #define AT91_RSTC_URSTIEN BIT(4) /* User Reset Interrupt Enable */ #define AT91_RSTC_ERSTL GENMASK(11, 8) /* External Reset Length */ +/** + * enum reset_type - reset types + * @RESET_TYPE_GENERAL: first power-up reset + * @RESET_TYPE_WAKEUP: return from backup mode + * @RESET_TYPE_WATCHDOG: watchdog fault + * @RESET_TYPE_SOFTWARE: processor reset required by software + * @RESET_TYPE_USER: NRST pin detected low + * @RESET_TYPE_CPU_FAIL: CPU clock failure detection + * @RESET_TYPE_XTAL_FAIL: 32KHz crystal failure dectection fault + * @RESET_TYPE_ULP2: ULP2 reset + */ enum reset_type { RESET_TYPE_GENERAL = 0, RESET_TYPE_WAKEUP = 1, @@ -50,6 +61,15 @@ enum reset_type { RESET_TYPE_ULP2 = 8, }; +/** + * struct at91_reset - AT91 reset specific data structure + * @rstc_base: base address for system reset + * @ramc_base: array with base addresses of RAM controllers + * @sclk: slow clock + * @nb: reset notifier block + * @args: SoC specific system reset arguments + * @ramc_lpr: SDRAM Controller Low Power Register + */ struct at91_reset { void __iomem *rstc_base; void __iomem *ramc_base[2]; -- cgit v1.2.3 From e17ad25bc31a3565c1adab924316d72935eef4a2 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 10 Jun 2022 12:24:11 +0300 Subject: power: reset: at91-reset: add at91_reset_data Add struct at91_reset_data to keep per platform related information. This is a prerequisite for adding reset_controller_dev support. Signed-off-by: Claudiu Beznea Signed-off-by: Sebastian Reichel --- drivers/power/reset/at91-reset.c | 45 ++++++++++++++++++++++++++++++---------- 1 file changed, 34 insertions(+), 11 deletions(-) diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c index e62798750b6b..bb073aba816f 100644 --- a/drivers/power/reset/at91-reset.c +++ b/drivers/power/reset/at91-reset.c @@ -66,6 +66,7 @@ enum reset_type { * @rstc_base: base address for system reset * @ramc_base: array with base addresses of RAM controllers * @sclk: slow clock + * @data: platform specific reset data * @nb: reset notifier block * @args: SoC specific system reset arguments * @ramc_lpr: SDRAM Controller Low Power Register @@ -74,11 +75,26 @@ struct at91_reset { void __iomem *rstc_base; void __iomem *ramc_base[2]; struct clk *sclk; + const struct at91_reset_data *data; struct notifier_block nb; u32 args; u32 ramc_lpr; }; +/** + * struct at91_reset_data - AT91 reset data + * @reset_args: SoC specific system reset arguments + * @n_device_reset: number of device resets + * @device_reset_min_id: min id for device reset + * @device_reset_max_id: max id for device reset + */ +struct at91_reset_data { + u32 reset_args; + u32 n_device_reset; + u8 device_reset_min_id; + u8 device_reset_max_id; +}; + /* * unless the SDRAM is cleanly shutdown before we hit the * reset register it can be left driving the data bus and @@ -115,7 +131,7 @@ static int at91_reset(struct notifier_block *this, unsigned long mode, "r" (reset->rstc_base), "r" (1), "r" cpu_to_le32(AT91_DDRSDRC_LPCB_POWER_DOWN), - "r" (reset->args), + "r" (reset->data->reset_args), "r" (reset->ramc_lpr) : "r4"); @@ -173,29 +189,34 @@ static const struct of_device_id at91_ramc_of_match[] = { { /* sentinel */ } }; +static const struct at91_reset_data sam9260 = { + .reset_args = AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST, +}; + +static const struct at91_reset_data samx7 = { + .reset_args = AT91_RSTC_KEY | AT91_RSTC_PROCRST, +}; + static const struct of_device_id at91_reset_of_match[] = { { .compatible = "atmel,at91sam9260-rstc", - .data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST | - AT91_RSTC_PROCRST), + .data = &sam9260, }, { .compatible = "atmel,at91sam9g45-rstc", - .data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST | - AT91_RSTC_PROCRST) + .data = &sam9260, }, { .compatible = "atmel,sama5d3-rstc", - .data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST | - AT91_RSTC_PROCRST) + .data = &sam9260, }, { .compatible = "atmel,samx7-rstc", - .data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PROCRST) + .data = &samx7, }, { .compatible = "microchip,sam9x60-rstc", - .data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PROCRST) + .data = &samx7, }, { /* sentinel */ } }; @@ -232,10 +253,12 @@ static int __init at91_reset_probe(struct platform_device *pdev) } } - match = of_match_node(at91_reset_of_match, pdev->dev.of_node); + reset->data = device_get_match_data(&pdev->dev); + if (!reset->data) + return -ENODEV; + reset->nb.notifier_call = at91_reset; reset->nb.priority = 192; - reset->args = (u32)match->data; reset->sclk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(reset->sclk)) -- cgit v1.2.3 From 5f37c797a4df2a3a5b6406af48cc565020c01d98 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 10 Jun 2022 12:24:12 +0300 Subject: power: reset: at91-reset: add reset_controller_dev support SAMA7G5 reset controller has 5 extra lines that goes to different devices (3 lines to USB PHYs, 1 line to DDR controller, 1 line to DDR PHY controller). These reset lines could be requested by different controller drivers (e.g. USB PHY driver) and these controllers' drivers could assert/deassert these lines when necessary. Thus add support for reset_controller_dev which brings this functionality. Signed-off-by: Claudiu Beznea Reviewed-by: Philipp Zabel Signed-off-by: Sebastian Reichel --- drivers/power/reset/at91-reset.c | 106 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 102 insertions(+), 4 deletions(-) diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c index bb073aba816f..bc9f1d9e7867 100644 --- a/drivers/power/reset/at91-reset.c +++ b/drivers/power/reset/at91-reset.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -65,8 +66,11 @@ enum reset_type { * struct at91_reset - AT91 reset specific data structure * @rstc_base: base address for system reset * @ramc_base: array with base addresses of RAM controllers + * @dev_base: base address for devices reset * @sclk: slow clock * @data: platform specific reset data + * @rcdev: reset controller device + * @lock: lock for devices reset register access * @nb: reset notifier block * @args: SoC specific system reset arguments * @ramc_lpr: SDRAM Controller Low Power Register @@ -74,13 +78,18 @@ enum reset_type { struct at91_reset { void __iomem *rstc_base; void __iomem *ramc_base[2]; + void __iomem *dev_base; struct clk *sclk; const struct at91_reset_data *data; + struct reset_controller_dev rcdev; + spinlock_t lock; struct notifier_block nb; u32 args; u32 ramc_lpr; }; +#define to_at91_reset(r) container_of(r, struct at91_reset, rcdev) + /** * struct at91_reset_data - AT91 reset data * @reset_args: SoC specific system reset arguments @@ -222,6 +231,89 @@ static const struct of_device_id at91_reset_of_match[] = { }; MODULE_DEVICE_TABLE(of, at91_reset_of_match); +static int at91_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct at91_reset *reset = to_at91_reset(rcdev); + unsigned long flags; + u32 val; + + spin_lock_irqsave(&reset->lock, flags); + val = readl_relaxed(reset->dev_base); + if (assert) + val |= BIT(id); + else + val &= ~BIT(id); + writel_relaxed(val, reset->dev_base); + spin_unlock_irqrestore(&reset->lock, flags); + + return 0; +} + +static int at91_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return at91_reset_update(rcdev, id, true); +} + +static int at91_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return at91_reset_update(rcdev, id, false); +} + +static int at91_reset_dev_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct at91_reset *reset = to_at91_reset(rcdev); + u32 val; + + val = readl_relaxed(reset->dev_base); + + return !!(val & BIT(id)); +} + +static const struct reset_control_ops at91_reset_ops = { + .assert = at91_reset_assert, + .deassert = at91_reset_deassert, + .status = at91_reset_dev_status, +}; + +static int at91_reset_of_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + struct at91_reset *reset = to_at91_reset(rcdev); + + if (!reset->data->n_device_reset || + (reset_spec->args[0] < reset->data->device_reset_min_id || + reset_spec->args[0] > reset->data->device_reset_max_id)) + return -EINVAL; + + return reset_spec->args[0]; +} + +static int at91_rcdev_init(struct at91_reset *reset, + struct platform_device *pdev) +{ + if (!reset->data->n_device_reset) + return 0; + + reset->dev_base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 1, + NULL); + if (IS_ERR(reset->dev_base)) + return -ENODEV; + + spin_lock_init(&reset->lock); + reset->rcdev.ops = &at91_reset_ops; + reset->rcdev.owner = THIS_MODULE; + reset->rcdev.of_node = pdev->dev.of_node; + reset->rcdev.nr_resets = reset->data->n_device_reset; + reset->rcdev.of_reset_n_cells = 1; + reset->rcdev.of_xlate = at91_reset_of_xlate; + + return devm_reset_controller_register(&pdev->dev, &reset->rcdev); +} + static int __init at91_reset_probe(struct platform_device *pdev) { const struct of_device_id *match; @@ -272,6 +364,10 @@ static int __init at91_reset_probe(struct platform_device *pdev) platform_set_drvdata(pdev, reset); + ret = at91_rcdev_init(reset, pdev); + if (ret) + goto disable_clk; + if (of_device_is_compatible(pdev->dev.of_node, "microchip,sam9x60-rstc")) { u32 val = readl(reset->rstc_base + AT91_RSTC_MR); @@ -280,14 +376,16 @@ static int __init at91_reset_probe(struct platform_device *pdev) } ret = register_restart_handler(&reset->nb); - if (ret) { - clk_disable_unprepare(reset->sclk); - return ret; - } + if (ret) + goto disable_clk; at91_reset_status(pdev, reset->rstc_base); return 0; + +disable_clk: + clk_disable_unprepare(reset->sclk); + return ret; } static int __exit at91_reset_remove(struct platform_device *pdev) -- cgit v1.2.3 From a22c8e8834bcc55e44d0bae738f0915df7e6f573 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 10 Jun 2022 12:24:13 +0300 Subject: power: reset: at91-reset: add support for SAMA7G5 Add support for SAMA7G5 including reset_controller_dev support for 3 lines (which are USB PHYs). Signed-off-by: Claudiu Beznea Signed-off-by: Sebastian Reichel --- drivers/power/reset/at91-reset.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c index bc9f1d9e7867..741e44a017c3 100644 --- a/drivers/power/reset/at91-reset.c +++ b/drivers/power/reset/at91-reset.c @@ -22,6 +22,8 @@ #include #include +#include + #define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */ #define AT91_RSTC_PROCRST BIT(0) /* Processor Reset */ #define AT91_RSTC_PERRST BIT(2) /* Peripheral Reset */ @@ -206,6 +208,13 @@ static const struct at91_reset_data samx7 = { .reset_args = AT91_RSTC_KEY | AT91_RSTC_PROCRST, }; +static const struct at91_reset_data sama7g5 = { + .reset_args = AT91_RSTC_KEY | AT91_RSTC_PROCRST, + .n_device_reset = 3, + .device_reset_min_id = SAMA7G5_RESET_USB_PHY1, + .device_reset_max_id = SAMA7G5_RESET_USB_PHY3, +}; + static const struct of_device_id at91_reset_of_match[] = { { .compatible = "atmel,at91sam9260-rstc", @@ -227,6 +236,10 @@ static const struct of_device_id at91_reset_of_match[] = { .compatible = "microchip,sam9x60-rstc", .data = &samx7, }, + { + .compatible = "microchip,sama7g5-rstc", + .data = &sama7g5, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, at91_reset_of_match); -- cgit v1.2.3 From f759942b72a9ad309282b2fedcebcee3c4c58e24 Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Mon, 6 Jun 2022 18:57:21 +0300 Subject: fs/ntfs3: Add missing error check We must check return value of log_read_rst Signed-off-by: Konstantin Komarov --- fs/ntfs3/fslog.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/fs/ntfs3/fslog.c b/fs/ntfs3/fslog.c index 614513460b8e..e7c494005122 100644 --- a/fs/ntfs3/fslog.c +++ b/fs/ntfs3/fslog.c @@ -3843,6 +3843,8 @@ int log_replay(struct ntfs_inode *ni, bool *initialized) memset(&rst_info2, 0, sizeof(struct restart_info)); err = log_read_rst(log, l_size, false, &rst_info2); + if (err) + goto out; /* Determine which restart area to use. */ if (!rst_info2.restart || rst_info2.last_lsn <= rst_info.last_lsn) -- cgit v1.2.3 From d2a632a8a11756197deb1341bbb09c09abaf20ce Mon Sep 17 00:00:00 2001 From: Mateusz Jończyk Date: Fri, 25 Feb 2022 22:50:09 +0100 Subject: rtc: mc146818-lib: reduce RTC_UIP polling period MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Waiting 1ms every time is not necessary, for example on some AMD boxes the RTC_UIP bit is documented as being high for around 270 microseconds in some cases [1], which agreed with experiments on an SB710 southbridge. So 100us seems optimal. This in preparation for mach_get_cmos_time() refactoring. The functions mc146818_get_time() and mach_get_cmos_time() in arch/x86/kernel/rtc.c perform the same function and the code is duplicated. mach_get_cmos_time() is busy waiting for the RTC_UIP bit to clear, so make mc146818_get_time() more similar to it by reducing the polling period. [1] AMD SB700/710/750 Register Reference Guide, page 307, https://developer.amd.com/wordpress/media/2012/10/43009_sb7xx_rrg_pub_1.00.pdf "SB700 A12: The UIP high pulse is 270 μS Typical when SS on SRC clock is OFF and 100μ min when SRC SS is ON." [sic] Signed-off-by: Mateusz Jończyk Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Borislav Petkov Cc: Dave Hansen Cc: x86@kernel.org Cc: "H. Peter Anvin" Cc: Alessandro Zummo Cc: Alexandre Belloni Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220225215011.861477-2-mat.jonczyk@o2.pl --- drivers/rtc/rtc-mc146818-lib.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/rtc/rtc-mc146818-lib.c b/drivers/rtc/rtc-mc146818-lib.c index 522449b25921..f1c09f1db044 100644 --- a/drivers/rtc/rtc-mc146818-lib.c +++ b/drivers/rtc/rtc-mc146818-lib.c @@ -21,13 +21,13 @@ bool mc146818_avoid_UIP(void (*callback)(unsigned char seconds, void *param), unsigned long flags; unsigned char seconds; - for (i = 0; i < 10; i++) { + for (i = 0; i < 100; i++) { spin_lock_irqsave(&rtc_lock, flags); /* * Check whether there is an update in progress during which the * readout is unspecified. The maximum update time is ~2ms. Poll - * every msec for completion. + * every 100 usec for completion. * * Store the second value before checking UIP so a long lasting * NMI which happens to hit after the UIP check cannot make @@ -37,7 +37,7 @@ bool mc146818_avoid_UIP(void (*callback)(unsigned char seconds, void *param), if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP) { spin_unlock_irqrestore(&rtc_lock, flags); - mdelay(1); + udelay(100); continue; } @@ -56,7 +56,7 @@ bool mc146818_avoid_UIP(void (*callback)(unsigned char seconds, void *param), */ if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP) { spin_unlock_irqrestore(&rtc_lock, flags); - mdelay(1); + udelay(100); continue; } -- cgit v1.2.3 From 8c798e1ec185431a57403a908c379eea1b6bc751 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Tue, 26 Apr 2022 09:10:52 +0200 Subject: rtc: rv8803: factor out existing register initialization to function The driver probe currently initializes some registers to non-POR values. These values are not reinstated if the RTC experiences voltage loss later on. Prepare for fixing this by factoring out the initialization to a separate function. Signed-off-by: Ahmad Fatoum Signed-off-by: Sascha Hauer Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220426071056.1187235-2-s.hauer@pengutronix.de --- drivers/rtc/rtc-rv8803.c | 43 +++++++++++++++++++++++++++++-------------- 1 file changed, 29 insertions(+), 14 deletions(-) diff --git a/drivers/rtc/rtc-rv8803.c b/drivers/rtc/rtc-rv8803.c index f69e0b1137cd..c880f8d6c742 100644 --- a/drivers/rtc/rtc-rv8803.c +++ b/drivers/rtc/rtc-rv8803.c @@ -64,6 +64,7 @@ struct rv8803_data { struct rtc_device *rtc; struct mutex flags_lock; u8 ctrl; + u8 backup; enum rv8803_type type; }; @@ -498,18 +499,32 @@ static int rx8900_trickle_charger_init(struct rv8803_data *rv8803) if (err < 0) return err; - flags = ~(RX8900_FLAG_VDETOFF | RX8900_FLAG_SWOFF) & (u8)err; - - if (of_property_read_bool(node, "epson,vdet-disable")) - flags |= RX8900_FLAG_VDETOFF; - - if (of_property_read_bool(node, "trickle-diode-disable")) - flags |= RX8900_FLAG_SWOFF; + flags = (u8)err; + flags &= ~(RX8900_FLAG_VDETOFF | RX8900_FLAG_SWOFF); + flags |= rv8803->backup; return i2c_smbus_write_byte_data(rv8803->client, RX8900_BACKUP_CTRL, flags); } +/* configure registers with values different than the Power-On reset defaults */ +static int rv8803_regs_configure(struct rv8803_data *rv8803) +{ + int err; + + err = rv8803_write_reg(rv8803->client, RV8803_EXT, RV8803_EXT_WADA); + if (err) + return err; + + err = rx8900_trickle_charger_init(rv8803); + if (err) { + dev_err(&rv8803->client->dev, "failed to init charger\n"); + return err; + } + + return 0; +} + static int rv8803_probe(struct i2c_client *client, const struct i2c_device_id *id) { @@ -576,15 +591,15 @@ static int rv8803_probe(struct i2c_client *client, if (!client->irq) clear_bit(RTC_FEATURE_ALARM, rv8803->rtc->features); - err = rv8803_write_reg(rv8803->client, RV8803_EXT, RV8803_EXT_WADA); - if (err) - return err; + if (of_property_read_bool(client->dev.of_node, "epson,vdet-disable")) + rv8803->backup |= RX8900_FLAG_VDETOFF; - err = rx8900_trickle_charger_init(rv8803); - if (err) { - dev_err(&client->dev, "failed to init charger\n"); + if (of_property_read_bool(client->dev.of_node, "trickle-diode-disable")) + rv8803->backup |= RX8900_FLAG_SWOFF; + + err = rv8803_regs_configure(rv8803); + if (err) return err; - } rv8803->rtc->ops = &rv8803_rtc_ops; rv8803->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; -- cgit v1.2.3 From f8176e0bb83ff8dcc6d9fa8595a0966e631d2ba7 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Tue, 26 Apr 2022 09:10:53 +0200 Subject: rtc: rv8803: initialize registers on post-probe voltage loss The driver probe currently initializes some registers to non-POR values. These values are not reinstated if the RTC experiences voltage loss later on. Fix this. Signed-off-by: Ahmad Fatoum Signed-off-by: Sascha Hauer Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220426071056.1187235-3-s.hauer@pengutronix.de --- drivers/rtc/rtc-rv8803.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/rtc/rtc-rv8803.c b/drivers/rtc/rtc-rv8803.c index c880f8d6c742..21a6f1eddb09 100644 --- a/drivers/rtc/rtc-rv8803.c +++ b/drivers/rtc/rtc-rv8803.c @@ -137,6 +137,13 @@ static int rv8803_write_regs(const struct i2c_client *client, return ret; } +static int rv8803_regs_configure(struct rv8803_data *rv8803); + +static int rv8803_regs_reset(struct rv8803_data *rv8803) +{ + return rv8803_regs_configure(rv8803); +} + static irqreturn_t rv8803_handle_irq(int irq, void *dev_id) { struct i2c_client *client = dev_id; @@ -270,6 +277,12 @@ static int rv8803_set_time(struct device *dev, struct rtc_time *tm) return flags; } + if (flags & RV8803_FLAG_V2F) { + ret = rv8803_regs_reset(rv8803); + if (ret) + return ret; + } + ret = rv8803_write_reg(rv8803->client, RV8803_FLAG, flags & ~(RV8803_FLAG_V1F | RV8803_FLAG_V2F)); -- cgit v1.2.3 From c27fee16fab17bc5d62b643285e7cd76a6c49d95 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Tue, 26 Apr 2022 09:10:54 +0200 Subject: rtc: rv8803: re-initialize all Epson RX8803 registers on voltage loss MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The reference manuals of both the RX8803 and RV8803 dictate that "[On V2F/VLF = ] all registers must be initialized". The RV-8803 application manual (rev. 1.6) further specifies that crossing V_LOW2 threshold enables flag V2F and triggers a Power-On reset. According to table 3.11 in the document, all control registers are defined to sensible values. However, The Epson RX-8803 doesn't offer the same guarantees. It explicitly states: During the initial power-up, the TEST bit is reset to "0" and the VLF bit is set to "1". ∗ At this point, all other register values are _undefined_, so be sure to perform a reset before using the module. Commit d3700b6b6479 ("rtc: rv8803: Stop the clock while setting the time") also had this rationale: Indeed, all the registers must be initialized if the voltage has been lower than VLOW2 (triggering V2F), but not low enough to trigger a POR. We should follow the advice and initialize all applicable registers. We can group the registers into 3 groups: A) Already correctly handled registers: * 0B-0Ch | Timer Counter | unused and disabled by clearing TE in 0Dh * 0Dh | Extension Reg | already initialized in rv8803_regs_configure * 0Eh | Flag Reg | handled in IRQ handler, except for VLF, VDET * 0Eh | VLF, VDET | cleared in ->set_time * 10h | 100th Seconds | Already reset via RESET bit * 20-21h | Capture Buffer | holds timestamp unused by driver * 2Fh | Event Control | resets automatically B) Registers that are hardware initialized on POR, but not on VLF: * 0Fh | Control Reg * 2Ch | OSC Offset C) RAM that is undefined on voltage loss: * 00-06h | Date/Time * 07h | RAM * 08-0Ah | Alarm This means we should initialize after VLF the registers in group B (RV8803_CTRL and RV8803_OSC_OFFSET). Group C is all-zero after voltage loss on the RV-8803, but undefined on the RX-8803. This is ok for Date/Time because ->get_time returns an error code for as long as the voltage loss flag is active. It's cleared on ->set_time however. Zeroing both RAM and alarm ensures a fixed value is read afterwards. Signed-off-by: Ahmad Fatoum Signed-off-by: Sascha Hauer Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220426071056.1187235-4-s.hauer@pengutronix.de --- drivers/rtc/rtc-rv8803.c | 40 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/rtc/rtc-rv8803.c b/drivers/rtc/rtc-rv8803.c index 21a6f1eddb09..fe1247e771b9 100644 --- a/drivers/rtc/rtc-rv8803.c +++ b/drivers/rtc/rtc-rv8803.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -33,6 +34,7 @@ #define RV8803_EXT 0x0D #define RV8803_FLAG 0x0E #define RV8803_CTRL 0x0F +#define RV8803_OSC_OFFSET 0x2C #define RV8803_EXT_WADA BIT(6) @@ -49,12 +51,15 @@ #define RV8803_CTRL_TIE BIT(4) #define RV8803_CTRL_UIE BIT(5) +#define RX8803_CTRL_CSEL GENMASK(7, 6) + #define RX8900_BACKUP_CTRL 0x18 #define RX8900_FLAG_SWOFF BIT(2) #define RX8900_FLAG_VDETOFF BIT(3) enum rv8803_type { rv_8803, + rx_8803, rx_8804, rx_8900 }; @@ -137,10 +142,41 @@ static int rv8803_write_regs(const struct i2c_client *client, return ret; } +static int rv8803_regs_init(struct rv8803_data *rv8803) +{ + int ret; + + ret = rv8803_write_reg(rv8803->client, RV8803_OSC_OFFSET, 0x00); + if (ret) + return ret; + + ret = rv8803_write_reg(rv8803->client, RV8803_CTRL, + FIELD_PREP(RX8803_CTRL_CSEL, 1)); /* 2s */ + if (ret) + return ret; + + ret = rv8803_write_regs(rv8803->client, RV8803_ALARM_MIN, 3, + (u8[]){ 0, 0, 0 }); + if (ret) + return ret; + + return rv8803_write_reg(rv8803->client, RV8803_RAM, 0x00); +} + static int rv8803_regs_configure(struct rv8803_data *rv8803); static int rv8803_regs_reset(struct rv8803_data *rv8803) { + /* + * The RV-8803 resets all registers to POR defaults after voltage-loss, + * the Epson RTCs don't, so we manually reset the remainder here. + */ + if (rv8803->type == rx_8803 || rv8803->type == rx_8900) { + int ret = rv8803_regs_init(rv8803); + if (ret) + return ret; + } + return rv8803_regs_configure(rv8803); } @@ -631,7 +667,7 @@ static int rv8803_probe(struct i2c_client *client, static const struct i2c_device_id rv8803_id[] = { { "rv8803", rv_8803 }, { "rv8804", rx_8804 }, - { "rx8803", rv_8803 }, + { "rx8803", rx_8803 }, { "rx8900", rx_8900 }, { } }; @@ -644,7 +680,7 @@ static const __maybe_unused struct of_device_id rv8803_of_match[] = { }, { .compatible = "epson,rx8803", - .data = (void *)rv_8803 + .data = (void *)rx_8803 }, { .compatible = "epson,rx8804", -- cgit v1.2.3 From 139682400a2ac549ed717eac3a09759a1762366d Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Thu, 28 Apr 2022 17:27:26 +0800 Subject: dt-bindings: rtc: mediatek: add mt6358 and mt6366 compatible Add mt6358 and mt6366 compatible in devicetree-binding document for MediaTek PMIC based RTC. mt6358 and mt6366 use same compatible data to store RTC_WRTGR address offset. mt6358-rtc should be used as fallback for mt6366-rtc. Signed-off-by: Allen-KH Cheng Signed-off-by: Yuchen Huang Acked-by: Krzysztof Kozlowski Reviewed-by: Matthias Brugger Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220428092726.25814-2-allen-kh.cheng@mediatek.com --- Documentation/devicetree/bindings/rtc/rtc-mt6397.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/rtc/rtc-mt6397.txt b/Documentation/devicetree/bindings/rtc/rtc-mt6397.txt index 55a0c8874c03..7212076a8f1b 100644 --- a/Documentation/devicetree/bindings/rtc/rtc-mt6397.txt +++ b/Documentation/devicetree/bindings/rtc/rtc-mt6397.txt @@ -14,6 +14,8 @@ For MediaTek PMIC wrapper bus bindings, see: Required properties: - compatible: Should be one of follows "mediatek,mt6323-rtc": for MT6323 PMIC + "mediatek,mt6358-rtc": for MT6358 PMIC + "mediatek,mt6366-rtc", "mediatek,mt6358-rtc": for MT6366 PMIC "mediatek,mt6397-rtc": for MT6397 PMIC Example: -- cgit v1.2.3 From 2023c5c8fe2e85ec7491d5a470fcca48f8144c02 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 23 May 2022 16:53:20 +0200 Subject: rtc: isl1208: do not advertise update interrupt feature if no interrupt specified If an ISL1208 device does not have an interrupt line routed, the feature shouldn't be advertised (it is by default in rtc core) or it'll confuse userspace requesting that feature (such as hwclock from util-linux). Signed-off-by: Quentin Schulz Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220523145320.123713-1-foss+kernel@0leil.net --- drivers/rtc/rtc-isl1208.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/rtc/rtc-isl1208.c b/drivers/rtc/rtc-isl1208.c index 182dfa605515..f448a525333e 100644 --- a/drivers/rtc/rtc-isl1208.c +++ b/drivers/rtc/rtc-isl1208.c @@ -880,10 +880,14 @@ isl1208_probe(struct i2c_client *client, const struct i2c_device_id *id) if (rc) return rc; - if (client->irq > 0) + if (client->irq > 0) { rc = isl1208_setup_irq(client, client->irq); - if (rc) - return rc; + if (rc) + return rc; + + } else { + clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, isl1208->rtc->features); + } if (evdet_irq > 0 && evdet_irq != client->irq) rc = isl1208_setup_irq(client, evdet_irq); -- cgit v1.2.3 From 162b05524ed30586bd2a7ede1f0392c3d1ed2d6e Mon Sep 17 00:00:00 2001 From: Tetsuo Handa Date: Fri, 10 Jun 2022 19:48:36 +0900 Subject: rtc: Replace flush_scheduled_work() with flush_work(). Since "struct rtc_device" is per a device struct, I assume that clear_uie() needs to wait for only one work associated with that device. Therefore, wait for only that work using flush_work(). Signed-off-by: Tetsuo Handa Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/8d3a0f55-d861-ba93-0d25-b1172eaa8343@I-love.SAKURA.ne.jp --- drivers/rtc/dev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/rtc/dev.c b/drivers/rtc/dev.c index 69325aeede1a..5cf90daf975c 100644 --- a/drivers/rtc/dev.c +++ b/drivers/rtc/dev.c @@ -96,7 +96,7 @@ static int clear_uie(struct rtc_device *rtc) } if (rtc->uie_task_active) { spin_unlock_irq(&rtc->irq_lock); - flush_scheduled_work(); + flush_work(&rtc->uie_task); spin_lock_irq(&rtc->irq_lock); } rtc->uie_irq_active = 0; -- cgit v1.2.3 From 33740c7f94f948767578e852e6f256038a56803d Mon Sep 17 00:00:00 2001 From: Tetsuo Handa Date: Sat, 11 Jun 2022 23:38:46 +0900 Subject: rtc: Remove unused rtc_dev_exit(). Commit 270a3bd6bdc21407 ("rtc: make class.c explicitly non-modular") removed rtc_dev_exit() call. Signed-off-by: Tetsuo Handa Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/1e2f9a99-435d-e149-7456-dfacd53be85a@I-love.SAKURA.ne.jp --- drivers/rtc/dev.c | 6 ------ drivers/rtc/rtc-core.h | 5 ----- 2 files changed, 11 deletions(-) diff --git a/drivers/rtc/dev.c b/drivers/rtc/dev.c index 5cf90daf975c..4aad9bb99868 100644 --- a/drivers/rtc/dev.c +++ b/drivers/rtc/dev.c @@ -566,9 +566,3 @@ void __init rtc_dev_init(void) if (err < 0) pr_err("failed to allocate char dev region\n"); } - -void __exit rtc_dev_exit(void) -{ - if (rtc_devt) - unregister_chrdev_region(rtc_devt, RTC_DEV_MAX); -} diff --git a/drivers/rtc/rtc-core.h b/drivers/rtc/rtc-core.h index 0abf98983e13..4b10a1b8f370 100644 --- a/drivers/rtc/rtc-core.h +++ b/drivers/rtc/rtc-core.h @@ -2,7 +2,6 @@ #ifdef CONFIG_RTC_INTF_DEV extern void __init rtc_dev_init(void); -extern void __exit rtc_dev_exit(void); extern void rtc_dev_prepare(struct rtc_device *rtc); #else @@ -11,10 +10,6 @@ static inline void rtc_dev_init(void) { } -static inline void rtc_dev_exit(void) -{ -} - static inline void rtc_dev_prepare(struct rtc_device *rtc) { } -- cgit v1.2.3 From 3f4a3322477ccc13fc6a2b15c2f6a4d0376f5ff2 Mon Sep 17 00:00:00 2001 From: Stephen Kitt Date: Fri, 10 Jun 2022 18:23:43 +0200 Subject: rtc: use simple i2c probe All these drivers have an i2c probe function which doesn't use the "struct i2c_device_id *id" parameter, so they can trivially be converted to the "probe_new" style of probe with a single argument. This change was done using the following Coccinelle script, and fixed up for whitespace changes: @ rule1 @ identifier fn; identifier client, id; @@ - static int fn(struct i2c_client *client, const struct i2c_device_id *id) + static int fn(struct i2c_client *client) { ...when != id } @ rule2 depends on rule1 @ identifier rule1.fn; identifier driver; @@ struct i2c_driver driver = { - .probe + .probe_new = ( fn | - &fn + fn ) , }; Signed-off-by: Stephen Kitt Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220610162346.4134094-1-steve@sk2.org --- drivers/rtc/rtc-ab-b5ze-s3.c | 5 ++--- drivers/rtc/rtc-ab-eoz9.c | 5 ++--- drivers/rtc/rtc-bq32k.c | 5 ++--- drivers/rtc/rtc-ds1374.c | 5 ++--- drivers/rtc/rtc-ds1672.c | 5 ++--- drivers/rtc/rtc-ds3232.c | 5 ++--- drivers/rtc/rtc-em3027.c | 5 ++--- drivers/rtc/rtc-fm3130.c | 5 ++--- drivers/rtc/rtc-hym8563.c | 5 ++--- drivers/rtc/rtc-isl12022.c | 5 ++--- drivers/rtc/rtc-max6900.c | 5 ++--- drivers/rtc/rtc-pcf8523.c | 5 ++--- drivers/rtc/rtc-pcf85363.c | 5 ++--- drivers/rtc/rtc-pcf8563.c | 5 ++--- drivers/rtc/rtc-pcf8583.c | 5 ++--- drivers/rtc/rtc-rv3029c2.c | 5 ++--- drivers/rtc/rtc-rx6110.c | 5 ++--- drivers/rtc/rtc-rx8581.c | 5 ++--- drivers/rtc/rtc-s35390a.c | 5 ++--- drivers/rtc/rtc-sd3078.c | 5 ++--- drivers/rtc/rtc-x1205.c | 5 ++--- 21 files changed, 42 insertions(+), 63 deletions(-) diff --git a/drivers/rtc/rtc-ab-b5ze-s3.c b/drivers/rtc/rtc-ab-b5ze-s3.c index 6e3e320dc727..f2b0971d2c65 100644 --- a/drivers/rtc/rtc-ab-b5ze-s3.c +++ b/drivers/rtc/rtc-ab-b5ze-s3.c @@ -817,8 +817,7 @@ static const struct regmap_config abb5zes3_rtc_regmap_config = { .val_bits = 8, }; -static int abb5zes3_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int abb5zes3_probe(struct i2c_client *client) { struct abb5zes3_rtc_data *data = NULL; struct device *dev = &client->dev; @@ -945,7 +944,7 @@ static struct i2c_driver abb5zes3_driver = { .pm = &abb5zes3_rtc_pm_ops, .of_match_table = of_match_ptr(abb5zes3_dt_match), }, - .probe = abb5zes3_probe, + .probe_new = abb5zes3_probe, .id_table = abb5zes3_id, }; module_i2c_driver(abb5zes3_driver); diff --git a/drivers/rtc/rtc-ab-eoz9.c b/drivers/rtc/rtc-ab-eoz9.c index e188ab517f1e..2f8deb8c4cd3 100644 --- a/drivers/rtc/rtc-ab-eoz9.c +++ b/drivers/rtc/rtc-ab-eoz9.c @@ -495,8 +495,7 @@ static void abeoz9_hwmon_register(struct device *dev, #endif -static int abeoz9_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int abeoz9_probe(struct i2c_client *client) { struct abeoz9_rtc_data *data = NULL; struct device *dev = &client->dev; @@ -580,7 +579,7 @@ static struct i2c_driver abeoz9_driver = { .name = "rtc-ab-eoz9", .of_match_table = of_match_ptr(abeoz9_dt_match), }, - .probe = abeoz9_probe, + .probe_new = abeoz9_probe, .id_table = abeoz9_id, }; diff --git a/drivers/rtc/rtc-bq32k.c b/drivers/rtc/rtc-bq32k.c index 2235c968842d..e0bbb11d912e 100644 --- a/drivers/rtc/rtc-bq32k.c +++ b/drivers/rtc/rtc-bq32k.c @@ -249,8 +249,7 @@ static void bq32k_sysfs_unregister(struct device *dev) device_remove_file(dev, &dev_attr_trickle_charge_bypass); } -static int bq32k_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int bq32k_probe(struct i2c_client *client) { struct device *dev = &client->dev; struct rtc_device *rtc; @@ -322,7 +321,7 @@ static struct i2c_driver bq32k_driver = { .name = "bq32k", .of_match_table = of_match_ptr(bq32k_of_match), }, - .probe = bq32k_probe, + .probe_new = bq32k_probe, .remove = bq32k_remove, .id_table = bq32k_id, }; diff --git a/drivers/rtc/rtc-ds1374.c b/drivers/rtc/rtc-ds1374.c index 8db5a631bca8..b19de5100b1a 100644 --- a/drivers/rtc/rtc-ds1374.c +++ b/drivers/rtc/rtc-ds1374.c @@ -467,8 +467,7 @@ static const struct watchdog_ops ds1374_wdt_ops = { * ***************************************************************************** */ -static int ds1374_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int ds1374_probe(struct i2c_client *client) { struct ds1374 *ds1374; int ret; @@ -575,7 +574,7 @@ static struct i2c_driver ds1374_driver = { .of_match_table = of_match_ptr(ds1374_of_match), .pm = &ds1374_pm, }, - .probe = ds1374_probe, + .probe_new = ds1374_probe, .remove = ds1374_remove, .id_table = ds1374_id, }; diff --git a/drivers/rtc/rtc-ds1672.c b/drivers/rtc/rtc-ds1672.c index 4cd8efbef6cf..a3bb2cd9c881 100644 --- a/drivers/rtc/rtc-ds1672.c +++ b/drivers/rtc/rtc-ds1672.c @@ -106,8 +106,7 @@ static const struct rtc_class_ops ds1672_rtc_ops = { .set_time = ds1672_set_time, }; -static int ds1672_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int ds1672_probe(struct i2c_client *client) { int err = 0; struct rtc_device *rtc; @@ -150,7 +149,7 @@ static struct i2c_driver ds1672_driver = { .name = "rtc-ds1672", .of_match_table = of_match_ptr(ds1672_of_match), }, - .probe = &ds1672_probe, + .probe_new = ds1672_probe, .id_table = ds1672_id, }; diff --git a/drivers/rtc/rtc-ds3232.c b/drivers/rtc/rtc-ds3232.c index 168bc27f1f5a..dd31a60c1fc6 100644 --- a/drivers/rtc/rtc-ds3232.c +++ b/drivers/rtc/rtc-ds3232.c @@ -566,8 +566,7 @@ static const struct dev_pm_ops ds3232_pm_ops = { #if IS_ENABLED(CONFIG_I2C) -static int ds3232_i2c_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int ds3232_i2c_probe(struct i2c_client *client) { struct regmap *regmap; static const struct regmap_config config = { @@ -604,7 +603,7 @@ static struct i2c_driver ds3232_driver = { .of_match_table = of_match_ptr(ds3232_of_match), .pm = &ds3232_pm_ops, }, - .probe = ds3232_i2c_probe, + .probe_new = ds3232_i2c_probe, .id_table = ds3232_id, }; diff --git a/drivers/rtc/rtc-em3027.c b/drivers/rtc/rtc-em3027.c index 9f176bce48ba..53f9f9391a5f 100644 --- a/drivers/rtc/rtc-em3027.c +++ b/drivers/rtc/rtc-em3027.c @@ -111,8 +111,7 @@ static const struct rtc_class_ops em3027_rtc_ops = { .set_time = em3027_set_time, }; -static int em3027_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int em3027_probe(struct i2c_client *client) { struct rtc_device *rtc; @@ -148,7 +147,7 @@ static struct i2c_driver em3027_driver = { .name = "rtc-em3027", .of_match_table = of_match_ptr(em3027_of_match), }, - .probe = &em3027_probe, + .probe_new = em3027_probe, .id_table = em3027_id, }; diff --git a/drivers/rtc/rtc-fm3130.c b/drivers/rtc/rtc-fm3130.c index 677ec2da13d8..f59bb81f23c0 100644 --- a/drivers/rtc/rtc-fm3130.c +++ b/drivers/rtc/rtc-fm3130.c @@ -340,8 +340,7 @@ static const struct rtc_class_ops fm3130_rtc_ops = { static struct i2c_driver fm3130_driver; -static int fm3130_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int fm3130_probe(struct i2c_client *client) { struct fm3130 *fm3130; int err = -ENODEV; @@ -518,7 +517,7 @@ static struct i2c_driver fm3130_driver = { .driver = { .name = "rtc-fm3130", }, - .probe = fm3130_probe, + .probe_new = fm3130_probe, .id_table = fm3130_id, }; diff --git a/drivers/rtc/rtc-hym8563.c b/drivers/rtc/rtc-hym8563.c index 90e602e99d03..cc710d682121 100644 --- a/drivers/rtc/rtc-hym8563.c +++ b/drivers/rtc/rtc-hym8563.c @@ -495,8 +495,7 @@ static int hym8563_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(hym8563_pm_ops, hym8563_suspend, hym8563_resume); -static int hym8563_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int hym8563_probe(struct i2c_client *client) { struct hym8563 *hym8563; int ret; @@ -572,7 +571,7 @@ static struct i2c_driver hym8563_driver = { .pm = &hym8563_pm_ops, .of_match_table = hym8563_dt_idtable, }, - .probe = hym8563_probe, + .probe_new = hym8563_probe, .id_table = hym8563_id, }; diff --git a/drivers/rtc/rtc-isl12022.c b/drivers/rtc/rtc-isl12022.c index 961bd5d1d109..79461ded1a48 100644 --- a/drivers/rtc/rtc-isl12022.c +++ b/drivers/rtc/rtc-isl12022.c @@ -232,8 +232,7 @@ static const struct rtc_class_ops isl12022_rtc_ops = { .set_time = isl12022_rtc_set_time, }; -static int isl12022_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int isl12022_probe(struct i2c_client *client) { struct isl12022 *isl12022; @@ -275,7 +274,7 @@ static struct i2c_driver isl12022_driver = { .of_match_table = of_match_ptr(isl12022_dt_match), #endif }, - .probe = isl12022_probe, + .probe_new = isl12022_probe, .id_table = isl12022_id, }; diff --git a/drivers/rtc/rtc-max6900.c b/drivers/rtc/rtc-max6900.c index 4beadfa41644..0a33851cc51f 100644 --- a/drivers/rtc/rtc-max6900.c +++ b/drivers/rtc/rtc-max6900.c @@ -197,8 +197,7 @@ static const struct rtc_class_ops max6900_rtc_ops = { .set_time = max6900_rtc_set_time, }; -static int -max6900_probe(struct i2c_client *client, const struct i2c_device_id *id) +static int max6900_probe(struct i2c_client *client) { struct rtc_device *rtc; @@ -225,7 +224,7 @@ static struct i2c_driver max6900_driver = { .driver = { .name = "rtc-max6900", }, - .probe = max6900_probe, + .probe_new = max6900_probe, .id_table = max6900_id, }; diff --git a/drivers/rtc/rtc-pcf8523.c b/drivers/rtc/rtc-pcf8523.c index b1b1943de844..6174b3fd4b98 100644 --- a/drivers/rtc/rtc-pcf8523.c +++ b/drivers/rtc/rtc-pcf8523.c @@ -390,8 +390,7 @@ static const struct regmap_config regmap_config = { .max_register = 0x13, }; -static int pcf8523_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int pcf8523_probe(struct i2c_client *client) { struct pcf8523 *pcf8523; struct rtc_device *rtc; @@ -485,7 +484,7 @@ static struct i2c_driver pcf8523_driver = { .name = "rtc-pcf8523", .of_match_table = pcf8523_of_match, }, - .probe = pcf8523_probe, + .probe_new = pcf8523_probe, .id_table = pcf8523_id, }; module_i2c_driver(pcf8523_driver); diff --git a/drivers/rtc/rtc-pcf85363.c b/drivers/rtc/rtc-pcf85363.c index bb3e9ba75f6c..c05b722f0060 100644 --- a/drivers/rtc/rtc-pcf85363.c +++ b/drivers/rtc/rtc-pcf85363.c @@ -350,8 +350,7 @@ static const struct pcf85x63_config pcf_85363_config = { .num_nvram = 2 }; -static int pcf85363_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int pcf85363_probe(struct i2c_client *client) { struct pcf85363 *pcf85363; const struct pcf85x63_config *config = &pcf_85363_config; @@ -436,7 +435,7 @@ static struct i2c_driver pcf85363_driver = { .name = "pcf85363", .of_match_table = of_match_ptr(dev_ids), }, - .probe = pcf85363_probe, + .probe_new = pcf85363_probe, }; module_i2c_driver(pcf85363_driver); diff --git a/drivers/rtc/rtc-pcf8563.c b/drivers/rtc/rtc-pcf8563.c index 9d06813e2e6d..11fa9788558b 100644 --- a/drivers/rtc/rtc-pcf8563.c +++ b/drivers/rtc/rtc-pcf8563.c @@ -509,8 +509,7 @@ static const struct rtc_class_ops pcf8563_rtc_ops = { .alarm_irq_enable = pcf8563_irq_enable, }; -static int pcf8563_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int pcf8563_probe(struct i2c_client *client) { struct pcf8563 *pcf8563; int err; @@ -606,7 +605,7 @@ static struct i2c_driver pcf8563_driver = { .name = "rtc-pcf8563", .of_match_table = of_match_ptr(pcf8563_of_match), }, - .probe = pcf8563_probe, + .probe_new = pcf8563_probe, .id_table = pcf8563_id, }; diff --git a/drivers/rtc/rtc-pcf8583.c b/drivers/rtc/rtc-pcf8583.c index c80ca20e5d8d..87074d178274 100644 --- a/drivers/rtc/rtc-pcf8583.c +++ b/drivers/rtc/rtc-pcf8583.c @@ -275,8 +275,7 @@ static const struct rtc_class_ops pcf8583_rtc_ops = { .set_time = pcf8583_rtc_set_time, }; -static int pcf8583_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int pcf8583_probe(struct i2c_client *client) { struct pcf8583 *pcf8583; @@ -307,7 +306,7 @@ static struct i2c_driver pcf8583_driver = { .driver = { .name = "pcf8583", }, - .probe = pcf8583_probe, + .probe_new = pcf8583_probe, .id_table = pcf8583_id, }; diff --git a/drivers/rtc/rtc-rv3029c2.c b/drivers/rtc/rtc-rv3029c2.c index 8cb84c9595fc..eb483a30bd92 100644 --- a/drivers/rtc/rtc-rv3029c2.c +++ b/drivers/rtc/rtc-rv3029c2.c @@ -784,8 +784,7 @@ static const struct regmap_config config = { #if IS_ENABLED(CONFIG_I2C) -static int rv3029_i2c_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int rv3029_i2c_probe(struct i2c_client *client) { struct regmap *regmap; if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_I2C_BLOCK | @@ -819,7 +818,7 @@ static struct i2c_driver rv3029_driver = { .name = "rv3029", .of_match_table = of_match_ptr(rv3029_of_match), }, - .probe = rv3029_i2c_probe, + .probe_new = rv3029_i2c_probe, .id_table = rv3029_id, }; diff --git a/drivers/rtc/rtc-rx6110.c b/drivers/rtc/rtc-rx6110.c index 758fd6e11a15..cc634558b928 100644 --- a/drivers/rtc/rtc-rx6110.c +++ b/drivers/rtc/rtc-rx6110.c @@ -419,8 +419,7 @@ static struct regmap_config regmap_i2c_config = { .read_flag_mask = 0x80, }; -static int rx6110_i2c_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int rx6110_i2c_probe(struct i2c_client *client) { struct i2c_adapter *adapter = client->adapter; struct rx6110_data *rx6110; @@ -464,7 +463,7 @@ static struct i2c_driver rx6110_i2c_driver = { .name = RX6110_DRIVER_NAME, .acpi_match_table = rx6110_i2c_acpi_match, }, - .probe = rx6110_i2c_probe, + .probe_new = rx6110_i2c_probe, .id_table = rx6110_i2c_id, }; diff --git a/drivers/rtc/rtc-rx8581.c b/drivers/rtc/rtc-rx8581.c index aed4898a0ff4..14edb7534c97 100644 --- a/drivers/rtc/rtc-rx8581.c +++ b/drivers/rtc/rtc-rx8581.c @@ -248,8 +248,7 @@ static const struct rx85x1_config rx8571_config = { .num_nvram = 2 }; -static int rx8581_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int rx8581_probe(struct i2c_client *client) { struct rx8581 *rx8581; const struct rx85x1_config *config = &rx8581_config; @@ -326,7 +325,7 @@ static struct i2c_driver rx8581_driver = { .name = "rtc-rx8581", .of_match_table = of_match_ptr(rx8581_of_match), }, - .probe = rx8581_probe, + .probe_new = rx8581_probe, .id_table = rx8581_id, }; diff --git a/drivers/rtc/rtc-s35390a.c b/drivers/rtc/rtc-s35390a.c index 26278c770731..81d97b1d3159 100644 --- a/drivers/rtc/rtc-s35390a.c +++ b/drivers/rtc/rtc-s35390a.c @@ -420,8 +420,7 @@ static const struct rtc_class_ops s35390a_rtc_ops = { .ioctl = s35390a_rtc_ioctl, }; -static int s35390a_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int s35390a_probe(struct i2c_client *client) { int err, err_read; unsigned int i; @@ -502,7 +501,7 @@ static struct i2c_driver s35390a_driver = { .name = "rtc-s35390a", .of_match_table = of_match_ptr(s35390a_of_match), }, - .probe = s35390a_probe, + .probe_new = s35390a_probe, .id_table = s35390a_id, }; diff --git a/drivers/rtc/rtc-sd3078.c b/drivers/rtc/rtc-sd3078.c index 24e8528e23ec..e2f90d768ca8 100644 --- a/drivers/rtc/rtc-sd3078.c +++ b/drivers/rtc/rtc-sd3078.c @@ -163,8 +163,7 @@ static const struct regmap_config regmap_config = { .max_register = 0x11, }; -static int sd3078_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int sd3078_probe(struct i2c_client *client) { int ret; struct sd3078 *sd3078; @@ -218,7 +217,7 @@ static struct i2c_driver sd3078_driver = { .name = "sd3078", .of_match_table = of_match_ptr(rtc_dt_match), }, - .probe = sd3078_probe, + .probe_new = sd3078_probe, .id_table = sd3078_id, }; diff --git a/drivers/rtc/rtc-x1205.c b/drivers/rtc/rtc-x1205.c index d1d5a44d9122..ba0d22a5b421 100644 --- a/drivers/rtc/rtc-x1205.c +++ b/drivers/rtc/rtc-x1205.c @@ -614,8 +614,7 @@ static void x1205_sysfs_unregister(struct device *dev) } -static int x1205_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int x1205_probe(struct i2c_client *client) { int err = 0; unsigned char sr; @@ -681,7 +680,7 @@ static struct i2c_driver x1205_driver = { .name = "rtc-x1205", .of_match_table = x1205_dt_ids, }, - .probe = x1205_probe, + .probe_new = x1205_probe, .remove = x1205_remove, .id_table = x1205_id, }; -- cgit v1.2.3 From 0b31d703598dc1993867597bbd45e87d824fc427 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Wed, 1 Jun 2022 13:33:20 +0100 Subject: rtc: Add driver for Microchip PolarFire SoC Add support for the built-in RTC on Microchip PolarFire SoC Co-Developed-by: Daire McNamara Signed-off-by: Daire McNamara Signed-off-by: Conor Dooley Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220601123320.2861043-2-conor.dooley@microchip.com --- drivers/rtc/Kconfig | 10 ++ drivers/rtc/Makefile | 1 + drivers/rtc/rtc-mpfs.c | 326 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 337 insertions(+) create mode 100644 drivers/rtc/rtc-mpfs.c diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index a00f901b5c1d..68859970b4d5 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1973,4 +1973,14 @@ config RTC_DRV_MSC313 This driver can also be built as a module, if so, the module will be called "rtc-msc313". +config RTC_DRV_POLARFIRE_SOC + tristate "Microchip PolarFire SoC built-in RTC" + depends on SOC_MICROCHIP_POLARFIRE + help + If you say yes here you will get support for the + built-in RTC on Polarfire SoC. + + This driver can also be built as a module, if so, the module + will be called "rtc-mpfs". + endif # RTC_CLASS diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index fb04467b652d..35386b1c1e56 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -130,6 +130,7 @@ obj-$(CONFIG_RTC_DRV_PIC32) += rtc-pic32.o obj-$(CONFIG_RTC_DRV_PL030) += rtc-pl030.o obj-$(CONFIG_RTC_DRV_PL031) += rtc-pl031.o obj-$(CONFIG_RTC_DRV_PM8XXX) += rtc-pm8xxx.o +obj-$(CONFIG_RTC_DRV_POLARFIRE_SOC) += rtc-mpfs.o obj-$(CONFIG_RTC_DRV_PS3) += rtc-ps3.o obj-$(CONFIG_RTC_DRV_PXA) += rtc-pxa.o obj-$(CONFIG_RTC_DRV_R7301) += rtc-r7301.o diff --git a/drivers/rtc/rtc-mpfs.c b/drivers/rtc/rtc-mpfs.c new file mode 100644 index 000000000000..db9c638e50f7 --- /dev/null +++ b/drivers/rtc/rtc-mpfs.c @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Microchip MPFS RTC driver + * + * Copyright (c) 2021-2022 Microchip Corporation. All rights reserved. + * + * Author: Daire McNamara + * & Conor Dooley + */ +#include "linux/bits.h" +#include "linux/iopoll.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CONTROL_REG 0x00 +#define MODE_REG 0x04 +#define PRESCALER_REG 0x08 +#define ALARM_LOWER_REG 0x0c +#define ALARM_UPPER_REG 0x10 +#define COMPARE_LOWER_REG 0x14 +#define COMPARE_UPPER_REG 0x18 +#define DATETIME_LOWER_REG 0x20 +#define DATETIME_UPPER_REG 0x24 + +#define CONTROL_RUNNING_BIT BIT(0) +#define CONTROL_START_BIT BIT(0) +#define CONTROL_STOP_BIT BIT(1) +#define CONTROL_ALARM_ON_BIT BIT(2) +#define CONTROL_ALARM_OFF_BIT BIT(3) +#define CONTROL_RESET_BIT BIT(4) +#define CONTROL_UPLOAD_BIT BIT(5) +#define CONTROL_DOWNLOAD_BIT BIT(6) +#define CONTROL_MATCH_BIT BIT(7) +#define CONTROL_WAKEUP_CLR_BIT BIT(8) +#define CONTROL_WAKEUP_SET_BIT BIT(9) +#define CONTROL_UPDATED_BIT BIT(10) + +#define MODE_CLOCK_CALENDAR BIT(0) +#define MODE_WAKE_EN BIT(1) +#define MODE_WAKE_RESET BIT(2) +#define MODE_WAKE_CONTINUE BIT(3) + +#define MAX_PRESCALER_COUNT GENMASK(25, 0) +#define DATETIME_UPPER_MASK GENMASK(29, 0) +#define ALARM_UPPER_MASK GENMASK(10, 0) + +#define UPLOAD_TIMEOUT_US 50 + +struct mpfs_rtc_dev { + struct rtc_device *rtc; + void __iomem *base; +}; + +static void mpfs_rtc_start(struct mpfs_rtc_dev *rtcdev) +{ + u32 ctrl; + + ctrl = readl(rtcdev->base + CONTROL_REG); + ctrl &= ~CONTROL_STOP_BIT; + ctrl |= CONTROL_START_BIT; + writel(ctrl, rtcdev->base + CONTROL_REG); +} + +static void mpfs_rtc_clear_irq(struct mpfs_rtc_dev *rtcdev) +{ + u32 val = readl(rtcdev->base + CONTROL_REG); + + val &= ~(CONTROL_ALARM_ON_BIT | CONTROL_STOP_BIT); + val |= CONTROL_ALARM_OFF_BIT; + writel(val, rtcdev->base + CONTROL_REG); + /* + * Ensure that the posted write to the CONTROL_REG register completed before + * returning from this function. Not doing this may result in the interrupt + * only being cleared some time after this function returns. + */ + (void)readl(rtcdev->base + CONTROL_REG); +} + +static int mpfs_rtc_readtime(struct device *dev, struct rtc_time *tm) +{ + struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev); + u64 time; + + time = readl(rtcdev->base + DATETIME_LOWER_REG); + time |= ((u64)readl(rtcdev->base + DATETIME_UPPER_REG) & DATETIME_UPPER_MASK) << 32; + rtc_time64_to_tm(time, tm); + + return 0; +} + +static int mpfs_rtc_settime(struct device *dev, struct rtc_time *tm) +{ + struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev); + u32 ctrl, prog; + u64 time; + int ret; + + time = rtc_tm_to_time64(tm); + + writel((u32)time, rtcdev->base + DATETIME_LOWER_REG); + writel((u32)(time >> 32) & DATETIME_UPPER_MASK, rtcdev->base + DATETIME_UPPER_REG); + + ctrl = readl(rtcdev->base + CONTROL_REG); + ctrl &= ~CONTROL_STOP_BIT; + ctrl |= CONTROL_UPLOAD_BIT; + writel(ctrl, rtcdev->base + CONTROL_REG); + + ret = read_poll_timeout(readl, prog, prog & CONTROL_UPLOAD_BIT, 0, UPLOAD_TIMEOUT_US, + false, rtcdev->base + CONTROL_REG); + if (ret) { + dev_err(dev, "timed out uploading time to rtc"); + return ret; + } + mpfs_rtc_start(rtcdev); + + return 0; +} + +static int mpfs_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev); + u32 mode = readl(rtcdev->base + MODE_REG); + u64 time; + + alrm->enabled = mode & MODE_WAKE_EN; + + time = (u64)readl(rtcdev->base + ALARM_LOWER_REG) << 32; + time |= (readl(rtcdev->base + ALARM_UPPER_REG) & ALARM_UPPER_MASK); + rtc_time64_to_tm(time, &alrm->time); + + return 0; +} + +static int mpfs_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev); + u32 mode, ctrl; + u64 time; + + /* Disable the alarm before updating */ + ctrl = readl(rtcdev->base + CONTROL_REG); + ctrl |= CONTROL_ALARM_OFF_BIT; + writel(ctrl, rtcdev->base + CONTROL_REG); + + time = rtc_tm_to_time64(&alrm->time); + + writel((u32)time, rtcdev->base + ALARM_LOWER_REG); + writel((u32)(time >> 32) & ALARM_UPPER_MASK, rtcdev->base + ALARM_UPPER_REG); + + /* Bypass compare register in alarm mode */ + writel(GENMASK(31, 0), rtcdev->base + COMPARE_LOWER_REG); + writel(GENMASK(29, 0), rtcdev->base + COMPARE_UPPER_REG); + + /* Configure the RTC to enable the alarm. */ + ctrl = readl(rtcdev->base + CONTROL_REG); + mode = readl(rtcdev->base + MODE_REG); + if (alrm->enabled) { + mode = MODE_WAKE_EN | MODE_WAKE_CONTINUE; + /* Enable the alarm */ + ctrl &= ~CONTROL_ALARM_OFF_BIT; + ctrl |= CONTROL_ALARM_ON_BIT; + } + ctrl &= ~CONTROL_STOP_BIT; + ctrl |= CONTROL_START_BIT; + writel(ctrl, rtcdev->base + CONTROL_REG); + writel(mode, rtcdev->base + MODE_REG); + + return 0; +} + +static int mpfs_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) +{ + struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev); + u32 ctrl; + + ctrl = readl(rtcdev->base + CONTROL_REG); + ctrl &= ~(CONTROL_ALARM_ON_BIT | CONTROL_ALARM_OFF_BIT | CONTROL_STOP_BIT); + + if (enabled) + ctrl |= CONTROL_ALARM_ON_BIT; + else + ctrl |= CONTROL_ALARM_OFF_BIT; + + writel(ctrl, rtcdev->base + CONTROL_REG); + + return 0; +} + +static inline struct clk *mpfs_rtc_init_clk(struct device *dev) +{ + struct clk *clk; + int ret; + + clk = devm_clk_get(dev, "rtc"); + if (IS_ERR(clk)) + return clk; + + ret = clk_prepare_enable(clk); + if (ret) + return ERR_PTR(ret); + + devm_add_action_or_reset(dev, (void (*) (void *))clk_disable_unprepare, clk); + return clk; +} + +static irqreturn_t mpfs_rtc_wakeup_irq_handler(int irq, void *dev) +{ + struct mpfs_rtc_dev *rtcdev = dev; + unsigned long pending; + + pending = readl(rtcdev->base + CONTROL_REG); + pending &= CONTROL_ALARM_ON_BIT; + mpfs_rtc_clear_irq(rtcdev); + + rtc_update_irq(rtcdev->rtc, 1, RTC_IRQF | RTC_AF); + + return IRQ_HANDLED; +} + +static const struct rtc_class_ops mpfs_rtc_ops = { + .read_time = mpfs_rtc_readtime, + .set_time = mpfs_rtc_settime, + .read_alarm = mpfs_rtc_readalarm, + .set_alarm = mpfs_rtc_setalarm, + .alarm_irq_enable = mpfs_rtc_alarm_irq_enable, +}; + +static int mpfs_rtc_probe(struct platform_device *pdev) +{ + struct mpfs_rtc_dev *rtcdev; + struct clk *clk; + u32 prescaler; + int wakeup_irq, ret; + + rtcdev = devm_kzalloc(&pdev->dev, sizeof(struct mpfs_rtc_dev), GFP_KERNEL); + if (!rtcdev) + return -ENOMEM; + + platform_set_drvdata(pdev, rtcdev); + + rtcdev->rtc = devm_rtc_allocate_device(&pdev->dev); + if (IS_ERR(rtcdev->rtc)) + return PTR_ERR(rtcdev->rtc); + + rtcdev->rtc->ops = &mpfs_rtc_ops; + + /* range is capped by alarm max, lower reg is 31:0 & upper is 10:0 */ + rtcdev->rtc->range_max = GENMASK_ULL(42, 0); + + clk = mpfs_rtc_init_clk(&pdev->dev); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + rtcdev->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(rtcdev->base)) { + dev_dbg(&pdev->dev, "invalid ioremap resources\n"); + return PTR_ERR(rtcdev->base); + } + + wakeup_irq = platform_get_irq(pdev, 0); + if (wakeup_irq <= 0) { + dev_dbg(&pdev->dev, "could not get wakeup irq\n"); + return wakeup_irq; + } + ret = devm_request_irq(&pdev->dev, wakeup_irq, mpfs_rtc_wakeup_irq_handler, 0, + dev_name(&pdev->dev), rtcdev); + if (ret) { + dev_dbg(&pdev->dev, "could not request wakeup irq\n"); + return ret; + } + + /* prescaler hardware adds 1 to reg value */ + prescaler = clk_get_rate(devm_clk_get(&pdev->dev, "rtcref")) - 1; + + if (prescaler > MAX_PRESCALER_COUNT) { + dev_dbg(&pdev->dev, "invalid prescaler %d\n", prescaler); + return -EINVAL; + } + + writel(prescaler, rtcdev->base + PRESCALER_REG); + dev_info(&pdev->dev, "prescaler set to: 0x%X \r\n", prescaler); + + device_init_wakeup(&pdev->dev, true); + ret = dev_pm_set_wake_irq(&pdev->dev, wakeup_irq); + if (ret) + dev_err(&pdev->dev, "failed to enable irq wake\n"); + + return devm_rtc_register_device(rtcdev->rtc); +} + +static int mpfs_rtc_remove(struct platform_device *pdev) +{ + dev_pm_clear_wake_irq(&pdev->dev); + + return 0; +} + +static const struct of_device_id mpfs_rtc_of_match[] = { + { .compatible = "microchip,mpfs-rtc" }, + { } +}; + +MODULE_DEVICE_TABLE(of, mpfs_rtc_of_match); + +static struct platform_driver mpfs_rtc_driver = { + .probe = mpfs_rtc_probe, + .remove = mpfs_rtc_remove, + .driver = { + .name = "mpfs_rtc", + .of_match_table = mpfs_rtc_of_match, + }, +}; + +module_platform_driver(mpfs_rtc_driver); + +MODULE_DESCRIPTION("Real time clock for Microchip Polarfire SoC"); +MODULE_AUTHOR("Daire McNamara "); +MODULE_AUTHOR("Conor Dooley "); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 1bdb08c180e8556d3d4cef844ea0f0bae79bb95d Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Wed, 1 Jun 2022 13:33:21 +0100 Subject: MAINTAINERS: add PolarFire SoC's RTC Add an entry for PolarFire SoC's RTC drver to the existing support for PolarFire SoC. Signed-off-by: Conor Dooley Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220601123320.2861043-3-conor.dooley@microchip.com --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index a6d3bd9d2a8d..69a960561e37 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17142,6 +17142,7 @@ L: linux-riscv@lists.infradead.org S: Supported F: arch/riscv/boot/dts/microchip/ F: drivers/mailbox/mailbox-mpfs.c +F: drivers/rtc/rtc-mpfs.c F: drivers/soc/microchip/ F: include/soc/microchip/mpfs.h -- cgit v1.2.3 From fa1f8e6ac455b20955f107023916eef946674cb8 Mon Sep 17 00:00:00 2001 From: Satya Priya Date: Wed, 22 Jun 2022 10:40:39 +0530 Subject: dt-bindings: rtc: qcom-pm8xxx-rtc: Update the maintainers section Update the maintainers section with latest mail ID. Signed-off-by: Satya Priya Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/1655874639-11273-3-git-send-email-quic_c_skakit@quicinc.com --- Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml b/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml index 6fa7d9fc2dc7..23ab5bb4f395 100644 --- a/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm PM8xxx PMIC RTC device maintainers: - - Satya Priya + - Satya Priya properties: compatible: -- cgit v1.2.3 From 5e665cf1f0c52163de5517bfb9258390e63772b2 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 23 Jun 2022 12:08:07 -0500 Subject: dt-bindings: rtc: Add TI K3 RTC description This adds the documentation for the devicetree bindings of the Texas Instruments RTC modules on K3 family of SoCs such as AM62x SoCs or newer. Signed-off-by: Nishanth Menon Reviewed-by: Krzysztof Kozlowski Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220623170808.20998-2-nm@ti.com --- .../devicetree/bindings/rtc/ti,k3-rtc.yaml | 62 ++++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/ti,k3-rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/ti,k3-rtc.yaml b/Documentation/devicetree/bindings/rtc/ti,k3-rtc.yaml new file mode 100644 index 000000000000..d995ef04a6eb --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/ti,k3-rtc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/ti,k3-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments K3 Real Time Clock + +maintainers: + - Nishanth Menon + +description: | + This RTC appears in the AM62x family of SoCs. + +allOf: + - $ref: "rtc.yaml#" + +properties: + compatible: + enum: + - ti,am62-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: VBUS Interface clock + - description: 32k Clock source (external or internal). + + clock-names: + items: + - const: vbus + - const: osc32k + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + rtc@2b1f0000 { + compatible = "ti,am62-rtc"; + reg = <0x2b1f0000 0x100>; + interrupts = ; + power-domains = <&bar 0>; + clocks = <&foo 0>, <&foo 1>; + clock-names = "vbus", "osc32k"; + wakeup-source; + }; -- cgit v1.2.3 From b09d633575e54e98e1362bd5c36cd9571cb71d8a Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 23 Jun 2022 12:08:08 -0500 Subject: rtc: Introduce ti-k3-rtc Introduce support for Texas Instruments Real Time Clock controller on newer K3 family of SoCs such as AM62x. The hardware module that is being supported is the "digital only" version which doesn't have capability of external wakeup sources and external power backup. However, for many practical applications, this should suffice as RTC is operational across low power sequences. The hardware block by itself is split into two distinct domains internally to further reduce the power consumption with the actual counter block and comparators clocked off a 32k clock source (which based on SoC integration can be sourced by an external crystal) and an register interface block which is driven by the bus clock. While optimal from power perspective, it does create some complicated synchronizations and sequences that one must be wary of in the driver handling. Acked-by: Andrew Davis Signed-off-by: Nishanth Menon Tested-by: Georgi Vlaev Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220623170808.20998-3-nm@ti.com --- drivers/rtc/Kconfig | 11 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-ti-k3.c | 680 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 692 insertions(+) create mode 100644 drivers/rtc/rtc-ti-k3.c diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 68859970b4d5..443b6d925335 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1929,6 +1929,17 @@ config RTC_DRV_ASPEED This driver can also be built as a module, if so, the module will be called "rtc-aspeed". +config RTC_DRV_TI_K3 + tristate "TI K3 RTC" + depends on ARCH_K3 || COMPILE_TEST + select REGMAP_MMIO + help + If you say yes here you get support for the Texas Instruments's + Real Time Clock for K3 architecture. + + This driver can also be built as a module, if so, the module + will be called "rtc-ti-k3". + comment "HID Sensor RTC drivers" config RTC_DRV_HID_SENSOR_TIME diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 35386b1c1e56..f83cd5ea9b11 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -173,6 +173,7 @@ obj-$(CONFIG_RTC_DRV_SUNPLUS) += rtc-sunplus.o obj-$(CONFIG_RTC_DRV_SUNXI) += rtc-sunxi.o obj-$(CONFIG_RTC_DRV_TEGRA) += rtc-tegra.o obj-$(CONFIG_RTC_DRV_TEST) += rtc-test.o +obj-$(CONFIG_RTC_DRV_TI_K3) += rtc-ti-k3.o obj-$(CONFIG_RTC_DRV_TPS6586X) += rtc-tps6586x.o obj-$(CONFIG_RTC_DRV_TPS65910) += rtc-tps65910.o obj-$(CONFIG_RTC_DRV_TWL4030) += rtc-twl.o diff --git a/drivers/rtc/rtc-ti-k3.c b/drivers/rtc/rtc-ti-k3.c new file mode 100644 index 000000000000..7a0f181d3fef --- /dev/null +++ b/drivers/rtc/rtc-ti-k3.c @@ -0,0 +1,680 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Texas Instruments K3 RTC driver + * + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Registers */ +#define REG_K3RTC_S_CNT_LSW 0x08 +#define REG_K3RTC_S_CNT_MSW 0x0c +#define REG_K3RTC_COMP 0x10 +#define REG_K3RTC_ON_OFF_S_CNT_LSW 0x20 +#define REG_K3RTC_ON_OFF_S_CNT_MSW 0x24 +#define REG_K3RTC_SCRATCH0 0x30 +#define REG_K3RTC_SCRATCH7 0x4c +#define REG_K3RTC_GENERAL_CTL 0x50 +#define REG_K3RTC_IRQSTATUS_RAW_SYS 0x54 +#define REG_K3RTC_IRQSTATUS_SYS 0x58 +#define REG_K3RTC_IRQENABLE_SET_SYS 0x5c +#define REG_K3RTC_IRQENABLE_CLR_SYS 0x60 +#define REG_K3RTC_SYNCPEND 0x68 +#define REG_K3RTC_KICK0 0x70 +#define REG_K3RTC_KICK1 0x74 + +/* Freeze when lsw is read and unfreeze when msw is read */ +#define K3RTC_CNT_FMODE_S_CNT_VALUE (0x2 << 24) + +/* Magic values for lock/unlock */ +#define K3RTC_KICK0_UNLOCK_VALUE 0x83e70b13 +#define K3RTC_KICK1_UNLOCK_VALUE 0x95a4f1e0 + +/* Multiplier for ppb conversions */ +#define K3RTC_PPB_MULT (1000000000LL) +/* Min and max values supported with 'offset' interface (swapped sign) */ +#define K3RTC_MIN_OFFSET (-277761) +#define K3RTC_MAX_OFFSET (277778) + +/** + * struct ti_k3_rtc_soc_data - Private of compatible data for ti-k3-rtc + * @unlock_irq_erratum: Has erratum for unlock infinite IRQs (erratum i2327) + */ +struct ti_k3_rtc_soc_data { + const bool unlock_irq_erratum; +}; + +static const struct regmap_config ti_k3_rtc_regmap_config = { + .name = "peripheral-registers", + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = REG_K3RTC_KICK1, +}; + +enum ti_k3_rtc_fields { + K3RTC_KICK0, + K3RTC_KICK1, + K3RTC_S_CNT_LSW, + K3RTC_S_CNT_MSW, + K3RTC_O32K_OSC_DEP_EN, + K3RTC_UNLOCK, + K3RTC_CNT_FMODE, + K3RTC_PEND, + K3RTC_RELOAD_FROM_BBD, + K3RTC_COMP, + + K3RTC_ALM_S_CNT_LSW, + K3RTC_ALM_S_CNT_MSW, + K3RTC_IRQ_STATUS_RAW, + K3RTC_IRQ_STATUS, + K3RTC_IRQ_ENABLE_SET, + K3RTC_IRQ_ENABLE_CLR, + + K3RTC_IRQ_STATUS_ALT, + K3RTC_IRQ_ENABLE_CLR_ALT, + + K3_RTC_MAX_FIELDS +}; + +static const struct reg_field ti_rtc_reg_fields[] = { + [K3RTC_KICK0] = REG_FIELD(REG_K3RTC_KICK0, 0, 31), + [K3RTC_KICK1] = REG_FIELD(REG_K3RTC_KICK1, 0, 31), + [K3RTC_S_CNT_LSW] = REG_FIELD(REG_K3RTC_S_CNT_LSW, 0, 31), + [K3RTC_S_CNT_MSW] = REG_FIELD(REG_K3RTC_S_CNT_MSW, 0, 15), + [K3RTC_O32K_OSC_DEP_EN] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 21, 21), + [K3RTC_UNLOCK] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 23, 23), + [K3RTC_CNT_FMODE] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 24, 25), + [K3RTC_PEND] = REG_FIELD(REG_K3RTC_SYNCPEND, 0, 1), + [K3RTC_RELOAD_FROM_BBD] = REG_FIELD(REG_K3RTC_SYNCPEND, 31, 31), + [K3RTC_COMP] = REG_FIELD(REG_K3RTC_COMP, 0, 31), + + /* We use on to off as alarm trigger */ + [K3RTC_ALM_S_CNT_LSW] = REG_FIELD(REG_K3RTC_ON_OFF_S_CNT_LSW, 0, 31), + [K3RTC_ALM_S_CNT_MSW] = REG_FIELD(REG_K3RTC_ON_OFF_S_CNT_MSW, 0, 15), + [K3RTC_IRQ_STATUS_RAW] = REG_FIELD(REG_K3RTC_IRQSTATUS_RAW_SYS, 0, 0), + [K3RTC_IRQ_STATUS] = REG_FIELD(REG_K3RTC_IRQSTATUS_SYS, 0, 0), + [K3RTC_IRQ_ENABLE_SET] = REG_FIELD(REG_K3RTC_IRQENABLE_SET_SYS, 0, 0), + [K3RTC_IRQ_ENABLE_CLR] = REG_FIELD(REG_K3RTC_IRQENABLE_CLR_SYS, 0, 0), + /* Off to on is alternate */ + [K3RTC_IRQ_STATUS_ALT] = REG_FIELD(REG_K3RTC_IRQSTATUS_SYS, 1, 1), + [K3RTC_IRQ_ENABLE_CLR_ALT] = REG_FIELD(REG_K3RTC_IRQENABLE_CLR_SYS, 1, 1), +}; + +/** + * struct ti_k3_rtc - Private data for ti-k3-rtc + * @irq: IRQ + * @sync_timeout_us: data sync timeout period in uSec + * @rate_32k: 32k clock rate in Hz + * @rtc_dev: rtc device + * @regmap: rtc mmio regmap + * @r_fields: rtc register fields + * @soc: SoC compatible match data + */ +struct ti_k3_rtc { + unsigned int irq; + u32 sync_timeout_us; + unsigned long rate_32k; + struct rtc_device *rtc_dev; + struct regmap *regmap; + struct regmap_field *r_fields[K3_RTC_MAX_FIELDS]; + const struct ti_k3_rtc_soc_data *soc; +}; + +static int k3rtc_field_read(struct ti_k3_rtc *priv, enum ti_k3_rtc_fields f) +{ + int ret; + int val; + + ret = regmap_field_read(priv->r_fields[f], &val); + /* + * We shouldn't be seeing regmap fail on us for mmio reads + * This is possible if clock context fails, but that isn't the case for us + */ + if (WARN_ON_ONCE(ret)) + return ret; + return val; +} + +static void k3rtc_field_write(struct ti_k3_rtc *priv, enum ti_k3_rtc_fields f, u32 val) +{ + regmap_field_write(priv->r_fields[f], val); +} + +/** + * k3rtc_fence - Ensure a register sync took place between the two domains + * @priv: pointer to priv data + * + * Return: 0 if the sync took place, else returns -ETIMEDOUT + */ +static int k3rtc_fence(struct ti_k3_rtc *priv) +{ + int ret; + + ret = regmap_field_read_poll_timeout(priv->r_fields[K3RTC_PEND], ret, + !ret, 2, priv->sync_timeout_us); + + return ret; +} + +static inline int k3rtc_check_unlocked(struct ti_k3_rtc *priv) +{ + int ret; + + ret = k3rtc_field_read(priv, K3RTC_UNLOCK); + if (ret < 0) + return ret; + + return (ret) ? 0 : 1; +} + +static int k3rtc_unlock_rtc(struct ti_k3_rtc *priv) +{ + int ret; + + ret = k3rtc_check_unlocked(priv); + if (!ret) + return ret; + + k3rtc_field_write(priv, K3RTC_KICK0, K3RTC_KICK0_UNLOCK_VALUE); + k3rtc_field_write(priv, K3RTC_KICK1, K3RTC_KICK1_UNLOCK_VALUE); + + /* Skip fence since we are going to check the unlock bit as fence */ + ret = regmap_field_read_poll_timeout(priv->r_fields[K3RTC_UNLOCK], ret, + !ret, 2, priv->sync_timeout_us); + + return ret; +} + +static int k3rtc_configure(struct device *dev) +{ + int ret; + struct ti_k3_rtc *priv = dev_get_drvdata(dev); + + /* + * HWBUG: The compare state machine is broken if the RTC module + * is NOT unlocked in under one second of boot - which is pretty long + * time from the perspective of Linux driver (module load, u-boot + * shell all can take much longer than this. + * + * In such occurrence, it is assumed that the RTC module is unusable + */ + if (priv->soc->unlock_irq_erratum) { + ret = k3rtc_check_unlocked(priv); + /* If there is an error OR if we are locked, return error */ + if (ret) { + dev_err(dev, + HW_ERR "Erratum i2327 unlock QUIRK! Cannot operate!!\n"); + return -EFAULT; + } + } else { + /* May need to explicitly unlock first time */ + ret = k3rtc_unlock_rtc(priv); + if (ret) { + dev_err(dev, "Failed to unlock(%d)!\n", ret); + return ret; + } + } + + /* Enable Shadow register sync on 32k clock boundary */ + k3rtc_field_write(priv, K3RTC_O32K_OSC_DEP_EN, 0x1); + + /* + * Wait at least clock sync time before proceeding further programming. + * This ensures that the 32k based sync is active. + */ + usleep_range(priv->sync_timeout_us, priv->sync_timeout_us + 5); + + /* We need to ensure fence here to make sure sync here */ + ret = k3rtc_fence(priv); + if (ret) { + dev_err(dev, + "Failed fence osc_dep enable(%d) - is 32k clk working?!\n", ret); + return ret; + } + + /* + * FMODE setting: Reading lower seconds will freeze value on higher + * seconds. This also implies that we must *ALWAYS* read lower seconds + * prior to reading higher seconds + */ + k3rtc_field_write(priv, K3RTC_CNT_FMODE, K3RTC_CNT_FMODE_S_CNT_VALUE); + + /* Clear any spurious IRQ sources if any */ + k3rtc_field_write(priv, K3RTC_IRQ_STATUS_ALT, 0x1); + k3rtc_field_write(priv, K3RTC_IRQ_STATUS, 0x1); + /* Disable all IRQs */ + k3rtc_field_write(priv, K3RTC_IRQ_ENABLE_CLR_ALT, 0x1); + k3rtc_field_write(priv, K3RTC_IRQ_ENABLE_CLR, 0x1); + + /* And.. Let us Sync the writes in */ + return k3rtc_fence(priv); +} + +static int ti_k3_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct ti_k3_rtc *priv = dev_get_drvdata(dev); + u32 seconds_lo, seconds_hi; + + seconds_lo = k3rtc_field_read(priv, K3RTC_S_CNT_LSW); + seconds_hi = k3rtc_field_read(priv, K3RTC_S_CNT_MSW); + + rtc_time64_to_tm((((time64_t)seconds_hi) << 32) | (time64_t)seconds_lo, tm); + + return 0; +} + +static int ti_k3_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct ti_k3_rtc *priv = dev_get_drvdata(dev); + time64_t seconds; + + seconds = rtc_tm_to_time64(tm); + + /* + * Read operation on LSW will freeze the RTC, so to update + * the time, we cannot use field operations. Just write since the + * reserved bits are ignored. + */ + regmap_write(priv->regmap, REG_K3RTC_S_CNT_LSW, seconds); + regmap_write(priv->regmap, REG_K3RTC_S_CNT_MSW, seconds >> 32); + + return k3rtc_fence(priv); +} + +static int ti_k3_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) +{ + struct ti_k3_rtc *priv = dev_get_drvdata(dev); + u32 reg; + u32 offset = enabled ? K3RTC_IRQ_ENABLE_SET : K3RTC_IRQ_ENABLE_CLR; + + reg = k3rtc_field_read(priv, K3RTC_IRQ_ENABLE_SET); + if ((enabled && reg) || (!enabled && !reg)) + return 0; + + k3rtc_field_write(priv, offset, 0x1); + + /* + * Ensure the write sync is through - NOTE: it should be OK to have + * ISR to fire as we are checking sync (which should be done in a 32k + * cycle or so). + */ + return k3rtc_fence(priv); +} + +static int ti_k3_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) +{ + struct ti_k3_rtc *priv = dev_get_drvdata(dev); + u32 seconds_lo, seconds_hi; + + seconds_lo = k3rtc_field_read(priv, K3RTC_ALM_S_CNT_LSW); + seconds_hi = k3rtc_field_read(priv, K3RTC_ALM_S_CNT_MSW); + + rtc_time64_to_tm((((time64_t)seconds_hi) << 32) | (time64_t)seconds_lo, &alarm->time); + + alarm->enabled = k3rtc_field_read(priv, K3RTC_IRQ_ENABLE_SET); + + return 0; +} + +static int ti_k3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) +{ + struct ti_k3_rtc *priv = dev_get_drvdata(dev); + time64_t seconds; + int ret; + + seconds = rtc_tm_to_time64(&alarm->time); + + k3rtc_field_write(priv, K3RTC_ALM_S_CNT_LSW, seconds); + k3rtc_field_write(priv, K3RTC_ALM_S_CNT_MSW, (seconds >> 32)); + + /* Make sure the alarm time is synced in */ + ret = k3rtc_fence(priv); + if (ret) { + dev_err(dev, "Failed to fence(%d)! Potential config issue?\n", ret); + return ret; + } + + /* Alarm IRQ enable will do a sync */ + return ti_k3_rtc_alarm_irq_enable(dev, alarm->enabled); +} + +static int ti_k3_rtc_read_offset(struct device *dev, long *offset) +{ + struct ti_k3_rtc *priv = dev_get_drvdata(dev); + u32 ticks_per_hr = priv->rate_32k * 3600; + int comp; + s64 tmp; + + comp = k3rtc_field_read(priv, K3RTC_COMP); + + /* Convert from RTC calibration register format to ppb format */ + tmp = comp * (s64)K3RTC_PPB_MULT; + if (tmp < 0) + tmp -= ticks_per_hr / 2LL; + else + tmp += ticks_per_hr / 2LL; + tmp = div_s64(tmp, ticks_per_hr); + + /* Offset value operates in negative way, so swap sign */ + *offset = (long)-tmp; + + return 0; +} + +static int ti_k3_rtc_set_offset(struct device *dev, long offset) +{ + struct ti_k3_rtc *priv = dev_get_drvdata(dev); + u32 ticks_per_hr = priv->rate_32k * 3600; + int comp; + s64 tmp; + + /* Make sure offset value is within supported range */ + if (offset < K3RTC_MIN_OFFSET || offset > K3RTC_MAX_OFFSET) + return -ERANGE; + + /* Convert from ppb format to RTC calibration register format */ + tmp = offset * (s64)ticks_per_hr; + if (tmp < 0) + tmp -= K3RTC_PPB_MULT / 2LL; + else + tmp += K3RTC_PPB_MULT / 2LL; + tmp = div_s64(tmp, K3RTC_PPB_MULT); + + /* Offset value operates in negative way, so swap sign */ + comp = (int)-tmp; + + k3rtc_field_write(priv, K3RTC_COMP, comp); + + return k3rtc_fence(priv); +} + +static irqreturn_t ti_k3_rtc_interrupt(s32 irq, void *dev_id) +{ + struct device *dev = dev_id; + struct ti_k3_rtc *priv = dev_get_drvdata(dev); + u32 reg; + int ret; + + /* + * IRQ assertion can be very fast, however, the IRQ Status clear + * de-assert depends on 32k clock edge in the 32k domain + * If we clear the status prior to the first 32k clock edge, + * the status bit is cleared, but the IRQ stays re-asserted. + * + * To prevent this condition, we need to wait for clock sync time. + * We can either do that by polling the 32k observability signal for + * a toggle OR we could just sleep and let the processor do other + * stuff. + */ + usleep_range(priv->sync_timeout_us, priv->sync_timeout_us + 2); + + /* Lets make sure that this is a valid interrupt */ + reg = k3rtc_field_read(priv, K3RTC_IRQ_STATUS); + + if (!reg) { + u32 raw = k3rtc_field_read(priv, K3RTC_IRQ_STATUS_RAW); + + dev_err(dev, + HW_ERR + "Erratum i2327/IRQ trig: status: 0x%08x / 0x%08x\n", reg, raw); + return IRQ_NONE; + } + + /* + * Write 1 to clear status reg + * We cannot use a field operation here due to a potential race between + * 32k domain and vbus domain. + */ + regmap_write(priv->regmap, REG_K3RTC_IRQSTATUS_SYS, 0x1); + + /* Sync the write in */ + ret = k3rtc_fence(priv); + if (ret) { + dev_err(dev, "Failed to fence irq status clr(%d)!\n", ret); + return IRQ_NONE; + } + + /* + * Force the 32k status to be reloaded back in to ensure status is + * reflected back correctly. + */ + k3rtc_field_write(priv, K3RTC_RELOAD_FROM_BBD, 0x1); + + /* Ensure the write sync is through */ + ret = k3rtc_fence(priv); + if (ret) { + dev_err(dev, "Failed to fence reload from bbd(%d)!\n", ret); + return IRQ_NONE; + } + + /* Now we ensure that the status bit is cleared */ + ret = regmap_field_read_poll_timeout(priv->r_fields[K3RTC_IRQ_STATUS], + ret, !ret, 2, priv->sync_timeout_us); + if (ret) { + dev_err(dev, "Time out waiting for status clear\n"); + return IRQ_NONE; + } + + /* Notify RTC core on event */ + rtc_update_irq(priv->rtc_dev, 1, RTC_IRQF | RTC_AF); + + return IRQ_HANDLED; +} + +static const struct rtc_class_ops ti_k3_rtc_ops = { + .read_time = ti_k3_rtc_read_time, + .set_time = ti_k3_rtc_set_time, + .read_alarm = ti_k3_rtc_read_alarm, + .set_alarm = ti_k3_rtc_set_alarm, + .read_offset = ti_k3_rtc_read_offset, + .set_offset = ti_k3_rtc_set_offset, + .alarm_irq_enable = ti_k3_rtc_alarm_irq_enable, +}; + +static int ti_k3_rtc_scratch_read(void *priv_data, unsigned int offset, + void *val, size_t bytes) +{ + struct ti_k3_rtc *priv = (struct ti_k3_rtc *)priv_data; + + return regmap_bulk_read(priv->regmap, REG_K3RTC_SCRATCH0 + offset, val, bytes / 4); +} + +static int ti_k3_rtc_scratch_write(void *priv_data, unsigned int offset, + void *val, size_t bytes) +{ + struct ti_k3_rtc *priv = (struct ti_k3_rtc *)priv_data; + int ret; + + ret = regmap_bulk_write(priv->regmap, REG_K3RTC_SCRATCH0 + offset, val, bytes / 4); + if (ret) + return ret; + + return k3rtc_fence(priv); +} + +static struct nvmem_config ti_k3_rtc_nvmem_config = { + .name = "ti_k3_rtc_scratch", + .word_size = 4, + .stride = 4, + .size = REG_K3RTC_SCRATCH7 - REG_K3RTC_SCRATCH0 + 4, + .reg_read = ti_k3_rtc_scratch_read, + .reg_write = ti_k3_rtc_scratch_write, +}; + +static int k3rtc_get_32kclk(struct device *dev, struct ti_k3_rtc *priv) +{ + int ret; + struct clk *clk; + + clk = devm_clk_get(dev, "osc32k"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + ret = clk_prepare_enable(clk); + if (ret) + return ret; + + ret = devm_add_action_or_reset(dev, (void (*)(void *))clk_disable_unprepare, clk); + if (ret) + return ret; + + priv->rate_32k = clk_get_rate(clk); + + /* Make sure we are exact 32k clock. Else, try to compensate delay */ + if (priv->rate_32k != 32768) + dev_warn(dev, "Clock rate %ld is not 32768! Could misbehave!\n", + priv->rate_32k); + + /* + * Sync timeout should be two 32k clk sync cycles = ~61uS. We double + * it to comprehend intermediate bus segment and cpu frequency + * deltas + */ + priv->sync_timeout_us = (u32)(DIV_ROUND_UP_ULL(1000000, priv->rate_32k) * 4); + + return ret; +} + +static int k3rtc_get_vbusclk(struct device *dev, struct ti_k3_rtc *priv) +{ + int ret; + struct clk *clk; + + /* Note: VBUS isn't a context clock, it is needed for hardware operation */ + clk = devm_clk_get(dev, "vbus"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + ret = clk_prepare_enable(clk); + if (ret) + return ret; + + return devm_add_action_or_reset(dev, (void (*)(void *))clk_disable_unprepare, clk); +} + +static int ti_k3_rtc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ti_k3_rtc *priv; + void __iomem *rtc_base; + int ret; + + priv = devm_kzalloc(dev, sizeof(struct ti_k3_rtc), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + rtc_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(rtc_base)) + return PTR_ERR(rtc_base); + + priv->regmap = devm_regmap_init_mmio(dev, rtc_base, &ti_k3_rtc_regmap_config); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + + ret = devm_regmap_field_bulk_alloc(dev, priv->regmap, priv->r_fields, + ti_rtc_reg_fields, K3_RTC_MAX_FIELDS); + if (ret) + return ret; + + ret = k3rtc_get_32kclk(dev, priv); + if (ret) + return ret; + ret = k3rtc_get_vbusclk(dev, priv); + if (ret) + return ret; + + ret = platform_get_irq(pdev, 0); + if (ret < 0) + return ret; + priv->irq = (unsigned int)ret; + + priv->rtc_dev = devm_rtc_allocate_device(dev); + if (IS_ERR(priv->rtc_dev)) + return PTR_ERR(priv->rtc_dev); + + priv->soc = of_device_get_match_data(dev); + + priv->rtc_dev->ops = &ti_k3_rtc_ops; + priv->rtc_dev->range_max = (1ULL << 48) - 1; /* 48Bit seconds */ + ti_k3_rtc_nvmem_config.priv = priv; + + ret = devm_request_threaded_irq(dev, priv->irq, NULL, + ti_k3_rtc_interrupt, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, + dev_name(dev), dev); + if (ret) { + dev_err(dev, "Could not request IRQ: %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, priv); + + ret = k3rtc_configure(dev); + if (ret) + return ret; + + if (device_property_present(dev, "wakeup-source")) + device_init_wakeup(dev, true); + else + device_set_wakeup_capable(dev, true); + + ret = devm_rtc_register_device(priv->rtc_dev); + if (ret) + return ret; + + return devm_rtc_nvmem_register(priv->rtc_dev, &ti_k3_rtc_nvmem_config); +} + +static const struct ti_k3_rtc_soc_data ti_k3_am62_data = { + .unlock_irq_erratum = true, +}; + +static const struct of_device_id ti_k3_rtc_of_match_table[] = { + {.compatible = "ti,am62-rtc", .data = &ti_k3_am62_data}, + {} +}; +MODULE_DEVICE_TABLE(of, ti_k3_rtc_of_match_table); + +static int __maybe_unused ti_k3_rtc_suspend(struct device *dev) +{ + struct ti_k3_rtc *priv = dev_get_drvdata(dev); + + if (device_may_wakeup(dev)) + enable_irq_wake(priv->irq); + return 0; +} + +static int __maybe_unused ti_k3_rtc_resume(struct device *dev) +{ + struct ti_k3_rtc *priv = dev_get_drvdata(dev); + + if (device_may_wakeup(dev)) + disable_irq_wake(priv->irq); + return 0; +} + +static SIMPLE_DEV_PM_OPS(ti_k3_rtc_pm_ops, ti_k3_rtc_suspend, ti_k3_rtc_resume); + +static struct platform_driver ti_k3_rtc_driver = { + .probe = ti_k3_rtc_probe, + .driver = { + .name = "rtc-ti-k3", + .of_match_table = ti_k3_rtc_of_match_table, + .pm = &ti_k3_rtc_pm_ops, + }, +}; +module_platform_driver(ti_k3_rtc_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("TI K3 RTC driver"); +MODULE_AUTHOR("Nishanth Menon"); -- cgit v1.2.3 From 592ff0c8d0648610511f4e4fb532f100168e6e0d Mon Sep 17 00:00:00 2001 From: keliu Date: Fri, 27 May 2022 07:36:36 +0000 Subject: rtc: Directly use ida_alloc()/free() Use ida_alloc()/ida_free() instead of deprecated ida_simple_get()/ida_simple_remove() . Signed-off-by: keliu Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220527073636.2474546-1-liuke94@huawei.com --- drivers/rtc/class.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/rtc/class.c b/drivers/rtc/class.c index 3c8eec2218df..e48223c00c67 100644 --- a/drivers/rtc/class.c +++ b/drivers/rtc/class.c @@ -36,7 +36,7 @@ static void rtc_device_release(struct device *dev) cancel_work_sync(&rtc->irqwork); - ida_simple_remove(&rtc_ida, rtc->id); + ida_free(&rtc_ida, rtc->id); mutex_destroy(&rtc->ops_lock); kfree(rtc); } @@ -262,7 +262,7 @@ static int rtc_device_get_id(struct device *dev) } if (id < 0) - id = ida_simple_get(&rtc_ida, 0, 0, GFP_KERNEL); + id = ida_alloc(&rtc_ida, GFP_KERNEL); return id; } @@ -368,7 +368,7 @@ struct rtc_device *devm_rtc_allocate_device(struct device *dev) rtc = rtc_allocate_device(); if (!rtc) { - ida_simple_remove(&rtc_ida, id); + ida_free(&rtc_ida, id); return ERR_PTR(-ENOMEM); } -- cgit v1.2.3 From aa30eccb24e5a66a2cf7f7b34a69c3651d12cc6a Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Tue, 21 Jun 2022 12:46:25 +0300 Subject: fs/ntfs3: Fallocate (FALLOC_FL_INSERT_RANGE) implementation Add functions for inserting hole in file and inserting range in run. Signed-off-by: Konstantin Komarov --- fs/ntfs3/attrib.c | 176 +++++++++++++++++++++++++++++++++++++++++++++++++++++ fs/ntfs3/ntfs_fs.h | 4 +- fs/ntfs3/run.c | 43 +++++++++++++ 3 files changed, 222 insertions(+), 1 deletion(-) diff --git a/fs/ntfs3/attrib.c b/fs/ntfs3/attrib.c index fc0623b029e6..86e688b95ad5 100644 --- a/fs/ntfs3/attrib.c +++ b/fs/ntfs3/attrib.c @@ -2081,3 +2081,179 @@ out: return err; } + +/* + * attr_insert_range - Insert range (hole) in file. + * Not for normal files. + */ +int attr_insert_range(struct ntfs_inode *ni, u64 vbo, u64 bytes) +{ + int err = 0; + struct runs_tree *run = &ni->file.run; + struct ntfs_sb_info *sbi = ni->mi.sbi; + struct ATTRIB *attr = NULL, *attr_b; + struct ATTR_LIST_ENTRY *le, *le_b; + struct mft_inode *mi, *mi_b; + CLST vcn, svcn, evcn1, len, next_svcn; + u64 data_size, alloc_size; + u32 mask; + __le16 a_flags; + + if (!bytes) + return 0; + + le_b = NULL; + attr_b = ni_find_attr(ni, NULL, &le_b, ATTR_DATA, NULL, 0, NULL, &mi_b); + if (!attr_b) + return -ENOENT; + + if (!is_attr_ext(attr_b)) { + /* It was checked above. See fallocate. */ + return -EOPNOTSUPP; + } + + if (!attr_b->non_res) { + data_size = le32_to_cpu(attr_b->res.data_size); + mask = sbi->cluster_mask; /* cluster_size - 1 */ + } else { + data_size = le64_to_cpu(attr_b->nres.data_size); + mask = (sbi->cluster_size << attr_b->nres.c_unit) - 1; + } + + if (vbo > data_size) { + /* Insert range after the file size is not allowed. */ + return -EINVAL; + } + + if ((vbo & mask) || (bytes & mask)) { + /* Allow to insert only frame aligned ranges. */ + return -EINVAL; + } + + vcn = vbo >> sbi->cluster_bits; + len = bytes >> sbi->cluster_bits; + + down_write(&ni->file.run_lock); + + if (!attr_b->non_res) { + err = attr_set_size(ni, ATTR_DATA, NULL, 0, run, + data_size + bytes, NULL, false, &attr); + if (err) + goto out; + if (!attr->non_res) { + /* Still resident. */ + char *data = Add2Ptr(attr, attr->res.data_off); + + memmove(data + bytes, data, bytes); + memset(data, 0, bytes); + err = 0; + goto out; + } + /* Resident files becomes nonresident. */ + le_b = NULL; + attr_b = ni_find_attr(ni, NULL, &le_b, ATTR_DATA, NULL, 0, NULL, + &mi_b); + if (!attr_b) + return -ENOENT; + if (!attr_b->non_res) { + err = -EINVAL; + goto out; + } + data_size = le64_to_cpu(attr_b->nres.data_size); + alloc_size = le64_to_cpu(attr_b->nres.alloc_size); + } + + /* + * Enumerate all attribute segments and shift start vcn. + */ + a_flags = attr_b->flags; + svcn = le64_to_cpu(attr_b->nres.svcn); + evcn1 = le64_to_cpu(attr_b->nres.evcn) + 1; + + if (svcn <= vcn && vcn < evcn1) { + attr = attr_b; + le = le_b; + mi = mi_b; + } else if (!le_b) { + err = -EINVAL; + goto out; + } else { + le = le_b; + attr = ni_find_attr(ni, attr_b, &le, ATTR_DATA, NULL, 0, &vcn, + &mi); + if (!attr) { + err = -EINVAL; + goto out; + } + + svcn = le64_to_cpu(attr->nres.svcn); + evcn1 = le64_to_cpu(attr->nres.evcn) + 1; + } + + run_truncate(run, 0); /* clear cached values. */ + err = attr_load_runs(attr, ni, run, NULL); + if (err) + goto out; + + if (!run_insert_range(run, vcn, len)) { + err = -ENOMEM; + goto out; + } + + /* Try to pack in current record as much as possible. */ + err = mi_pack_runs(mi, attr, run, evcn1 + len - svcn); + if (err) + goto out; + + next_svcn = le64_to_cpu(attr->nres.evcn) + 1; + run_truncate_head(run, next_svcn); + + while ((attr = ni_enum_attr_ex(ni, attr, &le, &mi)) && + attr->type == ATTR_DATA && !attr->name_len) { + le64_add_cpu(&attr->nres.svcn, len); + le64_add_cpu(&attr->nres.evcn, len); + if (le) { + le->vcn = attr->nres.svcn; + ni->attr_list.dirty = true; + } + mi->dirty = true; + } + + /* + * Update primary attribute segment in advance. + * pointer attr_b may become invalid (layout of mft is changed) + */ + if (vbo <= ni->i_valid) + ni->i_valid += bytes; + + attr_b->nres.data_size = le64_to_cpu(data_size + bytes); + attr_b->nres.alloc_size = le64_to_cpu(alloc_size + bytes); + + /* ni->valid may be not equal valid_size (temporary). */ + if (ni->i_valid > data_size + bytes) + attr_b->nres.valid_size = attr_b->nres.data_size; + else + attr_b->nres.valid_size = cpu_to_le64(ni->i_valid); + mi_b->dirty = true; + + if (next_svcn < evcn1 + len) { + err = ni_insert_nonresident(ni, ATTR_DATA, NULL, 0, run, + next_svcn, evcn1 + len - next_svcn, + a_flags, NULL, NULL); + if (err) + goto out; + } + + ni->vfs_inode.i_size += bytes; + ni->ni_flags |= NI_FLAG_UPDATE_PARENT; + mark_inode_dirty(&ni->vfs_inode); + +out: + run_truncate(run, 0); /* clear cached values. */ + + up_write(&ni->file.run_lock); + if (err) + make_bad_inode(&ni->vfs_inode); + + return err; +} diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h index fb825059d488..1f92e3a05f61 100644 --- a/fs/ntfs3/ntfs_fs.h +++ b/fs/ntfs3/ntfs_fs.h @@ -440,6 +440,7 @@ int attr_is_frame_compressed(struct ntfs_inode *ni, struct ATTRIB *attr, int attr_allocate_frame(struct ntfs_inode *ni, CLST frame, size_t compr_size, u64 new_valid); int attr_collapse_range(struct ntfs_inode *ni, u64 vbo, u64 bytes); +int attr_insert_range(struct ntfs_inode *ni, u64 vbo, u64 bytes); int attr_punch_hole(struct ntfs_inode *ni, u64 vbo, u64 bytes, u32 *frame_size); /* Functions from attrlist.c */ @@ -775,10 +776,11 @@ bool run_lookup_entry(const struct runs_tree *run, CLST vcn, CLST *lcn, void run_truncate(struct runs_tree *run, CLST vcn); void run_truncate_head(struct runs_tree *run, CLST vcn); void run_truncate_around(struct runs_tree *run, CLST vcn); -bool run_lookup(const struct runs_tree *run, CLST vcn, size_t *Index); +bool run_lookup(const struct runs_tree *run, CLST vcn, size_t *index); bool run_add_entry(struct runs_tree *run, CLST vcn, CLST lcn, CLST len, bool is_mft); bool run_collapse_range(struct runs_tree *run, CLST vcn, CLST len); +bool run_insert_range(struct runs_tree *run, CLST vcn, CLST len); bool run_get_entry(const struct runs_tree *run, size_t index, CLST *vcn, CLST *lcn, CLST *len); bool run_is_mapped_full(const struct runs_tree *run, CLST svcn, CLST evcn); diff --git a/fs/ntfs3/run.c b/fs/ntfs3/run.c index a8fec651f973..7609d45a2d72 100644 --- a/fs/ntfs3/run.c +++ b/fs/ntfs3/run.c @@ -547,6 +547,49 @@ bool run_collapse_range(struct runs_tree *run, CLST vcn, CLST len) return true; } +/* run_insert_range + * + * Helper for attr_insert_range(), + * which is helper for fallocate(insert_range). + */ +bool run_insert_range(struct runs_tree *run, CLST vcn, CLST len) +{ + size_t index; + struct ntfs_run *r, *e; + + if (WARN_ON(!run_lookup(run, vcn, &index))) + return false; /* Should never be here. */ + + e = run->runs + run->count; + r = run->runs + index; + + r = run->runs + index; + if (vcn > r->vcn) + r += 1; + + for (; r < e; r++) + r->vcn += len; + + r = run->runs + index; + + if (vcn > r->vcn) { + /* split fragment. */ + CLST len1 = vcn - r->vcn; + CLST len2 = r->len - len1; + CLST lcn2 = r->lcn == SPARSE_LCN ? SPARSE_LCN : (r->lcn + len1); + + r->len = len1; + + if (!run_add_entry(run, vcn + len, lcn2, len2, false)) + return false; + } + + if (!run_add_entry(run, vcn, SPARSE_LCN, len, false)) + return false; + + return true; +} + /* * run_get_entry - Return index-th mapped region. */ -- cgit v1.2.3 From e4d2f4fd5341064d2b3c5158da69421a581e7ec1 Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Tue, 21 Jun 2022 12:49:52 +0300 Subject: fs/ntfs3: Enable FALLOC_FL_INSERT_RANGE Changed logic in ntfs_fallocate - more clear checks in beginning instead of the middle of function and added FALLOC_FL_INSERT_RANGE. Fixes xfstest generic/064 Fixes: 4342306f0f0d ("fs/ntfs3: Add file operations and implementation") Signed-off-by: Konstantin Komarov --- fs/ntfs3/file.c | 97 ++++++++++++++++++++++++++++++++------------------------- 1 file changed, 55 insertions(+), 42 deletions(-) diff --git a/fs/ntfs3/file.c b/fs/ntfs3/file.c index 27c32692513c..bdffe4b8554b 100644 --- a/fs/ntfs3/file.c +++ b/fs/ntfs3/file.c @@ -533,21 +533,35 @@ static int ntfs_truncate(struct inode *inode, loff_t new_size) static long ntfs_fallocate(struct file *file, int mode, loff_t vbo, loff_t len) { struct inode *inode = file->f_mapping->host; + struct address_space *mapping = inode->i_mapping; struct super_block *sb = inode->i_sb; struct ntfs_sb_info *sbi = sb->s_fs_info; struct ntfs_inode *ni = ntfs_i(inode); loff_t end = vbo + len; loff_t vbo_down = round_down(vbo, PAGE_SIZE); - loff_t i_size; + bool is_supported_holes = is_sparsed(ni) || is_compressed(ni); + loff_t i_size, new_size; + bool map_locked; int err; /* No support for dir. */ if (!S_ISREG(inode->i_mode)) return -EOPNOTSUPP; - /* Return error if mode is not supported. */ - if (mode & ~(FALLOC_FL_KEEP_SIZE | FALLOC_FL_PUNCH_HOLE | - FALLOC_FL_COLLAPSE_RANGE)) { + /* + * vfs_fallocate checks all possible combinations of mode. + * Do additional checks here before ntfs_set_state(dirty). + */ + if (mode & FALLOC_FL_PUNCH_HOLE) { + if (!is_supported_holes) + return -EOPNOTSUPP; + } else if (mode & FALLOC_FL_COLLAPSE_RANGE) { + } else if (mode & FALLOC_FL_INSERT_RANGE) { + if (!is_supported_holes) + return -EOPNOTSUPP; + } else if (mode & + ~(FALLOC_FL_KEEP_SIZE | FALLOC_FL_PUNCH_HOLE | + FALLOC_FL_COLLAPSE_RANGE | FALLOC_FL_INSERT_RANGE)) { ntfs_inode_warn(inode, "fallocate(0x%x) is not supported", mode); return -EOPNOTSUPP; @@ -557,6 +571,8 @@ static long ntfs_fallocate(struct file *file, int mode, loff_t vbo, loff_t len) inode_lock(inode); i_size = inode->i_size; + new_size = max(end, i_size); + map_locked = false; if (WARN_ON(ni->ni_flags & NI_FLAG_COMPRESSED_MASK)) { /* Should never be here, see ntfs_file_open. */ @@ -564,38 +580,27 @@ static long ntfs_fallocate(struct file *file, int mode, loff_t vbo, loff_t len) goto out; } + if (mode & (FALLOC_FL_PUNCH_HOLE | FALLOC_FL_COLLAPSE_RANGE | + FALLOC_FL_INSERT_RANGE)) { + inode_dio_wait(inode); + filemap_invalidate_lock(mapping); + map_locked = true; + } + if (mode & FALLOC_FL_PUNCH_HOLE) { u32 frame_size; loff_t mask, vbo_a, end_a, tmp; - if (!(mode & FALLOC_FL_KEEP_SIZE)) { - err = -EINVAL; - goto out; - } - - err = filemap_write_and_wait_range(inode->i_mapping, vbo, - end - 1); + err = filemap_write_and_wait_range(mapping, vbo, end - 1); if (err) goto out; - err = filemap_write_and_wait_range(inode->i_mapping, end, - LLONG_MAX); + err = filemap_write_and_wait_range(mapping, end, LLONG_MAX); if (err) goto out; - inode_dio_wait(inode); - truncate_pagecache(inode, vbo_down); - if (!is_sparsed(ni) && !is_compressed(ni)) { - /* - * Normal file, can't make hole. - * TODO: Try to find way to save info about hole. - */ - err = -EOPNOTSUPP; - goto out; - } - ni_lock(ni); err = attr_punch_hole(ni, vbo, len, &frame_size); ni_unlock(ni); @@ -627,17 +632,11 @@ static long ntfs_fallocate(struct file *file, int mode, loff_t vbo, loff_t len) ni_unlock(ni); } } else if (mode & FALLOC_FL_COLLAPSE_RANGE) { - if (mode & ~FALLOC_FL_COLLAPSE_RANGE) { - err = -EINVAL; - goto out; - } - /* * Write tail of the last page before removed range since * it will get removed from the page cache below. */ - err = filemap_write_and_wait_range(inode->i_mapping, vbo_down, - vbo); + err = filemap_write_and_wait_range(mapping, vbo_down, vbo); if (err) goto out; @@ -645,34 +644,45 @@ static long ntfs_fallocate(struct file *file, int mode, loff_t vbo, loff_t len) * Write data that will be shifted to preserve them * when discarding page cache below. */ - err = filemap_write_and_wait_range(inode->i_mapping, end, - LLONG_MAX); + err = filemap_write_and_wait_range(mapping, end, LLONG_MAX); if (err) goto out; - /* Wait for existing dio to complete. */ - inode_dio_wait(inode); - truncate_pagecache(inode, vbo_down); ni_lock(ni); err = attr_collapse_range(ni, vbo, len); ni_unlock(ni); - } else { - /* - * Normal file: Allocate clusters, do not change 'valid' size. - */ - loff_t new_size = max(end, i_size); + } else if (mode & FALLOC_FL_INSERT_RANGE) { + /* Check new size. */ + err = inode_newsize_ok(inode, new_size); + if (err) + goto out; + + /* Write out all dirty pages. */ + err = filemap_write_and_wait_range(mapping, vbo_down, + LLONG_MAX); + if (err) + goto out; + truncate_pagecache(inode, vbo_down); + ni_lock(ni); + err = attr_insert_range(ni, vbo, len); + ni_unlock(ni); + } else { + /* Check new size. */ err = inode_newsize_ok(inode, new_size); if (err) goto out; + /* + * Allocate clusters, do not change 'valid' size. + */ err = ntfs_set_size(inode, new_size); if (err) goto out; - if (is_sparsed(ni) || is_compressed(ni)) { + if (is_supported_holes) { CLST vcn_v = ni->i_valid >> sbi->cluster_bits; CLST vcn = vbo >> sbi->cluster_bits; CLST cend = bytes_to_cluster(sbi, end); @@ -720,6 +730,9 @@ static long ntfs_fallocate(struct file *file, int mode, loff_t vbo, loff_t len) } out: + if (map_locked) + filemap_invalidate_unlock(mapping); + if (err == -EFBIG) err = -ENOSPC; -- cgit v1.2.3 From ed5fce76b5ea40c87b44cafbe4f3222da8ec981a Mon Sep 17 00:00:00 2001 From: Siddhesh Poyarekar Date: Tue, 28 Jun 2022 08:30:58 +0800 Subject: vfs: escape hash as well When a filesystem is mounted with a name that starts with a #: # mount '#name' /mnt/bad -t tmpfs this will cause the entry to look like this (leading space added so that git does not strip it out): #name /mnt/bad tmpfs rw,seclabel,relatime,inode64 0 0 This breaks getmntent and any code that aims to parse fstab as well as /proc/mounts with the same logic since they need to strip leading spaces or skip over comment lines, due to which they report incorrect output or skip over the line respectively. Solve this by translating the hash character into its octal encoding equivalent so that applications can decode the name correctly. Signed-off-by: Siddhesh Poyarekar Signed-off-by: Ian Kent Signed-off-by: Al Viro --- fs/proc_namespace.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/proc_namespace.c b/fs/proc_namespace.c index 49650e54d2f8..846f9455ae22 100644 --- a/fs/proc_namespace.c +++ b/fs/proc_namespace.c @@ -86,7 +86,7 @@ static void show_mnt_opts(struct seq_file *m, struct vfsmount *mnt) static inline void mangle(struct seq_file *m, const char *s) { - seq_escape(m, s, " \t\n\\"); + seq_escape(m, s, " \t\n\\#"); } static void show_type(struct seq_file *m, struct super_block *sb) -- cgit v1.2.3 From a5a3d94fc4edecb894bc79810aea511ff9261c09 Mon Sep 17 00:00:00 2001 From: Asmaa Mnebhi Date: Tue, 21 Jun 2022 08:49:30 -0400 Subject: power: reset: pwr-mlxbf: add missing include Add missing include for devm_work_autocancel to fix build error: drivers/power/reset/pwr-mlxbf.c: In function 'pwr_mlxbf_probe': drivers/power/reset/pwr-mlxbf.c:67:15: error: implicit declaration of function 'devm_work_autocancel' [-Werror=implicit-function-declaration] 67 | err = devm_work_autocancel(dev, &priv->send_work, pwr_mlxbf_send_work); | ^~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors Fixes: a4c0094fcf76 ("power: reset: pwr-mlxbf: add BlueField SoC power control driver") Reported-by: Stephen Rothwell Signed-off-by: Asmaa Mnebhi Signed-off-by: Sebastian Reichel --- drivers/power/reset/pwr-mlxbf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/power/reset/pwr-mlxbf.c b/drivers/power/reset/pwr-mlxbf.c index c1f9987834a2..1c4904c0e1f5 100644 --- a/drivers/power/reset/pwr-mlxbf.c +++ b/drivers/power/reset/pwr-mlxbf.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include -- cgit v1.2.3 From a578cc3af5cea5c7a912d2cfb8601875eb8ce451 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Wed, 29 Jun 2022 15:20:45 -0400 Subject: power: reset: pwr-mlxbf: change rst_pwr_hid and low_pwr_hid from global to local variables sparse reports drivers/power/reset/pwr-mlxbf.c:19:12: warning: symbol 'rst_pwr_hid' was not declared. Should it be static? drivers/power/reset/pwr-mlxbf.c:20:12: warning: symbol 'low_pwr_hid' was not declared. Should it be static? Both rst_pwr_hid and low_pwr_hid are only used in a single function so they should be local variables. Fixes: a4c0094fcf76 ("power: reset: pwr-mlxbf: add BlueField SoC power control driver") Signed-off-by: Tom Rix Acked-by: Asmaa Mnebhi Signed-off-by: Sebastian Reichel --- drivers/power/reset/pwr-mlxbf.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/power/reset/pwr-mlxbf.c b/drivers/power/reset/pwr-mlxbf.c index 1c4904c0e1f5..12dedf841a44 100644 --- a/drivers/power/reset/pwr-mlxbf.c +++ b/drivers/power/reset/pwr-mlxbf.c @@ -16,9 +16,6 @@ #include #include -const char *rst_pwr_hid = "MLNXBF24"; -const char *low_pwr_hid = "MLNXBF29"; - struct pwr_mlxbf { struct work_struct send_work; const char *hid; @@ -31,6 +28,8 @@ static void pwr_mlxbf_send_work(struct work_struct *work) static irqreturn_t pwr_mlxbf_irq(int irq, void *ptr) { + const char *rst_pwr_hid = "MLNXBF24"; + const char *low_pwr_hid = "MLNXBF29"; struct pwr_mlxbf *priv = ptr; if (!strncmp(priv->hid, rst_pwr_hid, 8)) -- cgit v1.2.3 From 321460ca3b55f48b3ba6008248264ab2bd6407d9 Mon Sep 17 00:00:00 2001 From: Pavel Skripkin Date: Thu, 21 Apr 2022 23:53:36 +0300 Subject: fs/ntfs3: Fix NULL deref in ntfs_update_mftmirr If ntfs_fill_super() wasn't called then sbi->sb will be equal to NULL. Code should check this ptr before dereferencing. Syzbot hit this issue via passing wrong mount param as can be seen from log below Fail log: ntfs3: Unknown parameter 'iochvrset' general protection fault, probably for non-canonical address 0xdffffc0000000003: 0000 [#1] PREEMPT SMP KASAN KASAN: null-ptr-deref in range [0x0000000000000018-0x000000000000001f] CPU: 1 PID: 3589 Comm: syz-executor210 Not tainted 5.18.0-rc3-syzkaller-00016-gb253435746d9 #0 ... Call Trace: put_ntfs+0x1ed/0x2a0 fs/ntfs3/super.c:463 ntfs_fs_free+0x6a/0xe0 fs/ntfs3/super.c:1363 put_fs_context+0x119/0x7a0 fs/fs_context.c:469 do_new_mount+0x2b4/0xad0 fs/namespace.c:3044 do_mount fs/namespace.c:3383 [inline] __do_sys_mount fs/namespace.c:3591 [inline] Fixes: 82cae269cfa9 ("fs/ntfs3: Add initialization of super block") Reported-and-tested-by: syzbot+c95173762127ad76a824@syzkaller.appspotmail.com Signed-off-by: Pavel Skripkin Signed-off-by: Konstantin Komarov --- fs/ntfs3/fsntfs.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/fs/ntfs3/fsntfs.c b/fs/ntfs3/fsntfs.c index 3de5700a9b83..891125ca6848 100644 --- a/fs/ntfs3/fsntfs.c +++ b/fs/ntfs3/fsntfs.c @@ -831,10 +831,15 @@ int ntfs_update_mftmirr(struct ntfs_sb_info *sbi, int wait) { int err; struct super_block *sb = sbi->sb; - u32 blocksize = sb->s_blocksize; + u32 blocksize; sector_t block1, block2; u32 bytes; + if (!sb) + return -EINVAL; + + blocksize = sb->s_blocksize; + if (!(sbi->flags & NTFS_FLAGS_MFTMIRR)) return 0; -- cgit v1.2.3 From e66af07ca2b57e01dbf6001ae565ab40037b2df3 Mon Sep 17 00:00:00 2001 From: Pavel Skripkin Date: Thu, 21 Apr 2022 23:53:45 +0300 Subject: fs/ntfs3: Make ntfs_update_mftmirr return void None of callers check the return value of ntfs_update_mftmirr(), so make it return void to make code simpler. Signed-off-by: Pavel Skripkin Signed-off-by: Konstantin Komarov --- fs/ntfs3/fsntfs.c | 20 +++++++------------- fs/ntfs3/ntfs_fs.h | 2 +- 2 files changed, 8 insertions(+), 14 deletions(-) diff --git a/fs/ntfs3/fsntfs.c b/fs/ntfs3/fsntfs.c index 891125ca6848..938acb246b58 100644 --- a/fs/ntfs3/fsntfs.c +++ b/fs/ntfs3/fsntfs.c @@ -827,7 +827,7 @@ int ntfs_refresh_zone(struct ntfs_sb_info *sbi) /* * ntfs_update_mftmirr - Update $MFTMirr data. */ -int ntfs_update_mftmirr(struct ntfs_sb_info *sbi, int wait) +void ntfs_update_mftmirr(struct ntfs_sb_info *sbi, int wait) { int err; struct super_block *sb = sbi->sb; @@ -836,12 +836,12 @@ int ntfs_update_mftmirr(struct ntfs_sb_info *sbi, int wait) u32 bytes; if (!sb) - return -EINVAL; + return; blocksize = sb->s_blocksize; if (!(sbi->flags & NTFS_FLAGS_MFTMIRR)) - return 0; + return; err = 0; bytes = sbi->mft.recs_mirr << sbi->record_bits; @@ -852,16 +852,13 @@ int ntfs_update_mftmirr(struct ntfs_sb_info *sbi, int wait) struct buffer_head *bh1, *bh2; bh1 = sb_bread(sb, block1++); - if (!bh1) { - err = -EIO; - goto out; - } + if (!bh1) + return; bh2 = sb_getblk(sb, block2++); if (!bh2) { put_bh(bh1); - err = -EIO; - goto out; + return; } if (buffer_locked(bh2)) @@ -881,13 +878,10 @@ int ntfs_update_mftmirr(struct ntfs_sb_info *sbi, int wait) put_bh(bh2); if (err) - goto out; + return; } sbi->flags &= ~NTFS_FLAGS_MFTMIRR; - -out: - return err; } /* diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h index 1f92e3a05f61..8f05b91f3c5e 100644 --- a/fs/ntfs3/ntfs_fs.h +++ b/fs/ntfs3/ntfs_fs.h @@ -593,7 +593,7 @@ int ntfs_look_free_mft(struct ntfs_sb_info *sbi, CLST *rno, bool mft, void ntfs_mark_rec_free(struct ntfs_sb_info *sbi, CLST rno); int ntfs_clear_mft_tail(struct ntfs_sb_info *sbi, size_t from, size_t to); int ntfs_refresh_zone(struct ntfs_sb_info *sbi); -int ntfs_update_mftmirr(struct ntfs_sb_info *sbi, int wait); +void ntfs_update_mftmirr(struct ntfs_sb_info *sbi, int wait); enum NTFS_DIRTY_FLAGS { NTFS_DIRTY_CLEAR = 0, NTFS_DIRTY_DIRTY = 1, -- cgit v1.2.3 From 4838ec0d80b110a5f30c7e3169dc5021efd203d4 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 30 Jun 2022 16:10:56 +0300 Subject: fs/ntfs3: Unlock on error in attr_insert_range() This error path needs to call up_write(&ni->file.run_lock) and do some other clean up before returning. Fixes: aa30eccb24e5 ("fs/ntfs3: Fallocate (FALLOC_FL_INSERT_RANGE) implementation") Signed-off-by: Dan Carpenter Signed-off-by: Konstantin Komarov --- fs/ntfs3/attrib.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/fs/ntfs3/attrib.c b/fs/ntfs3/attrib.c index 86e688b95ad5..3e9aefcb3e6c 100644 --- a/fs/ntfs3/attrib.c +++ b/fs/ntfs3/attrib.c @@ -2153,8 +2153,10 @@ int attr_insert_range(struct ntfs_inode *ni, u64 vbo, u64 bytes) le_b = NULL; attr_b = ni_find_attr(ni, NULL, &le_b, ATTR_DATA, NULL, 0, NULL, &mi_b); - if (!attr_b) - return -ENOENT; + if (!attr_b) { + err = -ENOENT; + goto out; + } if (!attr_b->non_res) { err = -EINVAL; goto out; -- cgit v1.2.3 From cc83b0c7e3064e2bb1f9d099bbfdaf493cd669fe Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Mon, 4 Jul 2022 19:53:19 +0100 Subject: fs/ntfs3: Remove duplicated assignment to variable r The assignment to variable r is duplicated, the second assignment is redundant and can be removed. Signed-off-by: Colin Ian King Signed-off-by: Konstantin Komarov --- fs/ntfs3/run.c | 1 - 1 file changed, 1 deletion(-) diff --git a/fs/ntfs3/run.c b/fs/ntfs3/run.c index 7609d45a2d72..aba8ab1b9fcb 100644 --- a/fs/ntfs3/run.c +++ b/fs/ntfs3/run.c @@ -563,7 +563,6 @@ bool run_insert_range(struct runs_tree *run, CLST vcn, CLST len) e = run->runs + run->count; r = run->runs + index; - r = run->runs + index; if (vcn > r->vcn) r += 1; -- cgit v1.2.3 From 604a9d272dc3802d880e0510b9d145b1090b3f8a Mon Sep 17 00:00:00 2001 From: Li kunyu Date: Mon, 4 Jul 2022 18:31:13 +0800 Subject: fs/ntfs3: Remove unnecessary 'NULL' values from pointers There is no need to initialize with NULL as it'll be rewritten later. Signed-off-by: Li kunyu Signed-off-by: Konstantin Komarov --- fs/ntfs3/index.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fs/ntfs3/index.c b/fs/ntfs3/index.c index 84ccc1409874..ba2a07dfeaf5 100644 --- a/fs/ntfs3/index.c +++ b/fs/ntfs3/index.c @@ -1678,8 +1678,8 @@ indx_insert_into_buffer(struct ntfs_index *indx, struct ntfs_inode *ni, { int err; const struct NTFS_DE *sp; - struct NTFS_DE *e, *de_t, *up_e = NULL; - struct indx_node *n2 = NULL; + struct NTFS_DE *e, *de_t, *up_e; + struct indx_node *n2; struct indx_node *n1 = fnd->nodes[level]; struct INDEX_HDR *hdr1 = &n1->index->ihdr; struct INDEX_HDR *hdr2; -- cgit v1.2.3 From f5bbc93937aca00fa2de458b7ffa2d9beb59649e Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 5 Jul 2022 22:52:02 +0100 Subject: dt-bindings: display: convert ilitek,ili9341.txt to dt-schema A dt-schema binding for the Ilitek ili9341 was created as panel/ilitek,ili9341.yaml but the txt binding was ignored in the process. Move the remaining items in the txt binding to the yaml one & delete it. The example in the txt binding has a spi-max-frequency which disagrees with the yaml replacement (and its own documentation) so change that to conform with the binding. There are no users in tree of the Adafruit yx240qv29 to check against. Link: https://cdn-learn.adafruit.com/assets/assets/000/046/879/original/SPEC-YX240QV29-T_Rev.A__1_.pdf Reviewed-by: Rob Herring Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20220705215213.1802496-2-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- .../devicetree/bindings/display/ilitek,ili9341.txt | 27 ------------ .../bindings/display/panel/ilitek,ili9341.yaml | 48 +++++++++++++++------- 2 files changed, 34 insertions(+), 41 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/ilitek,ili9341.txt diff --git a/Documentation/devicetree/bindings/display/ilitek,ili9341.txt b/Documentation/devicetree/bindings/display/ilitek,ili9341.txt deleted file mode 100644 index 169b32e4ee4e..000000000000 --- a/Documentation/devicetree/bindings/display/ilitek,ili9341.txt +++ /dev/null @@ -1,27 +0,0 @@ -Ilitek ILI9341 display panels - -This binding is for display panels using an Ilitek ILI9341 controller in SPI -mode. - -Required properties: -- compatible: "adafruit,yx240qv29", "ilitek,ili9341" -- dc-gpios: D/C pin -- reset-gpios: Reset pin - -The node for this driver must be a child node of a SPI controller, hence -all mandatory properties described in ../spi/spi-bus.txt must be specified. - -Optional properties: -- rotation: panel rotation in degrees counter clockwise (0,90,180,270) -- backlight: phandle of the backlight device attached to the panel - -Example: - display@0{ - compatible = "adafruit,yx240qv29", "ilitek,ili9341"; - reg = <0>; - spi-max-frequency = <32000000>; - dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; - rotation = <270>; - backlight = <&backlight>; - }; diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml index 6058948a9764..c5571391ca28 100644 --- a/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml +++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml @@ -21,6 +21,7 @@ properties: compatible: items: - enum: + - adafruit,yx240qv29 # ili9341 240*320 Color on stm32f429-disco board - st,sf-tc240t-9370-t - const: ilitek,ili9341 @@ -47,31 +48,50 @@ properties: vddi-led-supply: description: Voltage supply for the LED driver (1.65 .. 3.3 V) -additionalProperties: false +unevaluatedProperties: false required: - compatible - reg - dc-gpios - - port + +if: + properties: + compatible: + contains: + enum: + - st,sf-tc240t-9370-t +then: + required: + - port examples: - |+ + #include spi { #address-cells = <1>; #size-cells = <0>; panel: display@0 { - compatible = "st,sf-tc240t-9370-t", - "ilitek,ili9341"; - reg = <0>; - spi-3wire; - spi-max-frequency = <10000000>; - dc-gpios = <&gpiod 13 0>; - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; + compatible = "st,sf-tc240t-9370-t", + "ilitek,ili9341"; + reg = <0>; + spi-3wire; + spi-max-frequency = <10000000>; + dc-gpios = <&gpiod 13 0>; + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + display@1{ + compatible = "adafruit,yx240qv29", "ilitek,ili9341"; + reg = <1>; + spi-max-frequency = <10000000>; + dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + rotation = <270>; + backlight = <&backlight>; }; + }; ... -- cgit v1.2.3 From 5ec88543063c758f49fc5e89a70386f649b65102 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 5 Jul 2022 22:52:03 +0100 Subject: dt-bindings: display: ili9341: document canaan kd233's lcd The Canaan KD233 development board has a built in LCD. Add a specific compatible for it. Reviewed-by: Rob Herring Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20220705215213.1802496-3-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml index c5571391ca28..99e0cb9440cf 100644 --- a/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml +++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml @@ -24,6 +24,7 @@ properties: - adafruit,yx240qv29 # ili9341 240*320 Color on stm32f429-disco board - st,sf-tc240t-9370-t + - canaan,kd233-tft - const: ilitek,ili9341 reg: true -- cgit v1.2.3 From 727b05e46cffd74adca96ca13e57352339875586 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 5 Jul 2022 22:52:05 +0100 Subject: dt-bindings: memory-controllers: add canaan k210 sram controller The k210 U-Boot port has been using the clocks defined in the devicetree to bring up the board's SRAM, but this violates the dt-schema. As such, move the clocks to a dedicated node with the same compatible string & document it. Signed-off-by: Conor Dooley Reviewed-by: Rob Herring Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220705215213.1802496-5-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- .../memory-controllers/canaan,k210-sram.yaml | 52 ++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/canaan,k210-sram.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/canaan,k210-sram.yaml b/Documentation/devicetree/bindings/memory-controllers/canaan,k210-sram.yaml new file mode 100644 index 000000000000..f81fb866e319 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/canaan,k210-sram.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/canaan,k210-sram.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Canaan K210 SRAM memory controller + +description: + The Canaan K210 SRAM memory controller is responsible for the system's 8 MiB + of SRAM. The controller is initialised by the bootloader, which configures + its clocks, before OS bringup. + +maintainers: + - Conor Dooley + +properties: + compatible: + enum: + - canaan,k210-sram + + clocks: + minItems: 1 + items: + - description: sram0 clock + - description: sram1 clock + - description: aisram clock + + clock-names: + minItems: 1 + items: + - const: sram0 + - const: sram1 + - const: aisram + +required: + - compatible + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + memory-controller { + compatible = "canaan,k210-sram"; + clocks = <&sysclk K210_CLK_SRAM0>, + <&sysclk K210_CLK_SRAM1>, + <&sysclk K210_CLK_AI>; + clock-names = "sram0", "sram1", "aisram"; + }; -- cgit v1.2.3 From 465c12749b363e0259a3f50d84ec34261d9ba00e Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 5 Jul 2022 22:52:06 +0100 Subject: riscv: dts: canaan: fix the k210's memory node The k210 U-Boot port has been using the clocks defined in the devicetree to bring up the board's SRAM, but this violates the dt-schema. As such, move the clocks to a dedicated node with the same compatible string. The regs property does not fit in either node, so is replaced by comments. Tested-by: Niklas Cassel Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20220705215213.1802496-6-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- arch/riscv/boot/dts/canaan/k210.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index 44d338514761..cd4eae82d8b2 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -69,11 +69,13 @@ sram: memory@80000000 { device_type = "memory"; + reg = <0x80000000 0x400000>, /* sram0 4 MiB */ + <0x80400000 0x200000>, /* sram1 2 MiB */ + <0x80600000 0x200000>; /* aisram 2 MiB */ + }; + + sram_controller: memory-controller { compatible = "canaan,k210-sram"; - reg = <0x80000000 0x400000>, - <0x80400000 0x200000>, - <0x80600000 0x200000>; - reg-names = "sram0", "sram1", "aisram"; clocks = <&sysclk K210_CLK_SRAM0>, <&sysclk K210_CLK_SRAM1>, <&sysclk K210_CLK_AI>; -- cgit v1.2.3 From 3f64510e3d8058ae13395c7f93f0ffaf3b5e568e Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 5 Jul 2022 22:52:07 +0100 Subject: riscv: dts: canaan: fix the k210's timer nodes The timers on the k210 have non standard interrupt configurations, which leads to dtbs_check warnings: k210_generic.dtb: timer@502d0000: interrupts: [[14], [15]] is too long From schema: Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml Split the timer nodes in two, so that the second timer in the IP block can actually be accessed & in the process solve the dtbs_check warning. Reviewed-by: Serge Semin Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20220705215213.1802496-7-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- arch/riscv/boot/dts/canaan/k210.dtsi | 46 +++++++++++++++++++++++++++++------- 1 file changed, 38 insertions(+), 8 deletions(-) diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index cd4eae82d8b2..72f70128d751 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -319,28 +319,58 @@ timer0: timer@502d0000 { compatible = "snps,dw-apb-timer"; - reg = <0x502D0000 0x100>; - interrupts = <14>, <15>; + reg = <0x502D0000 0x14>; + interrupts = <14>; clocks = <&sysclk K210_CLK_TIMER0>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk"; resets = <&sysrst K210_RST_TIMER0>; }; - timer1: timer@502e0000 { + timer1: timer@502d0014 { compatible = "snps,dw-apb-timer"; - reg = <0x502E0000 0x100>; - interrupts = <16>, <17>; + reg = <0x502D0014 0x14>; + interrupts = <15>; + clocks = <&sysclk K210_CLK_TIMER0>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER0>; + }; + + timer2: timer@502e0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x502E0000 0x14>; + interrupts = <16>; clocks = <&sysclk K210_CLK_TIMER1>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk"; resets = <&sysrst K210_RST_TIMER1>; }; - timer2: timer@502f0000 { + timer3: timer@502e0014 { + compatible = "snps,dw-apb-timer"; + reg = <0x502E0014 0x114>; + interrupts = <17>; + clocks = <&sysclk K210_CLK_TIMER1>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER1>; + }; + + timer4: timer@502f0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x502F0000 0x14>; + interrupts = <18>; + clocks = <&sysclk K210_CLK_TIMER2>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER2>; + }; + + timer5: timer@502f0014 { compatible = "snps,dw-apb-timer"; - reg = <0x502F0000 0x100>; - interrupts = <18>, <19>; + reg = <0x502F0014 0x14>; + interrupts = <19>; clocks = <&sysclk K210_CLK_TIMER2>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk"; -- cgit v1.2.3 From 5f4c5824d53ee27aa387477ae2e61f1b756afb7a Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 5 Jul 2022 22:52:08 +0100 Subject: riscv: dts: canaan: fix mmc node names The newly-converted-to-dt-schema binding expects the mmc node name to be '^mmc(@.*)?$' so align the devicetree with the schema. Tested-by: Niklas Cassel Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20220705215213.1802496-8-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- arch/riscv/boot/dts/canaan/canaan_kd233.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maix_go.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maixduino.dts | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/canaan/canaan_kd233.dts b/arch/riscv/boot/dts/canaan/canaan_kd233.dts index 039b92abf046..40992d495aa8 100644 --- a/arch/riscv/boot/dts/canaan/canaan_kd233.dts +++ b/arch/riscv/boot/dts/canaan/canaan_kd233.dts @@ -142,7 +142,7 @@ cs-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; status = "okay"; - slot@0 { + mmc@0 { compatible = "mmc-spi-slot"; reg = <0>; voltage-ranges = <3300 3300>; diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts index b9e30df127fe..5e809d0e11fb 100644 --- a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts @@ -189,7 +189,7 @@ cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; status = "okay"; - slot@0 { + mmc@0 { compatible = "mmc-spi-slot"; reg = <0>; voltage-ranges = <3300 3300>; diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts index 8d23401b0bbb..4be5ffac6b4a 100644 --- a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts @@ -191,7 +191,7 @@ cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; status = "okay"; - slot@0 { + mmc@0 { compatible = "mmc-spi-slot"; reg = <0>; voltage-ranges = <3300 3300>; diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts index 24fd83b43d9d..5c63f79b18ec 100644 --- a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts @@ -199,7 +199,7 @@ cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; status = "okay"; - slot@0 { + mmc@0 { compatible = "mmc-spi-slot"; reg = <0>; voltage-ranges = <3300 3300>; diff --git a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts index 25341f38292a..59f7eaf74655 100644 --- a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts +++ b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts @@ -164,7 +164,7 @@ cs-gpios = <&gpio1_0 2 GPIO_ACTIVE_LOW>; status = "okay"; - slot@0 { + mmc@0 { compatible = "mmc-spi-slot"; reg = <0>; voltage-ranges = <3300 3300>; -- cgit v1.2.3 From 3bd204cbb7c4323337ca6c7ac4eb2ea85022eee0 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 5 Jul 2022 22:52:09 +0100 Subject: riscv: dts: canaan: fix kd233 display spi frequency The binding for the ili9341 specifies a const spi-max-frequency of 10 MHz but the kd233 devicetree entry has it listed at 15 Mhz. Align the devicetree with the value in the binding. Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20220705215213.1802496-9-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- arch/riscv/boot/dts/canaan/canaan_kd233.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/canaan/canaan_kd233.dts b/arch/riscv/boot/dts/canaan/canaan_kd233.dts index 40992d495aa8..4a540158f287 100644 --- a/arch/riscv/boot/dts/canaan/canaan_kd233.dts +++ b/arch/riscv/boot/dts/canaan/canaan_kd233.dts @@ -130,7 +130,7 @@ compatible = "ilitek,ili9341"; reg = <0>; dc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; - spi-max-frequency = <15000000>; + spi-max-frequency = <10000000>; status = "disabled"; }; }; -- cgit v1.2.3 From 9bd61feb7025c94564be39af90f4083ce2e13472 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 5 Jul 2022 22:52:10 +0100 Subject: riscv: dts: canaan: use custom compatible for k210 i2s The devicetrees using the Canaan k210 all have a sound-dai-cells value of 1, whereas the standard binding example for the DesignWare i2s and other use cases suggest 0. Use a k210 specific compatible which supports this difference. Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20220705215213.1802496-10-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- arch/riscv/boot/dts/canaan/k210.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index 72f70128d751..900dc629a945 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -251,7 +251,7 @@ }; i2s0: i2s@50250000 { - compatible = "snps,designware-i2s"; + compatible = "canaan,k210-i2s", "snps,designware-i2s"; reg = <0x50250000 0x200>; interrupts = <5>; clocks = <&sysclk K210_CLK_I2S0>; @@ -260,7 +260,7 @@ }; i2s1: i2s@50260000 { - compatible = "snps,designware-i2s"; + compatible = "canaan,k210-i2s", "snps,designware-i2s"; reg = <0x50260000 0x200>; interrupts = <6>; clocks = <&sysclk K210_CLK_I2S1>; @@ -269,7 +269,7 @@ }; i2s2: i2s@50270000 { - compatible = "snps,designware-i2s"; + compatible = "canaan,k210-i2s", "snps,designware-i2s"; reg = <0x50270000 0x200>; interrupts = <7>; clocks = <&sysclk K210_CLK_I2S2>; -- cgit v1.2.3 From 719a85a2c57fd7cce65f4a746ebf83d222e0c05f Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 5 Jul 2022 22:52:11 +0100 Subject: riscv: dts: canaan: remove spi-max-frequency from controllers spi-max-frequency is a device, not a controller property and should be removed. Link: https://lore.kernel.org/lkml/20220526014141.2872567-1-robh@kernel.org/ Tested-by: Niklas Cassel Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20220705215213.1802496-11-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- arch/riscv/boot/dts/canaan/k210.dtsi | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index 900dc629a945..948dc235e39d 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -451,7 +451,6 @@ clock-names = "ssi_clk", "pclk"; resets = <&sysrst K210_RST_SPI0>; reset-names = "spi"; - spi-max-frequency = <25000000>; num-cs = <4>; reg-io-width = <4>; }; @@ -467,7 +466,6 @@ clock-names = "ssi_clk", "pclk"; resets = <&sysrst K210_RST_SPI1>; reset-names = "spi"; - spi-max-frequency = <25000000>; num-cs = <4>; reg-io-width = <4>; }; @@ -483,8 +481,7 @@ clock-names = "ssi_clk", "pclk"; resets = <&sysrst K210_RST_SPI3>; reset-names = "spi"; - /* Could possibly go up to 200 MHz */ - spi-max-frequency = <100000000>; + num-cs = <4>; reg-io-width = <4>; }; -- cgit v1.2.3 From e19f975a39f002846e144ab35a6cf15ef81fa6d8 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 5 Jul 2022 22:52:12 +0100 Subject: riscv: dts: canaan: fix bus {ranges,reg} warnings The k210 devicetrees warn about missing/empty reg and/or ranges properties: arch/riscv/boot/dts/canaan/k210.dtsi:408.22-460.5: Warning (unit_address_vs_reg): /soc/bus@52000000: node has a unit name, but no reg or ranges property arch/riscv/boot/dts/canaan/k210.dtsi:352.22-406.5: Warning (simple_bus_reg): /soc/bus@50400000: missing or empty reg/ranges property Add a ranges properties that naively caps the buses after the allocation of their last devices. Tested-by: Niklas Cassel Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20220705215213.1802496-12-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- arch/riscv/boot/dts/canaan/k210.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index 948dc235e39d..a515e5fb1af3 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -163,7 +163,7 @@ #address-cells = <1>; #size-cells = <1>; compatible = "simple-pm-bus"; - ranges; + ranges = <0x50200000 0x50200000 0x200000>; clocks = <&sysclk K210_CLK_APB0>; gpio1: gpio@50200000 { @@ -382,7 +382,7 @@ #address-cells = <1>; #size-cells = <1>; compatible = "simple-pm-bus"; - ranges; + ranges = <0x50400000 0x50400000 0x40100>; clocks = <&sysclk K210_CLK_APB1>; wdt0: watchdog@50400000 { @@ -437,7 +437,7 @@ #address-cells = <1>; #size-cells = <1>; compatible = "simple-pm-bus"; - ranges; + ranges = <0x52000000 0x52000000 0x2000200>; clocks = <&sysclk K210_CLK_APB2>; spi0: spi@52000000 { -- cgit v1.2.3 From 6990ea211c7922134697bdc5416637da3a310301 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 5 Jul 2022 22:52:13 +0100 Subject: riscv: dts: canaan: add specific compatible for kd233's LCD Add the recently introduced compatible for the LCD on the Canaan KD233. Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20220705215213.1802496-13-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- arch/riscv/boot/dts/canaan/canaan_kd233.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/canaan/canaan_kd233.dts b/arch/riscv/boot/dts/canaan/canaan_kd233.dts index 4a540158f287..b0cd0105a5bd 100644 --- a/arch/riscv/boot/dts/canaan/canaan_kd233.dts +++ b/arch/riscv/boot/dts/canaan/canaan_kd233.dts @@ -127,7 +127,7 @@ cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; panel@0 { - compatible = "ilitek,ili9341"; + compatible = "canaan,kd233-tft", "ilitek,ili9341"; reg = <0>; dc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; spi-max-frequency = <10000000>; -- cgit v1.2.3 From 0ed048137fd982a78892a51721d9e7f6b281edbd Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 5 Jul 2022 22:52:14 +0100 Subject: riscv: dts: canaan: build all devicetress if SOC_CANAAN Testing & checking the Canaan devicetrees is inconvenient as only the devicetree corresponding to SOC_CANAAN_K210_DTB_BUILTIN will be built. Change the Makefile so that all devicetrees are built by default if SOC_CANAAN but only the one specified by SOC_CANAAN_K210_DTB_BUILTIN gets built as an object. Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20220705215213.1802496-14-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- arch/riscv/boot/dts/canaan/Makefile | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/canaan/Makefile b/arch/riscv/boot/dts/canaan/Makefile index c61b08ac8554..befe4eb7527b 100644 --- a/arch/riscv/boot/dts/canaan/Makefile +++ b/arch/riscv/boot/dts/canaan/Makefile @@ -1,3 +1,9 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .dtb, $(CONFIG_SOC_CANAAN_K210_DTB_SOURCE)) -obj-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .o, $(dtb-y)) +dtb-$(CONFIG_SOC_CANAAN) += canaan_kd233.dtb +dtb-$(CONFIG_SOC_CANAAN) += k210_generic.dtb +dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_bit.dtb +dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_dock.dtb +dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_go.dtb +dtb-$(CONFIG_SOC_CANAAN) += sipeed_maixduino.dtb + +obj-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .dtb.o, $(CONFIG_SOC_CANAAN_K210_DTB_SOURCE)) -- cgit v1.2.3 From 966f6551173ac46183db6621451702a7e4a3d4b5 Mon Sep 17 00:00:00 2001 From: Schspa Shi Date: Tue, 5 Jul 2022 11:32:44 +0800 Subject: power: supply: Fix typo in power_supply_check_supplies It seems to be a typo, there is no actual BUG, but it's better to fix it to avoid any possible BUG after we change the type of supplied_from. Signed-off-by: Schspa Shi Signed-off-by: Sebastian Reichel --- drivers/power/supply/power_supply_core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/power/supply/power_supply_core.c b/drivers/power/supply/power_supply_core.c index fad5890c899e..02228d68c599 100644 --- a/drivers/power/supply/power_supply_core.c +++ b/drivers/power/supply/power_supply_core.c @@ -263,13 +263,13 @@ static int power_supply_check_supplies(struct power_supply *psy) return 0; /* All supplies found, allocate char ** array for filling */ - psy->supplied_from = devm_kzalloc(&psy->dev, sizeof(psy->supplied_from), + psy->supplied_from = devm_kzalloc(&psy->dev, sizeof(*psy->supplied_from), GFP_KERNEL); if (!psy->supplied_from) return -ENOMEM; *psy->supplied_from = devm_kcalloc(&psy->dev, - cnt - 1, sizeof(char *), + cnt - 1, sizeof(**psy->supplied_from), GFP_KERNEL); if (!*psy->supplied_from) return -ENOMEM; -- cgit v1.2.3 From 491f1f483f4284fb2db0e09a5de4664683a25a88 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 29 Jun 2022 14:38:04 +0200 Subject: dt-bindings: power: reset: qcom,pshold: convert to dtschema Convert the Qualcomm Power Supply Hold Reset bindings to DT schema. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Sebastian Reichel --- .../bindings/power/reset/msm-poweroff.txt | 17 ----------- .../bindings/power/reset/qcom,pshold.yaml | 35 ++++++++++++++++++++++ 2 files changed, 35 insertions(+), 17 deletions(-) delete mode 100644 Documentation/devicetree/bindings/power/reset/msm-poweroff.txt create mode 100644 Documentation/devicetree/bindings/power/reset/qcom,pshold.yaml diff --git a/Documentation/devicetree/bindings/power/reset/msm-poweroff.txt b/Documentation/devicetree/bindings/power/reset/msm-poweroff.txt deleted file mode 100644 index ce44ad357565..000000000000 --- a/Documentation/devicetree/bindings/power/reset/msm-poweroff.txt +++ /dev/null @@ -1,17 +0,0 @@ -MSM Restart Driver - -A power supply hold (ps-hold) bit is set to power the msm chipsets. -Clearing that bit allows us to restart/poweroff. The difference -between poweroff and restart is determined by unique power manager IC -settings. - -Required Properties: --compatible: "qcom,pshold" --reg: Specifies the physical address of the ps-hold register - -Example: - - restart@fc4ab000 { - compatible = "qcom,pshold"; - reg = <0xfc4ab000 0x4>; - }; diff --git a/Documentation/devicetree/bindings/power/reset/qcom,pshold.yaml b/Documentation/devicetree/bindings/power/reset/qcom,pshold.yaml new file mode 100644 index 000000000000..527962d54a8f --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/qcom,pshold.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/reset/qcom,pshold.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SoC restart and power off + +maintainers: + - Bjorn Andersson + +description: + A power supply hold (ps-hold) bit is set to power the Qualcomm chipsets. + Clearing that bit allows us to restart/power off. The difference between + power off and restart is determined by unique power manager IC settings. + +properties: + compatible: + const: qcom,pshold + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + reset-controller@fc4ab000 { + compatible = "qcom,pshold"; + reg = <0xfc4ab000 0x4>; + }; -- cgit v1.2.3 From e8b60d9c0a852ec563e2227a5610092c3f4b85b0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 23 Jun 2022 16:31:57 +0200 Subject: power: supply: ab8500: Add MAINTAINERS entry I am maintaining these drivers so add patterns to MAINTAINERS for them. Signed-off-by: Linus Walleij Signed-off-by: Sebastian Reichel --- MAINTAINERS | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a6d3bd9d2a8d..ffafa78732c5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -260,6 +260,11 @@ W: http://www.adaptec.com/ F: Documentation/scsi/aacraid.rst F: drivers/scsi/aacraid/ +AB8500 BATTERY AND CHARGER DRIVERS +M: Linus Walleij +F: Documentation/devicetree/bindings/power/supply/*ab8500* +F: drivers/power/supply/*ab8500* + ABI/API L: linux-api@vger.kernel.org F: include/linux/syscalls.h -- cgit v1.2.3 From 6c50a08d9dd323a6a2e212f78059116edad8cc4e Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 23 Jun 2022 16:25:45 +0200 Subject: power: supply: ab8500: Drop external charger leftovers Some leftover code for external chargers only used with unreleased ASIC revisions and the header file for the unsupported PM2301 was left behind in an earlier cleanup, fix it by deleting the remnants. Signed-off-by: Linus Walleij Signed-off-by: Sebastian Reichel --- drivers/power/supply/ab8500-chargalg.h | 4 - drivers/power/supply/ab8500_chargalg.c | 23 +- drivers/power/supply/ab8500_charger.c | 45 +-- drivers/power/supply/pm2301_charger.h | 492 --------------------------------- 4 files changed, 2 insertions(+), 562 deletions(-) delete mode 100644 drivers/power/supply/pm2301_charger.h diff --git a/drivers/power/supply/ab8500-chargalg.h b/drivers/power/supply/ab8500-chargalg.h index f47a0061c36a..8534d067ba95 100644 --- a/drivers/power/supply/ab8500-chargalg.h +++ b/drivers/power/supply/ab8500-chargalg.h @@ -34,7 +34,6 @@ struct ux500_charger_ops { * @max_out_volt_uv maximum output charger voltage in uV * @max_out_curr_ua maximum output charger current in uA * @enabled indicates if this charger is used or not - * @external external charger unit (pm2xxx) */ struct ux500_charger { struct power_supply *psy; @@ -43,9 +42,6 @@ struct ux500_charger { int max_out_curr_ua; int wdt_refresh; bool enabled; - bool external; }; -extern struct blocking_notifier_head charger_notifier_list; - #endif /* _AB8500_CHARGALG_H_ */ diff --git a/drivers/power/supply/ab8500_chargalg.c b/drivers/power/supply/ab8500_chargalg.c index f4c017527de4..d56147f7eaec 100644 --- a/drivers/power/supply/ab8500_chargalg.c +++ b/drivers/power/supply/ab8500_chargalg.c @@ -246,9 +246,6 @@ struct ab8500_chargalg { struct kobject chargalg_kobject; }; -/*External charger prepare notifier*/ -BLOCKING_NOTIFIER_HEAD(charger_notifier_list); - /* Main battery properties */ static enum power_supply_property ab8500_chargalg_props[] = { POWER_SUPPLY_PROP_STATUS, @@ -343,8 +340,7 @@ static int ab8500_chargalg_check_charger_enable(struct ab8500_chargalg *di) return di->usb_chg->ops.check_enable(di->usb_chg, bi->constant_charge_voltage_max_uv, bi->constant_charge_current_max_ua); - } else if ((di->chg_info.charger_type & AC_CHG) && - !(di->ac_chg->external)) { + } else if (di->chg_info.charger_type & AC_CHG) { return di->ac_chg->ops.check_enable(di->ac_chg, bi->constant_charge_voltage_max_uv, bi->constant_charge_current_max_ua); @@ -473,15 +469,6 @@ static int ab8500_chargalg_kick_watchdog(struct ab8500_chargalg *di) /* Check if charger exists and kick watchdog if charging */ if (di->ac_chg && di->ac_chg->ops.kick_wd && di->chg_info.online_chg & AC_CHG) { - /* - * If AB charger watchdog expired, pm2xxx charging - * gets disabled. To be safe, kick both AB charger watchdog - * and pm2xxx watchdog. - */ - if (di->ac_chg->external && - di->usb_chg && di->usb_chg->ops.kick_wd) - di->usb_chg->ops.kick_wd(di->usb_chg); - return di->ac_chg->ops.kick_wd(di->ac_chg); } else if (di->usb_chg && di->usb_chg->ops.kick_wd && di->chg_info.online_chg & USB_CHG) @@ -517,14 +504,6 @@ static int ab8500_chargalg_ac_en(struct ab8500_chargalg *di, int enable, di->chg_info.ac_iset_ua = iset_ua; di->chg_info.ac_vset_uv = vset_uv; - /* Enable external charger */ - if (enable && di->ac_chg->external && - !ab8500_chargalg_ex_ac_enable_toggle) { - blocking_notifier_call_chain(&charger_notifier_list, - 0, di->dev); - ab8500_chargalg_ex_ac_enable_toggle++; - } - return di->ac_chg->ops.enable(di->ac_chg, enable, vset_uv, iset_ua); } diff --git a/drivers/power/supply/ab8500_charger.c b/drivers/power/supply/ab8500_charger.c index d04d087caa50..9701c3e735e7 100644 --- a/drivers/power/supply/ab8500_charger.c +++ b/drivers/power/supply/ab8500_charger.c @@ -1716,29 +1716,6 @@ static int ab8500_charger_usb_en(struct ux500_charger *charger, return ret; } -static int ab8500_external_charger_prepare(struct notifier_block *charger_nb, - unsigned long event, void *data) -{ - int ret; - struct device *dev = data; - /*Toggle External charger control pin*/ - ret = abx500_set_register_interruptible(dev, AB8500_SYS_CTRL1_BLOCK, - AB8500_SYS_CHARGER_CONTROL_REG, - EXTERNAL_CHARGER_DISABLE_REG_VAL); - if (ret < 0) { - dev_err(dev, "write reg failed %d\n", ret); - goto out; - } - ret = abx500_set_register_interruptible(dev, AB8500_SYS_CTRL1_BLOCK, - AB8500_SYS_CHARGER_CONTROL_REG, - EXTERNAL_CHARGER_ENABLE_REG_VAL); - if (ret < 0) - dev_err(dev, "Write reg failed %d\n", ret); - -out: - return ret; -} - /** * ab8500_charger_usb_check_enable() - enable usb charging * @charger: pointer to the ux500_charger structure @@ -3316,10 +3293,6 @@ static int __maybe_unused ab8500_charger_suspend(struct device *dev) return 0; } -static struct notifier_block charger_nb = { - .notifier_call = ab8500_external_charger_prepare, -}; - static char *supply_interface[] = { "ab8500_chargalg", "ab8500_fg", @@ -3540,7 +3513,6 @@ static int ab8500_charger_probe(struct platform_device *pdev) */ if (!is_ab8505(di->parent)) di->ac_chg.enabled = true; - di->ac_chg.external = false; /* USB supply */ /* ux500_charger sub-class */ @@ -3553,7 +3525,6 @@ static int ab8500_charger_probe(struct platform_device *pdev) di->usb_chg.max_out_curr_ua = ab8500_charge_output_curr_map[ARRAY_SIZE(ab8500_charge_output_curr_map) - 1]; di->usb_chg.wdt_refresh = CHG_WD_INTERVAL; - di->usb_chg.external = false; di->usb_state.usb_current_ua = -1; mutex_init(&di->charger_attached_mutex); @@ -3677,17 +3648,11 @@ static int ab8500_charger_probe(struct platform_device *pdev) goto remove_ab8500_bm; } - /* Notifier for external charger enabling */ - if (!di->ac_chg.enabled) - blocking_notifier_chain_register( - &charger_notifier_list, &charger_nb); - - di->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2); if (IS_ERR_OR_NULL(di->usb_phy)) { dev_err(dev, "failed to get usb transceiver\n"); ret = -EINVAL; - goto out_charger_notifier; + goto remove_ab8500_bm; } di->nb.notifier_call = ab8500_charger_usb_notifier_call; ret = usb_register_notifier(di->usb_phy, &di->nb); @@ -3696,7 +3661,6 @@ static int ab8500_charger_probe(struct platform_device *pdev) goto put_usb_phy; } - ret = component_master_add_with_match(&pdev->dev, &ab8500_charger_comp_ops, match); @@ -3711,10 +3675,6 @@ free_notifier: usb_unregister_notifier(di->usb_phy, &di->nb); put_usb_phy: usb_put_phy(di->usb_phy); -out_charger_notifier: - if (!di->ac_chg.enabled) - blocking_notifier_chain_unregister( - &charger_notifier_list, &charger_nb); remove_ab8500_bm: ab8500_bm_of_remove(di->usb_chg.psy, di->bm); return ret; @@ -3729,9 +3689,6 @@ static int ab8500_charger_remove(struct platform_device *pdev) usb_unregister_notifier(di->usb_phy, &di->nb); ab8500_bm_of_remove(di->usb_chg.psy, di->bm); usb_put_phy(di->usb_phy); - if (!di->ac_chg.enabled) - blocking_notifier_chain_unregister( - &charger_notifier_list, &charger_nb); return 0; } diff --git a/drivers/power/supply/pm2301_charger.h b/drivers/power/supply/pm2301_charger.h deleted file mode 100644 index 74397e377982..000000000000 --- a/drivers/power/supply/pm2301_charger.h +++ /dev/null @@ -1,492 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) ST-Ericsson SA 2012 - * - * PM2301 power supply interface - */ - -#ifndef PM2301_CHARGER_H -#define PM2301_CHARGER_H - -/* Watchdog timeout constant */ -#define WD_TIMER 0x30 /* 4min */ -#define WD_KICK_INTERVAL (30 * HZ) - -#define PM2XXX_NUM_INT_REG 0x6 - -/* Constant voltage/current */ -#define PM2XXX_CONST_CURR 0x0 -#define PM2XXX_CONST_VOLT 0x1 - -/* Lowest charger voltage is 3.39V -> 0x4E */ -#define LOW_VOLT_REG 0x4E - -#define PM2XXX_BATT_CTRL_REG1 0x00 -#define PM2XXX_BATT_CTRL_REG2 0x01 -#define PM2XXX_BATT_CTRL_REG3 0x02 -#define PM2XXX_BATT_CTRL_REG4 0x03 -#define PM2XXX_BATT_CTRL_REG5 0x04 -#define PM2XXX_BATT_CTRL_REG6 0x05 -#define PM2XXX_BATT_CTRL_REG7 0x06 -#define PM2XXX_BATT_CTRL_REG8 0x07 -#define PM2XXX_NTC_CTRL_REG1 0x08 -#define PM2XXX_NTC_CTRL_REG2 0x09 -#define PM2XXX_BATT_CTRL_REG9 0x0A -#define PM2XXX_BATT_STAT_REG1 0x0B -#define PM2XXX_INP_VOLT_VPWR2 0x11 -#define PM2XXX_INP_DROP_VPWR2 0x13 -#define PM2XXX_INP_VOLT_VPWR1 0x15 -#define PM2XXX_INP_DROP_VPWR1 0x17 -#define PM2XXX_INP_MODE_VPWR 0x18 -#define PM2XXX_BATT_WD_KICK 0x70 -#define PM2XXX_DEV_VER_STAT 0x0C -#define PM2XXX_THERM_WARN_CTRL_REG 0x20 -#define PM2XXX_BATT_DISC_REG 0x21 -#define PM2XXX_BATT_LOW_LEV_COMP_REG 0x22 -#define PM2XXX_BATT_LOW_LEV_VAL_REG 0x23 -#define PM2XXX_I2C_PAD_CTRL_REG 0x24 -#define PM2XXX_SW_CTRL_REG 0x26 -#define PM2XXX_LED_CTRL_REG 0x28 - -#define PM2XXX_REG_INT1 0x40 -#define PM2XXX_MASK_REG_INT1 0x50 -#define PM2XXX_SRCE_REG_INT1 0x60 -#define PM2XXX_REG_INT2 0x41 -#define PM2XXX_MASK_REG_INT2 0x51 -#define PM2XXX_SRCE_REG_INT2 0x61 -#define PM2XXX_REG_INT3 0x42 -#define PM2XXX_MASK_REG_INT3 0x52 -#define PM2XXX_SRCE_REG_INT3 0x62 -#define PM2XXX_REG_INT4 0x43 -#define PM2XXX_MASK_REG_INT4 0x53 -#define PM2XXX_SRCE_REG_INT4 0x63 -#define PM2XXX_REG_INT5 0x44 -#define PM2XXX_MASK_REG_INT5 0x54 -#define PM2XXX_SRCE_REG_INT5 0x64 -#define PM2XXX_REG_INT6 0x45 -#define PM2XXX_MASK_REG_INT6 0x55 -#define PM2XXX_SRCE_REG_INT6 0x65 - -#define VPWR_OVV 0x0 -#define VSYSTEM_OVV 0x1 - -/* control Reg 1 */ -#define PM2XXX_CH_RESUME_EN 0x1 -#define PM2XXX_CH_RESUME_DIS 0x0 - -/* control Reg 2 */ -#define PM2XXX_CH_AUTO_RESUME_EN 0X2 -#define PM2XXX_CH_AUTO_RESUME_DIS 0X0 -#define PM2XXX_CHARGER_ENA 0x4 -#define PM2XXX_CHARGER_DIS 0x0 - -/* control Reg 3 */ -#define PM2XXX_CH_WD_CC_PHASE_OFF 0x0 -#define PM2XXX_CH_WD_CC_PHASE_5MIN 0x1 -#define PM2XXX_CH_WD_CC_PHASE_10MIN 0x2 -#define PM2XXX_CH_WD_CC_PHASE_30MIN 0x3 -#define PM2XXX_CH_WD_CC_PHASE_60MIN 0x4 -#define PM2XXX_CH_WD_CC_PHASE_120MIN 0x5 -#define PM2XXX_CH_WD_CC_PHASE_240MIN 0x6 -#define PM2XXX_CH_WD_CC_PHASE_360MIN 0x7 - -#define PM2XXX_CH_WD_CV_PHASE_OFF (0x0<<3) -#define PM2XXX_CH_WD_CV_PHASE_5MIN (0x1<<3) -#define PM2XXX_CH_WD_CV_PHASE_10MIN (0x2<<3) -#define PM2XXX_CH_WD_CV_PHASE_30MIN (0x3<<3) -#define PM2XXX_CH_WD_CV_PHASE_60MIN (0x4<<3) -#define PM2XXX_CH_WD_CV_PHASE_120MIN (0x5<<3) -#define PM2XXX_CH_WD_CV_PHASE_240MIN (0x6<<3) -#define PM2XXX_CH_WD_CV_PHASE_360MIN (0x7<<3) - -/* control Reg 4 */ -#define PM2XXX_CH_WD_PRECH_PHASE_OFF 0x0 -#define PM2XXX_CH_WD_PRECH_PHASE_1MIN 0x1 -#define PM2XXX_CH_WD_PRECH_PHASE_5MIN 0x2 -#define PM2XXX_CH_WD_PRECH_PHASE_10MIN 0x3 -#define PM2XXX_CH_WD_PRECH_PHASE_30MIN 0x4 -#define PM2XXX_CH_WD_PRECH_PHASE_60MIN 0x5 -#define PM2XXX_CH_WD_PRECH_PHASE_120MIN 0x6 -#define PM2XXX_CH_WD_PRECH_PHASE_240MIN 0x7 - -/* control Reg 5 */ -#define PM2XXX_CH_WD_AUTO_TIMEOUT_NONE 0x0 -#define PM2XXX_CH_WD_AUTO_TIMEOUT_20MIN 0x1 - -/* control Reg 6 */ -#define PM2XXX_DIR_CH_CC_CURRENT_MASK 0x0F -#define PM2XXX_DIR_CH_CC_CURRENT_200MA 0x0 -#define PM2XXX_DIR_CH_CC_CURRENT_400MA 0x2 -#define PM2XXX_DIR_CH_CC_CURRENT_600MA 0x3 -#define PM2XXX_DIR_CH_CC_CURRENT_800MA 0x4 -#define PM2XXX_DIR_CH_CC_CURRENT_1000MA 0x5 -#define PM2XXX_DIR_CH_CC_CURRENT_1200MA 0x6 -#define PM2XXX_DIR_CH_CC_CURRENT_1400MA 0x7 -#define PM2XXX_DIR_CH_CC_CURRENT_1600MA 0x8 -#define PM2XXX_DIR_CH_CC_CURRENT_1800MA 0x9 -#define PM2XXX_DIR_CH_CC_CURRENT_2000MA 0xA -#define PM2XXX_DIR_CH_CC_CURRENT_2200MA 0xB -#define PM2XXX_DIR_CH_CC_CURRENT_2400MA 0xC -#define PM2XXX_DIR_CH_CC_CURRENT_2600MA 0xD -#define PM2XXX_DIR_CH_CC_CURRENT_2800MA 0xE -#define PM2XXX_DIR_CH_CC_CURRENT_3000MA 0xF - -#define PM2XXX_CH_PRECH_CURRENT_MASK 0x30 -#define PM2XXX_CH_PRECH_CURRENT_25MA (0x0<<4) -#define PM2XXX_CH_PRECH_CURRENT_50MA (0x1<<4) -#define PM2XXX_CH_PRECH_CURRENT_75MA (0x2<<4) -#define PM2XXX_CH_PRECH_CURRENT_100MA (0x3<<4) - -#define PM2XXX_CH_EOC_CURRENT_MASK 0xC0 -#define PM2XXX_CH_EOC_CURRENT_100MA (0x0<<6) -#define PM2XXX_CH_EOC_CURRENT_150MA (0x1<<6) -#define PM2XXX_CH_EOC_CURRENT_300MA (0x2<<6) -#define PM2XXX_CH_EOC_CURRENT_400MA (0x3<<6) - -/* control Reg 7 */ -#define PM2XXX_CH_PRECH_VOL_2_5 0x0 -#define PM2XXX_CH_PRECH_VOL_2_7 0x1 -#define PM2XXX_CH_PRECH_VOL_2_9 0x2 -#define PM2XXX_CH_PRECH_VOL_3_1 0x3 - -#define PM2XXX_CH_VRESUME_VOL_3_2 (0x0<<2) -#define PM2XXX_CH_VRESUME_VOL_3_4 (0x1<<2) -#define PM2XXX_CH_VRESUME_VOL_3_6 (0x2<<2) -#define PM2XXX_CH_VRESUME_VOL_3_8 (0x3<<2) - -/* control Reg 8 */ -#define PM2XXX_CH_VOLT_MASK 0x3F -#define PM2XXX_CH_VOLT_3_5 0x0 -#define PM2XXX_CH_VOLT_3_5225 0x1 -#define PM2XXX_CH_VOLT_3_6 0x4 -#define PM2XXX_CH_VOLT_3_7 0x8 -#define PM2XXX_CH_VOLT_4_0 0x14 -#define PM2XXX_CH_VOLT_4_175 0x1B -#define PM2XXX_CH_VOLT_4_2 0x1C -#define PM2XXX_CH_VOLT_4_275 0x1F -#define PM2XXX_CH_VOLT_4_3 0x20 - -/*NTC control register 1*/ -#define PM2XXX_BTEMP_HIGH_TH_45 0x0 -#define PM2XXX_BTEMP_HIGH_TH_50 0x1 -#define PM2XXX_BTEMP_HIGH_TH_55 0x2 -#define PM2XXX_BTEMP_HIGH_TH_60 0x3 -#define PM2XXX_BTEMP_HIGH_TH_65 0x4 - -#define PM2XXX_BTEMP_LOW_TH_N5 (0x0<<3) -#define PM2XXX_BTEMP_LOW_TH_0 (0x1<<3) -#define PM2XXX_BTEMP_LOW_TH_5 (0x2<<3) -#define PM2XXX_BTEMP_LOW_TH_10 (0x3<<3) - -/*NTC control register 2*/ -#define PM2XXX_NTC_BETA_COEFF_3477 0x0 -#define PM2XXX_NTC_BETA_COEFF_3964 0x1 - -#define PM2XXX_NTC_RES_10K (0x0<<2) -#define PM2XXX_NTC_RES_47K (0x1<<2) -#define PM2XXX_NTC_RES_100K (0x2<<2) -#define PM2XXX_NTC_RES_NO_NTC (0x3<<2) - -/* control Reg 9 */ -#define PM2XXX_CH_CC_MODEDROP_EN 1 -#define PM2XXX_CH_CC_MODEDROP_DIS 0 - -#define PM2XXX_CH_CC_REDUCED_CURRENT_100MA (0x0<<1) -#define PM2XXX_CH_CC_REDUCED_CURRENT_200MA (0x1<<1) -#define PM2XXX_CH_CC_REDUCED_CURRENT_400MA (0x2<<1) -#define PM2XXX_CH_CC_REDUCED_CURRENT_IDENT (0x3<<1) - -#define PM2XXX_CHARCHING_INFO_DIS (0<<3) -#define PM2XXX_CHARCHING_INFO_EN (1<<3) - -#define PM2XXX_CH_150MV_DROP_300MV (0<<4) -#define PM2XXX_CH_150MV_DROP_150MV (1<<4) - - -/* charger status register */ -#define PM2XXX_CHG_STATUS_OFF 0x0 -#define PM2XXX_CHG_STATUS_ON 0x1 -#define PM2XXX_CHG_STATUS_FULL 0x2 -#define PM2XXX_CHG_STATUS_ERR 0x3 -#define PM2XXX_CHG_STATUS_WAIT 0x4 -#define PM2XXX_CHG_STATUS_NOBAT 0x5 - -/* Input charger voltage VPWR2 */ -#define PM2XXX_VPWR2_OVV_6_0 0x0 -#define PM2XXX_VPWR2_OVV_6_3 0x1 -#define PM2XXX_VPWR2_OVV_10 0x2 -#define PM2XXX_VPWR2_OVV_NONE 0x3 - -/* Input charger drop VPWR2 */ -#define PM2XXX_VPWR2_HW_OPT_EN (0x1<<4) -#define PM2XXX_VPWR2_HW_OPT_DIS (0x0<<4) - -#define PM2XXX_VPWR2_VALID_EN (0x1<<3) -#define PM2XXX_VPWR2_VALID_DIS (0x0<<3) - -#define PM2XXX_VPWR2_DROP_EN (0x1<<2) -#define PM2XXX_VPWR2_DROP_DIS (0x0<<2) - -/* Input charger voltage VPWR1 */ -#define PM2XXX_VPWR1_OVV_6_0 0x0 -#define PM2XXX_VPWR1_OVV_6_3 0x1 -#define PM2XXX_VPWR1_OVV_10 0x2 -#define PM2XXX_VPWR1_OVV_NONE 0x3 - -/* Input charger drop VPWR1 */ -#define PM2XXX_VPWR1_HW_OPT_EN (0x1<<4) -#define PM2XXX_VPWR1_HW_OPT_DIS (0x0<<4) - -#define PM2XXX_VPWR1_VALID_EN (0x1<<3) -#define PM2XXX_VPWR1_VALID_DIS (0x0<<3) - -#define PM2XXX_VPWR1_DROP_EN (0x1<<2) -#define PM2XXX_VPWR1_DROP_DIS (0x0<<2) - -/* Battery low level comparator control register */ -#define PM2XXX_VBAT_LOW_MONITORING_DIS 0x0 -#define PM2XXX_VBAT_LOW_MONITORING_ENA 0x1 - -/* Battery low level value control register */ -#define PM2XXX_VBAT_LOW_LEVEL_2_3 0x0 -#define PM2XXX_VBAT_LOW_LEVEL_2_4 0x1 -#define PM2XXX_VBAT_LOW_LEVEL_2_5 0x2 -#define PM2XXX_VBAT_LOW_LEVEL_2_6 0x3 -#define PM2XXX_VBAT_LOW_LEVEL_2_7 0x4 -#define PM2XXX_VBAT_LOW_LEVEL_2_8 0x5 -#define PM2XXX_VBAT_LOW_LEVEL_2_9 0x6 -#define PM2XXX_VBAT_LOW_LEVEL_3_0 0x7 -#define PM2XXX_VBAT_LOW_LEVEL_3_1 0x8 -#define PM2XXX_VBAT_LOW_LEVEL_3_2 0x9 -#define PM2XXX_VBAT_LOW_LEVEL_3_3 0xA -#define PM2XXX_VBAT_LOW_LEVEL_3_4 0xB -#define PM2XXX_VBAT_LOW_LEVEL_3_5 0xC -#define PM2XXX_VBAT_LOW_LEVEL_3_6 0xD -#define PM2XXX_VBAT_LOW_LEVEL_3_7 0xE -#define PM2XXX_VBAT_LOW_LEVEL_3_8 0xF -#define PM2XXX_VBAT_LOW_LEVEL_3_9 0x10 -#define PM2XXX_VBAT_LOW_LEVEL_4_0 0x11 -#define PM2XXX_VBAT_LOW_LEVEL_4_1 0x12 -#define PM2XXX_VBAT_LOW_LEVEL_4_2 0x13 - -/* SW CTRL */ -#define PM2XXX_SWCTRL_HW 0x0 -#define PM2XXX_SWCTRL_SW 0x1 - - -/* LED Driver Control */ -#define PM2XXX_LED_CURRENT_MASK 0x0C -#define PM2XXX_LED_CURRENT_2_5MA (0X0<<2) -#define PM2XXX_LED_CURRENT_1MA (0X1<<2) -#define PM2XXX_LED_CURRENT_5MA (0X2<<2) -#define PM2XXX_LED_CURRENT_10MA (0X3<<2) - -#define PM2XXX_LED_SELECT_MASK 0x02 -#define PM2XXX_LED_SELECT_EN (0X0<<1) -#define PM2XXX_LED_SELECT_DIS (0X1<<1) - -#define PM2XXX_ANTI_OVERSHOOT_MASK 0x01 -#define PM2XXX_ANTI_OVERSHOOT_DIS 0X0 -#define PM2XXX_ANTI_OVERSHOOT_EN 0X1 - -enum pm2xxx_reg_int1 { - PM2XXX_INT1_ITVBATDISCONNECT = 0x02, - PM2XXX_INT1_ITVBATLOWR = 0x04, - PM2XXX_INT1_ITVBATLOWF = 0x08, -}; - -enum pm2xxx_mask_reg_int1 { - PM2XXX_INT1_M_ITVBATDISCONNECT = 0x02, - PM2XXX_INT1_M_ITVBATLOWR = 0x04, - PM2XXX_INT1_M_ITVBATLOWF = 0x08, -}; - -enum pm2xxx_source_reg_int1 { - PM2XXX_INT1_S_ITVBATDISCONNECT = 0x02, - PM2XXX_INT1_S_ITVBATLOWR = 0x04, - PM2XXX_INT1_S_ITVBATLOWF = 0x08, -}; - -enum pm2xxx_reg_int2 { - PM2XXX_INT2_ITVPWR2PLUG = 0x01, - PM2XXX_INT2_ITVPWR2UNPLUG = 0x02, - PM2XXX_INT2_ITVPWR1PLUG = 0x04, - PM2XXX_INT2_ITVPWR1UNPLUG = 0x08, -}; - -enum pm2xxx_mask_reg_int2 { - PM2XXX_INT2_M_ITVPWR2PLUG = 0x01, - PM2XXX_INT2_M_ITVPWR2UNPLUG = 0x02, - PM2XXX_INT2_M_ITVPWR1PLUG = 0x04, - PM2XXX_INT2_M_ITVPWR1UNPLUG = 0x08, -}; - -enum pm2xxx_source_reg_int2 { - PM2XXX_INT2_S_ITVPWR2PLUG = 0x03, - PM2XXX_INT2_S_ITVPWR1PLUG = 0x0c, -}; - -enum pm2xxx_reg_int3 { - PM2XXX_INT3_ITCHPRECHARGEWD = 0x01, - PM2XXX_INT3_ITCHCCWD = 0x02, - PM2XXX_INT3_ITCHCVWD = 0x04, - PM2XXX_INT3_ITAUTOTIMEOUTWD = 0x08, -}; - -enum pm2xxx_mask_reg_int3 { - PM2XXX_INT3_M_ITCHPRECHARGEWD = 0x01, - PM2XXX_INT3_M_ITCHCCWD = 0x02, - PM2XXX_INT3_M_ITCHCVWD = 0x04, - PM2XXX_INT3_M_ITAUTOTIMEOUTWD = 0x08, -}; - -enum pm2xxx_source_reg_int3 { - PM2XXX_INT3_S_ITCHPRECHARGEWD = 0x01, - PM2XXX_INT3_S_ITCHCCWD = 0x02, - PM2XXX_INT3_S_ITCHCVWD = 0x04, - PM2XXX_INT3_S_ITAUTOTIMEOUTWD = 0x08, -}; - -enum pm2xxx_reg_int4 { - PM2XXX_INT4_ITBATTEMPCOLD = 0x01, - PM2XXX_INT4_ITBATTEMPHOT = 0x02, - PM2XXX_INT4_ITVPWR2OVV = 0x04, - PM2XXX_INT4_ITVPWR1OVV = 0x08, - PM2XXX_INT4_ITCHARGINGON = 0x10, - PM2XXX_INT4_ITVRESUME = 0x20, - PM2XXX_INT4_ITBATTFULL = 0x40, - PM2XXX_INT4_ITCVPHASE = 0x80, -}; - -enum pm2xxx_mask_reg_int4 { - PM2XXX_INT4_M_ITBATTEMPCOLD = 0x01, - PM2XXX_INT4_M_ITBATTEMPHOT = 0x02, - PM2XXX_INT4_M_ITVPWR2OVV = 0x04, - PM2XXX_INT4_M_ITVPWR1OVV = 0x08, - PM2XXX_INT4_M_ITCHARGINGON = 0x10, - PM2XXX_INT4_M_ITVRESUME = 0x20, - PM2XXX_INT4_M_ITBATTFULL = 0x40, - PM2XXX_INT4_M_ITCVPHASE = 0x80, -}; - -enum pm2xxx_source_reg_int4 { - PM2XXX_INT4_S_ITBATTEMPCOLD = 0x01, - PM2XXX_INT4_S_ITBATTEMPHOT = 0x02, - PM2XXX_INT4_S_ITVPWR2OVV = 0x04, - PM2XXX_INT4_S_ITVPWR1OVV = 0x08, - PM2XXX_INT4_S_ITCHARGINGON = 0x10, - PM2XXX_INT4_S_ITVRESUME = 0x20, - PM2XXX_INT4_S_ITBATTFULL = 0x40, - PM2XXX_INT4_S_ITCVPHASE = 0x80, -}; - -enum pm2xxx_reg_int5 { - PM2XXX_INT5_ITTHERMALSHUTDOWNRISE = 0x01, - PM2XXX_INT5_ITTHERMALSHUTDOWNFALL = 0x02, - PM2XXX_INT5_ITTHERMALWARNINGRISE = 0x04, - PM2XXX_INT5_ITTHERMALWARNINGFALL = 0x08, - PM2XXX_INT5_ITVSYSTEMOVV = 0x10, -}; - -enum pm2xxx_mask_reg_int5 { - PM2XXX_INT5_M_ITTHERMALSHUTDOWNRISE = 0x01, - PM2XXX_INT5_M_ITTHERMALSHUTDOWNFALL = 0x02, - PM2XXX_INT5_M_ITTHERMALWARNINGRISE = 0x04, - PM2XXX_INT5_M_ITTHERMALWARNINGFALL = 0x08, - PM2XXX_INT5_M_ITVSYSTEMOVV = 0x10, -}; - -enum pm2xxx_source_reg_int5 { - PM2XXX_INT5_S_ITTHERMALSHUTDOWNRISE = 0x01, - PM2XXX_INT5_S_ITTHERMALSHUTDOWNFALL = 0x02, - PM2XXX_INT5_S_ITTHERMALWARNINGRISE = 0x04, - PM2XXX_INT5_S_ITTHERMALWARNINGFALL = 0x08, - PM2XXX_INT5_S_ITVSYSTEMOVV = 0x10, -}; - -enum pm2xxx_reg_int6 { - PM2XXX_INT6_ITVPWR2DROP = 0x01, - PM2XXX_INT6_ITVPWR1DROP = 0x02, - PM2XXX_INT6_ITVPWR2VALIDRISE = 0x04, - PM2XXX_INT6_ITVPWR2VALIDFALL = 0x08, - PM2XXX_INT6_ITVPWR1VALIDRISE = 0x10, - PM2XXX_INT6_ITVPWR1VALIDFALL = 0x20, -}; - -enum pm2xxx_mask_reg_int6 { - PM2XXX_INT6_M_ITVPWR2DROP = 0x01, - PM2XXX_INT6_M_ITVPWR1DROP = 0x02, - PM2XXX_INT6_M_ITVPWR2VALIDRISE = 0x04, - PM2XXX_INT6_M_ITVPWR2VALIDFALL = 0x08, - PM2XXX_INT6_M_ITVPWR1VALIDRISE = 0x10, - PM2XXX_INT6_M_ITVPWR1VALIDFALL = 0x20, -}; - -enum pm2xxx_source_reg_int6 { - PM2XXX_INT6_S_ITVPWR2DROP = 0x01, - PM2XXX_INT6_S_ITVPWR1DROP = 0x02, - PM2XXX_INT6_S_ITVPWR2VALIDRISE = 0x04, - PM2XXX_INT6_S_ITVPWR2VALIDFALL = 0x08, - PM2XXX_INT6_S_ITVPWR1VALIDRISE = 0x10, - PM2XXX_INT6_S_ITVPWR1VALIDFALL = 0x20, -}; - -struct pm2xxx_charger_info { - int charger_connected; - int charger_online; - int cv_active; - bool wd_expired; -}; - -struct pm2xxx_charger_event_flags { - bool mainextchnotok; - bool main_thermal_prot; - bool ovv; - bool chgwdexp; -}; - -struct pm2xxx_interrupts { - u8 reg[PM2XXX_NUM_INT_REG]; - int (*handler[PM2XXX_NUM_INT_REG])(void *, int); -}; - -struct pm2xxx_config { - struct i2c_client *pm2xxx_i2c; - struct i2c_device_id *pm2xxx_id; -}; - -struct pm2xxx_irq { - char *name; - irqreturn_t (*isr)(int irq, void *data); -}; - -struct pm2xxx_charger { - struct device *dev; - u8 chip_id; - bool vddadc_en_ac; - struct pm2xxx_config config; - bool ac_conn; - unsigned int gpio_irq; - int vbat; - int old_vbat; - int failure_case; - int failure_input_ovv; - unsigned int lpn_pin; - struct pm2xxx_interrupts *pm2_int; - struct regulator *regu; - struct pm2xxx_bm_data *bat; - struct mutex lock; - struct ab8500 *parent; - struct pm2xxx_charger_info ac; - struct pm2xxx_charger_platform_data *pdata; - struct workqueue_struct *charger_wq; - struct delayed_work check_vbat_work; - struct work_struct ac_work; - struct work_struct check_main_thermal_prot_work; - struct delayed_work check_hw_failure_work; - struct ux500_charger ac_chg; - struct power_supply_desc ac_chg_desc; - struct pm2xxx_charger_event_flags flags; -}; - -#endif /* PM2301_CHARGER_H */ -- cgit v1.2.3 From 13a4223df8a95735a6c1bafa859656ae4e78ff98 Mon Sep 17 00:00:00 2001 From: Jiang Jian Date: Thu, 23 Jun 2022 01:14:10 +0800 Subject: power: supply: ab8500_fg: drop duplicated 'is' in comment Fix word duplication typo 'is is' -> 'is'. Signed-off-by: Jiang Jian [update commit message] Signed-off-by: Sebastian Reichel --- drivers/power/supply/ab8500_fg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/supply/ab8500_fg.c b/drivers/power/supply/ab8500_fg.c index ec8a404d71b4..f6cf5eb97415 100644 --- a/drivers/power/supply/ab8500_fg.c +++ b/drivers/power/supply/ab8500_fg.c @@ -412,7 +412,7 @@ static int ab8500_fg_add_cap_sample(struct ab8500_fg *di, int sample) * ab8500_fg_clear_cap_samples() - Clear average filter * @di: pointer to the ab8500_fg structure * - * The capacity filter is is reset to zero. + * The capacity filter is reset to zero. */ static void ab8500_fg_clear_cap_samples(struct ab8500_fg *di) { -- cgit v1.2.3 From a1124c84d467223c71bcf9f2710993bb6927ea5c Mon Sep 17 00:00:00 2001 From: Tetsuo Handa Date: Thu, 9 Jun 2022 13:58:04 +0900 Subject: power: supply: ab8500: Remove flush_scheduled_work() call. It seems to me that ab8500 driver is using dedicated workqueues and is not calling schedule{,_delayed}_work{,_on}(). Then, there will be no work to flush using flush_scheduled_work(). Signed-off-by: Tetsuo Handa Reviewed-by: Linus Walleij Signed-off-by: Sebastian Reichel --- drivers/power/supply/ab8500_btemp.c | 1 - drivers/power/supply/ab8500_chargalg.c | 1 - drivers/power/supply/ab8500_charger.c | 2 -- drivers/power/supply/ab8500_fg.c | 1 - 4 files changed, 5 deletions(-) diff --git a/drivers/power/supply/ab8500_btemp.c b/drivers/power/supply/ab8500_btemp.c index b7e842dff567..863fabe05bdc 100644 --- a/drivers/power/supply/ab8500_btemp.c +++ b/drivers/power/supply/ab8500_btemp.c @@ -697,7 +697,6 @@ static void ab8500_btemp_unbind(struct device *dev, struct device *master, /* Delete the work queue */ destroy_workqueue(di->btemp_wq); - flush_scheduled_work(); } static const struct component_ops ab8500_btemp_component_ops = { diff --git a/drivers/power/supply/ab8500_chargalg.c b/drivers/power/supply/ab8500_chargalg.c index d56147f7eaec..ae4be553f424 100644 --- a/drivers/power/supply/ab8500_chargalg.c +++ b/drivers/power/supply/ab8500_chargalg.c @@ -1769,7 +1769,6 @@ static void ab8500_chargalg_unbind(struct device *dev, struct device *master, /* Delete the work queue */ destroy_workqueue(di->chargalg_wq); - flush_scheduled_work(); } static const struct component_ops ab8500_chargalg_component_ops = { diff --git a/drivers/power/supply/ab8500_charger.c b/drivers/power/supply/ab8500_charger.c index 9701c3e735e7..62c958b9ec37 100644 --- a/drivers/power/supply/ab8500_charger.c +++ b/drivers/power/supply/ab8500_charger.c @@ -3377,8 +3377,6 @@ static void ab8500_charger_unbind(struct device *dev) /* Delete the work queue */ destroy_workqueue(di->charger_wq); - flush_scheduled_work(); - /* Unbind fg, btemp, algorithm */ component_unbind_all(dev, di); } diff --git a/drivers/power/supply/ab8500_fg.c b/drivers/power/supply/ab8500_fg.c index f6cf5eb97415..1c7c5a6a2d0a 100644 --- a/drivers/power/supply/ab8500_fg.c +++ b/drivers/power/supply/ab8500_fg.c @@ -3227,7 +3227,6 @@ static int ab8500_fg_remove(struct platform_device *pdev) struct ab8500_fg *di = platform_get_drvdata(pdev); destroy_workqueue(di->fg_wq); - flush_scheduled_work(); component_del(&pdev->dev, &ab8500_fg_component_ops); list_del(&di->node); ab8500_fg_sysfs_exit(di); -- cgit v1.2.3 From 38d45444e257f7e3f6fbd242ba42371563984093 Mon Sep 17 00:00:00 2001 From: Zheng Bin Date: Thu, 12 May 2022 17:38:44 +0800 Subject: power: supply: ab8500: add missing destroy_workqueue in ab8500_charger_bind ab8500_charger_bind misses destroy_workqueue in error path, this patch fixes that. Signed-off-by: Zheng Bin Acked-by: Linus Walleij Signed-off-by: Sebastian Reichel --- drivers/power/supply/ab8500_charger.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/power/supply/ab8500_charger.c b/drivers/power/supply/ab8500_charger.c index 62c958b9ec37..c19c50442761 100644 --- a/drivers/power/supply/ab8500_charger.c +++ b/drivers/power/supply/ab8500_charger.c @@ -3351,6 +3351,7 @@ static int ab8500_charger_bind(struct device *dev) ret = component_bind_all(dev, di); if (ret) { dev_err(dev, "can't bind component devices\n"); + destroy_workqueue(di->charger_wq); return ret; } -- cgit v1.2.3 From c9d8468158adca6dffd2ff5b1befd35f75568b10 Mon Sep 17 00:00:00 2001 From: Liang He Date: Tue, 21 Jun 2022 23:17:20 +0800 Subject: power: supply: olpc_battery: Hold the reference returned by of_find_compatible_node In olpc_battery_probe(), we should hold the reference returned by of_find_compatible_node() and use it to call of_node_put() for refcount balance. Signed-off-by: Liang He Signed-off-by: Sebastian Reichel --- drivers/power/supply/olpc_battery.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/power/supply/olpc_battery.c b/drivers/power/supply/olpc_battery.c index e0476ec06601..a5da20ffd685 100644 --- a/drivers/power/supply/olpc_battery.c +++ b/drivers/power/supply/olpc_battery.c @@ -635,6 +635,7 @@ static int olpc_battery_probe(struct platform_device *pdev) struct power_supply_config bat_psy_cfg = {}; struct power_supply_config ac_psy_cfg = {}; struct olpc_battery_data *data; + struct device_node *np; uint8_t status; uint8_t ecver; int ret; @@ -649,7 +650,9 @@ static int olpc_battery_probe(struct platform_device *pdev) if (ret) return ret; - if (of_find_compatible_node(NULL, NULL, "olpc,xo1.75-ec")) { + np = of_find_compatible_node(NULL, NULL, "olpc,xo1.75-ec"); + if (np) { + of_node_put(np); /* XO 1.75 */ data->new_proto = true; data->little_endian = true; -- cgit v1.2.3 From b9d982385d0544132bc398b7a7e062d9a554d941 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sat, 25 Jun 2022 23:27:56 -0500 Subject: rtc: sun6i: add support for R329 RTC Allwinner R329 has a RTC with a similar time storage with H616 but a slightly different clock part. As we have already handled the R329 RTC clocks in the CCU driver, add a compatible string to RTC driver to allow probing of the RTC. Signed-off-by: Icenowy Zheng Signed-off-by: Samuel Holland Tested-by: Heiko Stuebner Reviewed-by: Heiko Stuebner Reviewed-by: Jernej Skrabec Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220626042756.58961-1-samuel@sholland.org --- drivers/rtc/rtc-sun6i.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c index 57540727ce1c..ed5516089e9a 100644 --- a/drivers/rtc/rtc-sun6i.c +++ b/drivers/rtc/rtc-sun6i.c @@ -875,6 +875,8 @@ static const struct of_device_id sun6i_rtc_dt_ids[] = { { .compatible = "allwinner,sun50i-h6-rtc" }, { .compatible = "allwinner,sun50i-h616-rtc", .data = (void *)RTC_LINEAR_DAY }, + { .compatible = "allwinner,sun50i-r329-rtc", + .data = (void *)RTC_LINEAR_DAY }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids); -- cgit v1.2.3 From f69060c14431f476b6993ea92bef77e20437af4e Mon Sep 17 00:00:00 2001 From: Srinivas Neeli Date: Sun, 26 Jun 2022 12:38:15 +0530 Subject: dt-bindings: rtc: zynqmp: Add clock information Added clock information and deprecated calibration support. Signed-off-by: Srinivas Neeli Reviewed-by: Rob Herring Acked-by: Krzysztof Kozlowski Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220626070817.3780977-1-srinivas.neeli@xilinx.com --- Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml b/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml index bdb72d3ddf2a..7ed0230f6c67 100644 --- a/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml @@ -23,8 +23,15 @@ properties: reg: maxItems: 1 + clocks: + maxItems: 1 + + clock-names: + items: + - const: rtc + interrupts: - minItems: 2 + maxItems: 2 interrupt-names: items: @@ -39,6 +46,7 @@ properties: minimum: 0x1 maximum: 0x1FFFFF default: 0x198233 + deprecated: true required: - compatible @@ -61,5 +69,7 @@ examples: interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x198233>; + clock-names = "rtc"; + clocks = <&rtc_clk>; }; }; -- cgit v1.2.3 From 85cab027d4e31beb082ec41b71cb8670eeb6fd46 Mon Sep 17 00:00:00 2001 From: Srinivas Neeli Date: Sun, 26 Jun 2022 12:38:16 +0530 Subject: rtc: zynqmp: Updated calibration value As per RTC spec default calibration value is 0x7FFF. We are in process to update the 0x7FFF as default value in the next version of TRM. Signed-off-by: Srinivas Neeli Acked-by: Peter Korsgaard Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220626070817.3780977-2-srinivas.neeli@xilinx.com --- drivers/rtc/rtc-zynqmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/rtc/rtc-zynqmp.c b/drivers/rtc/rtc-zynqmp.c index f440bb52be92..5da33d760419 100644 --- a/drivers/rtc/rtc-zynqmp.c +++ b/drivers/rtc/rtc-zynqmp.c @@ -36,7 +36,7 @@ #define RTC_OSC_EN BIT(24) #define RTC_BATT_EN BIT(31) -#define RTC_CALIB_DEF 0x198233 +#define RTC_CALIB_DEF 0x7FFF #define RTC_CALIB_MASK 0x1FFFFF #define RTC_ALRM_MASK BIT(1) #define RTC_MSEC 1000 -- cgit v1.2.3 From 07dcc6f9c76275d6679f28a69e042a2f9dc8f128 Mon Sep 17 00:00:00 2001 From: Srinivas Neeli Date: Sun, 26 Jun 2022 12:38:17 +0530 Subject: rtc: zynqmp: Add calibration set and get support Zynqmp RTC controller has a calibration feature to compensate time deviation due to input clock inaccuracy. Set and get calibration API's are used for setting and getting calibration value from the controller calibration register. Signed-off-by: Srinivas Neeli Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220626070817.3780977-3-srinivas.neeli@xilinx.com --- drivers/rtc/rtc-zynqmp.c | 113 +++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 94 insertions(+), 19 deletions(-) diff --git a/drivers/rtc/rtc-zynqmp.c b/drivers/rtc/rtc-zynqmp.c index 5da33d760419..1dd389b891fe 100644 --- a/drivers/rtc/rtc-zynqmp.c +++ b/drivers/rtc/rtc-zynqmp.c @@ -6,6 +6,7 @@ * */ +#include #include #include #include @@ -40,13 +41,19 @@ #define RTC_CALIB_MASK 0x1FFFFF #define RTC_ALRM_MASK BIT(1) #define RTC_MSEC 1000 +#define RTC_FR_MASK 0xF0000 +#define RTC_FR_MAX_TICKS 16 +#define RTC_PPB 1000000000LL +#define RTC_MIN_OFFSET -32768000 +#define RTC_MAX_OFFSET 32767000 struct xlnx_rtc_dev { struct rtc_device *rtc; void __iomem *reg_base; int alarm_irq; int sec_irq; - unsigned int calibval; + struct clk *rtc_clk; + unsigned int freq; }; static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm) @@ -61,13 +68,6 @@ static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm) */ new_time = rtc_tm_to_time64(tm) + 1; - /* - * Writing into calibration register will clear the Tick Counter and - * force the next second to be signaled exactly in 1 second period - */ - xrtcdev->calibval &= RTC_CALIB_MASK; - writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR)); - writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR); /* @@ -173,15 +173,76 @@ static void xlnx_init_rtc(struct xlnx_rtc_dev *xrtcdev) rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL); rtc_ctrl |= RTC_BATT_EN; writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL); +} - /* - * Based on crystal freq of 33.330 KHz - * set the seconds counter and enable, set fractions counter - * to default value suggested as per design spec - * to correct RTC delay in frequency over period of time. +static int xlnx_rtc_read_offset(struct device *dev, long *offset) +{ + struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); + unsigned long long rtc_ppb = RTC_PPB; + unsigned int tick_mult = do_div(rtc_ppb, xrtcdev->freq); + unsigned int calibval; + long offset_val; + + calibval = readl(xrtcdev->reg_base + RTC_CALIB_RD); + /* Offset with seconds ticks */ + offset_val = calibval & RTC_TICK_MASK; + offset_val = offset_val - RTC_CALIB_DEF; + offset_val = offset_val * tick_mult; + + /* Offset with fractional ticks */ + if (calibval & RTC_FR_EN) + offset_val += ((calibval & RTC_FR_MASK) >> RTC_FR_DATSHIFT) + * (tick_mult / RTC_FR_MAX_TICKS); + *offset = offset_val; + + return 0; +} + +static int xlnx_rtc_set_offset(struct device *dev, long offset) +{ + struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); + unsigned long long rtc_ppb = RTC_PPB; + unsigned int tick_mult = do_div(rtc_ppb, xrtcdev->freq); + unsigned char fract_tick; + unsigned int calibval; + short int max_tick; + int fract_offset; + + if (offset < RTC_MIN_OFFSET || offset > RTC_MAX_OFFSET) + return -ERANGE; + + /* Number ticks for given offset */ + max_tick = div_s64_rem(offset, tick_mult, &fract_offset); + + /* Number fractional ticks for given offset */ + if (fract_offset) { + if (fract_offset < 0) { + fract_offset = fract_offset + tick_mult; + max_tick--; + } + if (fract_offset > (tick_mult / RTC_FR_MAX_TICKS)) { + for (fract_tick = 1; fract_tick < 16; fract_tick++) { + if (fract_offset <= + (fract_tick * + (tick_mult / RTC_FR_MAX_TICKS))) + break; + } + } + } + + /* Zynqmp RTC uses second and fractional tick + * counters for compensation */ - xrtcdev->calibval &= RTC_CALIB_MASK; - writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR)); + calibval = max_tick + RTC_CALIB_DEF; + + if (fract_tick) + calibval |= RTC_FR_EN; + + calibval |= (fract_tick << RTC_FR_DATSHIFT); + + writel(calibval, (xrtcdev->reg_base + RTC_CALIB_WR)); + + return 0; } static const struct rtc_class_ops xlnx_rtc_ops = { @@ -190,6 +251,8 @@ static const struct rtc_class_ops xlnx_rtc_ops = { .read_alarm = xlnx_rtc_read_alarm, .set_alarm = xlnx_rtc_set_alarm, .alarm_irq_enable = xlnx_rtc_alarm_irq_enable, + .read_offset = xlnx_rtc_read_offset, + .set_offset = xlnx_rtc_set_offset, }; static irqreturn_t xlnx_rtc_interrupt(int irq, void *id) @@ -255,10 +318,22 @@ static int xlnx_rtc_probe(struct platform_device *pdev) return ret; } - ret = of_property_read_u32(pdev->dev.of_node, "calibration", - &xrtcdev->calibval); - if (ret) - xrtcdev->calibval = RTC_CALIB_DEF; + /* Getting the rtc_clk info */ + xrtcdev->rtc_clk = devm_clk_get_optional(&pdev->dev, "rtc_clk"); + if (IS_ERR(xrtcdev->rtc_clk)) { + if (PTR_ERR(xrtcdev->rtc_clk) != -EPROBE_DEFER) + dev_warn(&pdev->dev, "Device clock not found.\n"); + } + xrtcdev->freq = clk_get_rate(xrtcdev->rtc_clk); + if (!xrtcdev->freq) { + ret = of_property_read_u32(pdev->dev.of_node, "calibration", + &xrtcdev->freq); + if (ret) + xrtcdev->freq = RTC_CALIB_DEF; + } + ret = readl(xrtcdev->reg_base + RTC_CALIB_RD); + if (!ret) + writel(xrtcdev->freq, (xrtcdev->reg_base + RTC_CALIB_WR)); xlnx_init_rtc(xrtcdev); -- cgit v1.2.3 From bb42b7e9e30e7a07b7cb6790a22dc758b0dc123e Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Mon, 27 Jun 2022 16:08:22 +0800 Subject: rtc: rv8803: fix missing unlock on error in rv8803_set_time() Add the missing unlock before return from function rv8803_set_time() in the error handling case. Fixes: f8176e0bb83f ("rtc: rv8803: initialize registers on post-probe voltage loss") Reported-by: Hulk Robot Signed-off-by: Yang Yingliang Reviewed-by: Sascha Hauer Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220627080822.3881072-1-yangyingliang@huawei.com --- drivers/rtc/rtc-rv8803.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/rtc/rtc-rv8803.c b/drivers/rtc/rtc-rv8803.c index fe1247e771b9..3527a0521e9b 100644 --- a/drivers/rtc/rtc-rv8803.c +++ b/drivers/rtc/rtc-rv8803.c @@ -315,8 +315,10 @@ static int rv8803_set_time(struct device *dev, struct rtc_time *tm) if (flags & RV8803_FLAG_V2F) { ret = rv8803_regs_reset(rv8803); - if (ret) + if (ret) { + mutex_unlock(&rv8803->flags_lock); return ret; + } } ret = rv8803_write_reg(rv8803->client, RV8803_FLAG, -- cgit v1.2.3 From 03d7a732815069a78c8c655092e48fcdd52734fb Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Mon, 27 Jun 2022 16:59:43 -0400 Subject: rtc: mpfs: remove 'pending' variable from mpfs_rtc_wakeup_irq_handler() cppcheck reports [drivers/rtc/rtc-mpfs.c:219]: (style) Variable 'pending' is assigned a value that is never used. The fetched CONTROL_REG stored in pending is unused and partially duplicates the functionality of the later call to mpfs_rtc_clear(). This looks like leftover development code, so remove pending. Fixes: 0b31d703598d ("rtc: Add driver for Microchip PolarFire SoC") Signed-off-by: Tom Rix Reviewed-by: Conor Dooley Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220627205943.2075043-1-trix@redhat.com --- drivers/rtc/rtc-mpfs.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/rtc/rtc-mpfs.c b/drivers/rtc/rtc-mpfs.c index db9c638e50f7..f14d1925e0c9 100644 --- a/drivers/rtc/rtc-mpfs.c +++ b/drivers/rtc/rtc-mpfs.c @@ -213,10 +213,7 @@ static inline struct clk *mpfs_rtc_init_clk(struct device *dev) static irqreturn_t mpfs_rtc_wakeup_irq_handler(int irq, void *dev) { struct mpfs_rtc_dev *rtcdev = dev; - unsigned long pending; - pending = readl(rtcdev->base + CONTROL_REG); - pending &= CONTROL_ALARM_ON_BIT; mpfs_rtc_clear_irq(rtcdev); rtc_update_irq(rtcdev->rtc, 1, RTC_IRQF | RTC_AF); -- cgit v1.2.3 From 2a692245b6de1f17baef24db46fed03186ff3cc3 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Fri, 15 Jul 2022 15:53:30 +0200 Subject: rtc: vr41xx: remove driver Commit d3164e2f3b0a ("MIPS: Remove VR41xx support") removed support for MIPS VR41xx platform, so remove exclusive drivers for this platform, too. Signed-off-by: Thomas Bogendoerfer Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220715135330.134684-1-tsbogend@alpha.franken.de --- drivers/rtc/Kconfig | 10 -- drivers/rtc/Makefile | 1 - drivers/rtc/rtc-vr41xx.c | 363 ----------------------------------------------- 3 files changed, 374 deletions(-) delete mode 100644 drivers/rtc/rtc-vr41xx.c diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 443b6d925335..8eebc2e2dcc8 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1478,16 +1478,6 @@ config RTC_DRV_SUNPLUS This driver can also be built as a module. If so, the module will be called rtc-sunplus. -config RTC_DRV_VR41XX - tristate "NEC VR41XX" - depends on CPU_VR41XX || COMPILE_TEST - help - If you say Y here you will get access to the real time clock - built into your NEC VR41XX CPU. - - To compile this driver as a module, choose M here: the - module will be called rtc-vr41xx. - config RTC_DRV_PL030 tristate "ARM AMBA PL030 RTC" depends on ARM_AMBA diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index f83cd5ea9b11..aa8e6def05db 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -178,7 +178,6 @@ obj-$(CONFIG_RTC_DRV_TPS6586X) += rtc-tps6586x.o obj-$(CONFIG_RTC_DRV_TPS65910) += rtc-tps65910.o obj-$(CONFIG_RTC_DRV_TWL4030) += rtc-twl.o obj-$(CONFIG_RTC_DRV_V3020) += rtc-v3020.o -obj-$(CONFIG_RTC_DRV_VR41XX) += rtc-vr41xx.o obj-$(CONFIG_RTC_DRV_VT8500) += rtc-vt8500.o obj-$(CONFIG_RTC_DRV_WILCO_EC) += rtc-wilco-ec.o obj-$(CONFIG_RTC_DRV_WM831X) += rtc-wm831x.o diff --git a/drivers/rtc/rtc-vr41xx.c b/drivers/rtc/rtc-vr41xx.c deleted file mode 100644 index 5a9f9ad86d32..000000000000 --- a/drivers/rtc/rtc-vr41xx.c +++ /dev/null @@ -1,363 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Driver for NEC VR4100 series Real Time Clock unit. - * - * Copyright (C) 2003-2008 Yoichi Yuasa - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -MODULE_AUTHOR("Yoichi Yuasa "); -MODULE_DESCRIPTION("NEC VR4100 series RTC driver"); -MODULE_LICENSE("GPL v2"); - -/* RTC 1 registers */ -#define ETIMELREG 0x00 -#define ETIMEMREG 0x02 -#define ETIMEHREG 0x04 -/* RFU */ -#define ECMPLREG 0x08 -#define ECMPMREG 0x0a -#define ECMPHREG 0x0c -/* RFU */ -#define RTCL1LREG 0x10 -#define RTCL1HREG 0x12 -#define RTCL1CNTLREG 0x14 -#define RTCL1CNTHREG 0x16 -#define RTCL2LREG 0x18 -#define RTCL2HREG 0x1a -#define RTCL2CNTLREG 0x1c -#define RTCL2CNTHREG 0x1e - -/* RTC 2 registers */ -#define TCLKLREG 0x00 -#define TCLKHREG 0x02 -#define TCLKCNTLREG 0x04 -#define TCLKCNTHREG 0x06 -/* RFU */ -#define RTCINTREG 0x1e - #define TCLOCK_INT 0x08 - #define RTCLONG2_INT 0x04 - #define RTCLONG1_INT 0x02 - #define ELAPSEDTIME_INT 0x01 - -#define RTC_FREQUENCY 32768 -#define MAX_PERIODIC_RATE 6553 - -static void __iomem *rtc1_base; -static void __iomem *rtc2_base; - -#define rtc1_read(offset) readw(rtc1_base + (offset)) -#define rtc1_write(offset, value) writew((value), rtc1_base + (offset)) - -#define rtc2_read(offset) readw(rtc2_base + (offset)) -#define rtc2_write(offset, value) writew((value), rtc2_base + (offset)) - -/* 32-bit compat for ioctls that nobody else uses */ -#define RTC_EPOCH_READ32 _IOR('p', 0x0d, __u32) - -static unsigned long epoch = 1970; /* Jan 1 1970 00:00:00 */ - -static DEFINE_SPINLOCK(rtc_lock); -static char rtc_name[] = "RTC"; -static unsigned long periodic_count; -static unsigned int alarm_enabled; -static int aie_irq; -static int pie_irq; - -static inline time64_t read_elapsed_second(void) -{ - - unsigned long first_low, first_mid, first_high; - - unsigned long second_low, second_mid, second_high; - - do { - first_low = rtc1_read(ETIMELREG); - first_mid = rtc1_read(ETIMEMREG); - first_high = rtc1_read(ETIMEHREG); - second_low = rtc1_read(ETIMELREG); - second_mid = rtc1_read(ETIMEMREG); - second_high = rtc1_read(ETIMEHREG); - } while (first_low != second_low || first_mid != second_mid || - first_high != second_high); - - return ((u64)first_high << 17) | (first_mid << 1) | (first_low >> 15); -} - -static inline void write_elapsed_second(time64_t sec) -{ - spin_lock_irq(&rtc_lock); - - rtc1_write(ETIMELREG, (uint16_t)(sec << 15)); - rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1)); - rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17)); - - spin_unlock_irq(&rtc_lock); -} - -static int vr41xx_rtc_read_time(struct device *dev, struct rtc_time *time) -{ - time64_t epoch_sec, elapsed_sec; - - epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0); - elapsed_sec = read_elapsed_second(); - - rtc_time64_to_tm(epoch_sec + elapsed_sec, time); - - return 0; -} - -static int vr41xx_rtc_set_time(struct device *dev, struct rtc_time *time) -{ - time64_t epoch_sec, current_sec; - - epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0); - current_sec = rtc_tm_to_time64(time); - - write_elapsed_second(current_sec - epoch_sec); - - return 0; -} - -static int vr41xx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) -{ - unsigned long low, mid, high; - struct rtc_time *time = &wkalrm->time; - - spin_lock_irq(&rtc_lock); - - low = rtc1_read(ECMPLREG); - mid = rtc1_read(ECMPMREG); - high = rtc1_read(ECMPHREG); - wkalrm->enabled = alarm_enabled; - - spin_unlock_irq(&rtc_lock); - - rtc_time64_to_tm((high << 17) | (mid << 1) | (low >> 15), time); - - return 0; -} - -static int vr41xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) -{ - time64_t alarm_sec; - - alarm_sec = rtc_tm_to_time64(&wkalrm->time); - - spin_lock_irq(&rtc_lock); - - if (alarm_enabled) - disable_irq(aie_irq); - - rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15)); - rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1)); - rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17)); - - if (wkalrm->enabled) - enable_irq(aie_irq); - - alarm_enabled = wkalrm->enabled; - - spin_unlock_irq(&rtc_lock); - - return 0; -} - -static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) -{ - switch (cmd) { - case RTC_EPOCH_READ: - return put_user(epoch, (unsigned long __user *)arg); -#ifdef CONFIG_64BIT - case RTC_EPOCH_READ32: - return put_user(epoch, (unsigned int __user *)arg); -#endif - case RTC_EPOCH_SET: - /* Doesn't support before 1900 */ - if (arg < 1900) - return -EINVAL; - epoch = arg; - break; - default: - return -ENOIOCTLCMD; - } - - return 0; -} - -static int vr41xx_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) -{ - spin_lock_irq(&rtc_lock); - if (enabled) { - if (!alarm_enabled) { - enable_irq(aie_irq); - alarm_enabled = 1; - } - } else { - if (alarm_enabled) { - disable_irq(aie_irq); - alarm_enabled = 0; - } - } - spin_unlock_irq(&rtc_lock); - return 0; -} - -static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id) -{ - struct platform_device *pdev = (struct platform_device *)dev_id; - struct rtc_device *rtc = platform_get_drvdata(pdev); - - rtc2_write(RTCINTREG, ELAPSEDTIME_INT); - - rtc_update_irq(rtc, 1, RTC_AF); - - return IRQ_HANDLED; -} - -static irqreturn_t rtclong1_interrupt(int irq, void *dev_id) -{ - struct platform_device *pdev = (struct platform_device *)dev_id; - struct rtc_device *rtc = platform_get_drvdata(pdev); - unsigned long count = periodic_count; - - rtc2_write(RTCINTREG, RTCLONG1_INT); - - rtc1_write(RTCL1LREG, count); - rtc1_write(RTCL1HREG, count >> 16); - - rtc_update_irq(rtc, 1, RTC_PF); - - return IRQ_HANDLED; -} - -static const struct rtc_class_ops vr41xx_rtc_ops = { - .ioctl = vr41xx_rtc_ioctl, - .read_time = vr41xx_rtc_read_time, - .set_time = vr41xx_rtc_set_time, - .read_alarm = vr41xx_rtc_read_alarm, - .set_alarm = vr41xx_rtc_set_alarm, - .alarm_irq_enable = vr41xx_rtc_alarm_irq_enable, -}; - -static int rtc_probe(struct platform_device *pdev) -{ - struct resource *res; - struct rtc_device *rtc; - int retval; - - if (pdev->num_resources != 4) - return -EBUSY; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -EBUSY; - - rtc1_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); - if (!rtc1_base) - return -EBUSY; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (!res) { - retval = -EBUSY; - goto err_rtc1_iounmap; - } - - rtc2_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); - if (!rtc2_base) { - retval = -EBUSY; - goto err_rtc1_iounmap; - } - - rtc = devm_rtc_allocate_device(&pdev->dev); - if (IS_ERR(rtc)) { - retval = PTR_ERR(rtc); - goto err_iounmap_all; - } - - rtc->ops = &vr41xx_rtc_ops; - - /* 48-bit counter at 32.768 kHz */ - rtc->range_max = (1ULL << 33) - 1; - rtc->max_user_freq = MAX_PERIODIC_RATE; - - spin_lock_irq(&rtc_lock); - - rtc1_write(ECMPLREG, 0); - rtc1_write(ECMPMREG, 0); - rtc1_write(ECMPHREG, 0); - rtc1_write(RTCL1LREG, 0); - rtc1_write(RTCL1HREG, 0); - - spin_unlock_irq(&rtc_lock); - - aie_irq = platform_get_irq(pdev, 0); - if (aie_irq <= 0) { - retval = -EBUSY; - goto err_iounmap_all; - } - - retval = devm_request_irq(&pdev->dev, aie_irq, elapsedtime_interrupt, 0, - "elapsed_time", pdev); - if (retval < 0) - goto err_iounmap_all; - - pie_irq = platform_get_irq(pdev, 1); - if (pie_irq <= 0) { - retval = -EBUSY; - goto err_iounmap_all; - } - - retval = devm_request_irq(&pdev->dev, pie_irq, rtclong1_interrupt, 0, - "rtclong1", pdev); - if (retval < 0) - goto err_iounmap_all; - - platform_set_drvdata(pdev, rtc); - - disable_irq(aie_irq); - disable_irq(pie_irq); - - dev_info(&pdev->dev, "Real Time Clock of NEC VR4100 series\n"); - - retval = devm_rtc_register_device(rtc); - if (retval) - goto err_iounmap_all; - - return 0; - -err_iounmap_all: - rtc2_base = NULL; - -err_rtc1_iounmap: - rtc1_base = NULL; - - return retval; -} - -/* work with hotplug and coldplug */ -MODULE_ALIAS("platform:RTC"); - -static struct platform_driver rtc_platform_driver = { - .probe = rtc_probe, - .driver = { - .name = rtc_name, - }, -}; - -module_platform_driver(rtc_platform_driver); -- cgit v1.2.3 From 5c9f41443e8d5fbd414ad0dfa8e0996b937d135a Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 7 Jul 2022 17:31:56 +0200 Subject: rtc: cros-ec: Only warn once in .remove() about notifier_chain problems MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When a remove platform device callback returns an error code, the driver core emits an error message ("remove callback returned a non-zero value. This will be ignored.\n") and still removes the device. As the driver already emits a more specific error message, return 0 to suppress the core's error message. This is a preparation for making platform remove callbacks return void. Signed-off-by: Uwe Kleine-König Acked-by: Tzung-Bi Shih Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220707153156.214841-1-u.kleine-koenig@pengutronix.de --- drivers/rtc/rtc-cros-ec.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/rtc/rtc-cros-ec.c b/drivers/rtc/rtc-cros-ec.c index 70626793ca69..887f5193e253 100644 --- a/drivers/rtc/rtc-cros-ec.c +++ b/drivers/rtc/rtc-cros-ec.c @@ -375,10 +375,8 @@ static int cros_ec_rtc_remove(struct platform_device *pdev) ret = blocking_notifier_chain_unregister( &cros_ec_rtc->cros_ec->event_notifier, &cros_ec_rtc->notifier); - if (ret) { + if (ret) dev_err(dev, "failed to unregister notifier\n"); - return ret; - } return 0; } -- cgit v1.2.3 From 71af91565052214ad86f288e0d8ffb165f790995 Mon Sep 17 00:00:00 2001 From: Mathew McBride Date: Wed, 6 Jul 2022 07:42:36 +0000 Subject: rtc: rx8025: fix 12/24 hour mode detection on RX-8035 The 12/24hr flag in the RX-8035 can be found in the hour register, instead of the CTRL1 on the RX-8025. This was overlooked when support for the RX-8035 was added, and was causing read errors when the hour register 'overflowed'. To deal with the relevant register not always being visible in the relevant functions, determine the 12/24 mode at startup and store it in the driver state. Signed-off-by: Mathew McBride Fixes: f120e2e33ac8 ("rtc: rx8025: implement RX-8035 support") Cc: stable@vger.kernel.org Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220706074236.24011-1-matt@traverse.com.au --- drivers/rtc/rtc-rx8025.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/rtc/rtc-rx8025.c b/drivers/rtc/rtc-rx8025.c index b32117ccd74b..dde86f3e2a4b 100644 --- a/drivers/rtc/rtc-rx8025.c +++ b/drivers/rtc/rtc-rx8025.c @@ -55,6 +55,8 @@ #define RX8025_BIT_CTRL2_XST BIT(5) #define RX8025_BIT_CTRL2_VDET BIT(6) +#define RX8035_BIT_HOUR_1224 BIT(7) + /* Clock precision adjustment */ #define RX8025_ADJ_RESOLUTION 3050 /* in ppb */ #define RX8025_ADJ_DATA_MAX 62 @@ -78,6 +80,7 @@ struct rx8025_data { struct rtc_device *rtc; enum rx_model model; u8 ctrl1; + int is_24; }; static s32 rx8025_read_reg(const struct i2c_client *client, u8 number) @@ -226,7 +229,7 @@ static int rx8025_get_time(struct device *dev, struct rtc_time *dt) dt->tm_sec = bcd2bin(date[RX8025_REG_SEC] & 0x7f); dt->tm_min = bcd2bin(date[RX8025_REG_MIN] & 0x7f); - if (rx8025->ctrl1 & RX8025_BIT_CTRL1_1224) + if (rx8025->is_24) dt->tm_hour = bcd2bin(date[RX8025_REG_HOUR] & 0x3f); else dt->tm_hour = bcd2bin(date[RX8025_REG_HOUR] & 0x1f) % 12 @@ -254,7 +257,7 @@ static int rx8025_set_time(struct device *dev, struct rtc_time *dt) */ date[RX8025_REG_SEC] = bin2bcd(dt->tm_sec); date[RX8025_REG_MIN] = bin2bcd(dt->tm_min); - if (rx8025->ctrl1 & RX8025_BIT_CTRL1_1224) + if (rx8025->is_24) date[RX8025_REG_HOUR] = bin2bcd(dt->tm_hour); else date[RX8025_REG_HOUR] = (dt->tm_hour >= 12 ? 0x20 : 0) @@ -279,6 +282,7 @@ static int rx8025_init_client(struct i2c_client *client) struct rx8025_data *rx8025 = i2c_get_clientdata(client); u8 ctrl[2], ctrl2; int need_clear = 0; + int hour_reg; int err; err = rx8025_read_regs(client, RX8025_REG_CTRL1, 2, ctrl); @@ -303,6 +307,16 @@ static int rx8025_init_client(struct i2c_client *client) err = rx8025_write_reg(client, RX8025_REG_CTRL2, ctrl2); } + + if (rx8025->model == model_rx_8035) { + /* In RX-8035, 12/24 flag is in the hour register */ + hour_reg = rx8025_read_reg(client, RX8025_REG_HOUR); + if (hour_reg < 0) + return hour_reg; + rx8025->is_24 = (hour_reg & RX8035_BIT_HOUR_1224); + } else { + rx8025->is_24 = (ctrl[1] & RX8025_BIT_CTRL1_1224); + } out: return err; } @@ -329,7 +343,7 @@ static int rx8025_read_alarm(struct device *dev, struct rtc_wkalrm *t) /* Hardware alarms precision is 1 minute! */ t->time.tm_sec = 0; t->time.tm_min = bcd2bin(ald[0] & 0x7f); - if (rx8025->ctrl1 & RX8025_BIT_CTRL1_1224) + if (rx8025->is_24) t->time.tm_hour = bcd2bin(ald[1] & 0x3f); else t->time.tm_hour = bcd2bin(ald[1] & 0x1f) % 12 @@ -350,7 +364,7 @@ static int rx8025_set_alarm(struct device *dev, struct rtc_wkalrm *t) int err; ald[0] = bin2bcd(t->time.tm_min); - if (rx8025->ctrl1 & RX8025_BIT_CTRL1_1224) + if (rx8025->is_24) ald[1] = bin2bcd(t->time.tm_hour); else ald[1] = (t->time.tm_hour >= 12 ? 0x20 : 0) -- cgit v1.2.3 From 2830320122d87fb65632f09cdffe129046915d51 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 19 Jul 2022 15:51:42 -0600 Subject: dt-bindings: rtc: microcrystal,rv3032: Add missing type to 'trickle-voltage-millivolt' 'trickle-voltage-millivolt' is missing a type definition. '-millivolt' is not a standard unit (should be '-microvolt'). As the property is already in use, add a type reference. Signed-off-by: Rob Herring Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220719215143.1877566-1-robh@kernel.org --- Documentation/devicetree/bindings/rtc/microcrystal,rv3032.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/rtc/microcrystal,rv3032.yaml b/Documentation/devicetree/bindings/rtc/microcrystal,rv3032.yaml index 9593840a4a2b..60f9027e8299 100644 --- a/Documentation/devicetree/bindings/rtc/microcrystal,rv3032.yaml +++ b/Documentation/devicetree/bindings/rtc/microcrystal,rv3032.yaml @@ -32,6 +32,7 @@ properties: - 11000 trickle-voltage-millivolt: + $ref: /schemas/types.yaml#/definitions/uint32 enum: - 1750 - 3000 -- cgit v1.2.3 From 10e1fb88c7b7e71ae04895511f4f98a7721c9e6e Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Mon, 25 Jul 2022 09:19:19 +0200 Subject: dt-bindings: rtc: nxp,pcf85063: Convert to DT schema Convert the NXP PCF85063 RTC binding to DT schema format. Add 'interrupts' and 'wakeup-source' as this device has an interrupt which was not documented, but is in use. 'clock-output-names' and '#clock-cells' are added as well, those were probably missed when adding clkout support in commit 8c229ab6048b ("rtc: pcf85063: Add pcf85063 clkout control to common clock framework") Signed-off-by: Alexander Stein Reviewed-by: Krzysztof Kozlowski Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220725071919.25342-1-alexander.stein@ew.tq-group.com --- .../devicetree/bindings/rtc/nxp,pcf85063.txt | 32 -------- .../devicetree/bindings/rtc/nxp,pcf85063.yaml | 92 ++++++++++++++++++++++ 2 files changed, 92 insertions(+), 32 deletions(-) delete mode 100644 Documentation/devicetree/bindings/rtc/nxp,pcf85063.txt create mode 100644 Documentation/devicetree/bindings/rtc/nxp,pcf85063.yaml diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf85063.txt b/Documentation/devicetree/bindings/rtc/nxp,pcf85063.txt deleted file mode 100644 index 217b7cd06c11..000000000000 --- a/Documentation/devicetree/bindings/rtc/nxp,pcf85063.txt +++ /dev/null @@ -1,32 +0,0 @@ -* NXP PCF85063 Real Time Clock - -Required properties: -- compatible: Should one of contain: - "nxp,pca85073a", - "nxp,pcf85063", - "nxp,pcf85063a", - "nxp,pcf85063tp", - "microcrystal,rv8263" -- reg: I2C address for chip. - -Optional property: -- quartz-load-femtofarads: The capacitive load of the quartz(x-tal), - expressed in femto Farad (fF). Valid values are 7000 and 12500. - Default value (if no value is specified) is 7000fF. - -Optional child node: -- clock: Provide this if the square wave pin is used as boot-enabled fixed clock. - -Example: - -pcf85063: rtc@51 { - compatible = "nxp,pcf85063"; - reg = <0x51>; - quartz-load-femtofarads = <12500>; - - clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; -}; diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf85063.yaml b/Documentation/devicetree/bindings/rtc/nxp,pcf85063.yaml new file mode 100644 index 000000000000..2f892f8640d1 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/nxp,pcf85063.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/nxp,pcf85063.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP PCF85063 Real Time Clock + +maintainers: + - Alexander Stein + +properties: + compatible: + enum: + - microcrystal,rv8263 + - nxp,pcf85063 + - nxp,pcf85063a + - nxp,pcf85063tp + - nxp,pca85073a + + reg: + maxItems: 1 + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + + interrupts: + maxItems: 1 + + quartz-load-femtofarads: + description: + The capacitive load of the quartz(x-tal). + enum: [7000, 12500] + default: 7000 + + clock: + $ref: /schemas/clock/fixed-clock.yaml + description: + Provide this if the square wave pin is used as boot-enabled + fixed clock. + + wakeup-source: true + +allOf: + - $ref: rtc.yaml# + - if: + properties: + compatible: + contains: + enum: + - microcrystal,rv8263 + then: + properties: + quartz-load-femtofarads: false + - if: + properties: + compatible: + contains: + enum: + - nxp,pcf85063 + then: + properties: + quartz-load-femtofarads: + const: 7000 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <12500>; + + clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + }; -- cgit v1.2.3 From 8b30b09317ec6fda5f36a428e9e331253b5c4739 Mon Sep 17 00:00:00 2001 From: Mia Lin Date: Wed, 13 Jul 2022 17:06:45 +0800 Subject: dt-bindings: rtc: nuvoton: add NCT3018Y Real Time Clock Document devicetree bindings for the Nuvoton NCT3018Y Real Time Clock. Reviewed-by: Rob Herring Signed-off-by: Mia Lin Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220713090647.8028-2-mimi05633@gmail.com --- .../devicetree/bindings/rtc/nuvoton,nct3018y.yaml | 45 ++++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml diff --git a/Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml b/Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml new file mode 100644 index 000000000000..7a1857f5caa8 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/nuvoton,nct3018y.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NUVOTON NCT3018Y Real Time Clock + +allOf: + - $ref: "rtc.yaml#" + +maintainers: + - Medad CChien + - Mia Lin + +properties: + compatible: + const: nuvoton,nct3018y + + reg: + maxItems: 1 + + start-year: true + + reset-source: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + rtc@6f { + compatible = "nuvoton,nct3018y"; + reg = <0x6f>; + }; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 69a960561e37..9be1d80dc03c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2446,6 +2446,7 @@ S: Supported F: Documentation/devicetree/bindings/*/*/*npcm* F: Documentation/devicetree/bindings/*/*npcm* F: Documentation/devicetree/bindings/arm/npcm/* +F: Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml F: arch/arm/boot/dts/nuvoton-npcm* F: arch/arm/mach-npcm/ F: drivers/*/*npcm* -- cgit v1.2.3 From 5adbaed16cc63542057627642d2414f603f2db69 Mon Sep 17 00:00:00 2001 From: Mia Lin Date: Wed, 13 Jul 2022 17:06:47 +0800 Subject: rtc: Add NCT3018Y real time clock driver Add real time clock support for NCT3018Y. Signed-off-by: Mia Lin Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220713090647.8028-4-mimi05633@gmail.com --- MAINTAINERS | 1 + drivers/rtc/Kconfig | 10 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-nct3018y.c | 553 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 565 insertions(+) create mode 100644 drivers/rtc/rtc-nct3018y.c diff --git a/MAINTAINERS b/MAINTAINERS index 9be1d80dc03c..5f9233716ab5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2451,6 +2451,7 @@ F: arch/arm/boot/dts/nuvoton-npcm* F: arch/arm/mach-npcm/ F: drivers/*/*npcm* F: drivers/*/*/*npcm* +F: drivers/rtc/rtc-nct3018y.c F: include/dt-bindings/clock/nuvoton,npcm7xx-clock.h ARM/NUVOTON WPCM450 ARCHITECTURE diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 8eebc2e2dcc8..b8de25118ad0 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -383,6 +383,16 @@ config RTC_DRV_MAX77686 This driver can also be built as a module. If so, the module will be called rtc-max77686. +config RTC_DRV_NCT3018Y + tristate "Nuvoton NCT3018Y" + depends on OF + help + If you say yes here you get support for the Nuvoton NCT3018Y I2C RTC + chip. + + This driver can also be built as a module, if so, the module will be + called "rtc-nct3018y". + config RTC_DRV_RK808 tristate "Rockchip RK805/RK808/RK809/RK817/RK818 RTC" depends on MFD_RK808 diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index aa8e6def05db..aab22bc63432 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -112,6 +112,7 @@ obj-$(CONFIG_RTC_DRV_MV) += rtc-mv.o obj-$(CONFIG_RTC_DRV_MXC) += rtc-mxc.o obj-$(CONFIG_RTC_DRV_MXC_V2) += rtc-mxc_v2.o obj-$(CONFIG_RTC_DRV_GAMECUBE) += rtc-gamecube.o +obj-$(CONFIG_RTC_DRV_NCT3018Y) += rtc-nct3018y.o obj-$(CONFIG_RTC_DRV_NTXEC) += rtc-ntxec.o obj-$(CONFIG_RTC_DRV_OMAP) += rtc-omap.o obj-$(CONFIG_RTC_DRV_OPAL) += rtc-opal.o diff --git a/drivers/rtc/rtc-nct3018y.c b/drivers/rtc/rtc-nct3018y.c new file mode 100644 index 000000000000..d43acd3920ed --- /dev/null +++ b/drivers/rtc/rtc-nct3018y.c @@ -0,0 +1,553 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2022 Nuvoton Technology Corporation + +#include +#include +#include +#include +#include +#include +#include +#include + +#define NCT3018Y_REG_SC 0x00 /* seconds */ +#define NCT3018Y_REG_SCA 0x01 /* alarm */ +#define NCT3018Y_REG_MN 0x02 +#define NCT3018Y_REG_MNA 0x03 /* alarm */ +#define NCT3018Y_REG_HR 0x04 +#define NCT3018Y_REG_HRA 0x05 /* alarm */ +#define NCT3018Y_REG_DW 0x06 +#define NCT3018Y_REG_DM 0x07 +#define NCT3018Y_REG_MO 0x08 +#define NCT3018Y_REG_YR 0x09 +#define NCT3018Y_REG_CTRL 0x0A /* timer control */ +#define NCT3018Y_REG_ST 0x0B /* status */ +#define NCT3018Y_REG_CLKO 0x0C /* clock out */ + +#define NCT3018Y_BIT_AF BIT(7) +#define NCT3018Y_BIT_ST BIT(7) +#define NCT3018Y_BIT_DM BIT(6) +#define NCT3018Y_BIT_HF BIT(5) +#define NCT3018Y_BIT_DSM BIT(4) +#define NCT3018Y_BIT_AIE BIT(3) +#define NCT3018Y_BIT_OFIE BIT(2) +#define NCT3018Y_BIT_CIE BIT(1) +#define NCT3018Y_BIT_TWO BIT(0) + +#define NCT3018Y_REG_BAT_MASK 0x07 +#define NCT3018Y_REG_CLKO_F_MASK 0x03 /* frequenc mask */ +#define NCT3018Y_REG_CLKO_CKE 0x80 /* clock out enabled */ + +struct nct3018y { + struct rtc_device *rtc; + struct i2c_client *client; +#ifdef CONFIG_COMMON_CLK + struct clk_hw clkout_hw; +#endif +}; + +static int nct3018y_set_alarm_mode(struct i2c_client *client, bool on) +{ + int err, flags; + + dev_dbg(&client->dev, "%s:on:%d\n", __func__, on); + + flags = i2c_smbus_read_byte_data(client, NCT3018Y_REG_CTRL); + if (flags < 0) { + dev_dbg(&client->dev, + "Failed to read NCT3018Y_REG_CTRL\n"); + return flags; + } + + if (on) + flags |= NCT3018Y_BIT_AIE; + else + flags &= ~NCT3018Y_BIT_AIE; + + flags |= NCT3018Y_BIT_CIE; + err = i2c_smbus_write_byte_data(client, NCT3018Y_REG_CTRL, flags); + if (err < 0) { + dev_dbg(&client->dev, "Unable to write NCT3018Y_REG_CTRL\n"); + return err; + } + + flags = i2c_smbus_read_byte_data(client, NCT3018Y_REG_ST); + if (flags < 0) { + dev_dbg(&client->dev, + "Failed to read NCT3018Y_REG_ST\n"); + return flags; + } + + flags &= ~(NCT3018Y_BIT_AF); + err = i2c_smbus_write_byte_data(client, NCT3018Y_REG_ST, flags); + if (err < 0) { + dev_dbg(&client->dev, "Unable to write NCT3018Y_REG_ST\n"); + return err; + } + + return 0; +} + +static int nct3018y_get_alarm_mode(struct i2c_client *client, unsigned char *alarm_enable, + unsigned char *alarm_flag) +{ + int flags; + + if (alarm_enable) { + dev_dbg(&client->dev, "%s:NCT3018Y_REG_CTRL\n", __func__); + flags = i2c_smbus_read_byte_data(client, NCT3018Y_REG_CTRL); + if (flags < 0) + return flags; + *alarm_enable = flags & NCT3018Y_BIT_AIE; + } + + if (alarm_flag) { + dev_dbg(&client->dev, "%s:NCT3018Y_REG_ST\n", __func__); + flags = i2c_smbus_read_byte_data(client, NCT3018Y_REG_ST); + if (flags < 0) + return flags; + *alarm_flag = flags & NCT3018Y_BIT_AF; + } + + dev_dbg(&client->dev, "%s:alarm_enable:%x alarm_flag:%x\n", + __func__, *alarm_enable, *alarm_flag); + + return 0; +} + +static irqreturn_t nct3018y_irq(int irq, void *dev_id) +{ + struct nct3018y *nct3018y = i2c_get_clientdata(dev_id); + struct i2c_client *client = nct3018y->client; + int err; + unsigned char alarm_flag; + unsigned char alarm_enable; + + dev_dbg(&client->dev, "%s:irq:%d\n", __func__, irq); + err = nct3018y_get_alarm_mode(nct3018y->client, &alarm_enable, &alarm_flag); + if (err) + return IRQ_NONE; + + if (alarm_flag) { + dev_dbg(&client->dev, "%s:alarm flag:%x\n", + __func__, alarm_flag); + rtc_update_irq(nct3018y->rtc, 1, RTC_IRQF | RTC_AF); + nct3018y_set_alarm_mode(nct3018y->client, 0); + dev_dbg(&client->dev, "%s:IRQ_HANDLED\n", __func__); + return IRQ_HANDLED; + } + + return IRQ_NONE; +} + +/* + * In the routines that deal directly with the nct3018y hardware, we use + * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch. + */ +static int nct3018y_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct i2c_client *client = to_i2c_client(dev); + unsigned char buf[10]; + int err; + + err = i2c_smbus_read_i2c_block_data(client, NCT3018Y_REG_ST, 1, buf); + if (err < 0) + return err; + + if (!buf[0]) { + dev_dbg(&client->dev, " voltage <=1.7, date/time is not reliable.\n"); + return -EINVAL; + } + + err = i2c_smbus_read_i2c_block_data(client, NCT3018Y_REG_SC, sizeof(buf), buf); + if (err < 0) + return err; + + tm->tm_sec = bcd2bin(buf[0] & 0x7F); + tm->tm_min = bcd2bin(buf[2] & 0x7F); + tm->tm_hour = bcd2bin(buf[4] & 0x3F); + tm->tm_wday = buf[6] & 0x07; + tm->tm_mday = bcd2bin(buf[7] & 0x3F); + tm->tm_mon = bcd2bin(buf[8] & 0x1F) - 1; + tm->tm_year = bcd2bin(buf[9]) + 100; + + return 0; +} + +static int nct3018y_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct i2c_client *client = to_i2c_client(dev); + unsigned char buf[4] = {0}; + int err; + + buf[0] = bin2bcd(tm->tm_sec); + err = i2c_smbus_write_byte_data(client, NCT3018Y_REG_SC, buf[0]); + if (err < 0) { + dev_dbg(&client->dev, "Unable to write NCT3018Y_REG_SC\n"); + return err; + } + + buf[0] = bin2bcd(tm->tm_min); + err = i2c_smbus_write_byte_data(client, NCT3018Y_REG_MN, buf[0]); + if (err < 0) { + dev_dbg(&client->dev, "Unable to write NCT3018Y_REG_MN\n"); + return err; + } + + buf[0] = bin2bcd(tm->tm_hour); + err = i2c_smbus_write_byte_data(client, NCT3018Y_REG_HR, buf[0]); + if (err < 0) { + dev_dbg(&client->dev, "Unable to write NCT3018Y_REG_HR\n"); + return err; + } + + buf[0] = tm->tm_wday & 0x07; + buf[1] = bin2bcd(tm->tm_mday); + buf[2] = bin2bcd(tm->tm_mon + 1); + buf[3] = bin2bcd(tm->tm_year - 100); + err = i2c_smbus_write_i2c_block_data(client, NCT3018Y_REG_DW, + sizeof(buf), buf); + if (err < 0) { + dev_dbg(&client->dev, "Unable to write for day and mon and year\n"); + return -EIO; + } + + return err; +} + +static int nct3018y_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *tm) +{ + struct i2c_client *client = to_i2c_client(dev); + unsigned char buf[5]; + int err; + + err = i2c_smbus_read_i2c_block_data(client, NCT3018Y_REG_SCA, + sizeof(buf), buf); + if (err < 0) { + dev_dbg(&client->dev, "Unable to read date\n"); + return -EIO; + } + + dev_dbg(&client->dev, "%s: raw data is sec=%02x, min=%02x hr=%02x\n", + __func__, buf[0], buf[2], buf[4]); + + tm->time.tm_sec = bcd2bin(buf[0] & 0x7F); + tm->time.tm_min = bcd2bin(buf[2] & 0x7F); + tm->time.tm_hour = bcd2bin(buf[4] & 0x3F); + + err = nct3018y_get_alarm_mode(client, &tm->enabled, &tm->pending); + if (err < 0) + return err; + + dev_dbg(&client->dev, "%s:s=%d m=%d, hr=%d, enabled=%d, pending=%d\n", + __func__, tm->time.tm_sec, tm->time.tm_min, + tm->time.tm_hour, tm->enabled, tm->pending); + + return 0; +} + +static int nct3018y_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *tm) +{ + struct i2c_client *client = to_i2c_client(dev); + int err; + + dev_dbg(dev, "%s, sec=%d, min=%d hour=%d tm->enabled:%d\n", + __func__, tm->time.tm_sec, tm->time.tm_min, tm->time.tm_hour, + tm->enabled); + + err = i2c_smbus_write_byte_data(client, NCT3018Y_REG_SCA, bin2bcd(tm->time.tm_sec)); + if (err < 0) { + dev_dbg(&client->dev, "Unable to write NCT3018Y_REG_SCA\n"); + return err; + } + + err = i2c_smbus_write_byte_data(client, NCT3018Y_REG_MNA, bin2bcd(tm->time.tm_min)); + if (err < 0) { + dev_dbg(&client->dev, "Unable to write NCT3018Y_REG_MNA\n"); + return err; + } + + err = i2c_smbus_write_byte_data(client, NCT3018Y_REG_HRA, bin2bcd(tm->time.tm_hour)); + if (err < 0) { + dev_dbg(&client->dev, "Unable to write NCT3018Y_REG_HRA\n"); + return err; + } + + return nct3018y_set_alarm_mode(client, tm->enabled); +} + +static int nct3018y_irq_enable(struct device *dev, unsigned int enabled) +{ + dev_dbg(dev, "%s: alarm enable=%d\n", __func__, enabled); + + return nct3018y_set_alarm_mode(to_i2c_client(dev), enabled); +} + +static int nct3018y_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) +{ + struct i2c_client *client = to_i2c_client(dev); + int status, flags = 0; + + switch (cmd) { + case RTC_VL_READ: + status = i2c_smbus_read_byte_data(client, NCT3018Y_REG_ST); + if (status < 0) + return status; + + if (!(status & NCT3018Y_REG_BAT_MASK)) + flags |= RTC_VL_DATA_INVALID; + + return put_user(flags, (unsigned int __user *)arg); + + default: + return -ENOIOCTLCMD; + } +} + +#ifdef CONFIG_COMMON_CLK +/* + * Handling of the clkout + */ + +#define clkout_hw_to_nct3018y(_hw) container_of(_hw, struct nct3018y, clkout_hw) + +static const int clkout_rates[] = { + 32768, + 1024, + 32, + 1, +}; + +static unsigned long nct3018y_clkout_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct nct3018y *nct3018y = clkout_hw_to_nct3018y(hw); + struct i2c_client *client = nct3018y->client; + int flags; + + flags = i2c_smbus_read_byte_data(client, NCT3018Y_REG_CLKO); + if (flags < 0) + return 0; + + flags &= NCT3018Y_REG_CLKO_F_MASK; + return clkout_rates[flags]; +} + +static long nct3018y_clkout_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(clkout_rates); i++) + if (clkout_rates[i] <= rate) + return clkout_rates[i]; + + return 0; +} + +static int nct3018y_clkout_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct nct3018y *nct3018y = clkout_hw_to_nct3018y(hw); + struct i2c_client *client = nct3018y->client; + int i, flags; + + flags = i2c_smbus_read_byte_data(client, NCT3018Y_REG_CLKO); + if (flags < 0) + return flags; + + for (i = 0; i < ARRAY_SIZE(clkout_rates); i++) + if (clkout_rates[i] == rate) { + flags &= ~NCT3018Y_REG_CLKO_F_MASK; + flags |= i; + return i2c_smbus_write_byte_data(client, NCT3018Y_REG_CLKO, flags); + } + + return -EINVAL; +} + +static int nct3018y_clkout_control(struct clk_hw *hw, bool enable) +{ + struct nct3018y *nct3018y = clkout_hw_to_nct3018y(hw); + struct i2c_client *client = nct3018y->client; + int flags; + + flags = i2c_smbus_read_byte_data(client, NCT3018Y_REG_CLKO); + if (flags < 0) + return flags; + + if (enable) + flags |= NCT3018Y_REG_CLKO_CKE; + else + flags &= ~NCT3018Y_REG_CLKO_CKE; + + return i2c_smbus_write_byte_data(client, NCT3018Y_REG_CLKO, flags); +} + +static int nct3018y_clkout_prepare(struct clk_hw *hw) +{ + return nct3018y_clkout_control(hw, 1); +} + +static void nct3018y_clkout_unprepare(struct clk_hw *hw) +{ + nct3018y_clkout_control(hw, 0); +} + +static int nct3018y_clkout_is_prepared(struct clk_hw *hw) +{ + struct nct3018y *nct3018y = clkout_hw_to_nct3018y(hw); + struct i2c_client *client = nct3018y->client; + int flags; + + flags = i2c_smbus_read_byte_data(client, NCT3018Y_REG_CLKO); + if (flags < 0) + return flags; + + return flags & NCT3018Y_REG_CLKO_CKE; +} + +static const struct clk_ops nct3018y_clkout_ops = { + .prepare = nct3018y_clkout_prepare, + .unprepare = nct3018y_clkout_unprepare, + .is_prepared = nct3018y_clkout_is_prepared, + .recalc_rate = nct3018y_clkout_recalc_rate, + .round_rate = nct3018y_clkout_round_rate, + .set_rate = nct3018y_clkout_set_rate, +}; + +static struct clk *nct3018y_clkout_register_clk(struct nct3018y *nct3018y) +{ + struct i2c_client *client = nct3018y->client; + struct device_node *node = client->dev.of_node; + struct clk *clk; + struct clk_init_data init; + + init.name = "nct3018y-clkout"; + init.ops = &nct3018y_clkout_ops; + init.flags = 0; + init.parent_names = NULL; + init.num_parents = 0; + nct3018y->clkout_hw.init = &init; + + /* optional override of the clockname */ + of_property_read_string(node, "clock-output-names", &init.name); + + /* register the clock */ + clk = devm_clk_register(&client->dev, &nct3018y->clkout_hw); + + if (!IS_ERR(clk)) + of_clk_add_provider(node, of_clk_src_simple_get, clk); + + return clk; +} +#endif + +static const struct rtc_class_ops nct3018y_rtc_ops = { + .read_time = nct3018y_rtc_read_time, + .set_time = nct3018y_rtc_set_time, + .read_alarm = nct3018y_rtc_read_alarm, + .set_alarm = nct3018y_rtc_set_alarm, + .alarm_irq_enable = nct3018y_irq_enable, + .ioctl = nct3018y_ioctl, +}; + +static int nct3018y_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct nct3018y *nct3018y; + int err, flags; + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C | + I2C_FUNC_SMBUS_BYTE | + I2C_FUNC_SMBUS_BLOCK_DATA)) + return -ENODEV; + + nct3018y = devm_kzalloc(&client->dev, sizeof(struct nct3018y), + GFP_KERNEL); + if (!nct3018y) + return -ENOMEM; + + i2c_set_clientdata(client, nct3018y); + nct3018y->client = client; + device_set_wakeup_capable(&client->dev, 1); + + flags = i2c_smbus_read_byte_data(client, NCT3018Y_REG_CTRL); + if (flags < 0) { + dev_dbg(&client->dev, "%s: read error\n", __func__); + return flags; + } else if (flags & NCT3018Y_BIT_TWO) { + dev_dbg(&client->dev, "%s: NCT3018Y_BIT_TWO is set\n", __func__); + } + + flags = NCT3018Y_BIT_TWO; + err = i2c_smbus_write_byte_data(client, NCT3018Y_REG_CTRL, flags); + if (err < 0) { + dev_dbg(&client->dev, "Unable to write NCT3018Y_REG_CTRL\n"); + return err; + } + + flags = 0; + err = i2c_smbus_write_byte_data(client, NCT3018Y_REG_ST, flags); + if (err < 0) { + dev_dbg(&client->dev, "%s: write error\n", __func__); + return err; + } + + nct3018y->rtc = devm_rtc_allocate_device(&client->dev); + if (IS_ERR(nct3018y->rtc)) + return PTR_ERR(nct3018y->rtc); + + nct3018y->rtc->ops = &nct3018y_rtc_ops; + nct3018y->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; + nct3018y->rtc->range_max = RTC_TIMESTAMP_END_2099; + + if (client->irq > 0) { + err = devm_request_threaded_irq(&client->dev, client->irq, + NULL, nct3018y_irq, + IRQF_ONESHOT | IRQF_TRIGGER_FALLING, + "nct3018y", client); + if (err) { + dev_dbg(&client->dev, "unable to request IRQ %d\n", client->irq); + return err; + } + } else { + clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, nct3018y->rtc->features); + clear_bit(RTC_FEATURE_ALARM, nct3018y->rtc->features); + } + +#ifdef CONFIG_COMMON_CLK + /* register clk in common clk framework */ + nct3018y_clkout_register_clk(nct3018y); +#endif + + return devm_rtc_register_device(nct3018y->rtc); +} + +static const struct i2c_device_id nct3018y_id[] = { + { "nct3018y", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, nct3018y_id); + +static const struct of_device_id nct3018y_of_match[] = { + { .compatible = "nuvoton,nct3018y" }, + {} +}; +MODULE_DEVICE_TABLE(of, nct3018y_of_match); + +static struct i2c_driver nct3018y_driver = { + .driver = { + .name = "rtc-nct3018y", + .of_match_table = of_match_ptr(nct3018y_of_match), + }, + .probe = nct3018y_probe, + .id_table = nct3018y_id, +}; + +module_i2c_driver(nct3018y_driver); + +MODULE_AUTHOR("Medad CChien "); +MODULE_AUTHOR("Mia Lin "); +MODULE_DESCRIPTION("Nuvoton NCT3018Y RTC driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 12b827758f51d4b614a677dd453b0e854e46aa65 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 7 Jul 2022 01:15:33 +0200 Subject: of: also handle dma-noncoherent in of_dma_is_coherent() of_dma_is_coherent() currently expects the architecture to be non-coherent and some devices being coherent getting marked as such with the dma-coherent devicetree property. For PowerPC CONFIG_OF_DMA_DEFAULT_COHERENT was added which currently makes of_dma_is_coherent() always return true but doesn't handle the case of the architecture being coherent but some devices not. So modify the function to also check for dma-noncoherent and set a suitable default return value. If CONFIG_OF_DMA_DEFAULT_COHERENT is set the value starts with true and finding dma-noncoherent will set it to false and without CONFIG_OF_DMA_DEFAULT_COHERENT, the behaviour is reversed. Reviewed-by: Christoph Hellwig Reviewed-by: Rob Herring Reviewed-by: Guo Ren Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20220706231536.2041855-2-heiko@sntech.de Signed-off-by: Palmer Dabbelt --- drivers/of/address.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/of/address.c b/drivers/of/address.c index 94f017d808c4..96f0a12e507c 100644 --- a/drivers/of/address.c +++ b/drivers/of/address.c @@ -1045,26 +1045,29 @@ phys_addr_t __init of_dma_get_max_cpu_address(struct device_node *np) * * It returns true if "dma-coherent" property was found * for this device in the DT, or if DMA is coherent by - * default for OF devices on the current platform. + * default for OF devices on the current platform and no + * "dma-noncoherent" property was found for this device. */ bool of_dma_is_coherent(struct device_node *np) { struct device_node *node; - - if (IS_ENABLED(CONFIG_OF_DMA_DEFAULT_COHERENT)) - return true; + bool is_coherent = IS_ENABLED(CONFIG_OF_DMA_DEFAULT_COHERENT); node = of_node_get(np); while (node) { if (of_property_read_bool(node, "dma-coherent")) { - of_node_put(node); - return true; + is_coherent = true; + break; + } + if (of_property_read_bool(node, "dma-noncoherent")) { + is_coherent = false; + break; } node = of_get_next_dma_parent(node); } of_node_put(node); - return false; + return is_coherent; } EXPORT_SYMBOL_GPL(of_dma_is_coherent); -- cgit v1.2.3 From d1afce6709595b39cd159bdc54fe2093808c02fc Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 7 Jul 2022 01:15:34 +0200 Subject: dt-bindings: riscv: document cbom-block-size The Zicbom operates on a block-size defined for the cpu-core, which does not necessarily match other cache-sizes used. So add the necessary property for the system to know the core's block-size. Reviewed-by: Anup Patel Reviewed-by: Guo Ren Acked-by: Rob Herring Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20220706231536.2041855-3-heiko@sntech.de Signed-off-by: Palmer Dabbelt --- Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d632ac76532e..873dd12f6e89 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -63,6 +63,11 @@ properties: - riscv,sv48 - riscv,none + riscv,cbom-block-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The blocksize in bytes for the Zicbom cache operations. + riscv,isa: description: Identifies the specific RISC-V instruction set architecture -- cgit v1.2.3 From 1631ba1259d6d7f49b6028f2a1a0fa02be1c522a Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 7 Jul 2022 01:15:35 +0200 Subject: riscv: Add support for non-coherent devices using zicbom extension The Zicbom ISA-extension was ratified in november 2021 and introduces instructions for dcache invalidate, clean and flush operations. Implement cache management operations for non-coherent devices based on them. Of course not all cores will support this, so implement an alternative-based mechanism that replaces empty instructions with ones done around Zicbom instructions. As discussed in previous versions, assume the platform being coherent by default so that non-coherent devices need to get marked accordingly by firmware. Reviewed-by: Christoph Hellwig Signed-off-by: Heiko Stuebner Reviewed-by: Guo Ren Link: https://lore.kernel.org/r/20220706231536.2041855-4-heiko@sntech.de Signed-off-by: Palmer Dabbelt --- arch/riscv/Kconfig | 31 ++++++++++ arch/riscv/Makefile | 4 ++ arch/riscv/include/asm/cache.h | 4 ++ arch/riscv/include/asm/cacheflush.h | 10 ++++ arch/riscv/include/asm/errata_list.h | 19 +++++- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 24 ++++++++ arch/riscv/kernel/setup.c | 2 + arch/riscv/mm/Makefile | 1 + arch/riscv/mm/dma-noncoherent.c | 112 +++++++++++++++++++++++++++++++++++ 11 files changed, 208 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/mm/dma-noncoherent.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 32ffef9f6e5b..897ae28abf81 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -113,6 +113,7 @@ config RISCV select MODULES_USE_ELF_RELA if MODULES select MODULE_SECTIONS if MODULES select OF + select OF_DMA_DEFAULT_COHERENT select OF_EARLY_FLATTREE select OF_IRQ select PCI_DOMAINS_GENERIC if PCI @@ -218,6 +219,14 @@ config PGTABLE_LEVELS config LOCKDEP_SUPPORT def_bool y +config RISCV_DMA_NONCOHERENT + bool + select ARCH_HAS_DMA_PREP_COHERENT + select ARCH_HAS_SYNC_DMA_FOR_DEVICE + select ARCH_HAS_SYNC_DMA_FOR_CPU + select ARCH_HAS_SETUP_DMA_OPS + select DMA_DIRECT_REMAP + source "arch/riscv/Kconfig.socs" source "arch/riscv/Kconfig.erratas" @@ -376,6 +385,28 @@ config RISCV_ISA_SVPBMT If you don't know what to do here, say Y. +config CC_HAS_ZICBOM + bool + default y if 64BIT && $(cc-option,-mabi=lp64 -march=rv64ima_zicbom) + default y if 32BIT && $(cc-option,-mabi=ilp32 -march=rv32ima_zicbom) + +config RISCV_ISA_ZICBOM + bool "Zicbom extension support for non-coherent DMA operation" + depends on CC_HAS_ZICBOM + depends on !XIP_KERNEL + select RISCV_DMA_NONCOHERENT + select RISCV_ALTERNATIVE + default y + help + Adds support to dynamically detect the presence of the ZICBOM + extension (Cache Block Management Operations) and enable its + usage. + + The Zicbom extension can be used to handle for example + non-coherent DMA support on devices that need it. + + If you don't know what to do here, say Y. + config FPU bool "FPU support" default y diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 34cf8a598617..fbaabc98b3d2 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -56,6 +56,10 @@ riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei +# Check if the toolchain supports Zicbom extension +toolchain-supports-zicbom := $(call cc-option-yn, -march=$(riscv-march-y)_zicbom) +riscv-march-$(toolchain-supports-zicbom) := $(riscv-march-y)_zicbom + KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) KBUILD_AFLAGS += -march=$(riscv-march-y) diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index 9b58b104559e..d3036df23ccb 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -11,6 +11,10 @@ #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +#ifdef CONFIG_RISCV_DMA_NONCOHERENT +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES +#endif + /* * RISC-V requires the stack pointer to be 16-byte aligned, so ensure that * the flat loader aligns it accordingly. diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index 23ff70350992..a60acaecfeda 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -42,6 +42,16 @@ void flush_icache_mm(struct mm_struct *mm, bool local); #endif /* CONFIG_SMP */ +#ifdef CONFIG_RISCV_ISA_ZICBOM +void riscv_init_cbom_blocksize(void); +#else +static inline void riscv_init_cbom_blocksize(void) { } +#endif + +#ifdef CONFIG_RISCV_DMA_NONCOHERENT +void riscv_noncoherent_supported(void); +#endif + /* * Bits in sys_riscv_flush_icache()'s flags argument. */ diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index 9e2888dbb5b1..f7c015005847 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -20,7 +20,8 @@ #endif #define CPUFEATURE_SVPBMT 0 -#define CPUFEATURE_NUMBER 1 +#define CPUFEATURE_ZICBOM 1 +#define CPUFEATURE_NUMBER 2 #ifdef __ASSEMBLY__ @@ -93,6 +94,22 @@ asm volatile(ALTERNATIVE( \ #define ALT_THEAD_PMA(_val) #endif +#define ALT_CMO_OP(_op, _start, _size, _cachesize) \ +asm volatile(ALTERNATIVE( \ + __nops(5), \ + "mv a0, %1\n\t" \ + "j 2f\n\t" \ + "3:\n\t" \ + "cbo." __stringify(_op) " (a0)\n\t" \ + "add a0, a0, %0\n\t" \ + "2:\n\t" \ + "bltu a0, %2, 3b\n\t", 0, \ + CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM) \ + : : "r"(_cachesize), \ + "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \ + "r"((unsigned long)(_start) + (_size)) \ + : "a0") + #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index e48eebdd2631..ed4045e70f7a 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -54,6 +54,7 @@ extern unsigned long elf_hwcap; enum riscv_isa_ext_id { RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, RISCV_ISA_EXT_SVPBMT, + RISCV_ISA_EXT_ZICBOM, RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index fba9e9f46a8c..0365557f7122 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -89,6 +89,7 @@ int riscv_of_parent_hartid(struct device_node *node) static struct riscv_isa_ext_data isa_ext_arr[] = { __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), + __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), }; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1b3ec44e25f5..1e33beda4f01 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -198,6 +199,7 @@ void __init riscv_fill_hwcap(void) } else { SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); + SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); } #undef SET_ISA_EXT_MAP } @@ -259,6 +261,25 @@ static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage) return false; } +static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage) +{ +#ifdef CONFIG_RISCV_ISA_ZICBOM + switch (stage) { + case RISCV_ALTERNATIVES_EARLY_BOOT: + return false; + default: + if (riscv_isa_extension_available(NULL, ZICBOM)) { + riscv_noncoherent_supported(); + return true; + } else { + return false; + } + } +#endif + + return false; +} + /* * Probe presence of individual extensions. * @@ -273,6 +294,9 @@ static u32 __init_or_module cpufeature_probe(unsigned int stage) if (cpufeature_probe_svpbmt(stage)) cpu_req_feature |= (1U << CPUFEATURE_SVPBMT); + if (cpufeature_probe_zicbom(stage)) + cpu_req_feature |= (1U << CPUFEATURE_ZICBOM); + return cpu_req_feature; } diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index f0f36a4a0e9b..95ef6e2bf45c 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -296,6 +297,7 @@ void __init setup_arch(char **cmdline_p) #endif riscv_fill_hwcap(); + riscv_init_cbom_blocksize(); apply_boot_alternatives(); } diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile index ac7a25298a04..d76aabf4b94d 100644 --- a/arch/riscv/mm/Makefile +++ b/arch/riscv/mm/Makefile @@ -30,3 +30,4 @@ endif endif obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o +obj-$(CONFIG_RISCV_DMA_NONCOHERENT) += dma-noncoherent.o diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c new file mode 100644 index 000000000000..a8dc0bd9078d --- /dev/null +++ b/arch/riscv/mm/dma-noncoherent.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RISC-V specific functions to support DMA for non-coherent devices + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + */ + +#include +#include +#include +#include +#include +#include + +static unsigned int riscv_cbom_block_size = L1_CACHE_BYTES; +static bool noncoherent_supported; + +void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, + enum dma_data_direction dir) +{ + void *vaddr = phys_to_virt(paddr); + + switch (dir) { + case DMA_TO_DEVICE: + ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); + break; + case DMA_FROM_DEVICE: + ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); + break; + case DMA_BIDIRECTIONAL: + ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); + break; + default: + break; + } +} + +void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, + enum dma_data_direction dir) +{ + void *vaddr = phys_to_virt(paddr); + + switch (dir) { + case DMA_TO_DEVICE: + break; + case DMA_FROM_DEVICE: + case DMA_BIDIRECTIONAL: + ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); + break; + default: + break; + } +} + +void arch_dma_prep_coherent(struct page *page, size_t size) +{ + void *flush_addr = page_address(page); + + ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size); +} + +void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, + const struct iommu_ops *iommu, bool coherent) +{ + WARN_TAINT(!coherent && riscv_cbom_block_size > ARCH_DMA_MINALIGN, + TAINT_CPU_OUT_OF_SPEC, + "%s %s: ARCH_DMA_MINALIGN smaller than riscv,cbom-block-size (%d < %d)", + dev_driver_string(dev), dev_name(dev), + ARCH_DMA_MINALIGN, riscv_cbom_block_size); + + WARN_TAINT(!coherent && !noncoherent_supported, TAINT_CPU_OUT_OF_SPEC, + "%s %s: device non-coherent but no non-coherent operations supported", + dev_driver_string(dev), dev_name(dev)); + + dev->dma_coherent = coherent; +} + +#ifdef CONFIG_RISCV_ISA_ZICBOM +void riscv_init_cbom_blocksize(void) +{ + struct device_node *node; + int ret; + u32 val; + + for_each_of_cpu_node(node) { + int hartid = riscv_of_processor_hartid(node); + int cbom_hartid; + + if (hartid < 0) + continue; + + /* set block-size for cbom extension if available */ + ret = of_property_read_u32(node, "riscv,cbom-block-size", &val); + if (ret) + continue; + + if (!riscv_cbom_block_size) { + riscv_cbom_block_size = val; + cbom_hartid = hartid; + } else { + if (riscv_cbom_block_size != val) + pr_warn("cbom-block-size mismatched between harts %d and %d\n", + cbom_hartid, hartid); + } + } +} +#endif + +void riscv_noncoherent_supported(void) +{ + noncoherent_supported = true; +} -- cgit v1.2.3 From f00e0d7714895d10790e2bac4df00727ddb9abff Mon Sep 17 00:00:00 2001 From: William Dean Date: Sat, 23 Jul 2022 14:40:27 +0800 Subject: scsi: lpfc: Check the return value of alloc_workqueue() The function alloc_workqueue() in lpfc_sli4_driver_resource_setup() can fail, but there is no check of its return value. The return value should be checked. Link: https://lore.kernel.org/r/20220723064027.2956623-1-williamsukatube@163.com Fixes: 3cee98db2610 ("scsi: lpfc: Fix crash on driver unload in wq free") Reported-by: Hacash Robot Reviewed-by: James Smart Signed-off-by: William Dean Signed-off-by: Martin K. Petersen --- drivers/scsi/lpfc/lpfc_init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/scsi/lpfc/lpfc_init.c b/drivers/scsi/lpfc/lpfc_init.c index 4a0eadd1c22c..c69c5a0979ec 100644 --- a/drivers/scsi/lpfc/lpfc_init.c +++ b/drivers/scsi/lpfc/lpfc_init.c @@ -7948,6 +7948,8 @@ lpfc_sli4_driver_resource_setup(struct lpfc_hba *phba) /* The lpfc_wq workqueue for deferred irq use */ phba->wq = alloc_workqueue("lpfc_wq", WQ_MEM_RECLAIM, 0); + if (!phba->wq) + return -ENOMEM; /* * Initialize timers used by driver -- cgit v1.2.3 From 86a44f045b8cbfd885b7425f4cd8a1c353593057 Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Tue, 26 Jul 2022 15:52:21 -0700 Subject: scsi: ufs: core: Increase the maximum data buffer size Measurements for one particular UFS controller + UFS device show a 25% higher read bandwidth if the maximum data buffer size is increased from 512 KiB to 1 MiB. Hence increase the maximum size of the data buffer associated with a single request from SCSI_DEFAULT_MAX_SECTORS (1024) * 512 bytes = 512 KiB to 1 MiB. Notes: - The maximum data buffer size supported by the UFSHCI specification is 65535 * 256 KiB or about 16 GiB. - The maximum data buffer size for READ(10) commands is 65535 logical blocks. To transfer more than 65535 * 4096 bytes = 255 MiB with a single SCSI command, the READ(16) command is required. Support for READ(16) is optional in the UFS 3.1 and UFS 4.0 standards. Link: https://lore.kernel.org/r/20220726225232.1362251-1-bvanassche@acm.org Cc: Adrian Hunter Cc: Avri Altman Cc: Bean Huo Cc: Stanley Chu Tested-by: Avri Altman Acked-by: Avri Altman Signed-off-by: Bart Van Assche Signed-off-by: Martin K. Petersen --- drivers/ufs/core/ufshcd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index f4f8ded97ef2..dbe74f6b0c47 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -8304,6 +8304,7 @@ static struct scsi_host_template ufshcd_driver_template = { .cmd_per_lun = UFSHCD_CMD_PER_LUN, .can_queue = UFSHCD_CAN_QUEUE, .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX, + .max_sectors = (1 << 20) / SECTOR_SIZE, /* 1 MiB */ .max_host_blocked = 1, .track_queue_depth = 1, .sdev_groups = ufshcd_driver_groups, -- cgit v1.2.3 From 00511d2abf5708ad05dd5d1c36adb2468d274698 Mon Sep 17 00:00:00 2001 From: Peter Wang Date: Wed, 27 Jul 2022 11:05:26 +0800 Subject: scsi: ufs: core: Correct ufshcd_shutdown() flow After ufshcd_wl_shutdown() set device power off and link off, ufshcd_shutdown() could turn off clock/power. Also remove pm_runtime_get_sync. The reason why it is safe to remove pm_runtime_get_sync() is because: - ufshcd_wl_shutdown() -> pm_runtime_get_sync() will resume hba->dev too. - device resume(turn on clk/power) is not required, even if device is in RPM_SUSPENDED. Link: https://lore.kernel.org/r/20220727030526.31022-1-peter.wang@mediatek.com Fixes: b294ff3e3449 ("scsi: ufs: core: Enable power management for wlun") Cc: # 5.15.x Reviewed-by: Stanley Chu Signed-off-by: Peter Wang Signed-off-by: Martin K. Petersen --- drivers/ufs/core/ufshcd.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index dbe74f6b0c47..0dc6437e956a 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -9487,12 +9487,8 @@ EXPORT_SYMBOL(ufshcd_runtime_resume); int ufshcd_shutdown(struct ufs_hba *hba) { if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba)) - goto out; - - pm_runtime_get_sync(hba->dev); + ufshcd_suspend(hba); - ufshcd_suspend(hba); -out: hba->is_powered = false; /* allow force shutdown even in case of errors */ return 0; -- cgit v1.2.3 From dd0a66ada0bd0ae6c96ea45cfa1581797e867a40 Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Thu, 28 Jul 2022 00:41:24 +0300 Subject: scsi: target: core: Fix race during ACL removal Under huge load there is a possibility of race condition in updating se_dev_entry object in ACL removal procedure: NIP [c0080000154093d0] transport_lookup_cmd_lun+0x1f8/0x3d0 [target_core_mod] LR [c00800001542ab34] target_submit_cmd_map_sgls+0x11c/0x300 [target_core_mod] Call Trace: target_submit_cmd_map_sgls+0x11c/0x300 [target_core_mod] target_submit_cmd+0x44/0x60 [target_core_mod] tcm_qla2xxx_handle_cmd+0x88/0xe0 [tcm_qla2xxx] qlt_do_work+0x2e4/0x3d0 [qla2xxx] process_one_work+0x298/0x5c Despite usage of RCU primitives with deve->se_lun pointer, it has not become dereference-safe because deve->se_lun is updated and not synchronized with a reader. That change might be in a release function called by synchronize_rcu(). But, in fact, there is no point in setting that pointer to NULL for deleting deve. All access to deve->se_lun is already under rcu_read_lock. And either deve->se_lun is always valid or deve is not valid itself and will not be found in the list_for_*. The same applicable for deve->se_lun_acl too. So a better solution is to remove that NULLing. Link: https://lore.kernel.org/r/20220727214125.19647-2-d.bogdanov@yadro.com Reviewed-by: Mike Christie Signed-off-by: Dmitry Bogdanov Signed-off-by: Martin K. Petersen --- drivers/target/target_core_device.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/target/target_core_device.c b/drivers/target/target_core_device.c index 086ac9c9343c..88a844ae1fd0 100644 --- a/drivers/target/target_core_device.c +++ b/drivers/target/target_core_device.c @@ -434,9 +434,6 @@ void core_disable_device_list_for_node( kref_put(&orig->pr_kref, target_pr_kref_release); wait_for_completion(&orig->pr_comp); - rcu_assign_pointer(orig->se_lun, NULL); - rcu_assign_pointer(orig->se_lun_acl, NULL); - kfree_rcu(orig, rcu_head); core_scsi3_free_pr_reg_from_nacl(dev, nacl); -- cgit v1.2.3 From ef4f7e4bf1dc26aaa86cf8e5a13013684139be51 Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Thu, 28 Jul 2022 00:41:25 +0300 Subject: scsi: target: core: De-RCU of se_lun and se_lun acl se_lun and se_lun_acl are immutable pointers of struct se_dev_entry. Remove RCU usage for access to those pointers. Link: https://lore.kernel.org/r/20220727214125.19647-3-d.bogdanov@yadro.com Reviewed-by: Mike Christie Signed-off-by: Dmitry Bogdanov Signed-off-by: Martin K. Petersen --- drivers/target/target_core_alua.c | 3 +-- drivers/target/target_core_device.c | 29 +++++++++++------------------ drivers/target/target_core_pr.c | 28 ++++++++-------------------- drivers/target/target_core_stat.c | 10 ++++------ drivers/target/target_core_xcopy.c | 2 +- include/target/target_core_base.h | 4 ++-- 6 files changed, 27 insertions(+), 49 deletions(-) diff --git a/drivers/target/target_core_alua.c b/drivers/target/target_core_alua.c index 58df0145e8d0..fb91423a4e2e 100644 --- a/drivers/target/target_core_alua.c +++ b/drivers/target/target_core_alua.c @@ -934,8 +934,7 @@ static void core_alua_queue_state_change_ua(struct t10_alua_tg_pt_gp *tg_pt_gp) spin_lock(&lun->lun_deve_lock); list_for_each_entry(se_deve, &lun->lun_deve_list, lun_link) { - lacl = rcu_dereference_check(se_deve->se_lun_acl, - lockdep_is_held(&lun->lun_deve_lock)); + lacl = se_deve->se_lun_acl; /* * spc4r37 p.242: diff --git a/drivers/target/target_core_device.c b/drivers/target/target_core_device.c index 88a844ae1fd0..b7f16ee8aa0e 100644 --- a/drivers/target/target_core_device.c +++ b/drivers/target/target_core_device.c @@ -75,7 +75,7 @@ transport_lookup_cmd_lun(struct se_cmd *se_cmd) return TCM_WRITE_PROTECTED; } - se_lun = rcu_dereference(deve->se_lun); + se_lun = deve->se_lun; if (!percpu_ref_tryget_live(&se_lun->lun_ref)) { se_lun = NULL; @@ -152,7 +152,7 @@ int transport_lookup_tmr_lun(struct se_cmd *se_cmd) rcu_read_lock(); deve = target_nacl_find_deve(nacl, se_cmd->orig_fe_lun); if (deve) { - se_lun = rcu_dereference(deve->se_lun); + se_lun = deve->se_lun; if (!percpu_ref_tryget_live(&se_lun->lun_ref)) { se_lun = NULL; @@ -216,7 +216,7 @@ struct se_dev_entry *core_get_se_deve_from_rtpi( rcu_read_lock(); hlist_for_each_entry_rcu(deve, &nacl->lun_entry_hlist, link) { - lun = rcu_dereference(deve->se_lun); + lun = deve->se_lun; if (!lun) { pr_err("%s device entries device pointer is" " NULL, but Initiator has access.\n", @@ -243,11 +243,8 @@ void core_free_device_list_for_node( struct se_dev_entry *deve; mutex_lock(&nacl->lun_entry_mutex); - hlist_for_each_entry_rcu(deve, &nacl->lun_entry_hlist, link) { - struct se_lun *lun = rcu_dereference_check(deve->se_lun, - lockdep_is_held(&nacl->lun_entry_mutex)); - core_disable_device_list_for_node(lun, deve, nacl, tpg); - } + hlist_for_each_entry_rcu(deve, &nacl->lun_entry_hlist, link) + core_disable_device_list_for_node(deve->se_lun, deve, nacl, tpg); mutex_unlock(&nacl->lun_entry_mutex); } @@ -334,8 +331,7 @@ int core_enable_device_list_for_node( mutex_lock(&nacl->lun_entry_mutex); orig = target_nacl_find_deve(nacl, mapped_lun); if (orig && orig->se_lun) { - struct se_lun *orig_lun = rcu_dereference_check(orig->se_lun, - lockdep_is_held(&nacl->lun_entry_mutex)); + struct se_lun *orig_lun = orig->se_lun; if (orig_lun != lun) { pr_err("Existing orig->se_lun doesn't match new lun" @@ -355,8 +351,8 @@ int core_enable_device_list_for_node( return -EINVAL; } - rcu_assign_pointer(new->se_lun, lun); - rcu_assign_pointer(new->se_lun_acl, lun_acl); + new->se_lun = lun; + new->se_lun_acl = lun_acl; hlist_del_rcu(&orig->link); hlist_add_head_rcu(&new->link, &nacl->lun_entry_hlist); mutex_unlock(&nacl->lun_entry_mutex); @@ -374,8 +370,8 @@ int core_enable_device_list_for_node( return 0; } - rcu_assign_pointer(new->se_lun, lun); - rcu_assign_pointer(new->se_lun_acl, lun_acl); + new->se_lun = lun; + new->se_lun_acl = lun_acl; hlist_add_head_rcu(&new->link, &nacl->lun_entry_hlist); mutex_unlock(&nacl->lun_entry_mutex); @@ -454,10 +450,7 @@ void core_clear_lun_from_tpg(struct se_lun *lun, struct se_portal_group *tpg) mutex_lock(&nacl->lun_entry_mutex); hlist_for_each_entry_rcu(deve, &nacl->lun_entry_hlist, link) { - struct se_lun *tmp_lun = rcu_dereference_check(deve->se_lun, - lockdep_is_held(&nacl->lun_entry_mutex)); - - if (lun != tmp_lun) + if (lun != deve->se_lun) continue; core_disable_device_list_for_node(lun, deve, nacl, tpg); diff --git a/drivers/target/target_core_pr.c b/drivers/target/target_core_pr.c index 3829b61b56c1..a1d67554709f 100644 --- a/drivers/target/target_core_pr.c +++ b/drivers/target/target_core_pr.c @@ -739,8 +739,7 @@ static struct t10_pr_registration *__core_scsi3_alloc_registration( if (!deve_tmp->se_lun_acl) continue; - lacl_tmp = rcu_dereference_check(deve_tmp->se_lun_acl, - lockdep_is_held(&lun_tmp->lun_deve_lock)); + lacl_tmp = deve_tmp->se_lun_acl; nacl_tmp = lacl_tmp->se_lun_nacl; /* * Skip the matching struct se_node_acl that is allocated @@ -784,8 +783,7 @@ static struct t10_pr_registration *__core_scsi3_alloc_registration( * the original *pr_reg is processed in * __core_scsi3_add_registration() */ - dest_lun = rcu_dereference_check(deve_tmp->se_lun, - kref_read(&deve_tmp->pr_kref) != 0); + dest_lun = deve_tmp->se_lun; pr_reg_atp = __core_scsi3_do_alloc_registration(dev, nacl_tmp, dest_lun, deve_tmp, @@ -1437,34 +1435,26 @@ static void core_scsi3_nodeacl_undepend_item(struct se_node_acl *nacl) static int core_scsi3_lunacl_depend_item(struct se_dev_entry *se_deve) { - struct se_lun_acl *lun_acl; - /* * For nacl->dynamic_node_acl=1 */ - lun_acl = rcu_dereference_check(se_deve->se_lun_acl, - kref_read(&se_deve->pr_kref) != 0); - if (!lun_acl) + if (!se_deve->se_lun_acl) return 0; - return target_depend_item(&lun_acl->se_lun_group.cg_item); + return target_depend_item(&se_deve->se_lun_acl->se_lun_group.cg_item); } static void core_scsi3_lunacl_undepend_item(struct se_dev_entry *se_deve) { - struct se_lun_acl *lun_acl; - /* * For nacl->dynamic_node_acl=1 */ - lun_acl = rcu_dereference_check(se_deve->se_lun_acl, - kref_read(&se_deve->pr_kref) != 0); - if (!lun_acl) { + if (!se_deve->se_lun_acl) { kref_put(&se_deve->pr_kref, target_pr_kref_release); return; } - target_undepend_item(&lun_acl->se_lun_group.cg_item); + target_undepend_item(&se_deve->se_lun_acl->se_lun_group.cg_item); kref_put(&se_deve->pr_kref, target_pr_kref_release); } @@ -1751,8 +1741,7 @@ core_scsi3_decode_spec_i_port( * and then call __core_scsi3_add_registration() in the * 2nd loop which will never fail. */ - dest_lun = rcu_dereference_check(dest_se_deve->se_lun, - kref_read(&dest_se_deve->pr_kref) != 0); + dest_lun = dest_se_deve->se_lun; dest_pr_reg = __core_scsi3_alloc_registration(cmd->se_dev, dest_node_acl, dest_lun, dest_se_deve, @@ -3446,8 +3435,7 @@ after_iport_check: dest_pr_reg = __core_scsi3_locate_pr_reg(dev, dest_node_acl, iport_ptr); if (!dest_pr_reg) { - struct se_lun *dest_lun = rcu_dereference_check(dest_se_deve->se_lun, - kref_read(&dest_se_deve->pr_kref) != 0); + struct se_lun *dest_lun = dest_se_deve->se_lun; spin_unlock(&dev->dev_reservation_lock); if (core_scsi3_alloc_registration(cmd->se_dev, dest_node_acl, diff --git a/drivers/target/target_core_stat.c b/drivers/target/target_core_stat.c index 62d15bcc3d93..f85ee5b0fd80 100644 --- a/drivers/target/target_core_stat.c +++ b/drivers/target/target_core_stat.c @@ -877,7 +877,6 @@ static ssize_t target_stat_auth_dev_show(struct config_item *item, struct se_lun_acl *lacl = auth_to_lacl(item); struct se_node_acl *nacl = lacl->se_lun_nacl; struct se_dev_entry *deve; - struct se_lun *lun; ssize_t ret; rcu_read_lock(); @@ -886,9 +885,9 @@ static ssize_t target_stat_auth_dev_show(struct config_item *item, rcu_read_unlock(); return -ENODEV; } - lun = rcu_dereference(deve->se_lun); + /* scsiDeviceIndex */ - ret = snprintf(page, PAGE_SIZE, "%u\n", lun->lun_index); + ret = snprintf(page, PAGE_SIZE, "%u\n", deve->se_lun->lun_index); rcu_read_unlock(); return ret; } @@ -1217,7 +1216,6 @@ static ssize_t target_stat_iport_dev_show(struct config_item *item, struct se_lun_acl *lacl = iport_to_lacl(item); struct se_node_acl *nacl = lacl->se_lun_nacl; struct se_dev_entry *deve; - struct se_lun *lun; ssize_t ret; rcu_read_lock(); @@ -1226,9 +1224,9 @@ static ssize_t target_stat_iport_dev_show(struct config_item *item, rcu_read_unlock(); return -ENODEV; } - lun = rcu_dereference(deve->se_lun); + /* scsiDeviceIndex */ - ret = snprintf(page, PAGE_SIZE, "%u\n", lun->lun_index); + ret = snprintf(page, PAGE_SIZE, "%u\n", deve->se_lun->lun_index); rcu_read_unlock(); return ret; } diff --git a/drivers/target/target_core_xcopy.c b/drivers/target/target_core_xcopy.c index 6bb20aa9c5bc..8713cda0c2fb 100644 --- a/drivers/target/target_core_xcopy.c +++ b/drivers/target/target_core_xcopy.c @@ -88,7 +88,7 @@ static int target_xcopy_locate_se_dev_e4(struct se_session *sess, struct se_device *this_dev; int rc; - this_lun = rcu_dereference(deve->se_lun); + this_lun = deve->se_lun; this_dev = rcu_dereference_raw(this_lun->lun_se_dev); rc = target_xcopy_locate_se_dev_e4_iter(this_dev, dev_wwn); diff --git a/include/target/target_core_base.h b/include/target/target_core_base.h index c2b36f7d917d..8c920456edd9 100644 --- a/include/target/target_core_base.h +++ b/include/target/target_core_base.h @@ -665,9 +665,9 @@ struct se_dev_entry { /* Used for PR SPEC_I_PT=1 and REGISTER_AND_MOVE */ struct kref pr_kref; struct completion pr_comp; - struct se_lun_acl __rcu *se_lun_acl; + struct se_lun_acl *se_lun_acl; spinlock_t ua_lock; - struct se_lun __rcu *se_lun; + struct se_lun *se_lun; #define DEF_PR_REG_ACTIVE 1 unsigned long deve_flags; struct list_head alua_port_list; -- cgit v1.2.3 From a19066788d875731a01ee7fa189b2202f0120036 Mon Sep 17 00:00:00 2001 From: Daniil Lunev Date: Thu, 28 Jul 2022 11:18:21 +1000 Subject: scsi: ufs: ufs-pci: Correct check for RESET DSM dsm_fns is a bitmap, and it is 0-indexed according to the check in __intel_dsm function. But common initialization was checking it as if it was 1-indexed. This patch corrects the discrepancy. This change won't break any existing calls to the function, since before the change both bits 0 and 1 were checked and needed to be set. Link: https://lore.kernel.org/r/20220728111748.v3.1.I22460c4f4a9ccf2c96c3f9bb392b409926d80b2f@changeid Reviewed-by: Adrian Hunter Signed-off-by: Daniil Lunev Signed-off-by: Martin K. Petersen --- drivers/ufs/host/ufshcd-pci.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/ufs/host/ufshcd-pci.c b/drivers/ufs/host/ufshcd-pci.c index 24af1f389bf2..1c91f43e15c8 100644 --- a/drivers/ufs/host/ufshcd-pci.c +++ b/drivers/ufs/host/ufshcd-pci.c @@ -24,7 +24,7 @@ struct ufs_host { void (*late_init)(struct ufs_hba *hba); }; -enum { +enum intel_ufs_dsm_func_id { INTEL_DSM_FNS = 0, INTEL_DSM_RESET = 1, }; @@ -42,6 +42,15 @@ static const guid_t intel_dsm_guid = GUID_INIT(0x1A4832A0, 0x7D03, 0x43CA, 0xB0, 0x20, 0xF6, 0xDC, 0xD1, 0x2A, 0x19, 0x50); +static bool __intel_dsm_supported(struct intel_host *host, + enum intel_ufs_dsm_func_id fn) +{ + return fn < 32 && fn >= 0 && (host->dsm_fns & (1u << fn)); +} + +#define INTEL_DSM_SUPPORTED(host, name) \ + __intel_dsm_supported(host, INTEL_DSM_##name) + static int __intel_dsm(struct intel_host *intel_host, struct device *dev, unsigned int fn, u32 *result) { @@ -71,7 +80,7 @@ out: static int intel_dsm(struct intel_host *intel_host, struct device *dev, unsigned int fn, u32 *result) { - if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) + if (!__intel_dsm_supported(intel_host, fn)) return -EOPNOTSUPP; return __intel_dsm(intel_host, dev, fn, result); @@ -300,7 +309,7 @@ static int ufs_intel_device_reset(struct ufs_hba *hba) { struct intel_host *host = ufshcd_get_variant(hba); - if (host->dsm_fns & INTEL_DSM_RESET) { + if (INTEL_DSM_SUPPORTED(host, RESET)) { u32 result = 0; int err; @@ -342,7 +351,7 @@ static int ufs_intel_common_init(struct ufs_hba *hba) return -ENOMEM; ufshcd_set_variant(hba, host); intel_dsm_init(host, hba->dev); - if (host->dsm_fns & INTEL_DSM_RESET) { + if (INTEL_DSM_SUPPORTED(host, RESET)) { if (hba->vops->device_reset) hba->caps |= UFSHCD_CAP_DEEPSLEEP; } else { -- cgit v1.2.3 From fe442604199ed3e60d5411137159f9623534e956 Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Thu, 28 Jul 2022 15:18:48 -0700 Subject: scsi: core: Make sure that targets outlive devices This commit prevents that the following sequence triggers a kernel crash: - Deletion of a SCSI device is requested via sysfs. Device removal takes some time because blk_cleanup_queue() is waiting for the SCSI error handler. - The SCSI target associated with that SCSI device is removed. - scsi_remove_target() returns and its caller frees the resources associated with the SCSI target. - The error handler makes progress and invokes an LLD callback that dereferences the SCSI target pointer. Link: https://lore.kernel.org/r/20220728221851.1822295-2-bvanassche@acm.org Cc: Christoph Hellwig Cc: Mike Christie Cc: Hannes Reinecke Cc: John Garry Cc: Li Zhijian Reported-by: Mike Christie Reviewed-by: Ming Lei Reviewed-by: Mike Christie Signed-off-by: Bart Van Assche Signed-off-by: Martin K. Petersen --- drivers/scsi/scsi_scan.c | 2 ++ drivers/scsi/scsi_sysfs.c | 20 +++++++++++++++++--- include/scsi/scsi_device.h | 2 ++ 3 files changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/scsi/scsi_scan.c b/drivers/scsi/scsi_scan.c index 91ac901a6682..4c1efd6a3b0c 100644 --- a/drivers/scsi/scsi_scan.c +++ b/drivers/scsi/scsi_scan.c @@ -521,6 +521,8 @@ static struct scsi_target *scsi_alloc_target(struct device *parent, starget->state = STARGET_CREATED; starget->scsi_level = SCSI_2; starget->max_target_blocked = SCSI_DEFAULT_TARGET_BLOCKED; + init_waitqueue_head(&starget->sdev_wq); + retry: spin_lock_irqsave(shost->host_lock, flags); diff --git a/drivers/scsi/scsi_sysfs.c b/drivers/scsi/scsi_sysfs.c index 43949798a2e4..1bc9c26fe1d4 100644 --- a/drivers/scsi/scsi_sysfs.c +++ b/drivers/scsi/scsi_sysfs.c @@ -443,7 +443,9 @@ static void scsi_device_cls_release(struct device *class_dev) static void scsi_device_dev_release_usercontext(struct work_struct *work) { - struct scsi_device *sdev; + struct scsi_device *sdev = container_of(work, struct scsi_device, + ew.work); + struct scsi_target *starget = sdev->sdev_target; struct device *parent; struct list_head *this, *tmp; struct scsi_vpd *vpd_pg80 = NULL, *vpd_pg83 = NULL; @@ -452,8 +454,6 @@ static void scsi_device_dev_release_usercontext(struct work_struct *work) unsigned long flags; struct module *mod; - sdev = container_of(work, struct scsi_device, ew.work); - mod = sdev->host->hostt->module; scsi_dh_release_device(sdev); @@ -516,6 +516,9 @@ static void scsi_device_dev_release_usercontext(struct work_struct *work) kfree(sdev->inquiry); kfree(sdev); + if (starget && atomic_dec_return(&starget->sdev_count) == 0) + wake_up(&starget->sdev_wq); + if (parent) put_device(parent); module_put(mod); @@ -1535,6 +1538,14 @@ static void __scsi_remove_target(struct scsi_target *starget) goto restart; } spin_unlock_irqrestore(shost->host_lock, flags); + + /* + * After scsi_remove_target() returns its caller can remove resources + * associated with @starget, e.g. an rport or session. Wait until all + * devices associated with @starget have been removed to prevent that + * a SCSI error handling callback function triggers a use-after-free. + */ + wait_event(starget->sdev_wq, atomic_read(&starget->sdev_count) == 0); } /** @@ -1645,6 +1656,9 @@ void scsi_sysfs_device_initialize(struct scsi_device *sdev) list_add_tail(&sdev->same_target_siblings, &starget->devices); list_add_tail(&sdev->siblings, &shost->__devices); spin_unlock_irqrestore(shost->host_lock, flags); + + atomic_inc(&starget->sdev_count); + /* * device can now only be removed via __scsi_remove_device() so hold * the target. Target will be held in CREATED state until something diff --git a/include/scsi/scsi_device.h b/include/scsi/scsi_device.h index 7cf5f3b7589f..190d2081f4c6 100644 --- a/include/scsi/scsi_device.h +++ b/include/scsi/scsi_device.h @@ -309,6 +309,8 @@ struct scsi_target { struct list_head devices; struct device dev; struct kref reap_ref; /* last put renders target invisible */ + atomic_t sdev_count; + wait_queue_head_t sdev_wq; unsigned int channel; unsigned int id; /* target id ... replace * scsi_device.id eventually */ -- cgit v1.2.3 From 16728aaba62e8b3b170735fdc3d8aa972835c136 Mon Sep 17 00:00:00 2001 From: Ming Lei Date: Thu, 28 Jul 2022 15:18:49 -0700 Subject: scsi: core: Make sure that hosts outlive targets Fix the race conditions between SCSI LLD kernel module unloading and SCSI device and target removal by making sure that SCSI hosts are destroyed after all associated target and device objects have been freed. Link: https://lore.kernel.org/r/20220728221851.1822295-3-bvanassche@acm.org Cc: Christoph Hellwig Cc: Ming Lei Cc: Mike Christie Cc: Hannes Reinecke Cc: John Garry Reviewed-by: Mike Christie Signed-off-by: Ming Lei Signed-off-by: Bart Van Assche [ bvanassche: Reworked Ming's patch and split it ] Signed-off-by: Martin K. Petersen --- drivers/scsi/hosts.c | 8 ++++++++ drivers/scsi/scsi_scan.c | 7 +++++++ include/scsi/scsi_host.h | 3 +++ 3 files changed, 18 insertions(+) diff --git a/drivers/scsi/hosts.c b/drivers/scsi/hosts.c index ef6c0e37acce..8fa98c8d0ee0 100644 --- a/drivers/scsi/hosts.c +++ b/drivers/scsi/hosts.c @@ -190,6 +190,13 @@ void scsi_remove_host(struct Scsi_Host *shost) transport_unregister_device(&shost->shost_gendev); device_unregister(&shost->shost_dev); device_del(&shost->shost_gendev); + + /* + * After scsi_remove_host() has returned the scsi LLD module can be + * unloaded and/or the host resources can be released. Hence wait until + * the dependent SCSI targets and devices are gone before returning. + */ + wait_event(shost->targets_wq, atomic_read(&shost->target_count) == 0); } EXPORT_SYMBOL(scsi_remove_host); @@ -394,6 +401,7 @@ struct Scsi_Host *scsi_host_alloc(struct scsi_host_template *sht, int privsize) INIT_LIST_HEAD(&shost->starved_list); init_waitqueue_head(&shost->host_wait); mutex_init(&shost->scan_mutex); + init_waitqueue_head(&shost->targets_wq); index = ida_alloc(&host_index_ida, GFP_KERNEL); if (index < 0) { diff --git a/drivers/scsi/scsi_scan.c b/drivers/scsi/scsi_scan.c index 4c1efd6a3b0c..ac6059702d13 100644 --- a/drivers/scsi/scsi_scan.c +++ b/drivers/scsi/scsi_scan.c @@ -406,9 +406,14 @@ static void scsi_target_destroy(struct scsi_target *starget) static void scsi_target_dev_release(struct device *dev) { struct device *parent = dev->parent; + struct Scsi_Host *shost = dev_to_shost(parent); struct scsi_target *starget = to_scsi_target(dev); kfree(starget); + + if (atomic_dec_return(&shost->target_count) == 0) + wake_up(&shost->targets_wq); + put_device(parent); } @@ -523,6 +528,8 @@ static struct scsi_target *scsi_alloc_target(struct device *parent, starget->max_target_blocked = SCSI_DEFAULT_TARGET_BLOCKED; init_waitqueue_head(&starget->sdev_wq); + atomic_inc(&shost->target_count); + retry: spin_lock_irqsave(shost->host_lock, flags); diff --git a/include/scsi/scsi_host.h b/include/scsi/scsi_host.h index 667d889b92b5..339f975d356e 100644 --- a/include/scsi/scsi_host.h +++ b/include/scsi/scsi_host.h @@ -689,6 +689,9 @@ struct Scsi_Host { /* ldm bits */ struct device shost_gendev, shost_dev; + atomic_t target_count; + wait_queue_head_t targets_wq; + /* * Points to the transport data (if any) which is allocated * separately -- cgit v1.2.3 From 1a9283782df2c91c7db5656753a2f548c43de6a7 Mon Sep 17 00:00:00 2001 From: Ming Lei Date: Thu, 28 Jul 2022 15:18:50 -0700 Subject: scsi: core: Simplify LLD module reference counting Swap two statements in scsi_device_put() now that it is guaranteed that SCSI hosts outlive SCSI devices. Remove the reference counting code from scsi_sysfs.c that became superfluous because SCSI hosts now outlive SCSI devices. Link: https://lore.kernel.org/r/20220728221851.1822295-4-bvanassche@acm.org Cc: Christoph Hellwig Cc: Ming Lei Cc: Mike Christie Cc: Hannes Reinecke Cc: John Garry Reviewed-by: Mike Christie Signed-off-by: Ming Lei Signed-off-by: Bart Van Assche [ bvanassche: Extracted this patch from a larger patch ] Signed-off-by: Martin K. Petersen --- drivers/scsi/scsi.c | 9 ++++++--- drivers/scsi/scsi_sysfs.c | 9 --------- 2 files changed, 6 insertions(+), 12 deletions(-) diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index c59eac7a32f2..086ec5b5862d 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -586,10 +586,13 @@ EXPORT_SYMBOL(scsi_device_get); */ void scsi_device_put(struct scsi_device *sdev) { - struct module *mod = sdev->host->hostt->module; - + /* + * Decreasing the module reference count before the device reference + * count is safe since scsi_remove_host() only returns after all + * devices have been removed. + */ + module_put(sdev->host->hostt->module); put_device(&sdev->sdev_gendev); - module_put(mod); } EXPORT_SYMBOL(scsi_device_put); diff --git a/drivers/scsi/scsi_sysfs.c b/drivers/scsi/scsi_sysfs.c index 1bc9c26fe1d4..213ebc88f76a 100644 --- a/drivers/scsi/scsi_sysfs.c +++ b/drivers/scsi/scsi_sysfs.c @@ -452,9 +452,6 @@ static void scsi_device_dev_release_usercontext(struct work_struct *work) struct scsi_vpd *vpd_pg0 = NULL, *vpd_pg89 = NULL; struct scsi_vpd *vpd_pgb0 = NULL, *vpd_pgb1 = NULL, *vpd_pgb2 = NULL; unsigned long flags; - struct module *mod; - - mod = sdev->host->hostt->module; scsi_dh_release_device(sdev); @@ -521,17 +518,11 @@ static void scsi_device_dev_release_usercontext(struct work_struct *work) if (parent) put_device(parent); - module_put(mod); } static void scsi_device_dev_release(struct device *dev) { struct scsi_device *sdp = to_scsi_device(dev); - - /* Set module pointer as NULL in case of module unloading */ - if (!try_module_get(sdp->host->hostt->module)) - sdp->host->hostt->module = NULL; - execute_in_process_context(scsi_device_dev_release_usercontext, &sdp->ew); } -- cgit v1.2.3 From f323896fe6fa8fa55ed37cb8b804fa97ead641c3 Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Thu, 28 Jul 2022 15:18:51 -0700 Subject: scsi: core: Call blk_mq_free_tag_set() earlier There are two .exit_cmd_priv implementations. Both implementations use resources associated with the SCSI host. Make sure that these resources are still available when .exit_cmd_priv is called by moving the .exit_cmd_priv calls from scsi_host_dev_release() to scsi_forget_host(). Moving blk_mq_free_tag_set() from scsi_host_dev_release() to scsi_remove_host() is safe because scsi_forget_host() waits until all SCSI devices associated with the host have been removed. Fix the following use-after-free: ================================================================== BUG: KASAN: use-after-free in srp_exit_cmd_priv+0x27/0xd0 [ib_srp] Read of size 8 at addr ffff888100337000 by task multipathd/16727 Call Trace: dump_stack_lvl+0x34/0x44 print_report.cold+0x5e/0x5db kasan_report+0xab/0x120 srp_exit_cmd_priv+0x27/0xd0 [ib_srp] scsi_mq_exit_request+0x4d/0x70 blk_mq_free_rqs+0x143/0x410 __blk_mq_free_map_and_rqs+0x6e/0x100 blk_mq_free_tag_set+0x2b/0x160 scsi_host_dev_release+0xf3/0x1a0 device_release+0x54/0xe0 kobject_put+0xa5/0x120 device_release+0x54/0xe0 kobject_put+0xa5/0x120 scsi_device_dev_release_usercontext+0x4c1/0x4e0 execute_in_process_context+0x23/0x90 device_release+0x54/0xe0 kobject_put+0xa5/0x120 scsi_disk_release+0x3f/0x50 device_release+0x54/0xe0 kobject_put+0xa5/0x120 disk_release+0x17f/0x1b0 device_release+0x54/0xe0 kobject_put+0xa5/0x120 dm_put_table_device+0xa3/0x160 [dm_mod] dm_put_device+0xd0/0x140 [dm_mod] free_priority_group+0xd8/0x110 [dm_multipath] free_multipath+0x94/0xe0 [dm_multipath] dm_table_destroy+0xa2/0x1e0 [dm_mod] __dm_destroy+0x196/0x350 [dm_mod] dev_remove+0x10c/0x160 [dm_mod] ctl_ioctl+0x2c2/0x590 [dm_mod] dm_ctl_ioctl+0x5/0x10 [dm_mod] __x64_sys_ioctl+0xb4/0xf0 dm_ctl_ioctl+0x5/0x10 [dm_mod] __x64_sys_ioctl+0xb4/0xf0 do_syscall_64+0x3b/0x90 entry_SYSCALL_64_after_hwframe+0x46/0xb0 Link: https://lore.kernel.org/r/20220728221851.1822295-5-bvanassche@acm.org Fixes: 65ca846a5314 ("scsi: core: Introduce {init,exit}_cmd_priv()") Cc: Christoph Hellwig Cc: Mike Christie Cc: Hannes Reinecke Cc: John Garry Cc: Li Zhijian Reported-by: Li Zhijian Tested-by: Li Zhijian Reviewed-by: Ming Lei Reviewed-by: Mike Christie Signed-off-by: Bart Van Assche Signed-off-by: Martin K. Petersen --- drivers/scsi/hosts.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/scsi/hosts.c b/drivers/scsi/hosts.c index 8fa98c8d0ee0..6c63672971f1 100644 --- a/drivers/scsi/hosts.c +++ b/drivers/scsi/hosts.c @@ -197,6 +197,8 @@ void scsi_remove_host(struct Scsi_Host *shost) * the dependent SCSI targets and devices are gone before returning. */ wait_event(shost->targets_wq, atomic_read(&shost->target_count) == 0); + + scsi_mq_destroy_tags(shost); } EXPORT_SYMBOL(scsi_remove_host); @@ -302,8 +304,8 @@ int scsi_add_host_with_dma(struct Scsi_Host *shost, struct device *dev, return error; /* - * Any host allocation in this function will be freed in - * scsi_host_dev_release(). + * Any resources associated with the SCSI host in this function except + * the tag set will be freed by scsi_host_dev_release(). */ out_del_dev: device_del(&shost->shost_dev); @@ -319,6 +321,7 @@ int scsi_add_host_with_dma(struct Scsi_Host *shost, struct device *dev, pm_runtime_disable(&shost->shost_gendev); pm_runtime_set_suspended(&shost->shost_gendev); pm_runtime_put_noidle(&shost->shost_gendev); + scsi_mq_destroy_tags(shost); fail: return error; } @@ -352,9 +355,6 @@ static void scsi_host_dev_release(struct device *dev) kfree(dev_name(&shost->shost_dev)); } - if (shost->tag_set.tags) - scsi_mq_destroy_tags(shost); - kfree(shost->shost_data); ida_free(&host_index_ida, shost->host_no); -- cgit v1.2.3 From 4da8c5f76825269f28d6a89fa752934a4bcb6dfa Mon Sep 17 00:00:00 2001 From: Steffen Maier Date: Fri, 29 Jul 2022 18:25:29 +0200 Subject: scsi: zfcp: Fix missing auto port scan and thus missing target ports Case (1): The only waiter on wka_port->completion_wq is zfcp_fc_wka_port_get() trying to open a WKA port. As such it should only be woken up by WKA port *open* responses, not by WKA port close responses. Case (2): A close WKA port response coming in just after having sent a new open WKA port request and before blocking for the open response with wait_event() in zfcp_fc_wka_port_get() erroneously renders the wait_event a NOP because the close handler overwrites wka_port->status. Hence the wait_event condition is erroneously true and it does not enter blocking state. With non-negligible probability, the following time space sequence happens depending on timing without this fix: user process ERP thread zfcp work queue tasklet system work queue ============ ========== =============== ======= ================= $ echo 1 > online zfcp_ccw_set_online zfcp_ccw_activate zfcp_erp_adapter_reopen msleep scan backoff zfcp_erp_strategy | ... | zfcp_erp_action_cleanup | ... | queue delayed scan_work | queue ns_up_work | ns_up_work: | zfcp_fc_wka_port_get | open wka request | open response | GSPN FC-GS | RSPN FC-GS [NPIV-only] | zfcp_fc_wka_port_put | (--wka->refcount==0) | sched delayed wka->work | ~~~Case (1)~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ zfcp_erp_wait flush scan_work | wka->work: | wka->status=CLOSING | close wka request | scan_work: | zfcp_fc_wka_port_get | (wka->status==CLOSING) | wka->status=OPENING | open wka request | wait_event | | close response | | wka->status=OFFLINE | | wake_up /*WRONG*/ ~~~Case (2)~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | wka->work: | wka->status=CLOSING | close wka request zfcp_erp_wait flush scan_work | scan_work: | zfcp_fc_wka_port_get | (wka->status==CLOSING) | wka->status=OPENING | open wka request | close response | wka->status=OFFLINE | wake_up /*WRONG&NOP*/ | wait_event /*NOP*/ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | (wka->status!=ONLINE) | return -EIO | return early open response wka->status=ONLINE wake_up /*NOP*/ So we erroneously end up with no automatic port scan. This is a big problem when it happens during boot. The timing is influenced by v3.19 commit 18f87a67e6d6 ("zfcp: auto port scan resiliency"). Fix it by fully mutually excluding zfcp_fc_wka_port_get() and zfcp_fc_wka_port_offline(). For that to work, we make the latter block until we got the response for a close WKA port. In order not to penalize the system workqueue, we move wka_port->work to our own adapter workqueue. Note that before v2.6.30 commit 828bc1212a68 ("[SCSI] zfcp: Set WKA-port to offline on adapter deactivation"), zfcp did block in zfcp_fc_wka_port_offline() as well, but with a different condition. While at it, make non-functional cleanups to improve code reading in zfcp_fc_wka_port_get(). If we cannot send the WKA port open request, don't rely on the subsequent wait_event condition to immediately let this case pass without blocking. Also don't want to rely on the additional condition handling the refcount to be skipped just to finally return with -EIO. Link: https://lore.kernel.org/r/20220729162529.1620730-1-maier@linux.ibm.com Fixes: 5ab944f97e09 ("[SCSI] zfcp: attach and release SAN nameserver port on demand") Cc: #v2.6.28+ Reviewed-by: Benjamin Block Signed-off-by: Steffen Maier Signed-off-by: Martin K. Petersen --- drivers/s390/scsi/zfcp_fc.c | 29 ++++++++++++++++++++--------- drivers/s390/scsi/zfcp_fc.h | 6 ++++-- drivers/s390/scsi/zfcp_fsf.c | 4 ++-- 3 files changed, 26 insertions(+), 13 deletions(-) diff --git a/drivers/s390/scsi/zfcp_fc.c b/drivers/s390/scsi/zfcp_fc.c index 511bf8e0a436..b61acbb09be3 100644 --- a/drivers/s390/scsi/zfcp_fc.c +++ b/drivers/s390/scsi/zfcp_fc.c @@ -145,27 +145,33 @@ void zfcp_fc_enqueue_event(struct zfcp_adapter *adapter, static int zfcp_fc_wka_port_get(struct zfcp_fc_wka_port *wka_port) { + int ret = -EIO; + if (mutex_lock_interruptible(&wka_port->mutex)) return -ERESTARTSYS; if (wka_port->status == ZFCP_FC_WKA_PORT_OFFLINE || wka_port->status == ZFCP_FC_WKA_PORT_CLOSING) { wka_port->status = ZFCP_FC_WKA_PORT_OPENING; - if (zfcp_fsf_open_wka_port(wka_port)) + if (zfcp_fsf_open_wka_port(wka_port)) { + /* could not even send request, nothing to wait for */ wka_port->status = ZFCP_FC_WKA_PORT_OFFLINE; + goto out; + } } - mutex_unlock(&wka_port->mutex); - - wait_event(wka_port->completion_wq, + wait_event(wka_port->opened, wka_port->status == ZFCP_FC_WKA_PORT_ONLINE || wka_port->status == ZFCP_FC_WKA_PORT_OFFLINE); if (wka_port->status == ZFCP_FC_WKA_PORT_ONLINE) { atomic_inc(&wka_port->refcount); - return 0; + ret = 0; + goto out; } - return -EIO; +out: + mutex_unlock(&wka_port->mutex); + return ret; } static void zfcp_fc_wka_port_offline(struct work_struct *work) @@ -181,9 +187,12 @@ static void zfcp_fc_wka_port_offline(struct work_struct *work) wka_port->status = ZFCP_FC_WKA_PORT_CLOSING; if (zfcp_fsf_close_wka_port(wka_port)) { + /* could not even send request, nothing to wait for */ wka_port->status = ZFCP_FC_WKA_PORT_OFFLINE; - wake_up(&wka_port->completion_wq); + goto out; } + wait_event(wka_port->closed, + wka_port->status == ZFCP_FC_WKA_PORT_OFFLINE); out: mutex_unlock(&wka_port->mutex); } @@ -193,13 +202,15 @@ static void zfcp_fc_wka_port_put(struct zfcp_fc_wka_port *wka_port) if (atomic_dec_return(&wka_port->refcount) != 0) return; /* wait 10 milliseconds, other reqs might pop in */ - schedule_delayed_work(&wka_port->work, HZ / 100); + queue_delayed_work(wka_port->adapter->work_queue, &wka_port->work, + msecs_to_jiffies(10)); } static void zfcp_fc_wka_port_init(struct zfcp_fc_wka_port *wka_port, u32 d_id, struct zfcp_adapter *adapter) { - init_waitqueue_head(&wka_port->completion_wq); + init_waitqueue_head(&wka_port->opened); + init_waitqueue_head(&wka_port->closed); wka_port->adapter = adapter; wka_port->d_id = d_id; diff --git a/drivers/s390/scsi/zfcp_fc.h b/drivers/s390/scsi/zfcp_fc.h index 8aaf409ce9cb..97755407ce1b 100644 --- a/drivers/s390/scsi/zfcp_fc.h +++ b/drivers/s390/scsi/zfcp_fc.h @@ -185,7 +185,8 @@ enum zfcp_fc_wka_status { /** * struct zfcp_fc_wka_port - representation of well-known-address (WKA) FC port * @adapter: Pointer to adapter structure this WKA port belongs to - * @completion_wq: Wait for completion of open/close command + * @opened: Wait for completion of open command + * @closed: Wait for completion of close command * @status: Current status of WKA port * @refcount: Reference count to keep port open as long as it is in use * @d_id: FC destination id or well-known-address @@ -195,7 +196,8 @@ enum zfcp_fc_wka_status { */ struct zfcp_fc_wka_port { struct zfcp_adapter *adapter; - wait_queue_head_t completion_wq; + wait_queue_head_t opened; + wait_queue_head_t closed; enum zfcp_fc_wka_status status; atomic_t refcount; u32 d_id; diff --git a/drivers/s390/scsi/zfcp_fsf.c b/drivers/s390/scsi/zfcp_fsf.c index 4f1e4385ce58..19223b075568 100644 --- a/drivers/s390/scsi/zfcp_fsf.c +++ b/drivers/s390/scsi/zfcp_fsf.c @@ -1907,7 +1907,7 @@ static void zfcp_fsf_open_wka_port_handler(struct zfcp_fsf_req *req) wka_port->status = ZFCP_FC_WKA_PORT_ONLINE; } out: - wake_up(&wka_port->completion_wq); + wake_up(&wka_port->opened); } /** @@ -1966,7 +1966,7 @@ static void zfcp_fsf_close_wka_port_handler(struct zfcp_fsf_req *req) } wka_port->status = ZFCP_FC_WKA_PORT_OFFLINE; - wake_up(&wka_port->completion_wq); + wake_up(&wka_port->closed); } /** -- cgit v1.2.3 From 554b117e8fab4f7c53090eca693f47e0c7b18490 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Sat, 30 Jul 2022 13:37:36 +0100 Subject: scsi: FlashPoint: Remove redundant variable bm_int_st The variable bm_int_st is assigned a value but it is never read. The variable and the assignment are redundant and can be removed. Cleans up clang scan build warning: drivers/scsi/FlashPoint.c:1726:7: warning: Although the value stored to 'bm_int_st' is used in the enclosing expression, the value is never actually read from 'bm_int_st' [deadcode.DeadStores] Link: https://lore.kernel.org/r/20220730123736.147758-1-colin.i.king@gmail.com Acked-by: Khalid Aziz Signed-off-by: Colin Ian King Signed-off-by: Martin K. Petersen --- drivers/scsi/FlashPoint.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/FlashPoint.c b/drivers/scsi/FlashPoint.c index 90253208a72f..3d9c56ac8224 100644 --- a/drivers/scsi/FlashPoint.c +++ b/drivers/scsi/FlashPoint.c @@ -1712,7 +1712,7 @@ static unsigned char FlashPoint_InterruptPending(void *pCurrCard) static int FlashPoint_HandleInterrupt(void *pcard) { struct sccb *currSCCB; - unsigned char thisCard, result, bm_status, bm_int_st; + unsigned char thisCard, result, bm_status; unsigned short hp_int; unsigned char i, target; struct sccb_card *pCurrCard = pcard; @@ -1723,7 +1723,7 @@ static int FlashPoint_HandleInterrupt(void *pcard) MDISABLE_INT(ioport); - if ((bm_int_st = RD_HARPOON(ioport + hp_int_status)) & EXT_STATUS_ON) + if (RD_HARPOON(ioport + hp_int_status) & EXT_STATUS_ON) bm_status = RD_HARPOON(ioport + hp_ext_status) & (unsigned char)BAD_EXT_STATUS; else -- cgit v1.2.3 From 6464d5b8a2768e8ff63d24b76299fe614e205aa7 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Sat, 30 Jul 2022 13:45:09 +0100 Subject: scsi: megaraid_sas: Remove redundant variable cmd_type The variable cmd_type is assigned a value but it is never read. The variable and the assignment are redundant and can be removed. Cleans up clang scan build warning: drivers/scsi/megaraid/megaraid_sas_fusion.c:3228:10: warning: Although the value stored to 'cmd_type' is used in the enclosing expression, the value is never actually read from 'cmd_type' [deadcode.DeadStores] Link: https://lore.kernel.org/r/20220730124509.148457-1-colin.i.king@gmail.com Signed-off-by: Colin Ian King Signed-off-by: Martin K. Petersen --- drivers/scsi/megaraid/megaraid_sas_fusion.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/scsi/megaraid/megaraid_sas_fusion.c b/drivers/scsi/megaraid/megaraid_sas_fusion.c index 5b5885d9732b..e48d4261d0bc 100644 --- a/drivers/scsi/megaraid/megaraid_sas_fusion.c +++ b/drivers/scsi/megaraid/megaraid_sas_fusion.c @@ -3199,7 +3199,6 @@ megasas_build_io_fusion(struct megasas_instance *instance, struct megasas_cmd_fusion *cmd) { int sge_count; - u8 cmd_type; u16 pd_index = 0; u8 drive_type = 0; struct MPI2_RAID_SCSI_IO_REQUEST *io_request = cmd->io_request; @@ -3225,7 +3224,7 @@ megasas_build_io_fusion(struct megasas_instance *instance, */ io_request->IoFlags = cpu_to_le16(scp->cmd_len); - switch (cmd_type = megasas_cmd_type(scp)) { + switch (megasas_cmd_type(scp)) { case READ_WRITE_LDIO: megasas_build_ldio_fusion(instance, scp, cmd); break; -- cgit v1.2.3 From c6380f9924270d51cc233cfd592b279be3881e6d Mon Sep 17 00:00:00 2001 From: Slark Xiao Date: Fri, 22 Jul 2022 17:46:12 +0800 Subject: scsi: pm8001: Fix typo 'the the' in comment Replace 'the the' with 'the' in the comment. Link: https://lore.kernel.org/r/20220722094612.78583-1-slark_xiao@163.com Acked-by: Jack Wang Signed-off-by: Slark Xiao Signed-off-by: Martin K. Petersen --- drivers/scsi/pm8001/pm8001_hwi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/scsi/pm8001/pm8001_hwi.c b/drivers/scsi/pm8001/pm8001_hwi.c index a37595621d51..6a3c4c347061 100644 --- a/drivers/scsi/pm8001/pm8001_hwi.c +++ b/drivers/scsi/pm8001/pm8001_hwi.c @@ -3138,7 +3138,7 @@ int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb) * * when HBA driver received the identify done event or initiate FIS received * event(for SATA), it will invoke this function to notify the sas layer that - * the sas toplogy has formed, please discover the the whole sas domain, + * the sas toplogy has formed, please discover the whole sas domain, * while receive a broadcast(change) primitive just tell the sas * layer to discover the changed domain rather than the whole domain. */ -- cgit v1.2.3 From b0de7fa706506bf0591037908376351beda8c5d6 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Tue, 2 Aug 2022 08:43:34 +0200 Subject: regulator: pca9450: Remove restrictions for regulator-name The device bindings shouldn't put any constraints on the regulator-name property specified in the generic bindings. This allows using arbitrary and descriptive names for the regulators. Suggested-by: Mark Brown Fixes: 7ae9e3a6bf3f ("dt-bindings: regulator: add pca9450 regulator yaml") Signed-off-by: Frieder Schrempf Link: https://lore.kernel.org/r/20220802064335.8481-1-frieder@fris.de Signed-off-by: Mark Brown --- .../devicetree/bindings/regulator/nxp,pca9450-regulator.yaml | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml b/Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml index b539781e39aa..835b53302db8 100644 --- a/Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml @@ -47,12 +47,6 @@ properties: description: Properties for single LDO regulator. - properties: - regulator-name: - pattern: "^LDO[1-5]$" - description: - should be "LDO1", ..., "LDO5" - unevaluatedProperties: false "^BUCK[1-6]$": @@ -62,11 +56,6 @@ properties: Properties for single BUCK regulator. properties: - regulator-name: - pattern: "^BUCK[1-6]$" - description: - should be "BUCK1", ..., "BUCK6" - nxp,dvs-run-voltage: $ref: "/schemas/types.yaml#/definitions/uint32" minimum: 600000 -- cgit v1.2.3 From ff2557b7224ea9a19fb79eb4bd16d4deef57816a Mon Sep 17 00:00:00 2001 From: Ming Lei Date: Wed, 3 Aug 2022 20:07:57 +0800 Subject: io_uring: pass correct parameters to io_req_set_res The two parameters of 'res' and 'cflags' are swapped, so fix it. Without this fix, 'ublk del' hangs forever. Cc: Pavel Begunkov Fixes: de23077eda61f ("io_uring: set completion results upfront") Signed-off-by: Ming Lei Link: https://lore.kernel.org/r/20220803120757.1668278-1-ming.lei@redhat.com Signed-off-by: Jens Axboe --- io_uring/uring_cmd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/io_uring/uring_cmd.c b/io_uring/uring_cmd.c index 0a421ed51e7e..849d9708d612 100644 --- a/io_uring/uring_cmd.c +++ b/io_uring/uring_cmd.c @@ -46,7 +46,7 @@ void io_uring_cmd_done(struct io_uring_cmd *ioucmd, ssize_t ret, ssize_t res2) if (ret < 0) req_set_fail(req); - io_req_set_res(req, 0, ret); + io_req_set_res(req, ret, 0); if (req->ctx->flags & IORING_SETUP_CQE32) io_req_set_cqe32_extra(req, res2, 0); __io_req_complete(req, 0); -- cgit v1.2.3 From 460bbf2990b3fdc597601c2cf669a3371c069242 Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Thu, 12 May 2022 19:08:40 +0300 Subject: fs/ntfs3: Do not change mode if ntfs_set_ea failed ntfs_set_ea can fail with NOSPC, so we don't need to change mode in this situation. Fixes xfstest generic/449 Fixes: be71b5cba2e6 ("fs/ntfs3: Add attrib operations") Signed-off-by: Konstantin Komarov --- fs/ntfs3/xattr.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/fs/ntfs3/xattr.c b/fs/ntfs3/xattr.c index 2d29afe4b40b..ddd9fc9129ed 100644 --- a/fs/ntfs3/xattr.c +++ b/fs/ntfs3/xattr.c @@ -547,28 +547,23 @@ static noinline int ntfs_set_acl_ex(struct user_namespace *mnt_userns, { const char *name; size_t size, name_len; - void *value = NULL; - int err = 0; + void *value; + int err; int flags; + umode_t mode; if (S_ISLNK(inode->i_mode)) return -EOPNOTSUPP; + mode = inode->i_mode; switch (type) { case ACL_TYPE_ACCESS: /* Do not change i_mode if we are in init_acl */ if (acl && !init_acl) { - umode_t mode; - err = posix_acl_update_mode(mnt_userns, inode, &mode, &acl); if (err) goto out; - - if (inode->i_mode != mode) { - inode->i_mode = mode; - mark_inode_dirty(inode); - } } name = XATTR_NAME_POSIX_ACL_ACCESS; name_len = sizeof(XATTR_NAME_POSIX_ACL_ACCESS) - 1; @@ -604,8 +599,13 @@ static noinline int ntfs_set_acl_ex(struct user_namespace *mnt_userns, err = ntfs_set_ea(inode, name, name_len, value, size, flags, 0); if (err == -ENODATA && !size) err = 0; /* Removing non existed xattr. */ - if (!err) + if (!err) { set_cached_acl(inode, type, acl); + if (inode->i_mode != mode) { + inode->i_mode = mode; + mark_inode_dirty(inode); + } + } out: kfree(value); -- cgit v1.2.3 From 13747aac8984e069427e5de5d68bb6cefa98551e Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Thu, 12 May 2022 19:18:11 +0300 Subject: fs/ntfs3: Check reserved size for maximum allowed Also don't mask EFBIG Fixes xfstest generic/485 Fixes: 4342306f0f0d ("fs/ntfs3: Add file operations and implementation") Signed-off-by: Konstantin Komarov --- fs/ntfs3/attrib.c | 9 +++++++++ fs/ntfs3/file.c | 3 --- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/fs/ntfs3/attrib.c b/fs/ntfs3/attrib.c index 3e9aefcb3e6c..c9b718143603 100644 --- a/fs/ntfs3/attrib.c +++ b/fs/ntfs3/attrib.c @@ -2114,9 +2114,11 @@ int attr_insert_range(struct ntfs_inode *ni, u64 vbo, u64 bytes) if (!attr_b->non_res) { data_size = le32_to_cpu(attr_b->res.data_size); + alloc_size = data_size; mask = sbi->cluster_mask; /* cluster_size - 1 */ } else { data_size = le64_to_cpu(attr_b->nres.data_size); + alloc_size = le64_to_cpu(attr_b->nres.alloc_size); mask = (sbi->cluster_size << attr_b->nres.c_unit) - 1; } @@ -2130,6 +2132,13 @@ int attr_insert_range(struct ntfs_inode *ni, u64 vbo, u64 bytes) return -EINVAL; } + /* + * valid_size <= data_size <= alloc_size + * Check alloc_size for maximum possible. + */ + if (bytes > sbi->maxbytes_sparse - alloc_size) + return -EFBIG; + vcn = vbo >> sbi->cluster_bits; len = bytes >> sbi->cluster_bits; diff --git a/fs/ntfs3/file.c b/fs/ntfs3/file.c index bdffe4b8554b..cf16bde810cc 100644 --- a/fs/ntfs3/file.c +++ b/fs/ntfs3/file.c @@ -733,9 +733,6 @@ out: if (map_locked) filemap_invalidate_unlock(mapping); - if (err == -EFBIG) - err = -ENOSPC; - if (!err) { inode->i_ctime = inode->i_mtime = current_time(inode); mark_inode_dirty(inode); -- cgit v1.2.3 From c1e0ab3789215a3dfbe95f226955e93ea4803391 Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Fri, 13 May 2022 18:25:04 +0300 Subject: fs/ntfs3: extend ni_insert_nonresident to return inserted ATTR_LIST_ENTRY Fixes xfstest generic/300 Fixes: 4534a70b7056 ("fs/ntfs3: Add headers and misc files") Signed-off-by: Konstantin Komarov --- fs/ntfs3/attrib.c | 35 +++++++++++++++++++++-------------- fs/ntfs3/frecord.c | 4 ++-- fs/ntfs3/index.c | 2 +- fs/ntfs3/ntfs_fs.h | 2 +- 4 files changed, 25 insertions(+), 18 deletions(-) diff --git a/fs/ntfs3/attrib.c b/fs/ntfs3/attrib.c index c9b718143603..ad713f620155 100644 --- a/fs/ntfs3/attrib.c +++ b/fs/ntfs3/attrib.c @@ -320,7 +320,7 @@ int attr_make_nonresident(struct ntfs_inode *ni, struct ATTRIB *attr, err = ni_insert_nonresident(ni, attr_s->type, attr_name(attr_s), attr_s->name_len, run, 0, alen, - attr_s->flags, &attr, NULL); + attr_s->flags, &attr, NULL, NULL); if (err) goto out3; @@ -637,7 +637,7 @@ pack_runs: /* Insert new attribute segment. */ err = ni_insert_nonresident(ni, type, name, name_len, run, next_svcn, vcn - next_svcn, - attr_b->flags, &attr, &mi); + attr_b->flags, &attr, &mi, NULL); if (err) goto out; @@ -855,7 +855,7 @@ int attr_data_get_block(struct ntfs_inode *ni, CLST vcn, CLST clen, CLST *lcn, goto out; } - asize = le64_to_cpu(attr_b->nres.alloc_size) >> sbi->cluster_bits; + asize = le64_to_cpu(attr_b->nres.alloc_size) >> cluster_bits; if (vcn >= asize) { err = -EINVAL; goto out; @@ -1047,7 +1047,7 @@ ins_ext: if (evcn1 > next_svcn) { err = ni_insert_nonresident(ni, ATTR_DATA, NULL, 0, run, next_svcn, evcn1 - next_svcn, - attr_b->flags, &attr, &mi); + attr_b->flags, &attr, &mi, NULL); if (err) goto out; } @@ -1647,7 +1647,7 @@ ins_ext: if (evcn1 > next_svcn) { err = ni_insert_nonresident(ni, ATTR_DATA, NULL, 0, run, next_svcn, evcn1 - next_svcn, - attr_b->flags, &attr, &mi); + attr_b->flags, &attr, &mi, NULL); if (err) goto out; } @@ -1812,18 +1812,12 @@ int attr_collapse_range(struct ntfs_inode *ni, u64 vbo, u64 bytes) err = ni_insert_nonresident( ni, ATTR_DATA, NULL, 0, run, next_svcn, evcn1 - eat - next_svcn, a_flags, &attr, - &mi); + &mi, &le); if (err) goto out; /* Layout of records maybe changed. */ attr_b = NULL; - le = al_find_ex(ni, NULL, ATTR_DATA, NULL, 0, - &next_svcn); - if (!le) { - err = -EINVAL; - goto out; - } } /* Free all allocated memory. */ @@ -1936,9 +1930,10 @@ int attr_punch_hole(struct ntfs_inode *ni, u64 vbo, u64 bytes, u32 *frame_size) struct ATTRIB *attr = NULL, *attr_b; struct ATTR_LIST_ENTRY *le, *le_b; struct mft_inode *mi, *mi_b; - CLST svcn, evcn1, vcn, len, end, alen, dealloc; + CLST svcn, evcn1, vcn, len, end, alen, dealloc, next_svcn; u64 total_size, alloc_size; u32 mask; + __le16 a_flags; if (!bytes) return 0; @@ -2001,6 +1996,7 @@ int attr_punch_hole(struct ntfs_inode *ni, u64 vbo, u64 bytes, u32 *frame_size) svcn = le64_to_cpu(attr_b->nres.svcn); evcn1 = le64_to_cpu(attr_b->nres.evcn) + 1; + a_flags = attr_b->flags; if (svcn <= vcn && vcn < evcn1) { attr = attr_b; @@ -2048,6 +2044,17 @@ int attr_punch_hole(struct ntfs_inode *ni, u64 vbo, u64 bytes, u32 *frame_size) err = mi_pack_runs(mi, attr, run, evcn1 - svcn); if (err) goto out; + next_svcn = le64_to_cpu(attr->nres.evcn) + 1; + if (next_svcn < evcn1) { + err = ni_insert_nonresident(ni, ATTR_DATA, NULL, + 0, run, next_svcn, + evcn1 - next_svcn, + a_flags, &attr, &mi, + &le); + if (err) + goto out; + /* Layout of records maybe changed. */ + } } /* Free all allocated memory. */ run_truncate(run, 0); @@ -2250,7 +2257,7 @@ int attr_insert_range(struct ntfs_inode *ni, u64 vbo, u64 bytes) if (next_svcn < evcn1 + len) { err = ni_insert_nonresident(ni, ATTR_DATA, NULL, 0, run, next_svcn, evcn1 + len - next_svcn, - a_flags, NULL, NULL); + a_flags, NULL, NULL, NULL); if (err) goto out; } diff --git a/fs/ntfs3/frecord.c b/fs/ntfs3/frecord.c index 3576268ee0a1..64041152fd98 100644 --- a/fs/ntfs3/frecord.c +++ b/fs/ntfs3/frecord.c @@ -1406,7 +1406,7 @@ int ni_insert_nonresident(struct ntfs_inode *ni, enum ATTR_TYPE type, const __le16 *name, u8 name_len, const struct runs_tree *run, CLST svcn, CLST len, __le16 flags, struct ATTRIB **new_attr, - struct mft_inode **mi) + struct mft_inode **mi, struct ATTR_LIST_ENTRY **le) { int err; CLST plen; @@ -1439,7 +1439,7 @@ int ni_insert_nonresident(struct ntfs_inode *ni, enum ATTR_TYPE type, } err = ni_insert_attr(ni, type, name, name_len, asize, name_off, svcn, - &attr, mi, NULL); + &attr, mi, le); if (err) goto out; diff --git a/fs/ntfs3/index.c b/fs/ntfs3/index.c index ba2a07dfeaf5..440328147e7e 100644 --- a/fs/ntfs3/index.c +++ b/fs/ntfs3/index.c @@ -1347,7 +1347,7 @@ static int indx_create_allocate(struct ntfs_index *indx, struct ntfs_inode *ni, goto out; err = ni_insert_nonresident(ni, ATTR_ALLOC, in->name, in->name_len, - &run, 0, len, 0, &alloc, NULL); + &run, 0, len, 0, &alloc, NULL, NULL); if (err) goto out1; diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h index 8f05b91f3c5e..27b610c5bb29 100644 --- a/fs/ntfs3/ntfs_fs.h +++ b/fs/ntfs3/ntfs_fs.h @@ -529,7 +529,7 @@ int ni_insert_nonresident(struct ntfs_inode *ni, enum ATTR_TYPE type, const __le16 *name, u8 name_len, const struct runs_tree *run, CLST svcn, CLST len, __le16 flags, struct ATTRIB **new_attr, - struct mft_inode **mi); + struct mft_inode **mi, struct ATTR_LIST_ENTRY **le); int ni_insert_resident(struct ntfs_inode *ni, u32 data_size, enum ATTR_TYPE type, const __le16 *name, u8 name_len, struct ATTRIB **new_attr, struct mft_inode **mi, -- cgit v1.2.3 From b3e048720dee5641c522015d3f0ff0f0dc9cdc37 Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Fri, 13 May 2022 19:21:54 +0300 Subject: fs/ntfs3: Make ntfs_fallocate return -ENOSPC instead of -EFBIG In some cases we need to return ENOSPC Fixes xfstest generic/213 Fixes: 114346978cf6 ("fs/ntfs3: Check new size for limits") Signed-off-by: Konstantin Komarov --- fs/ntfs3/file.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/fs/ntfs3/file.c b/fs/ntfs3/file.c index cf16bde810cc..b5f8837f4145 100644 --- a/fs/ntfs3/file.c +++ b/fs/ntfs3/file.c @@ -671,6 +671,19 @@ static long ntfs_fallocate(struct file *file, int mode, loff_t vbo, loff_t len) ni_unlock(ni); } else { /* Check new size. */ + + /* generic/213: expected -ENOSPC instead of -EFBIG. */ + if (!is_supported_holes) { + loff_t to_alloc = new_size - inode_get_bytes(inode); + + if (to_alloc > 0 && + (to_alloc >> sbi->cluster_bits) > + wnd_zeroes(&sbi->used.bitmap)) { + err = -ENOSPC; + goto out; + } + } + err = inode_newsize_ok(inode, new_size); if (err) goto out; -- cgit v1.2.3 From 42f86b1226a42bfc79a7125af435432ad4680a32 Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Fri, 13 May 2022 19:54:23 +0300 Subject: fs/ntfs3: Fix work with fragmented xattr In some cases xattr is too fragmented, so we need to load it before writing. Signed-off-by: Konstantin Komarov --- fs/ntfs3/xattr.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/fs/ntfs3/xattr.c b/fs/ntfs3/xattr.c index ddd9fc9129ed..02f6a933ee79 100644 --- a/fs/ntfs3/xattr.c +++ b/fs/ntfs3/xattr.c @@ -118,7 +118,7 @@ static int ntfs_read_ea(struct ntfs_inode *ni, struct EA_FULL **ea, run_init(&run); - err = attr_load_runs(attr_ea, ni, &run, NULL); + err = attr_load_runs_range(ni, ATTR_EA, NULL, 0, &run, 0, size); if (!err) err = ntfs_read_run_nb(sbi, &run, 0, ea_p, size, NULL); run_close(&run); @@ -444,6 +444,11 @@ update_ea: /* Delete xattr, ATTR_EA */ ni_remove_attr_le(ni, attr, mi, le); } else if (attr->non_res) { + err = attr_load_runs_range(ni, ATTR_EA, NULL, 0, &ea_run, 0, + size); + if (err) + goto out; + err = ntfs_sb_write_run(sbi, &ea_run, 0, ea_all, size, 0); if (err) goto out; -- cgit v1.2.3 From 560f7736b94622c077344e2c541c43c63b4e90e4 Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Thu, 30 Jun 2022 18:31:26 +0300 Subject: fs/ntfs3: Fix very fragmented case in attr_punch_hole In some cases we need to ni_find_attr attr_b Signed-off-by: Konstantin Komarov --- fs/ntfs3/attrib.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/fs/ntfs3/attrib.c b/fs/ntfs3/attrib.c index ad713f620155..3d64335fa4c7 100644 --- a/fs/ntfs3/attrib.c +++ b/fs/ntfs3/attrib.c @@ -2054,6 +2054,7 @@ int attr_punch_hole(struct ntfs_inode *ni, u64 vbo, u64 bytes, u32 *frame_size) if (err) goto out; /* Layout of records maybe changed. */ + attr_b = NULL; } } /* Free all allocated memory. */ @@ -2073,6 +2074,14 @@ int attr_punch_hole(struct ntfs_inode *ni, u64 vbo, u64 bytes, u32 *frame_size) } total_size -= (u64)dealloc << sbi->cluster_bits; + if (!attr_b) { + attr_b = ni_find_attr(ni, NULL, NULL, ATTR_DATA, NULL, 0, NULL, + &mi_b); + if (!attr_b) { + err = -EINVAL; + goto out; + } + } attr_b->nres.total_size = cpu_to_le64(total_size); mi_b->dirty = true; @@ -2083,8 +2092,10 @@ int attr_punch_hole(struct ntfs_inode *ni, u64 vbo, u64 bytes, u32 *frame_size) out: up_write(&ni->file.run_lock); - if (err) + if (err) { + ntfs_set_state(sbi, NTFS_DIRTY_ERROR); make_bad_inode(&ni->vfs_inode); + } return err; } -- cgit v1.2.3 From 6700eabb90d50c50be21ecbb71131cd6ecf91ded Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Thu, 30 Jun 2022 18:49:24 +0300 Subject: fs/ntfs3: Remove unused mi_mark_free Cleaning up dead code Fix wrong comments Signed-off-by: Konstantin Komarov --- fs/ntfs3/namei.c | 2 +- fs/ntfs3/ntfs_fs.h | 1 - fs/ntfs3/record.c | 22 ---------------------- fs/ntfs3/super.c | 2 +- 4 files changed, 2 insertions(+), 25 deletions(-) diff --git a/fs/ntfs3/namei.c b/fs/ntfs3/namei.c index bc741213ad84..1cc700760c7e 100644 --- a/fs/ntfs3/namei.c +++ b/fs/ntfs3/namei.c @@ -208,7 +208,7 @@ static int ntfs_mkdir(struct user_namespace *mnt_userns, struct inode *dir, } /* - * ntfs_rmdir - inode_operations::rm_dir + * ntfs_rmdir - inode_operations::rmdir */ static int ntfs_rmdir(struct inode *dir, struct dentry *dentry) { diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h index 27b610c5bb29..0ea0cdab46b3 100644 --- a/fs/ntfs3/ntfs_fs.h +++ b/fs/ntfs3/ntfs_fs.h @@ -734,7 +734,6 @@ static inline struct ATTRIB *rec_find_attr_le(struct mft_inode *rec, int mi_write(struct mft_inode *mi, int wait); int mi_format_new(struct mft_inode *mi, struct ntfs_sb_info *sbi, CLST rno, __le16 flags, bool is_mft); -void mi_mark_free(struct mft_inode *mi); struct ATTRIB *mi_insert_attr(struct mft_inode *mi, enum ATTR_TYPE type, const __le16 *name, u8 name_len, u32 asize, u16 name_off); diff --git a/fs/ntfs3/record.c b/fs/ntfs3/record.c index 8fe0a876400a..7d2fac5ee215 100644 --- a/fs/ntfs3/record.c +++ b/fs/ntfs3/record.c @@ -394,28 +394,6 @@ int mi_format_new(struct mft_inode *mi, struct ntfs_sb_info *sbi, CLST rno, return err; } -/* - * mi_mark_free - Mark record as unused and marks it as free in bitmap. - */ -void mi_mark_free(struct mft_inode *mi) -{ - CLST rno = mi->rno; - struct ntfs_sb_info *sbi = mi->sbi; - - if (rno >= MFT_REC_RESERVED && rno < MFT_REC_FREE) { - ntfs_clear_mft_tail(sbi, rno, rno + 1); - mi->dirty = false; - return; - } - - if (mi->mrec) { - clear_rec_inuse(mi->mrec); - mi->dirty = true; - mi_write(mi, 0); - } - ntfs_mark_rec_free(sbi, rno); -} - /* * mi_insert_attr - Reserve space for new attribute. * diff --git a/fs/ntfs3/super.c b/fs/ntfs3/super.c index 4b0dad2ac598..eacea72ff92f 100644 --- a/fs/ntfs3/super.c +++ b/fs/ntfs3/super.c @@ -1377,7 +1377,7 @@ static const struct fs_context_operations ntfs_context_ops = { /* * ntfs_init_fs_context - Initialize spi and opts * - * This will called when mount/remount. We will first initiliaze + * This will called when mount/remount. We will first initialize * options so that if remount we can use just that. */ static int ntfs_init_fs_context(struct fs_context *fc) -- cgit v1.2.3 From 071100ea0e6c353258f322cb2f8dde9be62d6808 Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Thu, 30 Jun 2022 19:14:43 +0300 Subject: fs/ntfs3: Add new argument is_mft to ntfs_mark_rec_free This argument helps in avoiding double locking Signed-off-by: Konstantin Komarov --- fs/ntfs3/frecord.c | 12 ++++++------ fs/ntfs3/fsntfs.c | 9 ++++++--- fs/ntfs3/inode.c | 2 +- fs/ntfs3/ntfs_fs.h | 2 +- 4 files changed, 14 insertions(+), 11 deletions(-) diff --git a/fs/ntfs3/frecord.c b/fs/ntfs3/frecord.c index 64041152fd98..756d9a18fa00 100644 --- a/fs/ntfs3/frecord.c +++ b/fs/ntfs3/frecord.c @@ -1048,7 +1048,7 @@ out2: err = -EINVAL; out1: - ntfs_mark_rec_free(sbi, rno); + ntfs_mark_rec_free(sbi, rno, is_mft); out: return err; @@ -1243,7 +1243,7 @@ static int ni_expand_mft_list(struct ntfs_inode *ni) mft_min = mft_new; mi_min = mi_new; } else { - ntfs_mark_rec_free(sbi, mft_new); + ntfs_mark_rec_free(sbi, mft_new, true); mft_new = 0; ni_remove_mi(ni, mi_new); } @@ -1326,7 +1326,7 @@ static int ni_expand_mft_list(struct ntfs_inode *ni) out: if (mft_new) { - ntfs_mark_rec_free(sbi, mft_new); + ntfs_mark_rec_free(sbi, mft_new, true); ni_remove_mi(ni, mi_new); } @@ -1585,7 +1585,7 @@ int ni_delete_all(struct ntfs_inode *ni) mi->dirty = true; mi_write(mi, 0); - ntfs_mark_rec_free(sbi, mi->rno); + ntfs_mark_rec_free(sbi, mi->rno, false); ni_remove_mi(ni, mi); mi_put(mi); node = next; @@ -1596,7 +1596,7 @@ int ni_delete_all(struct ntfs_inode *ni) ni->mi.dirty = true; err = mi_write(&ni->mi, 0); - ntfs_mark_rec_free(sbi, ni->mi.rno); + ntfs_mark_rec_free(sbi, ni->mi.rno, false); return err; } @@ -3286,7 +3286,7 @@ int ni_write_inode(struct inode *inode, int sync, const char *hint) err = err2; if (is_empty) { - ntfs_mark_rec_free(sbi, mi->rno); + ntfs_mark_rec_free(sbi, mi->rno, false); rb_erase(node, &ni->mi_tree); mi_put(mi); } diff --git a/fs/ntfs3/fsntfs.c b/fs/ntfs3/fsntfs.c index 938acb246b58..fa4ca8b9b499 100644 --- a/fs/ntfs3/fsntfs.c +++ b/fs/ntfs3/fsntfs.c @@ -703,12 +703,14 @@ out: /* * ntfs_mark_rec_free - Mark record as free. + * is_mft - true if we are changing MFT */ -void ntfs_mark_rec_free(struct ntfs_sb_info *sbi, CLST rno) +void ntfs_mark_rec_free(struct ntfs_sb_info *sbi, CLST rno, bool is_mft) { struct wnd_bitmap *wnd = &sbi->mft.bitmap; - down_write_nested(&wnd->rw_lock, BITMAP_MUTEX_MFT); + if (!is_mft) + down_write_nested(&wnd->rw_lock, BITMAP_MUTEX_MFT); if (rno >= wnd->nbits) goto out; @@ -727,7 +729,8 @@ void ntfs_mark_rec_free(struct ntfs_sb_info *sbi, CLST rno) sbi->mft.next_free = rno; out: - up_write(&wnd->rw_lock); + if (!is_mft) + up_write(&wnd->rw_lock); } /* diff --git a/fs/ntfs3/inode.c b/fs/ntfs3/inode.c index 6c78930be035..a49da4ec6dc3 100644 --- a/fs/ntfs3/inode.c +++ b/fs/ntfs3/inode.c @@ -1636,7 +1636,7 @@ out4: ni->mi.dirty = false; discard_new_inode(inode); out3: - ntfs_mark_rec_free(sbi, ino); + ntfs_mark_rec_free(sbi, ino, false); out2: __putname(new_de); diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h index 0ea0cdab46b3..34c6ee56225c 100644 --- a/fs/ntfs3/ntfs_fs.h +++ b/fs/ntfs3/ntfs_fs.h @@ -590,7 +590,7 @@ int ntfs_look_for_free_space(struct ntfs_sb_info *sbi, CLST lcn, CLST len, enum ALLOCATE_OPT opt); int ntfs_look_free_mft(struct ntfs_sb_info *sbi, CLST *rno, bool mft, struct ntfs_inode *ni, struct mft_inode **mi); -void ntfs_mark_rec_free(struct ntfs_sb_info *sbi, CLST rno); +void ntfs_mark_rec_free(struct ntfs_sb_info *sbi, CLST rno, bool is_mft); int ntfs_clear_mft_tail(struct ntfs_sb_info *sbi, size_t from, size_t to); int ntfs_refresh_zone(struct ntfs_sb_info *sbi); void ntfs_update_mftmirr(struct ntfs_sb_info *sbi, int wait); -- cgit v1.2.3 From cf760ec0a0b4015ccf3b5e9ecb4caf6b5fb52f0b Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Fri, 1 Jul 2022 15:15:32 +0300 Subject: fs/ntfs3: Make static function attr_load_runs attr_load_runs is an internal function Signed-off-by: Konstantin Komarov --- fs/ntfs3/attrib.c | 4 ++-- fs/ntfs3/ntfs_fs.h | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/fs/ntfs3/attrib.c b/fs/ntfs3/attrib.c index 3d64335fa4c7..7454bd3ea02d 100644 --- a/fs/ntfs3/attrib.c +++ b/fs/ntfs3/attrib.c @@ -84,8 +84,8 @@ static inline bool attr_must_be_resident(struct ntfs_sb_info *sbi, /* * attr_load_runs - Load all runs stored in @attr. */ -int attr_load_runs(struct ATTRIB *attr, struct ntfs_inode *ni, - struct runs_tree *run, const CLST *vcn) +static int attr_load_runs(struct ATTRIB *attr, struct ntfs_inode *ni, + struct runs_tree *run, const CLST *vcn) { int err; CLST svcn = le64_to_cpu(attr->nres.svcn); diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h index 34c6ee56225c..83ed27bb624e 100644 --- a/fs/ntfs3/ntfs_fs.h +++ b/fs/ntfs3/ntfs_fs.h @@ -408,8 +408,6 @@ enum REPARSE_SIGN { }; /* Functions from attrib.c */ -int attr_load_runs(struct ATTRIB *attr, struct ntfs_inode *ni, - struct runs_tree *run, const CLST *vcn); int attr_allocate_clusters(struct ntfs_sb_info *sbi, struct runs_tree *run, CLST vcn, CLST lcn, CLST len, CLST *pre_alloc, enum ALLOCATE_OPT opt, CLST *alen, const size_t fr, -- cgit v1.2.3 From 42f66a7fdaa0d15691467fb7a808040f2d5ad0c0 Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Fri, 1 Jul 2022 15:18:29 +0300 Subject: fs/ntfs3: Fill duplicate info in ni_add_name Work with names must be completed in ni_add_name Signed-off-by: Konstantin Komarov --- fs/ntfs3/frecord.c | 20 ++++++++++++++------ fs/ntfs3/inode.c | 10 ---------- 2 files changed, 14 insertions(+), 16 deletions(-) diff --git a/fs/ntfs3/frecord.c b/fs/ntfs3/frecord.c index 756d9a18fa00..acd9f444bd64 100644 --- a/fs/ntfs3/frecord.c +++ b/fs/ntfs3/frecord.c @@ -1614,7 +1614,8 @@ struct ATTR_FILE_NAME *ni_fname_name(struct ntfs_inode *ni, struct ATTRIB *attr = NULL; struct ATTR_FILE_NAME *fname; - *le = NULL; + if (le) + *le = NULL; /* Enumerate all names. */ next: @@ -1630,7 +1631,7 @@ next: goto next; if (!uni) - goto next; + return fname; if (uni->len != fname->name_len) goto next; @@ -2969,7 +2970,7 @@ bool ni_remove_name_undo(struct ntfs_inode *dir_ni, struct ntfs_inode *ni, } /* - * ni_add_name - Add new name in MFT and in directory. + * ni_add_name - Add new name into MFT and into directory. */ int ni_add_name(struct ntfs_inode *dir_ni, struct ntfs_inode *ni, struct NTFS_DE *de) @@ -2978,13 +2979,20 @@ int ni_add_name(struct ntfs_inode *dir_ni, struct ntfs_inode *ni, struct ATTRIB *attr; struct ATTR_LIST_ENTRY *le; struct mft_inode *mi; + struct ATTR_FILE_NAME *fname; struct ATTR_FILE_NAME *de_name = (struct ATTR_FILE_NAME *)(de + 1); u16 de_key_size = le16_to_cpu(de->key_size); mi_get_ref(&ni->mi, &de->ref); mi_get_ref(&dir_ni->mi, &de_name->home); - /* Insert new name in MFT. */ + /* Fill duplicate from any ATTR_NAME. */ + fname = ni_fname_name(ni, NULL, NULL, NULL, NULL); + if (fname) + memcpy(&de_name->dup, &fname->dup, sizeof(fname->dup)); + de_name->dup.fa = ni->std_fa; + + /* Insert new name into MFT. */ err = ni_insert_resident(ni, de_key_size, ATTR_NAME, NULL, 0, &attr, &mi, &le); if (err) @@ -2992,7 +3000,7 @@ int ni_add_name(struct ntfs_inode *dir_ni, struct ntfs_inode *ni, memcpy(Add2Ptr(attr, SIZEOF_RESIDENT), de_name, de_key_size); - /* Insert new name in directory. */ + /* Insert new name into directory. */ err = indx_insert_entry(&dir_ni->dir, dir_ni, de, ni->mi.sbi, NULL, 0); if (err) ni_remove_attr_le(ni, attr, mi, le); @@ -3016,7 +3024,7 @@ int ni_rename(struct ntfs_inode *dir_ni, struct ntfs_inode *new_dir_ni, * 1) Add new name and remove old name. * 2) Remove old name and add new name. * - * In most cases (not all!) adding new name in MFT and in directory can + * In most cases (not all!) adding new name into MFT and into directory can * allocate additional cluster(s). * Second way may result to bad inode if we can't add new name * and then can't restore (add) old name. diff --git a/fs/ntfs3/inode.c b/fs/ntfs3/inode.c index a49da4ec6dc3..3ed319663747 100644 --- a/fs/ntfs3/inode.c +++ b/fs/ntfs3/inode.c @@ -1659,7 +1659,6 @@ int ntfs_link_inode(struct inode *inode, struct dentry *dentry) struct ntfs_inode *ni = ntfs_i(inode); struct ntfs_sb_info *sbi = inode->i_sb->s_fs_info; struct NTFS_DE *de; - struct ATTR_FILE_NAME *de_name; /* Allocate PATH_MAX bytes. */ de = __getname(); @@ -1674,15 +1673,6 @@ int ntfs_link_inode(struct inode *inode, struct dentry *dentry) if (err) goto out; - de_name = (struct ATTR_FILE_NAME *)(de + 1); - /* Fill duplicate info. */ - de_name->dup.cr_time = de_name->dup.m_time = de_name->dup.c_time = - de_name->dup.a_time = kernel2nt(&inode->i_ctime); - de_name->dup.alloc_size = de_name->dup.data_size = - cpu_to_le64(inode->i_size); - de_name->dup.fa = ni->std_fa; - de_name->dup.ea_size = de_name->dup.reparse = 0; - err = ni_add_name(ntfs_i(d_inode(dentry->d_parent)), ni, de); out: __putname(de); -- cgit v1.2.3 From 54033c135061b52d4405facba2e49177a5716a31 Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Wed, 6 Jul 2022 20:01:11 +0300 Subject: fs/ntfs3: Added comments to frecord functions Added some comments in frecord.c for more context. Also changed run_lookup to static because it's an internal function. Signed-off-by: Konstantin Komarov --- fs/ntfs3/bitmap.c | 3 +-- fs/ntfs3/frecord.c | 8 ++++---- fs/ntfs3/ntfs_fs.h | 1 - fs/ntfs3/run.c | 2 +- 4 files changed, 6 insertions(+), 8 deletions(-) diff --git a/fs/ntfs3/bitmap.c b/fs/ntfs3/bitmap.c index e3b5680fd516..bb9ebb160227 100644 --- a/fs/ntfs3/bitmap.c +++ b/fs/ntfs3/bitmap.c @@ -1393,9 +1393,8 @@ int wnd_extend(struct wnd_bitmap *wnd, size_t new_bits) void wnd_zone_set(struct wnd_bitmap *wnd, size_t lcn, size_t len) { - size_t zlen; + size_t zlen = wnd->zone_end - wnd->zone_bit; - zlen = wnd->zone_end - wnd->zone_bit; if (zlen) wnd_add_free_ext(wnd, wnd->zone_bit, zlen, false); diff --git a/fs/ntfs3/frecord.c b/fs/ntfs3/frecord.c index acd9f444bd64..bc48923693a9 100644 --- a/fs/ntfs3/frecord.c +++ b/fs/ntfs3/frecord.c @@ -1287,7 +1287,7 @@ static int ni_expand_mft_list(struct ntfs_inode *ni) done = asize - run_size - SIZEOF_NONRESIDENT; le32_sub_cpu(&ni->mi.mrec->used, done); - /* Estimate the size of second part: run_buf=NULL. */ + /* Estimate packed size (run_buf=NULL). */ err = run_pack(run, svcn, evcn + 1 - svcn, NULL, sbi->record_size, &plen); if (err < 0) @@ -1317,6 +1317,7 @@ static int ni_expand_mft_list(struct ntfs_inode *ni) attr->name_off = SIZEOF_NONRESIDENT_LE; attr->flags = 0; + /* This function can't fail - cause already checked above. */ run_pack(run, svcn, evcn + 1 - svcn, Add2Ptr(attr, SIZEOF_NONRESIDENT), run_size, &plen); @@ -1392,8 +1393,6 @@ int ni_expand_list(struct ntfs_inode *ni) /* Split MFT data as much as possible. */ err = ni_expand_mft_list(ni); - if (err) - goto out; out: return !err && !done ? -EOPNOTSUPP : err; @@ -1419,6 +1418,7 @@ int ni_insert_nonresident(struct ntfs_inode *ni, enum ATTR_TYPE type, u32 run_size, asize; struct ntfs_sb_info *sbi = ni->mi.sbi; + /* Estimate packed size (run_buf=NULL). */ err = run_pack(run, svcn, len, NULL, sbi->max_bytes_per_attr - run_off, &plen); if (err < 0) @@ -1448,12 +1448,12 @@ int ni_insert_nonresident(struct ntfs_inode *ni, enum ATTR_TYPE type, attr->name_off = cpu_to_le16(name_off); attr->flags = flags; + /* This function can't fail - cause already checked above. */ run_pack(run, svcn, len, Add2Ptr(attr, run_off), run_size, &plen); attr->nres.svcn = cpu_to_le64(svcn); attr->nres.evcn = cpu_to_le64((u64)svcn + len - 1); - err = 0; if (new_attr) *new_attr = attr; diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h index 83ed27bb624e..7a728d3589cf 100644 --- a/fs/ntfs3/ntfs_fs.h +++ b/fs/ntfs3/ntfs_fs.h @@ -773,7 +773,6 @@ bool run_lookup_entry(const struct runs_tree *run, CLST vcn, CLST *lcn, void run_truncate(struct runs_tree *run, CLST vcn); void run_truncate_head(struct runs_tree *run, CLST vcn); void run_truncate_around(struct runs_tree *run, CLST vcn); -bool run_lookup(const struct runs_tree *run, CLST vcn, size_t *index); bool run_add_entry(struct runs_tree *run, CLST vcn, CLST lcn, CLST len, bool is_mft); bool run_collapse_range(struct runs_tree *run, CLST vcn, CLST len); diff --git a/fs/ntfs3/run.c b/fs/ntfs3/run.c index aba8ab1b9fcb..4168b8adc131 100644 --- a/fs/ntfs3/run.c +++ b/fs/ntfs3/run.c @@ -31,7 +31,7 @@ struct ntfs_run { * Case of entry missing from list 'index' will be set to * point to insertion position for the entry question. */ -bool run_lookup(const struct runs_tree *run, CLST vcn, size_t *index) +static bool run_lookup(const struct runs_tree *run, CLST vcn, size_t *index) { size_t min_idx, max_idx, mid_idx; struct ntfs_run *r; -- cgit v1.2.3 From e6d9398c077d8e21a2ca50efab5cbf7ff5aff728 Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Wed, 6 Jul 2022 20:17:28 +0300 Subject: fs/ntfs3: Check possible errors in run_pack in advance Checking in advance speeds things up in some cases. Signed-off-by: Konstantin Komarov --- fs/ntfs3/run.c | 39 ++++++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/fs/ntfs3/run.c b/fs/ntfs3/run.c index 4168b8adc131..987a150108df 100644 --- a/fs/ntfs3/run.c +++ b/fs/ntfs3/run.c @@ -820,26 +820,36 @@ int run_pack(const struct runs_tree *run, CLST svcn, CLST len, u8 *run_buf, CLST next_vcn, vcn, lcn; CLST prev_lcn = 0; CLST evcn1 = svcn + len; + const struct ntfs_run *r, *r_end; int packed_size = 0; size_t i; - bool ok; s64 dlcn; int offset_size, size_size, tmp; - next_vcn = vcn = svcn; - *packed_vcns = 0; if (!len) goto out; - ok = run_lookup_entry(run, vcn, &lcn, &len, &i); + /* Check all required entries [svcn, encv1) available. */ + if (!run_lookup(run, svcn, &i)) + return -ENOENT; - if (!ok) - goto error; + r_end = run->runs + run->count; + r = run->runs + i; - if (next_vcn != vcn) - goto error; + for (next_vcn = r->vcn + r->len; next_vcn < evcn1; + next_vcn = r->vcn + r->len) { + if (++r >= r_end || r->vcn != next_vcn) + return -ENOENT; + } + + /* Repeat cycle above and pack runs. Assume no errors. */ + r = run->runs + i; + len = svcn - r->vcn; + vcn = svcn; + lcn = r->lcn == SPARSE_LCN ? SPARSE_LCN : (r->lcn + len); + len = r->len - len; for (;;) { next_vcn = vcn + len; @@ -888,12 +898,10 @@ int run_pack(const struct runs_tree *run, CLST svcn, CLST len, u8 *run_buf, if (packed_size + 1 >= run_buf_size || next_vcn >= evcn1) goto out; - ok = run_get_entry(run, ++i, &vcn, &lcn, &len); - if (!ok) - goto error; - - if (next_vcn != vcn) - goto error; + r += 1; + vcn = r->vcn; + lcn = r->lcn; + len = r->len; } out: @@ -902,9 +910,6 @@ out: run_buf[0] = 0; return packed_size + 1; - -error: - return -EOPNOTSUPP; } /* -- cgit v1.2.3 From 8335ebe195dcc76ece418485a9f08b9a9ad7fe23 Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Thu, 7 Jul 2022 19:25:43 +0300 Subject: fs/ntfs3: Make MFT zone less fragmented Now we take free space after the MFT zone if the MFT zone shrinks. Signed-off-by: Konstantin Komarov --- fs/ntfs3/fsntfs.c | 39 +++++++++++++++++++++++++-------------- fs/ntfs3/ntfs_fs.h | 1 + fs/ntfs3/super.c | 7 +++++++ 3 files changed, 33 insertions(+), 14 deletions(-) diff --git a/fs/ntfs3/fsntfs.c b/fs/ntfs3/fsntfs.c index fa4ca8b9b499..af1dca273b59 100644 --- a/fs/ntfs3/fsntfs.c +++ b/fs/ntfs3/fsntfs.c @@ -783,7 +783,7 @@ out: */ int ntfs_refresh_zone(struct ntfs_sb_info *sbi) { - CLST zone_limit, zone_max, lcn, vcn, len; + CLST lcn, vcn, len; size_t lcn_s, zlen; struct wnd_bitmap *wnd = &sbi->used.bitmap; struct ntfs_inode *ni = sbi->mft.ni; @@ -792,16 +792,6 @@ int ntfs_refresh_zone(struct ntfs_sb_info *sbi) if (wnd_zone_len(wnd)) return 0; - /* - * Compute the MFT zone at two steps. - * It would be nice if we are able to allocate 1/8 of - * total clusters for MFT but not more then 512 MB. - */ - zone_limit = (512 * 1024 * 1024) >> sbi->cluster_bits; - zone_max = wnd->nbits >> 3; - if (zone_max > zone_limit) - zone_max = zone_limit; - vcn = bytes_to_cluster(sbi, (u64)sbi->mft.bitmap.nbits << sbi->record_bits); @@ -815,7 +805,7 @@ int ntfs_refresh_zone(struct ntfs_sb_info *sbi) lcn_s = lcn + 1; /* Try to allocate clusters after last MFT run. */ - zlen = wnd_find(wnd, zone_max, lcn_s, 0, &lcn_s); + zlen = wnd_find(wnd, sbi->zone_max, lcn_s, 0, &lcn_s); if (!zlen) { ntfs_notice(sbi->sb, "MftZone: unavailable"); return 0; @@ -1397,7 +1387,7 @@ int ntfs_write_bh(struct ntfs_sb_info *sbi, struct NTFS_RECORD_HEADER *rhdr, if (buffer_locked(bh)) __wait_on_buffer(bh); - lock_buffer(nb->bh[idx]); + lock_buffer(bh); bh_data = bh->b_data + off; end_data = Add2Ptr(bh_data, op); @@ -2426,7 +2416,7 @@ static inline void ntfs_unmap_and_discard(struct ntfs_sb_info *sbi, CLST lcn, void mark_as_free_ex(struct ntfs_sb_info *sbi, CLST lcn, CLST len, bool trim) { - CLST end, i; + CLST end, i, zone_len, zlen; struct wnd_bitmap *wnd = &sbi->used.bitmap; down_write_nested(&wnd->rw_lock, BITMAP_MUTEX_CLUSTERS); @@ -2461,6 +2451,27 @@ void mark_as_free_ex(struct ntfs_sb_info *sbi, CLST lcn, CLST len, bool trim) ntfs_unmap_and_discard(sbi, lcn, len); wnd_set_free(wnd, lcn, len); + /* append to MFT zone, if possible. */ + zone_len = wnd_zone_len(wnd); + zlen = min(zone_len + len, sbi->zone_max); + + if (zlen == zone_len) { + /* MFT zone already has maximum size. */ + } else if (!zone_len) { + /* Create MFT zone. */ + wnd_zone_set(wnd, lcn, zlen); + } else { + CLST zone_lcn = wnd_zone_bit(wnd); + + if (lcn + len == zone_lcn) { + /* Append into head MFT zone. */ + wnd_zone_set(wnd, lcn, zlen); + } else if (zone_lcn + zone_len == lcn) { + /* Append into tail MFT zone. */ + wnd_zone_set(wnd, zone_lcn, zlen); + } + } + out: up_write(&wnd->rw_lock); } diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h index 7a728d3589cf..6a2bbf889faa 100644 --- a/fs/ntfs3/ntfs_fs.h +++ b/fs/ntfs3/ntfs_fs.h @@ -220,6 +220,7 @@ struct ntfs_sb_info { u32 flags; // See NTFS_FLAGS_XXX. + CLST zone_max; // Maximum MFT zone length in clusters CLST bad_clusters; // The count of marked bad clusters. u16 max_bytes_per_attr; // Maximum attribute size in record. diff --git a/fs/ntfs3/super.c b/fs/ntfs3/super.c index eacea72ff92f..6fad173a8b8f 100644 --- a/fs/ntfs3/super.c +++ b/fs/ntfs3/super.c @@ -867,6 +867,13 @@ static int ntfs_init_from_boot(struct super_block *sb, u32 sector_size, sb->s_maxbytes = 0xFFFFFFFFull << sbi->cluster_bits; #endif + /* + * Compute the MFT zone at two steps. + * It would be nice if we are able to allocate 1/8 of + * total clusters for MFT but not more then 512 MB. + */ + sbi->zone_max = min_t(CLST, 0x20000000 >> sbi->cluster_bits, clusters >> 3); + err = 0; out: -- cgit v1.2.3 From c12df45ee690112782049b8e85dff2e6cb1b3853 Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Wed, 13 Jul 2022 17:55:27 +0300 Subject: fs/ntfs3: New function ntfs_bad_inode There are repetitive steps in case of bad inode This commit wraps them in function Signed-off-by: Konstantin Komarov --- fs/ntfs3/attrib.c | 10 ++++------ fs/ntfs3/frecord.c | 6 ++---- fs/ntfs3/fsntfs.c | 14 ++++++++++++++ fs/ntfs3/inode.c | 6 ++---- fs/ntfs3/namei.c | 4 +--- fs/ntfs3/ntfs_fs.h | 2 ++ 6 files changed, 25 insertions(+), 17 deletions(-) diff --git a/fs/ntfs3/attrib.c b/fs/ntfs3/attrib.c index 7454bd3ea02d..5ba83eb0fc07 100644 --- a/fs/ntfs3/attrib.c +++ b/fs/ntfs3/attrib.c @@ -1912,7 +1912,7 @@ next_attr: out: up_write(&ni->file.run_lock); if (err) - make_bad_inode(&ni->vfs_inode); + _ntfs_bad_inode(&ni->vfs_inode); return err; } @@ -2092,10 +2092,8 @@ int attr_punch_hole(struct ntfs_inode *ni, u64 vbo, u64 bytes, u32 *frame_size) out: up_write(&ni->file.run_lock); - if (err) { - ntfs_set_state(sbi, NTFS_DIRTY_ERROR); - make_bad_inode(&ni->vfs_inode); - } + if (err) + _ntfs_bad_inode(&ni->vfs_inode); return err; } @@ -2282,7 +2280,7 @@ out: up_write(&ni->file.run_lock); if (err) - make_bad_inode(&ni->vfs_inode); + _ntfs_bad_inode(&ni->vfs_inode); return err; } diff --git a/fs/ntfs3/frecord.c b/fs/ntfs3/frecord.c index bc48923693a9..bdc568053fae 100644 --- a/fs/ntfs3/frecord.c +++ b/fs/ntfs3/frecord.c @@ -2328,10 +2328,8 @@ remove_wof: out: kfree(pages); - if (err) { - make_bad_inode(inode); - ntfs_set_state(sbi, NTFS_DIRTY_ERROR); - } + if (err) + _ntfs_bad_inode(inode); return err; } diff --git a/fs/ntfs3/fsntfs.c b/fs/ntfs3/fsntfs.c index af1dca273b59..3f9903baa53f 100644 --- a/fs/ntfs3/fsntfs.c +++ b/fs/ntfs3/fsntfs.c @@ -877,6 +877,20 @@ void ntfs_update_mftmirr(struct ntfs_sb_info *sbi, int wait) sbi->flags &= ~NTFS_FLAGS_MFTMIRR; } +/* + * ntfs_bad_inode + * + * Marks inode as bad and marks fs as 'dirty' + */ +void ntfs_bad_inode(struct inode *inode, const char *hint) +{ + struct ntfs_sb_info *sbi = inode->i_sb->s_fs_info; + + ntfs_inode_err(inode, "%s", hint); + make_bad_inode(inode); + ntfs_set_state(sbi, NTFS_DIRTY_ERROR); +} + /* * ntfs_set_state * diff --git a/fs/ntfs3/inode.c b/fs/ntfs3/inode.c index 3ed319663747..cd48687127c1 100644 --- a/fs/ntfs3/inode.c +++ b/fs/ntfs3/inode.c @@ -501,7 +501,7 @@ struct inode *ntfs_iget5(struct super_block *sb, const struct MFT_REF *ref, inode = ntfs_read_mft(inode, name, ref); else if (ref->seq != ntfs_i(inode)->mi.mrec->seq) { /* Inode overlaps? */ - make_bad_inode(inode); + _ntfs_bad_inode(inode); } return inode; @@ -1725,9 +1725,7 @@ int ntfs_unlink_inode(struct inode *dir, const struct dentry *dentry) if (inode->i_nlink) mark_inode_dirty(inode); } else if (!ni_remove_name_undo(dir_ni, ni, de, de2, undo_remove)) { - make_bad_inode(inode); - ntfs_inode_err(inode, "failed to undo unlink"); - ntfs_set_state(sbi, NTFS_DIRTY_ERROR); + _ntfs_bad_inode(inode); } else { if (ni_is_dirty(dir)) mark_inode_dirty(dir); diff --git a/fs/ntfs3/namei.c b/fs/ntfs3/namei.c index 1cc700760c7e..bc22cc321a74 100644 --- a/fs/ntfs3/namei.c +++ b/fs/ntfs3/namei.c @@ -308,9 +308,7 @@ static int ntfs_rename(struct user_namespace *mnt_userns, struct inode *dir, err = ni_rename(dir_ni, new_dir_ni, ni, de, new_de, &is_bad); if (is_bad) { /* Restore after failed rename failed too. */ - make_bad_inode(inode); - ntfs_inode_err(inode, "failed to undo rename"); - ntfs_set_state(sbi, NTFS_DIRTY_ERROR); + _ntfs_bad_inode(inode); } else if (!err) { inode->i_ctime = dir->i_ctime = dir->i_mtime = current_time(dir); diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h index 6a2bbf889faa..a9359675299f 100644 --- a/fs/ntfs3/ntfs_fs.h +++ b/fs/ntfs3/ntfs_fs.h @@ -593,6 +593,8 @@ void ntfs_mark_rec_free(struct ntfs_sb_info *sbi, CLST rno, bool is_mft); int ntfs_clear_mft_tail(struct ntfs_sb_info *sbi, size_t from, size_t to); int ntfs_refresh_zone(struct ntfs_sb_info *sbi); void ntfs_update_mftmirr(struct ntfs_sb_info *sbi, int wait); +void ntfs_bad_inode(struct inode *inode, const char *hint); +#define _ntfs_bad_inode(i) ntfs_bad_inode(i, __func__) enum NTFS_DIRTY_FLAGS { NTFS_DIRTY_CLEAR = 0, NTFS_DIRTY_DIRTY = 1, -- cgit v1.2.3 From 0e5b044cbf3a41b4efad7d9616342338f88b373d Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Wed, 13 Jul 2022 18:00:03 +0300 Subject: fs/ntfs3: Refactoring attr_set_size to restore after errors Added comments to code Added two undo labels for restoring after errors Signed-off-by: Konstantin Komarov --- fs/ntfs3/attrib.c | 180 ++++++++++++++++++++++++++++++++++++++---------------- 1 file changed, 126 insertions(+), 54 deletions(-) diff --git a/fs/ntfs3/attrib.c b/fs/ntfs3/attrib.c index 5ba83eb0fc07..c29b2debc909 100644 --- a/fs/ntfs3/attrib.c +++ b/fs/ntfs3/attrib.c @@ -173,7 +173,6 @@ int attr_allocate_clusters(struct ntfs_sb_info *sbi, struct runs_tree *run, { int err; CLST flen, vcn0 = vcn, pre = pre_alloc ? *pre_alloc : 0; - struct wnd_bitmap *wnd = &sbi->used.bitmap; size_t cnt = run->count; for (;;) { @@ -196,9 +195,7 @@ int attr_allocate_clusters(struct ntfs_sb_info *sbi, struct runs_tree *run, /* Add new fragment into run storage. */ if (!run_add_entry(run, vcn, lcn, flen, opt == ALLOCATE_MFT)) { /* Undo last 'ntfs_look_for_free_space' */ - down_write_nested(&wnd->rw_lock, BITMAP_MUTEX_CLUSTERS); - wnd_set_free(wnd, lcn, flen); - up_write(&wnd->rw_lock); + mark_as_free_ex(sbi, lcn, len, false); err = -ENOMEM; goto out; } @@ -419,40 +416,44 @@ int attr_set_size(struct ntfs_inode *ni, enum ATTR_TYPE type, struct mft_inode *mi, *mi_b; CLST alen, vcn, lcn, new_alen, old_alen, svcn, evcn; CLST next_svcn, pre_alloc = -1, done = 0; - bool is_ext; + bool is_ext, is_bad = false; u32 align; struct MFT_REC *rec; again: + alen = 0; le_b = NULL; attr_b = ni_find_attr(ni, NULL, &le_b, type, name, name_len, NULL, &mi_b); if (!attr_b) { err = -ENOENT; - goto out; + goto bad_inode; } if (!attr_b->non_res) { err = attr_set_size_res(ni, attr_b, le_b, mi_b, new_size, run, &attr_b); - if (err || !attr_b->non_res) - goto out; + if (err) + return err; + + /* Return if file is still resident. */ + if (!attr_b->non_res) + goto ok1; /* Layout of records may be changed, so do a full search. */ goto again; } is_ext = is_attr_ext(attr_b); - -again_1: align = sbi->cluster_size; - if (is_ext) align <<= attr_b->nres.c_unit; old_valid = le64_to_cpu(attr_b->nres.valid_size); old_size = le64_to_cpu(attr_b->nres.data_size); old_alloc = le64_to_cpu(attr_b->nres.alloc_size); + +again_1: old_alen = old_alloc >> cluster_bits; new_alloc = (new_size + align - 1) & ~(u64)(align - 1); @@ -475,24 +476,27 @@ again_1: mi = mi_b; } else if (!le_b) { err = -EINVAL; - goto out; + goto bad_inode; } else { le = le_b; attr = ni_find_attr(ni, attr_b, &le, type, name, name_len, &vcn, &mi); if (!attr) { err = -EINVAL; - goto out; + goto bad_inode; } next_le_1: svcn = le64_to_cpu(attr->nres.svcn); evcn = le64_to_cpu(attr->nres.evcn); } - + /* + * Here we have: + * attr,mi,le - last attribute segment (containing 'vcn'). + * attr_b,mi_b,le_b - base (primary) attribute segment. + */ next_le: rec = mi->mrec; - err = attr_load_runs(attr, ni, run, NULL); if (err) goto out; @@ -507,6 +511,13 @@ next_le: goto ok; } + /* + * Add clusters. In simple case we have to: + * - allocate space (vcn, lcn, len) + * - update packed run in 'mi' + * - update attr->nres.evcn + * - update attr_b->nres.data_size/attr_b->nres.alloc_size + */ to_allocate = new_alen - old_alen; add_alloc_in_same_attr_seg: lcn = 0; @@ -520,9 +531,11 @@ add_alloc_in_same_attr_seg: pre_alloc = 0; if (type == ATTR_DATA && !name_len && sbi->options->prealloc) { - CLST new_alen2 = bytes_to_cluster( - sbi, get_pre_allocated(new_size)); - pre_alloc = new_alen2 - new_alen; + pre_alloc = + bytes_to_cluster( + sbi, + get_pre_allocated(new_size)) - + new_alen; } /* Get the last LCN to allocate from. */ @@ -580,7 +593,7 @@ add_alloc_in_same_attr_seg: pack_runs: err = mi_pack_runs(mi, attr, run, vcn - svcn); if (err) - goto out; + goto undo_1; next_svcn = le64_to_cpu(attr->nres.evcn) + 1; new_alloc_tmp = (u64)next_svcn << cluster_bits; @@ -614,7 +627,7 @@ pack_runs: if (type == ATTR_LIST) { err = ni_expand_list(ni); if (err) - goto out; + goto undo_2; if (next_svcn < vcn) goto pack_runs; @@ -624,8 +637,9 @@ pack_runs: if (!ni->attr_list.size) { err = ni_create_attr_list(ni); + /* In case of error layout of records is not changed. */ if (err) - goto out; + goto undo_2; /* Layout of records is changed. */ } @@ -638,47 +652,56 @@ pack_runs: err = ni_insert_nonresident(ni, type, name, name_len, run, next_svcn, vcn - next_svcn, attr_b->flags, &attr, &mi, NULL); - if (err) - goto out; - - if (!is_mft) - run_truncate_head(run, evcn + 1); - svcn = le64_to_cpu(attr->nres.svcn); - evcn = le64_to_cpu(attr->nres.evcn); - - le_b = NULL; /* * Layout of records maybe changed. * Find base attribute to update. */ + le_b = NULL; attr_b = ni_find_attr(ni, NULL, &le_b, type, name, name_len, NULL, &mi_b); if (!attr_b) { - err = -ENOENT; - goto out; + err = -EINVAL; + goto bad_inode; } - attr_b->nres.alloc_size = cpu_to_le64((u64)vcn << cluster_bits); - attr_b->nres.data_size = attr_b->nres.alloc_size; - attr_b->nres.valid_size = attr_b->nres.alloc_size; + if (err) { + /* ni_insert_nonresident failed. */ + attr = NULL; + goto undo_2; + } + + if (!is_mft) + run_truncate_head(run, evcn + 1); + + svcn = le64_to_cpu(attr->nres.svcn); + evcn = le64_to_cpu(attr->nres.evcn); + + /* + * Attribute is in consistency state. + * Save this point to restore to if next steps fail. + */ + old_valid = old_size = old_alloc = (u64)vcn << cluster_bits; + attr_b->nres.valid_size = attr_b->nres.data_size = + attr_b->nres.alloc_size = cpu_to_le64(old_size); mi_b->dirty = true; goto again_1; } if (new_size != old_size || (new_alloc != old_alloc && !keep_prealloc)) { + /* + * Truncate clusters. In simple case we have to: + * - update packed run in 'mi' + * - update attr->nres.evcn + * - update attr_b->nres.data_size/attr_b->nres.alloc_size + * - mark and trim clusters as free (vcn, lcn, len) + */ + CLST dlen = 0; + vcn = max(svcn, new_alen); new_alloc_tmp = (u64)vcn << cluster_bits; - alen = 0; - err = run_deallocate_ex(sbi, run, vcn, evcn - vcn + 1, &alen, - true); - if (err) - goto out; - - run_truncate(run, vcn); - if (vcn > svcn) { err = mi_pack_runs(mi, attr, run, vcn - svcn); if (err) @@ -697,7 +720,7 @@ pack_runs: if (!al_remove_le(ni, le)) { err = -EINVAL; - goto out; + goto bad_inode; } le = (struct ATTR_LIST_ENTRY *)((u8 *)le - le_sz); @@ -723,12 +746,20 @@ pack_runs: attr_b->nres.valid_size = attr_b->nres.alloc_size; } + mi_b->dirty = true; - if (is_ext) + err = run_deallocate_ex(sbi, run, vcn, evcn - vcn + 1, &dlen, + true); + if (err) + goto out; + + if (is_ext) { + /* dlen - really deallocated clusters. */ le64_sub_cpu(&attr_b->nres.total_size, - ((u64)alen << cluster_bits)); + ((u64)dlen << cluster_bits)); + } - mi_b->dirty = true; + run_truncate(run, vcn); if (new_alloc_tmp <= new_alloc) goto ok; @@ -747,7 +778,7 @@ pack_runs: if (le->type != type || le->name_len != name_len || memcmp(le_name(le), name, name_len * sizeof(short))) { err = -EINVAL; - goto out; + goto bad_inode; } err = ni_load_mi(ni, le, &mi); @@ -757,7 +788,7 @@ pack_runs: attr = mi_find_attr(mi, NULL, type, name, name_len, &le->id); if (!attr) { err = -EINVAL; - goto out; + goto bad_inode; } goto next_le_1; } @@ -772,13 +803,13 @@ ok: } } -out: - if (!err && attr_b && ret) +ok1: + if (ret) *ret = attr_b; /* Update inode_set_bytes. */ - if (!err && ((type == ATTR_DATA && !name_len) || - (type == ATTR_ALLOC && name == I30_NAME))) { + if (((type == ATTR_DATA && !name_len) || + (type == ATTR_ALLOC && name == I30_NAME))) { bool dirty = false; if (ni->vfs_inode.i_size != new_size) { @@ -786,7 +817,7 @@ out: dirty = true; } - if (attr_b && attr_b->non_res) { + if (attr_b->non_res) { new_alloc = le64_to_cpu(attr_b->nres.alloc_size); if (inode_get_bytes(&ni->vfs_inode) != new_alloc) { inode_set_bytes(&ni->vfs_inode, new_alloc); @@ -800,6 +831,47 @@ out: } } + return 0; + +undo_2: + vcn -= alen; + attr_b->nres.data_size = cpu_to_le64(old_size); + attr_b->nres.valid_size = cpu_to_le64(old_valid); + attr_b->nres.alloc_size = cpu_to_le64(old_alloc); + + /* Restore 'attr' and 'mi'. */ + if (attr) + goto restore_run; + + if (le64_to_cpu(attr_b->nres.svcn) <= svcn && + svcn <= le64_to_cpu(attr_b->nres.evcn)) { + attr = attr_b; + le = le_b; + mi = mi_b; + } else if (!le_b) { + err = -EINVAL; + goto bad_inode; + } else { + le = le_b; + attr = ni_find_attr(ni, attr_b, &le, type, name, name_len, + &svcn, &mi); + if (!attr) + goto bad_inode; + } + +restore_run: + if (mi_pack_runs(mi, attr, run, evcn - svcn + 1)) + is_bad = true; + +undo_1: + run_deallocate_ex(sbi, run, vcn, alen, NULL, false); + + run_truncate(run, vcn); +out: + if (is_bad) { +bad_inode: + _ntfs_bad_inode(&ni->vfs_inode); + } return err; } -- cgit v1.2.3 From 20abc64f78346ac591344133301661b77e1c8253 Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Wed, 13 Jul 2022 18:18:48 +0300 Subject: fs/ntfs3: Refactoring attr_punch_hole to restore after errors Added comments to code Added new function run_clone to make a copy of run Added done and undo labels for restoring after errors Signed-off-by: Konstantin Komarov --- fs/ntfs3/attrib.c | 117 ++++++++++++++++++++++++++++++++++++----------------- fs/ntfs3/ntfs_fs.h | 1 + fs/ntfs3/run.c | 25 ++++++++++++ 3 files changed, 105 insertions(+), 38 deletions(-) diff --git a/fs/ntfs3/attrib.c b/fs/ntfs3/attrib.c index c29b2debc909..cf3729ce771b 100644 --- a/fs/ntfs3/attrib.c +++ b/fs/ntfs3/attrib.c @@ -140,7 +140,10 @@ failed: } if (lcn != SPARSE_LCN) { - mark_as_free_ex(sbi, lcn, clen, trim); + if (sbi) { + /* mark bitmap range [lcn + clen) as free and trim clusters. */ + mark_as_free_ex(sbi, lcn, clen, trim); + } dn += clen; } @@ -2002,10 +2005,11 @@ int attr_punch_hole(struct ntfs_inode *ni, u64 vbo, u64 bytes, u32 *frame_size) struct ATTRIB *attr = NULL, *attr_b; struct ATTR_LIST_ENTRY *le, *le_b; struct mft_inode *mi, *mi_b; - CLST svcn, evcn1, vcn, len, end, alen, dealloc, next_svcn; + CLST svcn, evcn1, vcn, len, end, alen, hole, next_svcn; u64 total_size, alloc_size; u32 mask; __le16 a_flags; + struct runs_tree run2; if (!bytes) return 0; @@ -2057,6 +2061,9 @@ int attr_punch_hole(struct ntfs_inode *ni, u64 vbo, u64 bytes, u32 *frame_size) } down_write(&ni->file.run_lock); + run_init(&run2); + run_truncate(run, 0); + /* * Enumerate all attribute segments and punch hole where necessary. */ @@ -2064,7 +2071,7 @@ int attr_punch_hole(struct ntfs_inode *ni, u64 vbo, u64 bytes, u32 *frame_size) vcn = vbo >> sbi->cluster_bits; len = bytes >> sbi->cluster_bits; end = vcn + len; - dealloc = 0; + hole = 0; svcn = le64_to_cpu(attr_b->nres.svcn); evcn1 = le64_to_cpu(attr_b->nres.evcn) + 1; @@ -2076,14 +2083,14 @@ int attr_punch_hole(struct ntfs_inode *ni, u64 vbo, u64 bytes, u32 *frame_size) mi = mi_b; } else if (!le_b) { err = -EINVAL; - goto out; + goto bad_inode; } else { le = le_b; attr = ni_find_attr(ni, attr_b, &le, ATTR_DATA, NULL, 0, &vcn, &mi); if (!attr) { err = -EINVAL; - goto out; + goto bad_inode; } svcn = le64_to_cpu(attr->nres.svcn); @@ -2091,69 +2098,91 @@ int attr_punch_hole(struct ntfs_inode *ni, u64 vbo, u64 bytes, u32 *frame_size) } while (svcn < end) { - CLST vcn1, zero, dealloc2; + CLST vcn1, zero, hole2 = hole; err = attr_load_runs(attr, ni, run, &svcn); if (err) - goto out; + goto done; vcn1 = max(vcn, svcn); zero = min(end, evcn1) - vcn1; - dealloc2 = dealloc; - err = run_deallocate_ex(sbi, run, vcn1, zero, &dealloc, true); + /* + * Check range [vcn1 + zero). + * Calculate how many clusters there are. + * Don't do any destructive actions. + */ + err = run_deallocate_ex(NULL, run, vcn1, zero, &hole2, false); if (err) - goto out; + goto done; - if (dealloc2 == dealloc) { - /* Looks like the required range is already sparsed. */ - } else { - if (!run_add_entry(run, vcn1, SPARSE_LCN, zero, - false)) { - err = -ENOMEM; - goto out; - } + /* Check if required range is already hole. */ + if (hole2 == hole) + goto next_attr; - err = mi_pack_runs(mi, attr, run, evcn1 - svcn); + /* Make a clone of run to undo. */ + err = run_clone(run, &run2); + if (err) + goto done; + + /* Make a hole range (sparse) [vcn1 + zero). */ + if (!run_add_entry(run, vcn1, SPARSE_LCN, zero, false)) { + err = -ENOMEM; + goto done; + } + + /* Update run in attribute segment. */ + err = mi_pack_runs(mi, attr, run, evcn1 - svcn); + if (err) + goto done; + next_svcn = le64_to_cpu(attr->nres.evcn) + 1; + if (next_svcn < evcn1) { + /* Insert new attribute segment. */ + err = ni_insert_nonresident(ni, ATTR_DATA, NULL, 0, run, + next_svcn, + evcn1 - next_svcn, a_flags, + &attr, &mi, &le); if (err) - goto out; - next_svcn = le64_to_cpu(attr->nres.evcn) + 1; - if (next_svcn < evcn1) { - err = ni_insert_nonresident(ni, ATTR_DATA, NULL, - 0, run, next_svcn, - evcn1 - next_svcn, - a_flags, &attr, &mi, - &le); - if (err) - goto out; - /* Layout of records maybe changed. */ - attr_b = NULL; - } + goto undo_punch; + + /* Layout of records maybe changed. */ + attr_b = NULL; } + + /* Real deallocate. Should not fail. */ + run_deallocate_ex(sbi, &run2, vcn1, zero, &hole, true); + +next_attr: /* Free all allocated memory. */ run_truncate(run, 0); if (evcn1 >= alen) break; + /* Get next attribute segment. */ attr = ni_enum_attr_ex(ni, attr, &le, &mi); if (!attr) { err = -EINVAL; - goto out; + goto bad_inode; } svcn = le64_to_cpu(attr->nres.svcn); evcn1 = le64_to_cpu(attr->nres.evcn) + 1; } - total_size -= (u64)dealloc << sbi->cluster_bits; +done: + if (!hole) + goto out; + if (!attr_b) { attr_b = ni_find_attr(ni, NULL, NULL, ATTR_DATA, NULL, 0, NULL, &mi_b); if (!attr_b) { err = -EINVAL; - goto out; + goto bad_inode; } } + + total_size -= (u64)hole << sbi->cluster_bits; attr_b->nres.total_size = cpu_to_le64(total_size); mi_b->dirty = true; @@ -2163,11 +2192,23 @@ int attr_punch_hole(struct ntfs_inode *ni, u64 vbo, u64 bytes, u32 *frame_size) mark_inode_dirty(&ni->vfs_inode); out: + run_close(&run2); up_write(&ni->file.run_lock); - if (err) - _ntfs_bad_inode(&ni->vfs_inode); - return err; + +bad_inode: + _ntfs_bad_inode(&ni->vfs_inode); + goto out; + +undo_punch: + /* + * Restore packed runs. + * 'mi_pack_runs' should not fail, cause we restore original. + */ + if (mi_pack_runs(mi, attr, &run2, evcn1 - svcn)) + goto bad_inode; + + goto done; } /* diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h index a9359675299f..c37fa9ca5689 100644 --- a/fs/ntfs3/ntfs_fs.h +++ b/fs/ntfs3/ntfs_fs.h @@ -798,6 +798,7 @@ int run_unpack_ex(struct runs_tree *run, struct ntfs_sb_info *sbi, CLST ino, #define run_unpack_ex run_unpack #endif int run_get_highest_vcn(CLST vcn, const u8 *run_buf, u64 *highest_vcn); +int run_clone(const struct runs_tree *run, struct runs_tree *new_run); /* Globals from super.c */ void *ntfs_set_shared(void *ptr, u32 bytes); diff --git a/fs/ntfs3/run.c b/fs/ntfs3/run.c index 987a150108df..aaaa0d3d35a2 100644 --- a/fs/ntfs3/run.c +++ b/fs/ntfs3/run.c @@ -1156,3 +1156,28 @@ int run_get_highest_vcn(CLST vcn, const u8 *run_buf, u64 *highest_vcn) *highest_vcn = vcn64 - 1; return 0; } + +/* + * run_clone + * + * Make a copy of run + */ +int run_clone(const struct runs_tree *run, struct runs_tree *new_run) +{ + size_t bytes = run->count * sizeof(struct ntfs_run); + + if (bytes > new_run->allocated) { + struct ntfs_run *new_ptr = kvmalloc(bytes, GFP_KERNEL); + + if (!new_ptr) + return -ENOMEM; + + kvfree(new_run->runs); + new_run->runs = new_ptr; + new_run->allocated = bytes; + } + + memcpy(new_run->runs, run->runs, bytes); + new_run->count = run->count; + return 0; +} -- cgit v1.2.3 From 9256ec35359f52c1e390cf419873cf519ee332b6 Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Wed, 13 Jul 2022 18:44:24 +0300 Subject: fs/ntfs3: Refactoring attr_insert_range to restore after errors Added done and undo labels for restoring after errors Signed-off-by: Konstantin Komarov --- fs/ntfs3/attrib.c | 117 +++++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 86 insertions(+), 31 deletions(-) diff --git a/fs/ntfs3/attrib.c b/fs/ntfs3/attrib.c index cf3729ce771b..71f870d497ae 100644 --- a/fs/ntfs3/attrib.c +++ b/fs/ntfs3/attrib.c @@ -2275,30 +2275,29 @@ int attr_insert_range(struct ntfs_inode *ni, u64 vbo, u64 bytes) if (!attr_b->non_res) { err = attr_set_size(ni, ATTR_DATA, NULL, 0, run, - data_size + bytes, NULL, false, &attr); - if (err) - goto out; - if (!attr->non_res) { - /* Still resident. */ - char *data = Add2Ptr(attr, attr->res.data_off); + data_size + bytes, NULL, false, NULL); - memmove(data + bytes, data, bytes); - memset(data, 0, bytes); - err = 0; - goto out; - } - /* Resident files becomes nonresident. */ le_b = NULL; attr_b = ni_find_attr(ni, NULL, &le_b, ATTR_DATA, NULL, 0, NULL, &mi_b); if (!attr_b) { - err = -ENOENT; - goto out; - } - if (!attr_b->non_res) { err = -EINVAL; + goto bad_inode; + } + + if (err) goto out; + + if (!attr_b->non_res) { + /* Still resident. */ + char *data = Add2Ptr(attr_b, attr_b->res.data_off); + + memmove(data + bytes, data, bytes); + memset(data, 0, bytes); + goto done; } + + /* Resident files becomes nonresident. */ data_size = le64_to_cpu(attr_b->nres.data_size); alloc_size = le64_to_cpu(attr_b->nres.alloc_size); } @@ -2316,14 +2315,14 @@ int attr_insert_range(struct ntfs_inode *ni, u64 vbo, u64 bytes) mi = mi_b; } else if (!le_b) { err = -EINVAL; - goto out; + goto bad_inode; } else { le = le_b; attr = ni_find_attr(ni, attr_b, &le, ATTR_DATA, NULL, 0, &vcn, &mi); if (!attr) { err = -EINVAL; - goto out; + goto bad_inode; } svcn = le64_to_cpu(attr->nres.svcn); @@ -2346,7 +2345,6 @@ int attr_insert_range(struct ntfs_inode *ni, u64 vbo, u64 bytes) goto out; next_svcn = le64_to_cpu(attr->nres.evcn) + 1; - run_truncate_head(run, next_svcn); while ((attr = ni_enum_attr_ex(ni, attr, &le, &mi)) && attr->type == ATTR_DATA && !attr->name_len) { @@ -2359,9 +2357,27 @@ int attr_insert_range(struct ntfs_inode *ni, u64 vbo, u64 bytes) mi->dirty = true; } + if (next_svcn < evcn1 + len) { + err = ni_insert_nonresident(ni, ATTR_DATA, NULL, 0, run, + next_svcn, evcn1 + len - next_svcn, + a_flags, NULL, NULL, NULL); + + le_b = NULL; + attr_b = ni_find_attr(ni, NULL, &le_b, ATTR_DATA, NULL, 0, NULL, + &mi_b); + if (!attr_b) { + err = -EINVAL; + goto bad_inode; + } + + if (err) { + /* ni_insert_nonresident failed. Try to undo. */ + goto undo_insert_range; + } + } + /* - * Update primary attribute segment in advance. - * pointer attr_b may become invalid (layout of mft is changed) + * Update primary attribute segment. */ if (vbo <= ni->i_valid) ni->i_valid += bytes; @@ -2376,14 +2392,7 @@ int attr_insert_range(struct ntfs_inode *ni, u64 vbo, u64 bytes) attr_b->nres.valid_size = cpu_to_le64(ni->i_valid); mi_b->dirty = true; - if (next_svcn < evcn1 + len) { - err = ni_insert_nonresident(ni, ATTR_DATA, NULL, 0, run, - next_svcn, evcn1 + len - next_svcn, - a_flags, NULL, NULL, NULL); - if (err) - goto out; - } - +done: ni->vfs_inode.i_size += bytes; ni->ni_flags |= NI_FLAG_UPDATE_PARENT; mark_inode_dirty(&ni->vfs_inode); @@ -2392,8 +2401,54 @@ out: run_truncate(run, 0); /* clear cached values. */ up_write(&ni->file.run_lock); - if (err) - _ntfs_bad_inode(&ni->vfs_inode); return err; + +bad_inode: + _ntfs_bad_inode(&ni->vfs_inode); + goto out; + +undo_insert_range: + svcn = le64_to_cpu(attr_b->nres.svcn); + evcn1 = le64_to_cpu(attr_b->nres.evcn) + 1; + + if (svcn <= vcn && vcn < evcn1) { + attr = attr_b; + le = le_b; + mi = mi_b; + } else if (!le_b) { + goto bad_inode; + } else { + le = le_b; + attr = ni_find_attr(ni, attr_b, &le, ATTR_DATA, NULL, 0, &vcn, + &mi); + if (!attr) { + goto bad_inode; + } + + svcn = le64_to_cpu(attr->nres.svcn); + evcn1 = le64_to_cpu(attr->nres.evcn) + 1; + } + + if (attr_load_runs(attr, ni, run, NULL)) + goto bad_inode; + + if (!run_collapse_range(run, vcn, len)) + goto bad_inode; + + if (mi_pack_runs(mi, attr, run, evcn1 + len - svcn)) + goto bad_inode; + + while ((attr = ni_enum_attr_ex(ni, attr, &le, &mi)) && + attr->type == ATTR_DATA && !attr->name_len) { + le64_sub_cpu(&attr->nres.svcn, len); + le64_sub_cpu(&attr->nres.evcn, len); + if (le) { + le->vcn = attr->nres.svcn; + ni->attr_list.dirty = true; + } + mi->dirty = true; + } + + goto out; } -- cgit v1.2.3 From 8039edba043d1eaee74bd76e0280a49ba5e195d7 Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Wed, 13 Jul 2022 19:11:15 +0300 Subject: fs/ntfs3: Create MFT zone only if length is large enough Also removed uninformative print Signed-off-by: Konstantin Komarov --- fs/ntfs3/fsntfs.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/fs/ntfs3/fsntfs.c b/fs/ntfs3/fsntfs.c index 3f9903baa53f..209ca71c3ba0 100644 --- a/fs/ntfs3/fsntfs.c +++ b/fs/ntfs3/fsntfs.c @@ -806,12 +806,6 @@ int ntfs_refresh_zone(struct ntfs_sb_info *sbi) /* Try to allocate clusters after last MFT run. */ zlen = wnd_find(wnd, sbi->zone_max, lcn_s, 0, &lcn_s); - if (!zlen) { - ntfs_notice(sbi->sb, "MftZone: unavailable"); - return 0; - } - - /* Truncate too large zone. */ wnd_zone_set(wnd, lcn_s, zlen); return 0; @@ -2472,8 +2466,9 @@ void mark_as_free_ex(struct ntfs_sb_info *sbi, CLST lcn, CLST len, bool trim) if (zlen == zone_len) { /* MFT zone already has maximum size. */ } else if (!zone_len) { - /* Create MFT zone. */ - wnd_zone_set(wnd, lcn, zlen); + /* Create MFT zone only if 'zlen' is large enough. */ + if (zlen == sbi->zone_max) + wnd_zone_set(wnd, lcn, zlen); } else { CLST zone_lcn = wnd_zone_bit(wnd); -- cgit v1.2.3 From 451e45a0e6df21e63acfd493feb5194f4697ce11 Mon Sep 17 00:00:00 2001 From: Konstantin Komarov Date: Wed, 13 Jul 2022 19:18:19 +0300 Subject: fs/ntfs3: Make ni_ins_new_attr return error Function ni_ins_new_attr now returns ERR_PTR(err), so we check it now in other functions like ni_expand_mft_list Signed-off-by: Konstantin Komarov --- fs/ntfs3/frecord.c | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/fs/ntfs3/frecord.c b/fs/ntfs3/frecord.c index bdc568053fae..381a38a06ec2 100644 --- a/fs/ntfs3/frecord.c +++ b/fs/ntfs3/frecord.c @@ -469,7 +469,7 @@ ni_ins_new_attr(struct ntfs_inode *ni, struct mft_inode *mi, &ref, &le); if (err) { /* No memory or no space. */ - return NULL; + return ERR_PTR(err); } le_added = true; @@ -1011,6 +1011,8 @@ static int ni_ins_attr_ext(struct ntfs_inode *ni, struct ATTR_LIST_ENTRY *le, name_off, svcn, ins_le); if (!attr) continue; + if (IS_ERR(attr)) + return PTR_ERR(attr); if (ins_attr) *ins_attr = attr; @@ -1032,8 +1034,15 @@ insert_ext: attr = ni_ins_new_attr(ni, mi, le, type, name, name_len, asize, name_off, svcn, ins_le); - if (!attr) + if (!attr) { + err = -EINVAL; goto out2; + } + + if (IS_ERR(attr)) { + err = PTR_ERR(attr); + goto out2; + } if (ins_attr) *ins_attr = attr; @@ -1045,7 +1054,6 @@ insert_ext: out2: ni_remove_mi(ni, mi); mi_put(mi); - err = -EINVAL; out1: ntfs_mark_rec_free(sbi, rno, is_mft); @@ -1101,6 +1109,11 @@ static int ni_insert_attr(struct ntfs_inode *ni, enum ATTR_TYPE type, if (asize <= free) { attr = ni_ins_new_attr(ni, &ni->mi, NULL, type, name, name_len, asize, name_off, svcn, ins_le); + if (IS_ERR(attr)) { + err = PTR_ERR(attr); + goto out; + } + if (attr) { if (ins_attr) *ins_attr = attr; @@ -1198,6 +1211,11 @@ static int ni_insert_attr(struct ntfs_inode *ni, enum ATTR_TYPE type, goto out; } + if (IS_ERR(attr)) { + err = PTR_ERR(attr); + goto out; + } + if (ins_attr) *ins_attr = attr; if (ins_mi) @@ -1313,6 +1331,11 @@ static int ni_expand_mft_list(struct ntfs_inode *ni) goto out; } + if (IS_ERR(attr)) { + err = PTR_ERR(attr); + goto out; + } + attr->non_res = 1; attr->name_off = SIZEOF_NONRESIDENT_LE; attr->flags = 0; -- cgit v1.2.3 From d20ec7529236a2fcdb2d856fc0bd80b409a217fc Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 7 Jul 2022 01:15:36 +0200 Subject: riscv: implement cache-management errata for T-Head SoCs The T-Head C906 and C910 implement a scheme for handling cache operations different from the generic Zicbom extension. Add an errata for it next to the generic dma coherency ops. Reviewed-by: Samuel Holland Tested-by: Samuel Holland Reviewed-by: Guo Ren Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20220706231536.2041855-5-heiko@sntech.de Signed-off-by: Palmer Dabbelt --- arch/riscv/Kconfig.erratas | 11 +++++++++ arch/riscv/errata/thead/errata.c | 20 +++++++++++++++ arch/riscv/include/asm/errata_list.h | 48 ++++++++++++++++++++++++++++++++---- 3 files changed, 74 insertions(+), 5 deletions(-) diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas index 457ac72c9b36..3223e533fd87 100644 --- a/arch/riscv/Kconfig.erratas +++ b/arch/riscv/Kconfig.erratas @@ -55,4 +55,15 @@ config ERRATA_THEAD_PBMT If you don't know what to do here, say "Y". +config ERRATA_THEAD_CMO + bool "Apply T-Head cache management errata" + depends on ERRATA_THEAD + select RISCV_DMA_NONCOHERENT + default y + help + This will apply the cache management errata to handle the + non-standard handling on non-coherent operations on T-Head SoCs. + + If you don't know what to do here, say "Y". + endmenu diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c index b37b6fedd53b..202c83f677b2 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -27,6 +27,23 @@ static bool errata_probe_pbmt(unsigned int stage, return false; } +static bool errata_probe_cmo(unsigned int stage, + unsigned long arch_id, unsigned long impid) +{ +#ifdef CONFIG_ERRATA_THEAD_CMO + if (arch_id != 0 || impid != 0) + return false; + + if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) + return false; + + riscv_noncoherent_supported(); + return true; +#else + return false; +#endif +} + static u32 thead_errata_probe(unsigned int stage, unsigned long archid, unsigned long impid) { @@ -35,6 +52,9 @@ static u32 thead_errata_probe(unsigned int stage, if (errata_probe_pbmt(stage, archid, impid)) cpu_req_errata |= (1U << ERRATA_THEAD_PBMT); + if (errata_probe_cmo(stage, archid, impid)) + cpu_req_errata |= (1U << ERRATA_THEAD_CMO); + return cpu_req_errata; } diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index f7c015005847..0f66e368e351 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -16,7 +16,8 @@ #ifdef CONFIG_ERRATA_THEAD #define ERRATA_THEAD_PBMT 0 -#define ERRATA_THEAD_NUMBER 1 +#define ERRATA_THEAD_CMO 1 +#define ERRATA_THEAD_NUMBER 2 #endif #define CPUFEATURE_SVPBMT 0 @@ -94,17 +95,54 @@ asm volatile(ALTERNATIVE( \ #define ALT_THEAD_PMA(_val) #endif +/* + * dcache.ipa rs1 (invalidate, physical address) + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | + * 0000001 01010 rs1 000 00000 0001011 + * dache.iva rs1 (invalida, virtual address) + * 0000001 00110 rs1 000 00000 0001011 + * + * dcache.cpa rs1 (clean, physical address) + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | + * 0000001 01001 rs1 000 00000 0001011 + * dcache.cva rs1 (clean, virtual address) + * 0000001 00100 rs1 000 00000 0001011 + * + * dcache.cipa rs1 (clean then invalidate, physical address) + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | + * 0000001 01011 rs1 000 00000 0001011 + * dcache.civa rs1 (... virtual address) + * 0000001 00111 rs1 000 00000 0001011 + * + * sync.s (make sure all cache operations finished) + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | + * 0000000 11001 00000 000 00000 0001011 + */ +#define THEAD_inval_A0 ".long 0x0265000b" +#define THEAD_clean_A0 ".long 0x0245000b" +#define THEAD_flush_A0 ".long 0x0275000b" +#define THEAD_SYNC_S ".long 0x0190000b" + #define ALT_CMO_OP(_op, _start, _size, _cachesize) \ -asm volatile(ALTERNATIVE( \ - __nops(5), \ +asm volatile(ALTERNATIVE_2( \ + __nops(6), \ "mv a0, %1\n\t" \ "j 2f\n\t" \ "3:\n\t" \ "cbo." __stringify(_op) " (a0)\n\t" \ "add a0, a0, %0\n\t" \ "2:\n\t" \ - "bltu a0, %2, 3b\n\t", 0, \ - CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM) \ + "bltu a0, %2, 3b\n\t" \ + "nop", 0, CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ + "mv a0, %1\n\t" \ + "j 2f\n\t" \ + "3:\n\t" \ + THEAD_##_op##_A0 "\n\t" \ + "add a0, a0, %0\n\t" \ + "2:\n\t" \ + "bltu a0, %2, 3b\n\t" \ + THEAD_SYNC_S, THEAD_VENDOR_ID, \ + ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \ : : "r"(_cachesize), \ "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \ "r"((unsigned long)(_start) + (_size)) \ -- cgit v1.2.3 From f482aa98652795846cc55da98ebe331eb74f3d0b Mon Sep 17 00:00:00 2001 From: Peilin Ye Date: Wed, 3 Aug 2022 15:23:43 -0700 Subject: audit, io_uring, io-wq: Fix memory leak in io_sq_thread() and io_wqe_worker() Currently @audit_context is allocated twice for io_uring workers: 1. copy_process() calls audit_alloc(); 2. io_sq_thread() or io_wqe_worker() calls audit_alloc_kernel() (which is effectively audit_alloc()) and overwrites @audit_context, causing: BUG: memory leak unreferenced object 0xffff888144547400 (size 1024): <...> hex dump (first 32 bytes): 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ backtrace: [] audit_alloc+0x133/0x210 [] copy_process+0xcd3/0x2340 [] create_io_thread+0x63/0x90 [] create_io_worker+0xb4/0x230 [] io_wqe_enqueue+0x248/0x3b0 [] io_queue_iowq+0xba/0x200 [] io_queue_async+0x113/0x180 [] io_req_task_submit+0x18f/0x1a0 [] io_apoll_task_func+0xdd/0x120 [] tctx_task_work+0x11f/0x570 [] task_work_run+0x7e/0xc0 [] get_signal+0xc18/0xf10 [] arch_do_signal_or_restart+0x2b/0x730 [] exit_to_user_mode_prepare+0x5e/0x180 [] syscall_exit_to_user_mode+0x12/0x20 [] do_syscall_64+0x40/0x80 Then, 3. io_sq_thread() or io_wqe_worker() frees @audit_context using audit_free(); 4. do_exit() eventually calls audit_free() again, which is okay because audit_free() does a NULL check. As suggested by Paul Moore, fix it by deleting audit_alloc_kernel() and redundant audit_free() calls. Fixes: 5bd2182d58e9 ("audit,io_uring,io-wq: add some basic audit support to io_uring") Suggested-by: Paul Moore Cc: stable@vger.kernel.org Signed-off-by: Peilin Ye Acked-by: Paul Moore Link: https://lore.kernel.org/r/20220803222343.31673-1-yepeilin.cs@gmail.com Signed-off-by: Jens Axboe --- include/linux/audit.h | 5 ----- io_uring/io-wq.c | 3 --- io_uring/sqpoll.c | 4 ---- kernel/auditsc.c | 25 ------------------------- 4 files changed, 37 deletions(-) diff --git a/include/linux/audit.h b/include/linux/audit.h index 00f7a80f1a3e..3608992848d3 100644 --- a/include/linux/audit.h +++ b/include/linux/audit.h @@ -285,7 +285,6 @@ static inline int audit_signal_info(int sig, struct task_struct *t) /* These are defined in auditsc.c */ /* Public API */ extern int audit_alloc(struct task_struct *task); -extern int audit_alloc_kernel(struct task_struct *task); extern void __audit_free(struct task_struct *task); extern void __audit_uring_entry(u8 op); extern void __audit_uring_exit(int success, long code); @@ -578,10 +577,6 @@ static inline int audit_alloc(struct task_struct *task) { return 0; } -static inline int audit_alloc_kernel(struct task_struct *task) -{ - return 0; -} static inline void audit_free(struct task_struct *task) { } static inline void audit_uring_entry(u8 op) diff --git a/io_uring/io-wq.c b/io_uring/io-wq.c index 77df5b43bf52..c6536d4b2da0 100644 --- a/io_uring/io-wq.c +++ b/io_uring/io-wq.c @@ -624,8 +624,6 @@ static int io_wqe_worker(void *data) snprintf(buf, sizeof(buf), "iou-wrk-%d", wq->task->pid); set_task_comm(current, buf); - audit_alloc_kernel(current); - while (!test_bit(IO_WQ_BIT_EXIT, &wq->state)) { long ret; @@ -660,7 +658,6 @@ static int io_wqe_worker(void *data) if (test_bit(IO_WQ_BIT_EXIT, &wq->state)) io_worker_handle_work(worker); - audit_free(current); io_worker_exit(worker); return 0; } diff --git a/io_uring/sqpoll.c b/io_uring/sqpoll.c index 76d4d70c733a..559652380672 100644 --- a/io_uring/sqpoll.c +++ b/io_uring/sqpoll.c @@ -235,8 +235,6 @@ static int io_sq_thread(void *data) set_cpus_allowed_ptr(current, cpu_online_mask); current->flags |= PF_NO_SETAFFINITY; - audit_alloc_kernel(current); - mutex_lock(&sqd->lock); while (1) { bool cap_entries, sqt_spin = false; @@ -310,8 +308,6 @@ static int io_sq_thread(void *data) io_run_task_work(); mutex_unlock(&sqd->lock); - audit_free(current); - complete(&sqd->exited); do_exit(0); } diff --git a/kernel/auditsc.c b/kernel/auditsc.c index 3a8c9d744800..dd8d9ab747c3 100644 --- a/kernel/auditsc.c +++ b/kernel/auditsc.c @@ -1073,31 +1073,6 @@ int audit_alloc(struct task_struct *tsk) return 0; } -/** - * audit_alloc_kernel - allocate an audit_context for a kernel task - * @tsk: the kernel task - * - * Similar to the audit_alloc() function, but intended for kernel private - * threads. Returns zero on success, negative values on failure. - */ -int audit_alloc_kernel(struct task_struct *tsk) -{ - /* - * At the moment we are just going to call into audit_alloc() to - * simplify the code, but there two things to keep in mind with this - * approach: - * - * 1. Filtering internal kernel tasks is a bit laughable in almost all - * cases, but there is at least one case where there is a benefit: - * the '-a task,never' case allows the admin to effectively disable - * task auditing at runtime. - * - * 2. The {set,clear}_task_syscall_work() ops likely have zero effect - * on these internal kernel tasks, but they probably don't hurt either. - */ - return audit_alloc(tsk); -} - static inline void audit_free_context(struct audit_context *context) { /* resetting is extra work, but it is likely just noise */ -- cgit v1.2.3 From cc18cc5e82033d406f54144ad6f8092206004684 Mon Sep 17 00:00:00 2001 From: Pavel Begunkov Date: Thu, 4 Aug 2022 15:13:46 +0100 Subject: io_uring: mem-account pbuf buckets Potentially, someone may create as many pbuf bucket as there are indexes in an xarray without any other restrictions bounding our memory usage, put memory needed for the buckets under memory accounting. Cc: Signed-off-by: Pavel Begunkov Link: https://lore.kernel.org/r/d34c452e45793e978d26e2606211ec9070d329ea.1659622312.git.asml.silence@gmail.com Signed-off-by: Jens Axboe --- io_uring/kbuf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/io_uring/kbuf.c b/io_uring/kbuf.c index e538fa7cb727..a73f40a4cfe6 100644 --- a/io_uring/kbuf.c +++ b/io_uring/kbuf.c @@ -436,7 +436,7 @@ int io_provide_buffers(struct io_kiocb *req, unsigned int issue_flags) bl = io_buffer_get_list(ctx, p->bgid); if (unlikely(!bl)) { - bl = kzalloc(sizeof(*bl), GFP_KERNEL); + bl = kzalloc(sizeof(*bl), GFP_KERNEL_ACCOUNT); if (!bl) { ret = -ENOMEM; goto err; -- cgit v1.2.3 From 4a933e62083ead6cd064293a7505c56165859320 Mon Sep 17 00:00:00 2001 From: Pavel Begunkov Date: Thu, 4 Aug 2022 15:15:30 +0100 Subject: io_uring/net: send retry for zerocopy io_uring handles short sends/recvs for stream sockets when MSG_WAITALL is set, however new zerocopy send is inconsistent in this regard, which might be confusing. Handle short sends. Signed-off-by: Pavel Begunkov Link: https://lore.kernel.org/r/b876a4838597d9bba4f3215db60d72c33c448ad0.1659622472.git.asml.silence@gmail.com Signed-off-by: Jens Axboe --- io_uring/net.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/io_uring/net.c b/io_uring/net.c index 32fc3da04e41..f9f080b3cc1e 100644 --- a/io_uring/net.c +++ b/io_uring/net.c @@ -70,6 +70,7 @@ struct io_sendzc { unsigned flags; unsigned addr_len; void __user *addr; + size_t done_io; }; #define IO_APOLL_MULTI_POLLED (REQ_F_APOLL_MULTISHOT | REQ_F_POLLED) @@ -878,6 +879,7 @@ int io_sendzc_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) zc->addr = u64_to_user_ptr(READ_ONCE(sqe->addr2)); zc->addr_len = READ_ONCE(sqe->addr_len); + zc->done_io = 0; #ifdef CONFIG_COMPAT if (req->ctx->compat) @@ -1012,11 +1014,23 @@ int io_sendzc(struct io_kiocb *req, unsigned int issue_flags) if (unlikely(ret < min_ret)) { if (ret == -EAGAIN && (issue_flags & IO_URING_F_NONBLOCK)) return -EAGAIN; - return ret == -ERESTARTSYS ? -EINTR : ret; + if (ret > 0 && io_net_retry(sock, msg.msg_flags)) { + zc->len -= ret; + zc->buf += ret; + zc->done_io += ret; + req->flags |= REQ_F_PARTIAL_IO; + return -EAGAIN; + } + if (ret == -ERESTARTSYS) + ret = -EINTR; + } else if (zc->flags & IORING_RECVSEND_NOTIF_FLUSH) { + io_notif_slot_flush_submit(notif_slot, 0); } - if (zc->flags & IORING_RECVSEND_NOTIF_FLUSH) - io_notif_slot_flush_submit(notif_slot, 0); + if (ret >= 0) + ret += zc->done_io; + else if (zc->done_io) + ret = zc->done_io; io_req_set_res(req, ret, 0); return IOU_OK; } -- cgit v1.2.3 From f882c4bef9cb914d9f7be171afb10ed26536bfa7 Mon Sep 17 00:00:00 2001 From: Meng Tang Date: Fri, 5 Aug 2022 15:45:34 +0800 Subject: ALSA: hda/realtek: Add quirk for another Asus K42JZ model There is another Asus K42JZ model with the PCI SSID 1043:1313 that requires the quirk ALC269VB_FIXUP_ASUS_MIC_NO_PRESENCE. Add the corresponding entry to the quirk table. Signed-off-by: Meng Tang Cc: Link: https://lore.kernel.org/r/20220805074534.20003-1-tangmeng@uniontech.com Signed-off-by: Takashi Iwai --- sound/pci/hda/patch_realtek.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 8a57636f622e..4197567b6f26 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -6909,6 +6909,7 @@ enum { ALC269_FIXUP_LIMIT_INT_MIC_BOOST, ALC269VB_FIXUP_ASUS_ZENBOOK, ALC269VB_FIXUP_ASUS_ZENBOOK_UX31A, + ALC269VB_FIXUP_ASUS_MIC_NO_PRESENCE, ALC269_FIXUP_LIMIT_INT_MIC_BOOST_MUTE_LED, ALC269VB_FIXUP_ORDISSIMO_EVE2, ALC283_FIXUP_CHROME_BOOK, @@ -7497,6 +7498,15 @@ static const struct hda_fixup alc269_fixups[] = { .chained = true, .chain_id = ALC269VB_FIXUP_ASUS_ZENBOOK, }, + [ALC269VB_FIXUP_ASUS_MIC_NO_PRESENCE] = { + .type = HDA_FIXUP_PINS, + .v.pins = (const struct hda_pintbl[]) { + { 0x18, 0x01a110f0 }, /* use as headset mic */ + { } + }, + .chained = true, + .chain_id = ALC269_FIXUP_HEADSET_MIC + }, [ALC269_FIXUP_LIMIT_INT_MIC_BOOST_MUTE_LED] = { .type = HDA_FIXUP_FUNC, .v.func = alc269_fixup_limit_int_mic_boost, @@ -9274,6 +9284,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = { SND_PCI_QUIRK(0x1043, 0x12a0, "ASUS X441UV", ALC233_FIXUP_EAPD_COEF_AND_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1043, 0x12e0, "ASUS X541SA", ALC256_FIXUP_ASUS_MIC), SND_PCI_QUIRK(0x1043, 0x12f0, "ASUS X541UV", ALC256_FIXUP_ASUS_MIC), + SND_PCI_QUIRK(0x1043, 0x1313, "Asus K42JZ", ALC269VB_FIXUP_ASUS_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1043, 0x13b0, "ASUS Z550SA", ALC256_FIXUP_ASUS_MIC), SND_PCI_QUIRK(0x1043, 0x1427, "Asus Zenbook UX31E", ALC269VB_FIXUP_ASUS_ZENBOOK), SND_PCI_QUIRK(0x1043, 0x1517, "Asus Zenbook UX31A", ALC269VB_FIXUP_ASUS_ZENBOOK_UX31A), -- cgit v1.2.3 From d501cc4cfc6be1ab9aef3ff0fa3b2afc52a1af23 Mon Sep 17 00:00:00 2001 From: David Jander Date: Fri, 5 Aug 2022 10:44:58 +0200 Subject: spi: spi.c: Add missing __percpu annotations in users of spi_statistics Fixes sparse warnings of this kind: drivers/spi/spi.c:117:16: sparse: expected struct spi_statistics * drivers/spi/spi.c:117:16: sparse: got struct spi_statistics [noderef] __percpu *[assigned] pcpu_stats Reported-by: kernel test robot Signed-off-by: David Jander Link: https://lore.kernel.org/r/20220805084458.1602277-1-david@protonic.nl Signed-off-by: Mark Brown --- drivers/spi/spi.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 1c14d682ffed..1b5969448542 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -95,7 +95,7 @@ static ssize_t driver_override_show(struct device *dev, } static DEVICE_ATTR_RW(driver_override); -static struct spi_statistics *spi_alloc_pcpu_stats(struct device *dev) +static struct spi_statistics __percpu *spi_alloc_pcpu_stats(struct device *dev) { struct spi_statistics __percpu *pcpu_stats; @@ -162,7 +162,7 @@ static struct device_attribute dev_attr_spi_device_##field = { \ } #define SPI_STATISTICS_SHOW_NAME(name, file, field) \ -static ssize_t spi_statistics_##name##_show(struct spi_statistics *stat, \ +static ssize_t spi_statistics_##name##_show(struct spi_statistics __percpu *stat, \ char *buf) \ { \ ssize_t len; \ @@ -309,7 +309,7 @@ static const struct attribute_group *spi_master_groups[] = { NULL, }; -static void spi_statistics_add_transfer_stats(struct spi_statistics *pcpu_stats, +static void spi_statistics_add_transfer_stats(struct spi_statistics __percpu *pcpu_stats, struct spi_transfer *xfer, struct spi_controller *ctlr) { @@ -1275,8 +1275,8 @@ static int spi_transfer_wait(struct spi_controller *ctlr, struct spi_message *msg, struct spi_transfer *xfer) { - struct spi_statistics *statm = ctlr->pcpu_statistics; - struct spi_statistics *stats = msg->spi->pcpu_statistics; + struct spi_statistics __percpu *statm = ctlr->pcpu_statistics; + struct spi_statistics __percpu *stats = msg->spi->pcpu_statistics; u32 speed_hz = xfer->speed_hz; unsigned long long ms; @@ -1432,8 +1432,8 @@ static int spi_transfer_one_message(struct spi_controller *ctlr, struct spi_transfer *xfer; bool keep_cs = false; int ret = 0; - struct spi_statistics *statm = ctlr->pcpu_statistics; - struct spi_statistics *stats = msg->spi->pcpu_statistics; + struct spi_statistics __percpu *statm = ctlr->pcpu_statistics; + struct spi_statistics __percpu *stats = msg->spi->pcpu_statistics; spi_set_cs(msg->spi, true, false); -- cgit v1.2.3 From 706864c99e0e2d301da9e749395909bc309c50a0 Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Thu, 4 Aug 2022 18:18:23 +0200 Subject: MAINTAINERS: rectify entry for ARM/HPE GXP ARCHITECTURE Commit 8cc35b86546d ("spi: dt-bindings: add documentation for hpe,gxp-spifi") adds the spi dt-binding file hpe,gxp-spifi.yaml and commit a1848b0fa251 ("MAINTAINERS: add spi support to GXP") adds a file entry hpe,gxp-spi.yaml in ARM/HPE GXP ARCHITECTURE. Note the different file name. Hence, ./scripts/get_maintainer.pl --self-test=patterns complains about a broken reference. Repair this file reference in ARM/HPE GXP ARCHITECTURE. Signed-off-by: Lukas Bulwahn Link: https://lore.kernel.org/r/20220804161823.20912-1-lukas.bulwahn@gmail.com Signed-off-by: Mark Brown --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 8678dcb2de92..09fdd1e3d987 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2140,7 +2140,7 @@ M: Jean-Marie Verdun M: Nick Hawkins S: Maintained F: Documentation/devicetree/bindings/arm/hpe,gxp.yaml -F: Documentation/devicetree/bindings/spi/hpe,gxp-spi.yaml +F: Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml F: Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml F: arch/arm/boot/dts/hpe-bmc* F: arch/arm/boot/dts/hpe-gxp* -- cgit v1.2.3 From 666d3b612f91dab4a6616586dc99d2e43f07f52d Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Fri, 5 Aug 2022 13:04:39 +0100 Subject: ALSA: ice1712: remove redundant assignment to new The variable new is initialized with a value but it is never read. It is being re-assigned a new value in every case path in the following switch statement. The assignment is redundant and can be removed. Cleans up clang scan build warning: sound/pci/ice1712/quartet.c:569:8: warning: Although the value stored to 'new' is used in the enclosing expression, the value is never actually read from 'new' [deadcode.DeadStores] Signed-off-by: Colin Ian King Link: https://lore.kernel.org/r/20220805120439.2341600-1-colin.i.king@gmail.com Signed-off-by: Takashi Iwai --- sound/pci/ice1712/quartet.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/pci/ice1712/quartet.c b/sound/pci/ice1712/quartet.c index 0dfa093f7dca..20b3e8f94719 100644 --- a/sound/pci/ice1712/quartet.c +++ b/sound/pci/ice1712/quartet.c @@ -566,7 +566,7 @@ static int qtet_ain12_sw_put(struct snd_kcontrol *kcontrol, { struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol); unsigned int old, new, tmp, masked_old; - old = new = get_scr(ice); + old = get_scr(ice); masked_old = old & (SCR_AIN12_SEL1 | SCR_AIN12_SEL0); tmp = ucontrol->value.integer.value[0]; if (tmp == 2) -- cgit v1.2.3 From d1f6222c4978817712e0f2825ce9e830763f0695 Mon Sep 17 00:00:00 2001 From: Dylan Yudaken Date: Fri, 5 Aug 2022 04:54:50 -0700 Subject: io_uring: fix io_recvmsg_prep_multishot sparse warnings Fix casts missing the __user parts. This seemed to only cause errors on the alpha build, or if checked with sparse, but it was definitely an oversight. Reported-by: kernel test robot Fixes: 9bb66906f23e ("io_uring: support multishot in recvmsg") Signed-off-by: Dylan Yudaken Link: https://lore.kernel.org/r/20220805115450.3921352-1-dylany@fb.com Signed-off-by: Jens Axboe --- io_uring/net.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/io_uring/net.c b/io_uring/net.c index f9f080b3cc1e..e6fc9748fbd2 100644 --- a/io_uring/net.c +++ b/io_uring/net.c @@ -576,12 +576,12 @@ static int io_recvmsg_prep_multishot(struct io_async_msghdr *kmsg, if (kmsg->controllen) { unsigned long control = ubuf + hdr - kmsg->controllen; - kmsg->msg.msg_control_user = (void *) control; + kmsg->msg.msg_control_user = (void __user *) control; kmsg->msg.msg_controllen = kmsg->controllen; } sr->buf = *buf; /* stash for later copy */ - *buf = (void *) (ubuf + hdr); + *buf = (void __user *) (ubuf + hdr); kmsg->payloadlen = *len = *len - hdr; return 0; } -- cgit v1.2.3 From 7d839e325af221ff69d52e15c112cf09da91d149 Mon Sep 17 00:00:00 2001 From: "Darrick J. Wong" Date: Thu, 28 Jul 2022 13:35:31 -0700 Subject: xfs: check return codes when flushing block devices If a blkdev_issue_flush fails, fsync needs to report that to upper levels. Modify xfs_file_fsync to capture the errors, while trying to flush as much data and log updates to disk as possible. If log writes cannot flush the data device, we need to shut down the log immediately because we've violated a log invariant. Modify this code to check the return value of blkdev_issue_flush as well. This behavior seems to go back to about 2.6.15 or so, which makes this fixes tag a bit misleading. Link: https://elixir.bootlin.com/linux/v2.6.15/source/fs/xfs/xfs_vnodeops.c#L1187 Fixes: b5071ada510a ("xfs: remove xfs_blkdev_issue_flush") Signed-off-by: Darrick J. Wong Reviewed-by: Dave Chinner --- fs/xfs/xfs_file.c | 22 ++++++++++++++-------- fs/xfs/xfs_log.c | 12 ++++++++++-- 2 files changed, 24 insertions(+), 10 deletions(-) diff --git a/fs/xfs/xfs_file.c b/fs/xfs/xfs_file.c index 5a171c0b244b..b3d1392eb758 100644 --- a/fs/xfs/xfs_file.c +++ b/fs/xfs/xfs_file.c @@ -142,7 +142,7 @@ xfs_file_fsync( { struct xfs_inode *ip = XFS_I(file->f_mapping->host); struct xfs_mount *mp = ip->i_mount; - int error = 0; + int error, err2; int log_flushed = 0; trace_xfs_file_fsync(ip); @@ -163,18 +163,21 @@ xfs_file_fsync( * inode size in case of an extending write. */ if (XFS_IS_REALTIME_INODE(ip)) - blkdev_issue_flush(mp->m_rtdev_targp->bt_bdev); + error = blkdev_issue_flush(mp->m_rtdev_targp->bt_bdev); else if (mp->m_logdev_targp != mp->m_ddev_targp) - blkdev_issue_flush(mp->m_ddev_targp->bt_bdev); + error = blkdev_issue_flush(mp->m_ddev_targp->bt_bdev); /* * Any inode that has dirty modifications in the log is pinned. The - * racy check here for a pinned inode while not catch modifications + * racy check here for a pinned inode will not catch modifications * that happen concurrently to the fsync call, but fsync semantics * only require to sync previously completed I/O. */ - if (xfs_ipincount(ip)) - error = xfs_fsync_flush_log(ip, datasync, &log_flushed); + if (xfs_ipincount(ip)) { + err2 = xfs_fsync_flush_log(ip, datasync, &log_flushed); + if (err2 && !error) + error = err2; + } /* * If we only have a single device, and the log force about was @@ -184,8 +187,11 @@ xfs_file_fsync( * commit. */ if (!log_flushed && !XFS_IS_REALTIME_INODE(ip) && - mp->m_logdev_targp == mp->m_ddev_targp) - blkdev_issue_flush(mp->m_ddev_targp->bt_bdev); + mp->m_logdev_targp == mp->m_ddev_targp) { + err2 = blkdev_issue_flush(mp->m_ddev_targp->bt_bdev); + if (err2 && !error) + error = err2; + } return error; } diff --git a/fs/xfs/xfs_log.c b/fs/xfs/xfs_log.c index 4b1c0a9c6368..386b0307aed8 100644 --- a/fs/xfs/xfs_log.c +++ b/fs/xfs/xfs_log.c @@ -1925,9 +1925,17 @@ xlog_write_iclog( * device cache first to ensure all metadata writeback covered * by the LSN in this iclog is on stable storage. This is slow, * but it *must* complete before we issue the external log IO. + * + * If the flush fails, we cannot conclude that past metadata + * writeback from the log succeeded. Repeating the flush is + * not possible, hence we must shut down with log IO error to + * avoid shutdown re-entering this path and erroring out again. */ - if (log->l_targ != log->l_mp->m_ddev_targp) - blkdev_issue_flush(log->l_mp->m_ddev_targp->bt_bdev); + if (log->l_targ != log->l_mp->m_ddev_targp && + blkdev_issue_flush(log->l_mp->m_ddev_targp->bt_bdev)) { + xlog_force_shutdown(log, SHUTDOWN_LOG_IO_ERROR); + return; + } } if (iclog->ic_flags & XLOG_ICL_NEED_FUA) iclog->ic_bio.bi_opf |= REQ_FUA; -- cgit v1.2.3 From f0c2d7d2abca24d19831c99edea458704fac8087 Mon Sep 17 00:00:00 2001 From: "Darrick J. Wong" Date: Wed, 3 Aug 2022 17:33:00 -0700 Subject: xfs: fix intermittent hang during quotacheck Every now and then, I see the following hang during mount time quotacheck when running fstests. Turning on KASAN seems to make it happen somewhat more frequently. I've edited the backtrace for brevity. XFS (sdd): Quotacheck needed: Please wait. XFS: Assertion failed: bp->b_flags & _XBF_DELWRI_Q, file: fs/xfs/xfs_buf.c, line: 2411 ------------[ cut here ]------------ WARNING: CPU: 0 PID: 1831409 at fs/xfs/xfs_message.c:104 assfail+0x46/0x4a [xfs] CPU: 0 PID: 1831409 Comm: mount Tainted: G W 5.19.0-rc6-xfsx #rc6 09911566947b9f737b036b4af85e399e4b9aef64 Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS 1.15.0-1 04/01/2014 RIP: 0010:assfail+0x46/0x4a [xfs] Code: a0 8f 41 a0 e8 45 fe ff ff 8a 1d 2c 36 10 00 80 fb 01 76 0f 0f b6 f3 48 c7 c7 c0 f0 4f a0 e8 10 f0 02 e1 80 e3 01 74 02 0f 0b <0f> 0b 5b c3 48 8d 45 10 48 89 e2 4c 89 e6 48 89 1c 24 48 89 44 24 RSP: 0018:ffffc900078c7b30 EFLAGS: 00010246 RAX: 0000000000000000 RBX: ffff8880099ac000 RCX: 000000007fffffff RDX: 0000000000000000 RSI: 0000000000000000 RDI: ffffffffa0418fa0 RBP: ffff8880197bc1c0 R08: 0000000000000000 R09: 000000000000000a R10: 000000000000000a R11: f000000000000000 R12: ffffc900078c7d20 R13: 00000000fffffff5 R14: ffffc900078c7d20 R15: 0000000000000000 FS: 00007f0449903800(0000) GS:ffff88803ec00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00005610ada631f0 CR3: 0000000014dd8002 CR4: 00000000001706f0 Call Trace: xfs_buf_delwri_pushbuf+0x150/0x160 [xfs 4561f5b32c9bfb874ec98d58d0719464e1f87368] xfs_qm_flush_one+0xd6/0x130 [xfs 4561f5b32c9bfb874ec98d58d0719464e1f87368] xfs_qm_dquot_walk.isra.0+0x109/0x1e0 [xfs 4561f5b32c9bfb874ec98d58d0719464e1f87368] xfs_qm_quotacheck+0x319/0x490 [xfs 4561f5b32c9bfb874ec98d58d0719464e1f87368] xfs_qm_mount_quotas+0x65/0x2c0 [xfs 4561f5b32c9bfb874ec98d58d0719464e1f87368] xfs_mountfs+0x6b5/0xab0 [xfs 4561f5b32c9bfb874ec98d58d0719464e1f87368] xfs_fs_fill_super+0x781/0x990 [xfs 4561f5b32c9bfb874ec98d58d0719464e1f87368] get_tree_bdev+0x175/0x280 vfs_get_tree+0x1a/0x80 path_mount+0x6f5/0xaa0 __x64_sys_mount+0x103/0x140 do_syscall_64+0x2b/0x80 entry_SYSCALL_64_after_hwframe+0x46/0xb0 I /think/ this can happen if xfs_qm_flush_one is racing with xfs_qm_dquot_isolate (i.e. dquot reclaim) when the second function has taken the dquot flush lock but xfs_qm_dqflush hasn't yet locked the dquot buffer, let alone queued it to the delwri list. In this case, flush_one will fail to get the dquot flush lock, but it can lock the incore buffer, but xfs_buf_delwri_pushbuf will then trip over this ASSERT, which checks that the buffer isn't on a delwri list. The hang results because the _delwri_submit_buffers ignores non DELWRI_Q buffers, which means that xfs_buf_iowait waits forever for an IO that has not yet been scheduled. AFAICT, a reasonable solution here is to detect a dquot buffer that is not on a DELWRI list, drop it, and return -EAGAIN to try the flush again. It's not /that/ big of a deal if quotacheck writes the dquot buffer repeatedly before we even set QUOTA_CHKD. Signed-off-by: Darrick J. Wong Reviewed-by: Dave Chinner --- fs/xfs/xfs_qm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/fs/xfs/xfs_qm.c b/fs/xfs/xfs_qm.c index 57dd3b722265..95ea99070377 100644 --- a/fs/xfs/xfs_qm.c +++ b/fs/xfs/xfs_qm.c @@ -1234,6 +1234,11 @@ xfs_qm_flush_one( if (error) goto out_unlock; + if (!(bp->b_flags & _XBF_DELWRI_Q)) { + error = -EAGAIN; + xfs_buf_relse(bp); + goto out_unlock; + } xfs_buf_unlock(bp); xfs_buf_delwri_pushbuf(bp, buffer_list); -- cgit v1.2.3 From d62113303d691bcd8d0675ae4ac63e7769afc56c Mon Sep 17 00:00:00 2001 From: Chandan Babu R Date: Thu, 4 Aug 2022 08:59:27 -0700 Subject: xfs: Fix false ENOSPC when performing direct write on a delalloc extent in cow fork On a higly fragmented filesystem a Direct IO write can fail with -ENOSPC error even though the filesystem has sufficient number of free blocks. This occurs if the file offset range on which the write operation is being performed has a delalloc extent in the cow fork and this delalloc extent begins much before the Direct IO range. In such a scenario, xfs_reflink_allocate_cow() invokes xfs_bmapi_write() to allocate the blocks mapped by the delalloc extent. The extent thus allocated may not cover the beginning of file offset range on which the Direct IO write was issued. Hence xfs_reflink_allocate_cow() ends up returning -ENOSPC. The following script reliably recreates the bug described above. #!/usr/bin/bash device=/dev/loop0 shortdev=$(basename $device) mntpnt=/mnt/ file1=${mntpnt}/file1 file2=${mntpnt}/file2 fragmentedfile=${mntpnt}/fragmentedfile punchprog=/root/repos/xfstests-dev/src/punch-alternating errortag=/sys/fs/xfs/${shortdev}/errortag/bmap_alloc_minlen_extent umount $device > /dev/null 2>&1 echo "Create FS" mkfs.xfs -f -m reflink=1 $device > /dev/null 2>&1 if [[ $? != 0 ]]; then echo "mkfs failed." exit 1 fi echo "Mount FS" mount $device $mntpnt > /dev/null 2>&1 if [[ $? != 0 ]]; then echo "mount failed." exit 1 fi echo "Create source file" xfs_io -f -c "pwrite 0 32M" $file1 > /dev/null 2>&1 sync echo "Create Reflinked file" xfs_io -f -c "reflink $file1" $file2 &>/dev/null echo "Set cowextsize" xfs_io -c "cowextsize 16M" $file1 > /dev/null 2>&1 echo "Fragment FS" xfs_io -f -c "pwrite 0 64M" $fragmentedfile > /dev/null 2>&1 sync $punchprog $fragmentedfile echo "Allocate block sized extent from now onwards" echo -n 1 > $errortag echo "Create 16MiB delalloc extent in CoW fork" xfs_io -c "pwrite 0 4k" $file1 > /dev/null 2>&1 sync echo "Direct I/O write at offset 12k" xfs_io -d -c "pwrite 12k 8k" $file1 This commit fixes the bug by invoking xfs_bmapi_write() in a loop until disk blocks are allocated for atleast the starting file offset of the Direct IO write range. Fixes: 3c68d44a2b49 ("xfs: allocate direct I/O COW blocks in iomap_begin") Reported-and-Root-caused-by: Wengang Wang Signed-off-by: Chandan Babu R Reviewed-by: Darrick J. Wong [djwong: slight editing to make the locking less grody, and fix some style things] Signed-off-by: Darrick J. Wong --- fs/xfs/xfs_reflink.c | 198 ++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 163 insertions(+), 35 deletions(-) diff --git a/fs/xfs/xfs_reflink.c b/fs/xfs/xfs_reflink.c index 724806c7ce3e..0a32b54456eb 100644 --- a/fs/xfs/xfs_reflink.c +++ b/fs/xfs/xfs_reflink.c @@ -341,9 +341,41 @@ xfs_find_trim_cow_extent( return 0; } -/* Allocate all CoW reservations covering a range of blocks in a file. */ -int -xfs_reflink_allocate_cow( +static int +xfs_reflink_convert_unwritten( + struct xfs_inode *ip, + struct xfs_bmbt_irec *imap, + struct xfs_bmbt_irec *cmap, + bool convert_now) +{ + xfs_fileoff_t offset_fsb = imap->br_startoff; + xfs_filblks_t count_fsb = imap->br_blockcount; + int error; + + /* + * cmap might larger than imap due to cowextsize hint. + */ + xfs_trim_extent(cmap, offset_fsb, count_fsb); + + /* + * COW fork extents are supposed to remain unwritten until we're ready + * to initiate a disk write. For direct I/O we are going to write the + * data and need the conversion, but for buffered writes we're done. + */ + if (!convert_now || cmap->br_state == XFS_EXT_NORM) + return 0; + + trace_xfs_reflink_convert_cow(ip, cmap); + + error = xfs_reflink_convert_cow_locked(ip, offset_fsb, count_fsb); + if (!error) + cmap->br_state = XFS_EXT_NORM; + + return error; +} + +static int +xfs_reflink_fill_cow_hole( struct xfs_inode *ip, struct xfs_bmbt_irec *imap, struct xfs_bmbt_irec *cmap, @@ -352,25 +384,12 @@ xfs_reflink_allocate_cow( bool convert_now) { struct xfs_mount *mp = ip->i_mount; - xfs_fileoff_t offset_fsb = imap->br_startoff; - xfs_filblks_t count_fsb = imap->br_blockcount; struct xfs_trans *tp; - int nimaps, error = 0; - bool found; xfs_filblks_t resaligned; - xfs_extlen_t resblks = 0; - - ASSERT(xfs_isilocked(ip, XFS_ILOCK_EXCL)); - if (!ip->i_cowfp) { - ASSERT(!xfs_is_reflink_inode(ip)); - xfs_ifork_init_cow(ip); - } - - error = xfs_find_trim_cow_extent(ip, imap, cmap, shared, &found); - if (error || !*shared) - return error; - if (found) - goto convert; + xfs_extlen_t resblks; + int nimaps; + int error; + bool found; resaligned = xfs_aligned_fsb_count(imap->br_startoff, imap->br_blockcount, xfs_get_cowextsz_hint(ip)); @@ -386,17 +405,17 @@ xfs_reflink_allocate_cow( *lockmode = XFS_ILOCK_EXCL; - /* - * Check for an overlapping extent again now that we dropped the ilock. - */ error = xfs_find_trim_cow_extent(ip, imap, cmap, shared, &found); if (error || !*shared) goto out_trans_cancel; + if (found) { xfs_trans_cancel(tp); goto convert; } + ASSERT(cmap->br_startoff > imap->br_startoff); + /* Allocate the entire reservation as unwritten blocks. */ nimaps = 1; error = xfs_bmapi_write(tp, ip, imap->br_startoff, imap->br_blockcount, @@ -416,26 +435,135 @@ xfs_reflink_allocate_cow( */ if (nimaps == 0) return -ENOSPC; + convert: - xfs_trim_extent(cmap, offset_fsb, count_fsb); - /* - * COW fork extents are supposed to remain unwritten until we're ready - * to initiate a disk write. For direct I/O we are going to write the - * data and need the conversion, but for buffered writes we're done. - */ - if (!convert_now || cmap->br_state == XFS_EXT_NORM) - return 0; - trace_xfs_reflink_convert_cow(ip, cmap); - error = xfs_reflink_convert_cow_locked(ip, offset_fsb, count_fsb); - if (!error) - cmap->br_state = XFS_EXT_NORM; + return xfs_reflink_convert_unwritten(ip, imap, cmap, convert_now); + +out_trans_cancel: + xfs_trans_cancel(tp); return error; +} + +static int +xfs_reflink_fill_delalloc( + struct xfs_inode *ip, + struct xfs_bmbt_irec *imap, + struct xfs_bmbt_irec *cmap, + bool *shared, + uint *lockmode, + bool convert_now) +{ + struct xfs_mount *mp = ip->i_mount; + struct xfs_trans *tp; + int nimaps; + int error; + bool found; + + do { + xfs_iunlock(ip, *lockmode); + *lockmode = 0; + + error = xfs_trans_alloc_inode(ip, &M_RES(mp)->tr_write, 0, 0, + false, &tp); + if (error) + return error; + + *lockmode = XFS_ILOCK_EXCL; + + error = xfs_find_trim_cow_extent(ip, imap, cmap, shared, + &found); + if (error || !*shared) + goto out_trans_cancel; + + if (found) { + xfs_trans_cancel(tp); + break; + } + + ASSERT(isnullstartblock(cmap->br_startblock) || + cmap->br_startblock == DELAYSTARTBLOCK); + + /* + * Replace delalloc reservation with an unwritten extent. + */ + nimaps = 1; + error = xfs_bmapi_write(tp, ip, cmap->br_startoff, + cmap->br_blockcount, + XFS_BMAPI_COWFORK | XFS_BMAPI_PREALLOC, 0, + cmap, &nimaps); + if (error) + goto out_trans_cancel; + + xfs_inode_set_cowblocks_tag(ip); + error = xfs_trans_commit(tp); + if (error) + return error; + + /* + * Allocation succeeded but the requested range was not even + * partially satisfied? Bail out! + */ + if (nimaps == 0) + return -ENOSPC; + } while (cmap->br_startoff + cmap->br_blockcount <= imap->br_startoff); + + return xfs_reflink_convert_unwritten(ip, imap, cmap, convert_now); out_trans_cancel: xfs_trans_cancel(tp); return error; } +/* Allocate all CoW reservations covering a range of blocks in a file. */ +int +xfs_reflink_allocate_cow( + struct xfs_inode *ip, + struct xfs_bmbt_irec *imap, + struct xfs_bmbt_irec *cmap, + bool *shared, + uint *lockmode, + bool convert_now) +{ + int error; + bool found; + + ASSERT(xfs_isilocked(ip, XFS_ILOCK_EXCL)); + if (!ip->i_cowfp) { + ASSERT(!xfs_is_reflink_inode(ip)); + xfs_ifork_init_cow(ip); + } + + error = xfs_find_trim_cow_extent(ip, imap, cmap, shared, &found); + if (error || !*shared) + return error; + + /* CoW fork has a real extent */ + if (found) + return xfs_reflink_convert_unwritten(ip, imap, cmap, + convert_now); + + /* + * CoW fork does not have an extent and data extent is shared. + * Allocate a real extent in the CoW fork. + */ + if (cmap->br_startoff > imap->br_startoff) + return xfs_reflink_fill_cow_hole(ip, imap, cmap, shared, + lockmode, convert_now); + + /* + * CoW fork has a delalloc reservation. Replace it with a real extent. + * There may or may not be a data fork mapping. + */ + if (isnullstartblock(cmap->br_startblock) || + cmap->br_startblock == DELAYSTARTBLOCK) + return xfs_reflink_fill_delalloc(ip, imap, cmap, shared, + lockmode, convert_now); + + /* Shouldn't get here. */ + ASSERT(0); + return -EFSCORRUPTED; +} + /* * Cancel CoW reservations for some block range of an inode. * -- cgit v1.2.3 From 221f9d9cdf429df8c3843b4291f4f412fde11543 Mon Sep 17 00:00:00 2001 From: Jiri Slaby Date: Tue, 19 Jul 2022 10:56:20 +0200 Subject: posix-timers: Make do_clock_gettime() static MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit do_clock_gettime() is used only in posix-stubs.c, so make it static. It avoids a compiler warning too: time/posix-stubs.c:73:5: warning: no previous prototype for ‘do_clock_gettime’ [-Wmissing-prototypes] Signed-off-by: Jiri Slaby Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20220719085620.30567-1-jslaby@suse.cz --- kernel/time/posix-stubs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/kernel/time/posix-stubs.c b/kernel/time/posix-stubs.c index fcb3b21d8bdc..90ea5f373e50 100644 --- a/kernel/time/posix-stubs.c +++ b/kernel/time/posix-stubs.c @@ -70,7 +70,7 @@ SYSCALL_DEFINE2(clock_settime, const clockid_t, which_clock, return do_sys_settimeofday64(&new_tp, NULL); } -int do_clock_gettime(clockid_t which_clock, struct timespec64 *tp) +static int do_clock_gettime(clockid_t which_clock, struct timespec64 *tp) { switch (which_clock) { case CLOCK_REALTIME: @@ -90,6 +90,7 @@ int do_clock_gettime(clockid_t which_clock, struct timespec64 *tp) return 0; } + SYSCALL_DEFINE2(clock_gettime, const clockid_t, which_clock, struct __kernel_timespec __user *, tp) { -- cgit v1.2.3 From f83bb2592482fe94c6eea07a8121763c80f36ce5 Mon Sep 17 00:00:00 2001 From: Meng Tang Date: Mon, 8 Aug 2022 15:34:06 +0800 Subject: ALSA: hda/conexant: Add quirk for LENOVO 20149 Notebook model There is another LENOVO 20149 (Type1Sku0) Notebook model with CX20590, the device PCI SSID is 17aa:3977, which headphones are not responding, that requires the quirk CXT_PINCFG_LENOVO_NOTEBOOK. Add the corresponding entry to the quirk table. Signed-off-by: Meng Tang Cc: Link: https://lore.kernel.org/r/20220808073406.19460-1-tangmeng@uniontech.com Signed-off-by: Takashi Iwai --- sound/pci/hda/patch_conexant.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/sound/pci/hda/patch_conexant.c b/sound/pci/hda/patch_conexant.c index 83ae21a01bbf..7b1a30a551f6 100644 --- a/sound/pci/hda/patch_conexant.c +++ b/sound/pci/hda/patch_conexant.c @@ -222,6 +222,7 @@ enum { CXT_PINCFG_LEMOTE_A1205, CXT_PINCFG_COMPAQ_CQ60, CXT_FIXUP_STEREO_DMIC, + CXT_PINCFG_LENOVO_NOTEBOOK, CXT_FIXUP_INC_MIC_BOOST, CXT_FIXUP_HEADPHONE_MIC_PIN, CXT_FIXUP_HEADPHONE_MIC, @@ -772,6 +773,14 @@ static const struct hda_fixup cxt_fixups[] = { .type = HDA_FIXUP_FUNC, .v.func = cxt_fixup_stereo_dmic, }, + [CXT_PINCFG_LENOVO_NOTEBOOK] = { + .type = HDA_FIXUP_PINS, + .v.pins = (const struct hda_pintbl[]) { + { 0x1a, 0x05d71030 }, + { } + }, + .chain_id = CXT_FIXUP_STEREO_DMIC, + }, [CXT_FIXUP_INC_MIC_BOOST] = { .type = HDA_FIXUP_FUNC, .v.func = cxt5066_increase_mic_boost, @@ -971,7 +980,7 @@ static const struct snd_pci_quirk cxt5066_fixups[] = { SND_PCI_QUIRK(0x17aa, 0x3905, "Lenovo G50-30", CXT_FIXUP_STEREO_DMIC), SND_PCI_QUIRK(0x17aa, 0x390b, "Lenovo G50-80", CXT_FIXUP_STEREO_DMIC), SND_PCI_QUIRK(0x17aa, 0x3975, "Lenovo U300s", CXT_FIXUP_STEREO_DMIC), - SND_PCI_QUIRK(0x17aa, 0x3977, "Lenovo IdeaPad U310", CXT_FIXUP_STEREO_DMIC), + SND_PCI_QUIRK(0x17aa, 0x3977, "Lenovo IdeaPad U310", CXT_PINCFG_LENOVO_NOTEBOOK), SND_PCI_QUIRK(0x17aa, 0x3978, "Lenovo G50-70", CXT_FIXUP_STEREO_DMIC), SND_PCI_QUIRK(0x17aa, 0x397b, "Lenovo S205", CXT_FIXUP_STEREO_DMIC), SND_PCI_QUIRK_VENDOR(0x17aa, "Thinkpad", CXT_FIXUP_THINKPAD_ACPI), -- cgit v1.2.3 From e6cfcdda8cbe81eaf821c897369a65fec987b404 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 8 Aug 2022 09:32:33 -0500 Subject: x86/bugs: Enable STIBP for IBPB mitigated RETBleed AMD's "Technical Guidance for Mitigating Branch Type Confusion, Rev. 1.0 2022-07-12" whitepaper, under section 6.1.2 "IBPB On Privileged Mode Entry / SMT Safety" says: Similar to the Jmp2Ret mitigation, if the code on the sibling thread cannot be trusted, software should set STIBP to 1 or disable SMT to ensure SMT safety when using this mitigation. So, like already being done for retbleed=unret, and now also for retbleed=ibpb, force STIBP on machines that have it, and report its SMT vulnerability status accordingly. [ bp: Remove the "we" and remove "[AMD]" applicability parameter which doesn't work here. ] Fixes: 3ebc17006888 ("x86/bugs: Add retbleed=ibpb") Signed-off-by: Kim Phillips Signed-off-by: Borislav Petkov Cc: stable@vger.kernel.org # 5.10, 5.15, 5.19 Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Link: https://lore.kernel.org/r/20220804192201.439596-1-kim.phillips@amd.com --- Documentation/admin-guide/kernel-parameters.txt | 29 ++++++++++++++++++------- arch/x86/kernel/cpu/bugs.c | 10 +++++---- 2 files changed, 27 insertions(+), 12 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 5e9147fe8968..523b19624026 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5209,20 +5209,33 @@ Speculative Code Execution with Return Instructions) vulnerability. + AMD-based UNRET and IBPB mitigations alone do not stop + sibling threads from influencing the predictions of other + sibling threads. For that reason, STIBP is used on pro- + cessors that support it, and mitigate SMT on processors + that don't. + off - no mitigation auto - automatically select a migitation auto,nosmt - automatically select a mitigation, disabling SMT if necessary for the full mitigation (only on Zen1 and older without STIBP). - ibpb - mitigate short speculation windows on - basic block boundaries too. Safe, highest - perf impact. - unret - force enable untrained return thunks, - only effective on AMD f15h-f17h - based systems. - unret,nosmt - like unret, will disable SMT when STIBP - is not available. + ibpb - On AMD, mitigate short speculation + windows on basic block boundaries too. + Safe, highest perf impact. It also + enables STIBP if present. Not suitable + on Intel. + ibpb,nosmt - Like "ibpb" above but will disable SMT + when STIBP is not available. This is + the alternative for systems which do not + have STIBP. + unret - Force enable untrained return thunks, + only effective on AMD f15h-f17h based + systems. + unret,nosmt - Like unret, but will disable SMT when STIBP + is not available. This is the alternative for + systems which do not have STIBP. Selecting 'auto' will choose a mitigation method at run time according to the CPU. diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 6761668100b9..d50686ca5870 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -152,7 +152,7 @@ void __init check_bugs(void) /* * spectre_v2_user_select_mitigation() relies on the state set by * retbleed_select_mitigation(); specifically the STIBP selection is - * forced for UNRET. + * forced for UNRET or IBPB. */ spectre_v2_user_select_mitigation(); ssb_select_mitigation(); @@ -1179,7 +1179,8 @@ spectre_v2_user_select_mitigation(void) boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON)) mode = SPECTRE_V2_USER_STRICT_PREFERRED; - if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET) { + if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET || + retbleed_mitigation == RETBLEED_MITIGATION_IBPB) { if (mode != SPECTRE_V2_USER_STRICT && mode != SPECTRE_V2_USER_STRICT_PREFERRED) pr_info("Selecting STIBP always-on mode to complement retbleed mitigation\n"); @@ -2320,10 +2321,11 @@ static ssize_t srbds_show_state(char *buf) static ssize_t retbleed_show_state(char *buf) { - if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET) { + if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET || + retbleed_mitigation == RETBLEED_MITIGATION_IBPB) { if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD && boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) - return sprintf(buf, "Vulnerable: untrained return thunk on non-Zen uarch\n"); + return sprintf(buf, "Vulnerable: untrained return thunk / IBPB on non-AMD based uarch\n"); return sprintf(buf, "%s; SMT %s\n", retbleed_strings[retbleed_mitigation], -- cgit v1.2.3 From c9a1dd673f28da9624776e75b78ae04125544852 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 27 Jul 2022 12:00:18 +0200 Subject: rtc: zynqmp: initialize fract_tick fract_tick is used uninitialized when fract_offset is 0 Reported-by: kernel test robot Signed-off-by: Alexandre Belloni Reviewed-by: Nathan Chancellor Reviewed-by: Michal Simek Link: https://lore.kernel.org/r/20220727100018.3301470-1-alexandre.belloni@bootlin.com --- drivers/rtc/rtc-zynqmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/rtc/rtc-zynqmp.c b/drivers/rtc/rtc-zynqmp.c index 1dd389b891fe..c9b85c838ebe 100644 --- a/drivers/rtc/rtc-zynqmp.c +++ b/drivers/rtc/rtc-zynqmp.c @@ -203,7 +203,7 @@ static int xlnx_rtc_set_offset(struct device *dev, long offset) struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); unsigned long long rtc_ppb = RTC_PPB; unsigned int tick_mult = do_div(rtc_ppb, xrtcdev->freq); - unsigned char fract_tick; + unsigned char fract_tick = 0; unsigned int calibval; short int max_tick; int fract_offset; -- cgit v1.2.3 From 6492fed7d8c95f53b0b804ef541324d924d95d41 Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Mon, 8 Aug 2022 20:23:59 +0200 Subject: rtc: rtc-cmos: Do not check ACPI_FADT_LOW_POWER_S0 The ACPI_FADT_LOW_POWER_S0 flag merely means that it is better to use low-power S0 idle on the given platform than S3 (provided that the latter is supported) and it doesn't preclude using either of them (which of them will be used depends on the choices made by user space). For this reason, there is no benefit from checking that flag in use_acpi_alarm_quirks(). First off, it cannot be a bug to do S3 with use_acpi_alarm set, because S3 can be used on systems with ACPI_FADT_LOW_POWER_S0 and it must work if really supported, so the ACPI_FADT_LOW_POWER_S0 check is not needed to protect the S3-capable systems from failing. Second, suspend-to-idle can be carried out on a system with ACPI_FADT_LOW_POWER_S0 unset and it is expected to work, so if setting use_acpi_alarm is needed to handle that case correctly, it should be set regardless of the ACPI_FADT_LOW_POWER_S0 value. Accordingly, drop the ACPI_FADT_LOW_POWER_S0 check from use_acpi_alarm_quirks(). Signed-off-by: Rafael J. Wysocki Reviewed-by: Mario Limonciello Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/12054246.O9o76ZdvQC@kreacher --- drivers/rtc/rtc-cmos.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c index 7c006c2b125f..bdb1df843c78 100644 --- a/drivers/rtc/rtc-cmos.c +++ b/drivers/rtc/rtc-cmos.c @@ -1260,9 +1260,6 @@ static void use_acpi_alarm_quirks(void) if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) return; - if (!(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) - return; - if (!is_hpet_enabled()) return; -- cgit v1.2.3 From 0f3e72b5c8cfa0b57dc4fc7703a0a42dbc200ba9 Mon Sep 17 00:00:00 2001 From: Jason Gunthorpe Date: Sun, 31 Jul 2022 15:54:56 +0300 Subject: vfio: Move vfio.c to vfio_main.c If a source file has the same name as a module then kbuild only supports a single source file in the module. Rename vfio.c to vfio_main.c so that we can have more that one .c file in vfio.ko. Signed-off-by: Jason Gunthorpe Signed-off-by: Yishai Hadas Link: https://lore.kernel.org/r/20220731125503.142683-5-yishaih@nvidia.com Signed-off-by: Alex Williamson --- drivers/vfio/Makefile | 2 + drivers/vfio/vfio.c | 2135 ---------------------------------------------- drivers/vfio/vfio_main.c | 2135 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 2137 insertions(+), 2135 deletions(-) delete mode 100644 drivers/vfio/vfio.c create mode 100644 drivers/vfio/vfio_main.c diff --git a/drivers/vfio/Makefile b/drivers/vfio/Makefile index fee73f3d9480..1a32357592e3 100644 --- a/drivers/vfio/Makefile +++ b/drivers/vfio/Makefile @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 vfio_virqfd-y := virqfd.o +vfio-y += vfio_main.o + obj-$(CONFIG_VFIO) += vfio.o obj-$(CONFIG_VFIO_VIRQFD) += vfio_virqfd.o obj-$(CONFIG_VFIO_IOMMU_TYPE1) += vfio_iommu_type1.o diff --git a/drivers/vfio/vfio.c b/drivers/vfio/vfio.c deleted file mode 100644 index 7cb56c382c97..000000000000 --- a/drivers/vfio/vfio.c +++ /dev/null @@ -1,2135 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * VFIO core - * - * Copyright (C) 2012 Red Hat, Inc. All rights reserved. - * Author: Alex Williamson - * - * Derived from original vfio: - * Copyright 2010 Cisco Systems, Inc. All rights reserved. - * Author: Tom Lyon, pugs@cisco.com - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "vfio.h" - -#define DRIVER_VERSION "0.3" -#define DRIVER_AUTHOR "Alex Williamson " -#define DRIVER_DESC "VFIO - User Level meta-driver" - -static struct vfio { - struct class *class; - struct list_head iommu_drivers_list; - struct mutex iommu_drivers_lock; - struct list_head group_list; - struct mutex group_lock; /* locks group_list */ - struct ida group_ida; - dev_t group_devt; -} vfio; - -struct vfio_iommu_driver { - const struct vfio_iommu_driver_ops *ops; - struct list_head vfio_next; -}; - -struct vfio_container { - struct kref kref; - struct list_head group_list; - struct rw_semaphore group_lock; - struct vfio_iommu_driver *iommu_driver; - void *iommu_data; - bool noiommu; -}; - -struct vfio_group { - struct device dev; - struct cdev cdev; - refcount_t users; - unsigned int container_users; - struct iommu_group *iommu_group; - struct vfio_container *container; - struct list_head device_list; - struct mutex device_lock; - struct list_head vfio_next; - struct list_head container_next; - enum vfio_group_type type; - unsigned int dev_counter; - struct rw_semaphore group_rwsem; - struct kvm *kvm; - struct file *opened_file; - struct blocking_notifier_head notifier; -}; - -#ifdef CONFIG_VFIO_NOIOMMU -static bool noiommu __read_mostly; -module_param_named(enable_unsafe_noiommu_mode, - noiommu, bool, S_IRUGO | S_IWUSR); -MODULE_PARM_DESC(enable_unsafe_noiommu_mode, "Enable UNSAFE, no-IOMMU mode. This mode provides no device isolation, no DMA translation, no host kernel protection, cannot be used for device assignment to virtual machines, requires RAWIO permissions, and will taint the kernel. If you do not know what this is for, step away. (default: false)"); -#endif - -static DEFINE_XARRAY(vfio_device_set_xa); -static const struct file_operations vfio_group_fops; - -int vfio_assign_device_set(struct vfio_device *device, void *set_id) -{ - unsigned long idx = (unsigned long)set_id; - struct vfio_device_set *new_dev_set; - struct vfio_device_set *dev_set; - - if (WARN_ON(!set_id)) - return -EINVAL; - - /* - * Atomically acquire a singleton object in the xarray for this set_id - */ - xa_lock(&vfio_device_set_xa); - dev_set = xa_load(&vfio_device_set_xa, idx); - if (dev_set) - goto found_get_ref; - xa_unlock(&vfio_device_set_xa); - - new_dev_set = kzalloc(sizeof(*new_dev_set), GFP_KERNEL); - if (!new_dev_set) - return -ENOMEM; - mutex_init(&new_dev_set->lock); - INIT_LIST_HEAD(&new_dev_set->device_list); - new_dev_set->set_id = set_id; - - xa_lock(&vfio_device_set_xa); - dev_set = __xa_cmpxchg(&vfio_device_set_xa, idx, NULL, new_dev_set, - GFP_KERNEL); - if (!dev_set) { - dev_set = new_dev_set; - goto found_get_ref; - } - - kfree(new_dev_set); - if (xa_is_err(dev_set)) { - xa_unlock(&vfio_device_set_xa); - return xa_err(dev_set); - } - -found_get_ref: - dev_set->device_count++; - xa_unlock(&vfio_device_set_xa); - mutex_lock(&dev_set->lock); - device->dev_set = dev_set; - list_add_tail(&device->dev_set_list, &dev_set->device_list); - mutex_unlock(&dev_set->lock); - return 0; -} -EXPORT_SYMBOL_GPL(vfio_assign_device_set); - -static void vfio_release_device_set(struct vfio_device *device) -{ - struct vfio_device_set *dev_set = device->dev_set; - - if (!dev_set) - return; - - mutex_lock(&dev_set->lock); - list_del(&device->dev_set_list); - mutex_unlock(&dev_set->lock); - - xa_lock(&vfio_device_set_xa); - if (!--dev_set->device_count) { - __xa_erase(&vfio_device_set_xa, - (unsigned long)dev_set->set_id); - mutex_destroy(&dev_set->lock); - kfree(dev_set); - } - xa_unlock(&vfio_device_set_xa); -} - -#ifdef CONFIG_VFIO_NOIOMMU -static void *vfio_noiommu_open(unsigned long arg) -{ - if (arg != VFIO_NOIOMMU_IOMMU) - return ERR_PTR(-EINVAL); - if (!capable(CAP_SYS_RAWIO)) - return ERR_PTR(-EPERM); - - return NULL; -} - -static void vfio_noiommu_release(void *iommu_data) -{ -} - -static long vfio_noiommu_ioctl(void *iommu_data, - unsigned int cmd, unsigned long arg) -{ - if (cmd == VFIO_CHECK_EXTENSION) - return noiommu && (arg == VFIO_NOIOMMU_IOMMU) ? 1 : 0; - - return -ENOTTY; -} - -static int vfio_noiommu_attach_group(void *iommu_data, - struct iommu_group *iommu_group, enum vfio_group_type type) -{ - return 0; -} - -static void vfio_noiommu_detach_group(void *iommu_data, - struct iommu_group *iommu_group) -{ -} - -static const struct vfio_iommu_driver_ops vfio_noiommu_ops = { - .name = "vfio-noiommu", - .owner = THIS_MODULE, - .open = vfio_noiommu_open, - .release = vfio_noiommu_release, - .ioctl = vfio_noiommu_ioctl, - .attach_group = vfio_noiommu_attach_group, - .detach_group = vfio_noiommu_detach_group, -}; - -/* - * Only noiommu containers can use vfio-noiommu and noiommu containers can only - * use vfio-noiommu. - */ -static inline bool vfio_iommu_driver_allowed(struct vfio_container *container, - const struct vfio_iommu_driver *driver) -{ - return container->noiommu == (driver->ops == &vfio_noiommu_ops); -} -#else -static inline bool vfio_iommu_driver_allowed(struct vfio_container *container, - const struct vfio_iommu_driver *driver) -{ - return true; -} -#endif /* CONFIG_VFIO_NOIOMMU */ - -/* - * IOMMU driver registration - */ -int vfio_register_iommu_driver(const struct vfio_iommu_driver_ops *ops) -{ - struct vfio_iommu_driver *driver, *tmp; - - if (WARN_ON(!ops->register_device != !ops->unregister_device)) - return -EINVAL; - - driver = kzalloc(sizeof(*driver), GFP_KERNEL); - if (!driver) - return -ENOMEM; - - driver->ops = ops; - - mutex_lock(&vfio.iommu_drivers_lock); - - /* Check for duplicates */ - list_for_each_entry(tmp, &vfio.iommu_drivers_list, vfio_next) { - if (tmp->ops == ops) { - mutex_unlock(&vfio.iommu_drivers_lock); - kfree(driver); - return -EINVAL; - } - } - - list_add(&driver->vfio_next, &vfio.iommu_drivers_list); - - mutex_unlock(&vfio.iommu_drivers_lock); - - return 0; -} -EXPORT_SYMBOL_GPL(vfio_register_iommu_driver); - -void vfio_unregister_iommu_driver(const struct vfio_iommu_driver_ops *ops) -{ - struct vfio_iommu_driver *driver; - - mutex_lock(&vfio.iommu_drivers_lock); - list_for_each_entry(driver, &vfio.iommu_drivers_list, vfio_next) { - if (driver->ops == ops) { - list_del(&driver->vfio_next); - mutex_unlock(&vfio.iommu_drivers_lock); - kfree(driver); - return; - } - } - mutex_unlock(&vfio.iommu_drivers_lock); -} -EXPORT_SYMBOL_GPL(vfio_unregister_iommu_driver); - -static void vfio_group_get(struct vfio_group *group); - -/* - * Container objects - containers are created when /dev/vfio/vfio is - * opened, but their lifecycle extends until the last user is done, so - * it's freed via kref. Must support container/group/device being - * closed in any order. - */ -static void vfio_container_get(struct vfio_container *container) -{ - kref_get(&container->kref); -} - -static void vfio_container_release(struct kref *kref) -{ - struct vfio_container *container; - container = container_of(kref, struct vfio_container, kref); - - kfree(container); -} - -static void vfio_container_put(struct vfio_container *container) -{ - kref_put(&container->kref, vfio_container_release); -} - -/* - * Group objects - create, release, get, put, search - */ -static struct vfio_group * -__vfio_group_get_from_iommu(struct iommu_group *iommu_group) -{ - struct vfio_group *group; - - list_for_each_entry(group, &vfio.group_list, vfio_next) { - if (group->iommu_group == iommu_group) { - vfio_group_get(group); - return group; - } - } - return NULL; -} - -static struct vfio_group * -vfio_group_get_from_iommu(struct iommu_group *iommu_group) -{ - struct vfio_group *group; - - mutex_lock(&vfio.group_lock); - group = __vfio_group_get_from_iommu(iommu_group); - mutex_unlock(&vfio.group_lock); - return group; -} - -static void vfio_group_release(struct device *dev) -{ - struct vfio_group *group = container_of(dev, struct vfio_group, dev); - - mutex_destroy(&group->device_lock); - iommu_group_put(group->iommu_group); - ida_free(&vfio.group_ida, MINOR(group->dev.devt)); - kfree(group); -} - -static struct vfio_group *vfio_group_alloc(struct iommu_group *iommu_group, - enum vfio_group_type type) -{ - struct vfio_group *group; - int minor; - - group = kzalloc(sizeof(*group), GFP_KERNEL); - if (!group) - return ERR_PTR(-ENOMEM); - - minor = ida_alloc_max(&vfio.group_ida, MINORMASK, GFP_KERNEL); - if (minor < 0) { - kfree(group); - return ERR_PTR(minor); - } - - device_initialize(&group->dev); - group->dev.devt = MKDEV(MAJOR(vfio.group_devt), minor); - group->dev.class = vfio.class; - group->dev.release = vfio_group_release; - cdev_init(&group->cdev, &vfio_group_fops); - group->cdev.owner = THIS_MODULE; - - refcount_set(&group->users, 1); - init_rwsem(&group->group_rwsem); - INIT_LIST_HEAD(&group->device_list); - mutex_init(&group->device_lock); - group->iommu_group = iommu_group; - /* put in vfio_group_release() */ - iommu_group_ref_get(iommu_group); - group->type = type; - BLOCKING_INIT_NOTIFIER_HEAD(&group->notifier); - - return group; -} - -static struct vfio_group *vfio_create_group(struct iommu_group *iommu_group, - enum vfio_group_type type) -{ - struct vfio_group *group; - struct vfio_group *ret; - int err; - - group = vfio_group_alloc(iommu_group, type); - if (IS_ERR(group)) - return group; - - err = dev_set_name(&group->dev, "%s%d", - group->type == VFIO_NO_IOMMU ? "noiommu-" : "", - iommu_group_id(iommu_group)); - if (err) { - ret = ERR_PTR(err); - goto err_put; - } - - mutex_lock(&vfio.group_lock); - - /* Did we race creating this group? */ - ret = __vfio_group_get_from_iommu(iommu_group); - if (ret) - goto err_unlock; - - err = cdev_device_add(&group->cdev, &group->dev); - if (err) { - ret = ERR_PTR(err); - goto err_unlock; - } - - list_add(&group->vfio_next, &vfio.group_list); - - mutex_unlock(&vfio.group_lock); - return group; - -err_unlock: - mutex_unlock(&vfio.group_lock); -err_put: - put_device(&group->dev); - return ret; -} - -static void vfio_group_put(struct vfio_group *group) -{ - if (!refcount_dec_and_mutex_lock(&group->users, &vfio.group_lock)) - return; - - /* - * These data structures all have paired operations that can only be - * undone when the caller holds a live reference on the group. Since all - * pairs must be undone these WARN_ON's indicate some caller did not - * properly hold the group reference. - */ - WARN_ON(!list_empty(&group->device_list)); - WARN_ON(group->container || group->container_users); - WARN_ON(group->notifier.head); - - list_del(&group->vfio_next); - cdev_device_del(&group->cdev, &group->dev); - mutex_unlock(&vfio.group_lock); - - put_device(&group->dev); -} - -static void vfio_group_get(struct vfio_group *group) -{ - refcount_inc(&group->users); -} - -/* - * Device objects - create, release, get, put, search - */ -/* Device reference always implies a group reference */ -static void vfio_device_put(struct vfio_device *device) -{ - if (refcount_dec_and_test(&device->refcount)) - complete(&device->comp); -} - -static bool vfio_device_try_get(struct vfio_device *device) -{ - return refcount_inc_not_zero(&device->refcount); -} - -static struct vfio_device *vfio_group_get_device(struct vfio_group *group, - struct device *dev) -{ - struct vfio_device *device; - - mutex_lock(&group->device_lock); - list_for_each_entry(device, &group->device_list, group_next) { - if (device->dev == dev && vfio_device_try_get(device)) { - mutex_unlock(&group->device_lock); - return device; - } - } - mutex_unlock(&group->device_lock); - return NULL; -} - -/* - * VFIO driver API - */ -void vfio_init_group_dev(struct vfio_device *device, struct device *dev, - const struct vfio_device_ops *ops) -{ - init_completion(&device->comp); - device->dev = dev; - device->ops = ops; -} -EXPORT_SYMBOL_GPL(vfio_init_group_dev); - -void vfio_uninit_group_dev(struct vfio_device *device) -{ - vfio_release_device_set(device); -} -EXPORT_SYMBOL_GPL(vfio_uninit_group_dev); - -static struct vfio_group *vfio_noiommu_group_alloc(struct device *dev, - enum vfio_group_type type) -{ - struct iommu_group *iommu_group; - struct vfio_group *group; - int ret; - - iommu_group = iommu_group_alloc(); - if (IS_ERR(iommu_group)) - return ERR_CAST(iommu_group); - - ret = iommu_group_set_name(iommu_group, "vfio-noiommu"); - if (ret) - goto out_put_group; - ret = iommu_group_add_device(iommu_group, dev); - if (ret) - goto out_put_group; - - group = vfio_create_group(iommu_group, type); - if (IS_ERR(group)) { - ret = PTR_ERR(group); - goto out_remove_device; - } - iommu_group_put(iommu_group); - return group; - -out_remove_device: - iommu_group_remove_device(dev); -out_put_group: - iommu_group_put(iommu_group); - return ERR_PTR(ret); -} - -static struct vfio_group *vfio_group_find_or_alloc(struct device *dev) -{ - struct iommu_group *iommu_group; - struct vfio_group *group; - - iommu_group = iommu_group_get(dev); -#ifdef CONFIG_VFIO_NOIOMMU - if (!iommu_group && noiommu) { - /* - * With noiommu enabled, create an IOMMU group for devices that - * don't already have one, implying no IOMMU hardware/driver - * exists. Taint the kernel because we're about to give a DMA - * capable device to a user without IOMMU protection. - */ - group = vfio_noiommu_group_alloc(dev, VFIO_NO_IOMMU); - if (!IS_ERR(group)) { - add_taint(TAINT_USER, LOCKDEP_STILL_OK); - dev_warn(dev, "Adding kernel taint for vfio-noiommu group on device\n"); - } - return group; - } -#endif - if (!iommu_group) - return ERR_PTR(-EINVAL); - - /* - * VFIO always sets IOMMU_CACHE because we offer no way for userspace to - * restore cache coherency. It has to be checked here because it is only - * valid for cases where we are using iommu groups. - */ - if (!device_iommu_capable(dev, IOMMU_CAP_CACHE_COHERENCY)) { - iommu_group_put(iommu_group); - return ERR_PTR(-EINVAL); - } - - group = vfio_group_get_from_iommu(iommu_group); - if (!group) - group = vfio_create_group(iommu_group, VFIO_IOMMU); - - /* The vfio_group holds a reference to the iommu_group */ - iommu_group_put(iommu_group); - return group; -} - -static int __vfio_register_dev(struct vfio_device *device, - struct vfio_group *group) -{ - struct vfio_device *existing_device; - - if (IS_ERR(group)) - return PTR_ERR(group); - - /* - * If the driver doesn't specify a set then the device is added to a - * singleton set just for itself. - */ - if (!device->dev_set) - vfio_assign_device_set(device, device); - - existing_device = vfio_group_get_device(group, device->dev); - if (existing_device) { - dev_WARN(device->dev, "Device already exists on group %d\n", - iommu_group_id(group->iommu_group)); - vfio_device_put(existing_device); - if (group->type == VFIO_NO_IOMMU || - group->type == VFIO_EMULATED_IOMMU) - iommu_group_remove_device(device->dev); - vfio_group_put(group); - return -EBUSY; - } - - /* Our reference on group is moved to the device */ - device->group = group; - - /* Refcounting can't start until the driver calls register */ - refcount_set(&device->refcount, 1); - - mutex_lock(&group->device_lock); - list_add(&device->group_next, &group->device_list); - group->dev_counter++; - mutex_unlock(&group->device_lock); - - return 0; -} - -int vfio_register_group_dev(struct vfio_device *device) -{ - return __vfio_register_dev(device, - vfio_group_find_or_alloc(device->dev)); -} -EXPORT_SYMBOL_GPL(vfio_register_group_dev); - -/* - * Register a virtual device without IOMMU backing. The user of this - * device must not be able to directly trigger unmediated DMA. - */ -int vfio_register_emulated_iommu_dev(struct vfio_device *device) -{ - return __vfio_register_dev(device, - vfio_noiommu_group_alloc(device->dev, VFIO_EMULATED_IOMMU)); -} -EXPORT_SYMBOL_GPL(vfio_register_emulated_iommu_dev); - -static struct vfio_device *vfio_device_get_from_name(struct vfio_group *group, - char *buf) -{ - struct vfio_device *it, *device = ERR_PTR(-ENODEV); - - mutex_lock(&group->device_lock); - list_for_each_entry(it, &group->device_list, group_next) { - int ret; - - if (it->ops->match) { - ret = it->ops->match(it, buf); - if (ret < 0) { - device = ERR_PTR(ret); - break; - } - } else { - ret = !strcmp(dev_name(it->dev), buf); - } - - if (ret && vfio_device_try_get(it)) { - device = it; - break; - } - } - mutex_unlock(&group->device_lock); - - return device; -} - -/* - * Decrement the device reference count and wait for the device to be - * removed. Open file descriptors for the device... */ -void vfio_unregister_group_dev(struct vfio_device *device) -{ - struct vfio_group *group = device->group; - unsigned int i = 0; - bool interrupted = false; - long rc; - - vfio_device_put(device); - rc = try_wait_for_completion(&device->comp); - while (rc <= 0) { - if (device->ops->request) - device->ops->request(device, i++); - - if (interrupted) { - rc = wait_for_completion_timeout(&device->comp, - HZ * 10); - } else { - rc = wait_for_completion_interruptible_timeout( - &device->comp, HZ * 10); - if (rc < 0) { - interrupted = true; - dev_warn(device->dev, - "Device is currently in use, task" - " \"%s\" (%d) " - "blocked until device is released", - current->comm, task_pid_nr(current)); - } - } - } - - mutex_lock(&group->device_lock); - list_del(&device->group_next); - group->dev_counter--; - mutex_unlock(&group->device_lock); - - if (group->type == VFIO_NO_IOMMU || group->type == VFIO_EMULATED_IOMMU) - iommu_group_remove_device(device->dev); - - /* Matches the get in vfio_register_group_dev() */ - vfio_group_put(group); -} -EXPORT_SYMBOL_GPL(vfio_unregister_group_dev); - -/* - * VFIO base fd, /dev/vfio/vfio - */ -static long vfio_ioctl_check_extension(struct vfio_container *container, - unsigned long arg) -{ - struct vfio_iommu_driver *driver; - long ret = 0; - - down_read(&container->group_lock); - - driver = container->iommu_driver; - - switch (arg) { - /* No base extensions yet */ - default: - /* - * If no driver is set, poll all registered drivers for - * extensions and return the first positive result. If - * a driver is already set, further queries will be passed - * only to that driver. - */ - if (!driver) { - mutex_lock(&vfio.iommu_drivers_lock); - list_for_each_entry(driver, &vfio.iommu_drivers_list, - vfio_next) { - - if (!list_empty(&container->group_list) && - !vfio_iommu_driver_allowed(container, - driver)) - continue; - if (!try_module_get(driver->ops->owner)) - continue; - - ret = driver->ops->ioctl(NULL, - VFIO_CHECK_EXTENSION, - arg); - module_put(driver->ops->owner); - if (ret > 0) - break; - } - mutex_unlock(&vfio.iommu_drivers_lock); - } else - ret = driver->ops->ioctl(container->iommu_data, - VFIO_CHECK_EXTENSION, arg); - } - - up_read(&container->group_lock); - - return ret; -} - -/* hold write lock on container->group_lock */ -static int __vfio_container_attach_groups(struct vfio_container *container, - struct vfio_iommu_driver *driver, - void *data) -{ - struct vfio_group *group; - int ret = -ENODEV; - - list_for_each_entry(group, &container->group_list, container_next) { - ret = driver->ops->attach_group(data, group->iommu_group, - group->type); - if (ret) - goto unwind; - } - - return ret; - -unwind: - list_for_each_entry_continue_reverse(group, &container->group_list, - container_next) { - driver->ops->detach_group(data, group->iommu_group); - } - - return ret; -} - -static long vfio_ioctl_set_iommu(struct vfio_container *container, - unsigned long arg) -{ - struct vfio_iommu_driver *driver; - long ret = -ENODEV; - - down_write(&container->group_lock); - - /* - * The container is designed to be an unprivileged interface while - * the group can be assigned to specific users. Therefore, only by - * adding a group to a container does the user get the privilege of - * enabling the iommu, which may allocate finite resources. There - * is no unset_iommu, but by removing all the groups from a container, - * the container is deprivileged and returns to an unset state. - */ - if (list_empty(&container->group_list) || container->iommu_driver) { - up_write(&container->group_lock); - return -EINVAL; - } - - mutex_lock(&vfio.iommu_drivers_lock); - list_for_each_entry(driver, &vfio.iommu_drivers_list, vfio_next) { - void *data; - - if (!vfio_iommu_driver_allowed(container, driver)) - continue; - if (!try_module_get(driver->ops->owner)) - continue; - - /* - * The arg magic for SET_IOMMU is the same as CHECK_EXTENSION, - * so test which iommu driver reported support for this - * extension and call open on them. We also pass them the - * magic, allowing a single driver to support multiple - * interfaces if they'd like. - */ - if (driver->ops->ioctl(NULL, VFIO_CHECK_EXTENSION, arg) <= 0) { - module_put(driver->ops->owner); - continue; - } - - data = driver->ops->open(arg); - if (IS_ERR(data)) { - ret = PTR_ERR(data); - module_put(driver->ops->owner); - continue; - } - - ret = __vfio_container_attach_groups(container, driver, data); - if (ret) { - driver->ops->release(data); - module_put(driver->ops->owner); - continue; - } - - container->iommu_driver = driver; - container->iommu_data = data; - break; - } - - mutex_unlock(&vfio.iommu_drivers_lock); - up_write(&container->group_lock); - - return ret; -} - -static long vfio_fops_unl_ioctl(struct file *filep, - unsigned int cmd, unsigned long arg) -{ - struct vfio_container *container = filep->private_data; - struct vfio_iommu_driver *driver; - void *data; - long ret = -EINVAL; - - if (!container) - return ret; - - switch (cmd) { - case VFIO_GET_API_VERSION: - ret = VFIO_API_VERSION; - break; - case VFIO_CHECK_EXTENSION: - ret = vfio_ioctl_check_extension(container, arg); - break; - case VFIO_SET_IOMMU: - ret = vfio_ioctl_set_iommu(container, arg); - break; - default: - driver = container->iommu_driver; - data = container->iommu_data; - - if (driver) /* passthrough all unrecognized ioctls */ - ret = driver->ops->ioctl(data, cmd, arg); - } - - return ret; -} - -static int vfio_fops_open(struct inode *inode, struct file *filep) -{ - struct vfio_container *container; - - container = kzalloc(sizeof(*container), GFP_KERNEL); - if (!container) - return -ENOMEM; - - INIT_LIST_HEAD(&container->group_list); - init_rwsem(&container->group_lock); - kref_init(&container->kref); - - filep->private_data = container; - - return 0; -} - -static int vfio_fops_release(struct inode *inode, struct file *filep) -{ - struct vfio_container *container = filep->private_data; - struct vfio_iommu_driver *driver = container->iommu_driver; - - if (driver && driver->ops->notify) - driver->ops->notify(container->iommu_data, - VFIO_IOMMU_CONTAINER_CLOSE); - - filep->private_data = NULL; - - vfio_container_put(container); - - return 0; -} - -static const struct file_operations vfio_fops = { - .owner = THIS_MODULE, - .open = vfio_fops_open, - .release = vfio_fops_release, - .unlocked_ioctl = vfio_fops_unl_ioctl, - .compat_ioctl = compat_ptr_ioctl, -}; - -/* - * VFIO Group fd, /dev/vfio/$GROUP - */ -static void __vfio_group_unset_container(struct vfio_group *group) -{ - struct vfio_container *container = group->container; - struct vfio_iommu_driver *driver; - - lockdep_assert_held_write(&group->group_rwsem); - - down_write(&container->group_lock); - - driver = container->iommu_driver; - if (driver) - driver->ops->detach_group(container->iommu_data, - group->iommu_group); - - if (group->type == VFIO_IOMMU) - iommu_group_release_dma_owner(group->iommu_group); - - group->container = NULL; - group->container_users = 0; - list_del(&group->container_next); - - /* Detaching the last group deprivileges a container, remove iommu */ - if (driver && list_empty(&container->group_list)) { - driver->ops->release(container->iommu_data); - module_put(driver->ops->owner); - container->iommu_driver = NULL; - container->iommu_data = NULL; - } - - up_write(&container->group_lock); - - vfio_container_put(container); -} - -/* - * VFIO_GROUP_UNSET_CONTAINER should fail if there are other users or - * if there was no container to unset. Since the ioctl is called on - * the group, we know that still exists, therefore the only valid - * transition here is 1->0. - */ -static int vfio_group_unset_container(struct vfio_group *group) -{ - lockdep_assert_held_write(&group->group_rwsem); - - if (!group->container) - return -EINVAL; - if (group->container_users != 1) - return -EBUSY; - __vfio_group_unset_container(group); - return 0; -} - -static int vfio_group_set_container(struct vfio_group *group, int container_fd) -{ - struct fd f; - struct vfio_container *container; - struct vfio_iommu_driver *driver; - int ret = 0; - - lockdep_assert_held_write(&group->group_rwsem); - - if (group->container || WARN_ON(group->container_users)) - return -EINVAL; - - if (group->type == VFIO_NO_IOMMU && !capable(CAP_SYS_RAWIO)) - return -EPERM; - - f = fdget(container_fd); - if (!f.file) - return -EBADF; - - /* Sanity check, is this really our fd? */ - if (f.file->f_op != &vfio_fops) { - fdput(f); - return -EINVAL; - } - - container = f.file->private_data; - WARN_ON(!container); /* fget ensures we don't race vfio_release */ - - down_write(&container->group_lock); - - /* Real groups and fake groups cannot mix */ - if (!list_empty(&container->group_list) && - container->noiommu != (group->type == VFIO_NO_IOMMU)) { - ret = -EPERM; - goto unlock_out; - } - - if (group->type == VFIO_IOMMU) { - ret = iommu_group_claim_dma_owner(group->iommu_group, f.file); - if (ret) - goto unlock_out; - } - - driver = container->iommu_driver; - if (driver) { - ret = driver->ops->attach_group(container->iommu_data, - group->iommu_group, - group->type); - if (ret) { - if (group->type == VFIO_IOMMU) - iommu_group_release_dma_owner( - group->iommu_group); - goto unlock_out; - } - } - - group->container = container; - group->container_users = 1; - container->noiommu = (group->type == VFIO_NO_IOMMU); - list_add(&group->container_next, &container->group_list); - - /* Get a reference on the container and mark a user within the group */ - vfio_container_get(container); - -unlock_out: - up_write(&container->group_lock); - fdput(f); - return ret; -} - -static const struct file_operations vfio_device_fops; - -/* true if the vfio_device has open_device() called but not close_device() */ -static bool vfio_assert_device_open(struct vfio_device *device) -{ - return !WARN_ON_ONCE(!READ_ONCE(device->open_count)); -} - -static int vfio_device_assign_container(struct vfio_device *device) -{ - struct vfio_group *group = device->group; - - lockdep_assert_held_write(&group->group_rwsem); - - if (!group->container || !group->container->iommu_driver || - WARN_ON(!group->container_users)) - return -EINVAL; - - if (group->type == VFIO_NO_IOMMU && !capable(CAP_SYS_RAWIO)) - return -EPERM; - - get_file(group->opened_file); - group->container_users++; - return 0; -} - -static void vfio_device_unassign_container(struct vfio_device *device) -{ - down_write(&device->group->group_rwsem); - WARN_ON(device->group->container_users <= 1); - device->group->container_users--; - fput(device->group->opened_file); - up_write(&device->group->group_rwsem); -} - -static struct file *vfio_device_open(struct vfio_device *device) -{ - struct vfio_iommu_driver *iommu_driver; - struct file *filep; - int ret; - - down_write(&device->group->group_rwsem); - ret = vfio_device_assign_container(device); - up_write(&device->group->group_rwsem); - if (ret) - return ERR_PTR(ret); - - if (!try_module_get(device->dev->driver->owner)) { - ret = -ENODEV; - goto err_unassign_container; - } - - mutex_lock(&device->dev_set->lock); - device->open_count++; - if (device->open_count == 1) { - /* - * Here we pass the KVM pointer with the group under the read - * lock. If the device driver will use it, it must obtain a - * reference and release it during close_device. - */ - down_read(&device->group->group_rwsem); - device->kvm = device->group->kvm; - - if (device->ops->open_device) { - ret = device->ops->open_device(device); - if (ret) - goto err_undo_count; - } - - iommu_driver = device->group->container->iommu_driver; - if (iommu_driver && iommu_driver->ops->register_device) - iommu_driver->ops->register_device( - device->group->container->iommu_data, device); - - up_read(&device->group->group_rwsem); - } - mutex_unlock(&device->dev_set->lock); - - /* - * We can't use anon_inode_getfd() because we need to modify - * the f_mode flags directly to allow more than just ioctls - */ - filep = anon_inode_getfile("[vfio-device]", &vfio_device_fops, - device, O_RDWR); - if (IS_ERR(filep)) { - ret = PTR_ERR(filep); - goto err_close_device; - } - - /* - * TODO: add an anon_inode interface to do this. - * Appears to be missing by lack of need rather than - * explicitly prevented. Now there's need. - */ - filep->f_mode |= (FMODE_PREAD | FMODE_PWRITE); - - if (device->group->type == VFIO_NO_IOMMU) - dev_warn(device->dev, "vfio-noiommu device opened by user " - "(%s:%d)\n", current->comm, task_pid_nr(current)); - /* - * On success the ref of device is moved to the file and - * put in vfio_device_fops_release() - */ - return filep; - -err_close_device: - mutex_lock(&device->dev_set->lock); - down_read(&device->group->group_rwsem); - if (device->open_count == 1 && device->ops->close_device) { - device->ops->close_device(device); - - iommu_driver = device->group->container->iommu_driver; - if (iommu_driver && iommu_driver->ops->unregister_device) - iommu_driver->ops->unregister_device( - device->group->container->iommu_data, device); - } -err_undo_count: - up_read(&device->group->group_rwsem); - device->open_count--; - if (device->open_count == 0 && device->kvm) - device->kvm = NULL; - mutex_unlock(&device->dev_set->lock); - module_put(device->dev->driver->owner); -err_unassign_container: - vfio_device_unassign_container(device); - return ERR_PTR(ret); -} - -static int vfio_group_get_device_fd(struct vfio_group *group, char *buf) -{ - struct vfio_device *device; - struct file *filep; - int fdno; - int ret; - - device = vfio_device_get_from_name(group, buf); - if (IS_ERR(device)) - return PTR_ERR(device); - - fdno = get_unused_fd_flags(O_CLOEXEC); - if (fdno < 0) { - ret = fdno; - goto err_put_device; - } - - filep = vfio_device_open(device); - if (IS_ERR(filep)) { - ret = PTR_ERR(filep); - goto err_put_fdno; - } - - fd_install(fdno, filep); - return fdno; - -err_put_fdno: - put_unused_fd(fdno); -err_put_device: - vfio_device_put(device); - return ret; -} - -static long vfio_group_fops_unl_ioctl(struct file *filep, - unsigned int cmd, unsigned long arg) -{ - struct vfio_group *group = filep->private_data; - long ret = -ENOTTY; - - switch (cmd) { - case VFIO_GROUP_GET_STATUS: - { - struct vfio_group_status status; - unsigned long minsz; - - minsz = offsetofend(struct vfio_group_status, flags); - - if (copy_from_user(&status, (void __user *)arg, minsz)) - return -EFAULT; - - if (status.argsz < minsz) - return -EINVAL; - - status.flags = 0; - - down_read(&group->group_rwsem); - if (group->container) - status.flags |= VFIO_GROUP_FLAGS_CONTAINER_SET | - VFIO_GROUP_FLAGS_VIABLE; - else if (!iommu_group_dma_owner_claimed(group->iommu_group)) - status.flags |= VFIO_GROUP_FLAGS_VIABLE; - up_read(&group->group_rwsem); - - if (copy_to_user((void __user *)arg, &status, minsz)) - return -EFAULT; - - ret = 0; - break; - } - case VFIO_GROUP_SET_CONTAINER: - { - int fd; - - if (get_user(fd, (int __user *)arg)) - return -EFAULT; - - if (fd < 0) - return -EINVAL; - - down_write(&group->group_rwsem); - ret = vfio_group_set_container(group, fd); - up_write(&group->group_rwsem); - break; - } - case VFIO_GROUP_UNSET_CONTAINER: - down_write(&group->group_rwsem); - ret = vfio_group_unset_container(group); - up_write(&group->group_rwsem); - break; - case VFIO_GROUP_GET_DEVICE_FD: - { - char *buf; - - buf = strndup_user((const char __user *)arg, PAGE_SIZE); - if (IS_ERR(buf)) - return PTR_ERR(buf); - - ret = vfio_group_get_device_fd(group, buf); - kfree(buf); - break; - } - } - - return ret; -} - -static int vfio_group_fops_open(struct inode *inode, struct file *filep) -{ - struct vfio_group *group = - container_of(inode->i_cdev, struct vfio_group, cdev); - int ret; - - down_write(&group->group_rwsem); - - /* users can be zero if this races with vfio_group_put() */ - if (!refcount_inc_not_zero(&group->users)) { - ret = -ENODEV; - goto err_unlock; - } - - if (group->type == VFIO_NO_IOMMU && !capable(CAP_SYS_RAWIO)) { - ret = -EPERM; - goto err_put; - } - - /* - * Do we need multiple instances of the group open? Seems not. - */ - if (group->opened_file) { - ret = -EBUSY; - goto err_put; - } - group->opened_file = filep; - filep->private_data = group; - - up_write(&group->group_rwsem); - return 0; -err_put: - vfio_group_put(group); -err_unlock: - up_write(&group->group_rwsem); - return ret; -} - -static int vfio_group_fops_release(struct inode *inode, struct file *filep) -{ - struct vfio_group *group = filep->private_data; - - filep->private_data = NULL; - - down_write(&group->group_rwsem); - /* - * Device FDs hold a group file reference, therefore the group release - * is only called when there are no open devices. - */ - WARN_ON(group->notifier.head); - if (group->container) { - WARN_ON(group->container_users != 1); - __vfio_group_unset_container(group); - } - group->opened_file = NULL; - up_write(&group->group_rwsem); - - vfio_group_put(group); - - return 0; -} - -static const struct file_operations vfio_group_fops = { - .owner = THIS_MODULE, - .unlocked_ioctl = vfio_group_fops_unl_ioctl, - .compat_ioctl = compat_ptr_ioctl, - .open = vfio_group_fops_open, - .release = vfio_group_fops_release, -}; - -/* - * VFIO Device fd - */ -static int vfio_device_fops_release(struct inode *inode, struct file *filep) -{ - struct vfio_device *device = filep->private_data; - struct vfio_iommu_driver *iommu_driver; - - mutex_lock(&device->dev_set->lock); - vfio_assert_device_open(device); - down_read(&device->group->group_rwsem); - if (device->open_count == 1 && device->ops->close_device) - device->ops->close_device(device); - - iommu_driver = device->group->container->iommu_driver; - if (iommu_driver && iommu_driver->ops->unregister_device) - iommu_driver->ops->unregister_device( - device->group->container->iommu_data, device); - up_read(&device->group->group_rwsem); - device->open_count--; - if (device->open_count == 0) - device->kvm = NULL; - mutex_unlock(&device->dev_set->lock); - - module_put(device->dev->driver->owner); - - vfio_device_unassign_container(device); - - vfio_device_put(device); - - return 0; -} - -/* - * vfio_mig_get_next_state - Compute the next step in the FSM - * @cur_fsm - The current state the device is in - * @new_fsm - The target state to reach - * @next_fsm - Pointer to the next step to get to new_fsm - * - * Return 0 upon success, otherwise -errno - * Upon success the next step in the state progression between cur_fsm and - * new_fsm will be set in next_fsm. - * - * This breaks down requests for combination transitions into smaller steps and - * returns the next step to get to new_fsm. The function may need to be called - * multiple times before reaching new_fsm. - * - */ -int vfio_mig_get_next_state(struct vfio_device *device, - enum vfio_device_mig_state cur_fsm, - enum vfio_device_mig_state new_fsm, - enum vfio_device_mig_state *next_fsm) -{ - enum { VFIO_DEVICE_NUM_STATES = VFIO_DEVICE_STATE_RUNNING_P2P + 1 }; - /* - * The coding in this table requires the driver to implement the - * following FSM arcs: - * RESUMING -> STOP - * STOP -> RESUMING - * STOP -> STOP_COPY - * STOP_COPY -> STOP - * - * If P2P is supported then the driver must also implement these FSM - * arcs: - * RUNNING -> RUNNING_P2P - * RUNNING_P2P -> RUNNING - * RUNNING_P2P -> STOP - * STOP -> RUNNING_P2P - * Without P2P the driver must implement: - * RUNNING -> STOP - * STOP -> RUNNING - * - * The coding will step through multiple states for some combination - * transitions; if all optional features are supported, this means the - * following ones: - * RESUMING -> STOP -> RUNNING_P2P - * RESUMING -> STOP -> RUNNING_P2P -> RUNNING - * RESUMING -> STOP -> STOP_COPY - * RUNNING -> RUNNING_P2P -> STOP - * RUNNING -> RUNNING_P2P -> STOP -> RESUMING - * RUNNING -> RUNNING_P2P -> STOP -> STOP_COPY - * RUNNING_P2P -> STOP -> RESUMING - * RUNNING_P2P -> STOP -> STOP_COPY - * STOP -> RUNNING_P2P -> RUNNING - * STOP_COPY -> STOP -> RESUMING - * STOP_COPY -> STOP -> RUNNING_P2P - * STOP_COPY -> STOP -> RUNNING_P2P -> RUNNING - */ - static const u8 vfio_from_fsm_table[VFIO_DEVICE_NUM_STATES][VFIO_DEVICE_NUM_STATES] = { - [VFIO_DEVICE_STATE_STOP] = { - [VFIO_DEVICE_STATE_STOP] = VFIO_DEVICE_STATE_STOP, - [VFIO_DEVICE_STATE_RUNNING] = VFIO_DEVICE_STATE_RUNNING_P2P, - [VFIO_DEVICE_STATE_STOP_COPY] = VFIO_DEVICE_STATE_STOP_COPY, - [VFIO_DEVICE_STATE_RESUMING] = VFIO_DEVICE_STATE_RESUMING, - [VFIO_DEVICE_STATE_RUNNING_P2P] = VFIO_DEVICE_STATE_RUNNING_P2P, - [VFIO_DEVICE_STATE_ERROR] = VFIO_DEVICE_STATE_ERROR, - }, - [VFIO_DEVICE_STATE_RUNNING] = { - [VFIO_DEVICE_STATE_STOP] = VFIO_DEVICE_STATE_RUNNING_P2P, - [VFIO_DEVICE_STATE_RUNNING] = VFIO_DEVICE_STATE_RUNNING, - [VFIO_DEVICE_STATE_STOP_COPY] = VFIO_DEVICE_STATE_RUNNING_P2P, - [VFIO_DEVICE_STATE_RESUMING] = VFIO_DEVICE_STATE_RUNNING_P2P, - [VFIO_DEVICE_STATE_RUNNING_P2P] = VFIO_DEVICE_STATE_RUNNING_P2P, - [VFIO_DEVICE_STATE_ERROR] = VFIO_DEVICE_STATE_ERROR, - }, - [VFIO_DEVICE_STATE_STOP_COPY] = { - [VFIO_DEVICE_STATE_STOP] = VFIO_DEVICE_STATE_STOP, - [VFIO_DEVICE_STATE_RUNNING] = VFIO_DEVICE_STATE_STOP, - [VFIO_DEVICE_STATE_STOP_COPY] = VFIO_DEVICE_STATE_STOP_COPY, - [VFIO_DEVICE_STATE_RESUMING] = VFIO_DEVICE_STATE_STOP, - [VFIO_DEVICE_STATE_RUNNING_P2P] = VFIO_DEVICE_STATE_STOP, - [VFIO_DEVICE_STATE_ERROR] = VFIO_DEVICE_STATE_ERROR, - }, - [VFIO_DEVICE_STATE_RESUMING] = { - [VFIO_DEVICE_STATE_STOP] = VFIO_DEVICE_STATE_STOP, - [VFIO_DEVICE_STATE_RUNNING] = VFIO_DEVICE_STATE_STOP, - [VFIO_DEVICE_STATE_STOP_COPY] = VFIO_DEVICE_STATE_STOP, - [VFIO_DEVICE_STATE_RESUMING] = VFIO_DEVICE_STATE_RESUMING, - [VFIO_DEVICE_STATE_RUNNING_P2P] = VFIO_DEVICE_STATE_STOP, - [VFIO_DEVICE_STATE_ERROR] = VFIO_DEVICE_STATE_ERROR, - }, - [VFIO_DEVICE_STATE_RUNNING_P2P] = { - [VFIO_DEVICE_STATE_STOP] = VFIO_DEVICE_STATE_STOP, - [VFIO_DEVICE_STATE_RUNNING] = VFIO_DEVICE_STATE_RUNNING, - [VFIO_DEVICE_STATE_STOP_COPY] = VFIO_DEVICE_STATE_STOP, - [VFIO_DEVICE_STATE_RESUMING] = VFIO_DEVICE_STATE_STOP, - [VFIO_DEVICE_STATE_RUNNING_P2P] = VFIO_DEVICE_STATE_RUNNING_P2P, - [VFIO_DEVICE_STATE_ERROR] = VFIO_DEVICE_STATE_ERROR, - }, - [VFIO_DEVICE_STATE_ERROR] = { - [VFIO_DEVICE_STATE_STOP] = VFIO_DEVICE_STATE_ERROR, - [VFIO_DEVICE_STATE_RUNNING] = VFIO_DEVICE_STATE_ERROR, - [VFIO_DEVICE_STATE_STOP_COPY] = VFIO_DEVICE_STATE_ERROR, - [VFIO_DEVICE_STATE_RESUMING] = VFIO_DEVICE_STATE_ERROR, - [VFIO_DEVICE_STATE_RUNNING_P2P] = VFIO_DEVICE_STATE_ERROR, - [VFIO_DEVICE_STATE_ERROR] = VFIO_DEVICE_STATE_ERROR, - }, - }; - - static const unsigned int state_flags_table[VFIO_DEVICE_NUM_STATES] = { - [VFIO_DEVICE_STATE_STOP] = VFIO_MIGRATION_STOP_COPY, - [VFIO_DEVICE_STATE_RUNNING] = VFIO_MIGRATION_STOP_COPY, - [VFIO_DEVICE_STATE_STOP_COPY] = VFIO_MIGRATION_STOP_COPY, - [VFIO_DEVICE_STATE_RESUMING] = VFIO_MIGRATION_STOP_COPY, - [VFIO_DEVICE_STATE_RUNNING_P2P] = - VFIO_MIGRATION_STOP_COPY | VFIO_MIGRATION_P2P, - [VFIO_DEVICE_STATE_ERROR] = ~0U, - }; - - if (WARN_ON(cur_fsm >= ARRAY_SIZE(vfio_from_fsm_table) || - (state_flags_table[cur_fsm] & device->migration_flags) != - state_flags_table[cur_fsm])) - return -EINVAL; - - if (new_fsm >= ARRAY_SIZE(vfio_from_fsm_table) || - (state_flags_table[new_fsm] & device->migration_flags) != - state_flags_table[new_fsm]) - return -EINVAL; - - /* - * Arcs touching optional and unsupported states are skipped over. The - * driver will instead see an arc from the original state to the next - * logical state, as per the above comment. - */ - *next_fsm = vfio_from_fsm_table[cur_fsm][new_fsm]; - while ((state_flags_table[*next_fsm] & device->migration_flags) != - state_flags_table[*next_fsm]) - *next_fsm = vfio_from_fsm_table[*next_fsm][new_fsm]; - - return (*next_fsm != VFIO_DEVICE_STATE_ERROR) ? 0 : -EINVAL; -} -EXPORT_SYMBOL_GPL(vfio_mig_get_next_state); - -/* - * Convert the drivers's struct file into a FD number and return it to userspace - */ -static int vfio_ioct_mig_return_fd(struct file *filp, void __user *arg, - struct vfio_device_feature_mig_state *mig) -{ - int ret; - int fd; - - fd = get_unused_fd_flags(O_CLOEXEC); - if (fd < 0) { - ret = fd; - goto out_fput; - } - - mig->data_fd = fd; - if (copy_to_user(arg, mig, sizeof(*mig))) { - ret = -EFAULT; - goto out_put_unused; - } - fd_install(fd, filp); - return 0; - -out_put_unused: - put_unused_fd(fd); -out_fput: - fput(filp); - return ret; -} - -static int -vfio_ioctl_device_feature_mig_device_state(struct vfio_device *device, - u32 flags, void __user *arg, - size_t argsz) -{ - size_t minsz = - offsetofend(struct vfio_device_feature_mig_state, data_fd); - struct vfio_device_feature_mig_state mig; - struct file *filp = NULL; - int ret; - - if (!device->mig_ops) - return -ENOTTY; - - ret = vfio_check_feature(flags, argsz, - VFIO_DEVICE_FEATURE_SET | - VFIO_DEVICE_FEATURE_GET, - sizeof(mig)); - if (ret != 1) - return ret; - - if (copy_from_user(&mig, arg, minsz)) - return -EFAULT; - - if (flags & VFIO_DEVICE_FEATURE_GET) { - enum vfio_device_mig_state curr_state; - - ret = device->mig_ops->migration_get_state(device, - &curr_state); - if (ret) - return ret; - mig.device_state = curr_state; - goto out_copy; - } - - /* Handle the VFIO_DEVICE_FEATURE_SET */ - filp = device->mig_ops->migration_set_state(device, mig.device_state); - if (IS_ERR(filp) || !filp) - goto out_copy; - - return vfio_ioct_mig_return_fd(filp, arg, &mig); -out_copy: - mig.data_fd = -1; - if (copy_to_user(arg, &mig, sizeof(mig))) - return -EFAULT; - if (IS_ERR(filp)) - return PTR_ERR(filp); - return 0; -} - -static int vfio_ioctl_device_feature_migration(struct vfio_device *device, - u32 flags, void __user *arg, - size_t argsz) -{ - struct vfio_device_feature_migration mig = { - .flags = device->migration_flags, - }; - int ret; - - if (!device->mig_ops) - return -ENOTTY; - - ret = vfio_check_feature(flags, argsz, VFIO_DEVICE_FEATURE_GET, - sizeof(mig)); - if (ret != 1) - return ret; - if (copy_to_user(arg, &mig, sizeof(mig))) - return -EFAULT; - return 0; -} - -static int vfio_ioctl_device_feature(struct vfio_device *device, - struct vfio_device_feature __user *arg) -{ - size_t minsz = offsetofend(struct vfio_device_feature, flags); - struct vfio_device_feature feature; - - if (copy_from_user(&feature, arg, minsz)) - return -EFAULT; - - if (feature.argsz < minsz) - return -EINVAL; - - /* Check unknown flags */ - if (feature.flags & - ~(VFIO_DEVICE_FEATURE_MASK | VFIO_DEVICE_FEATURE_SET | - VFIO_DEVICE_FEATURE_GET | VFIO_DEVICE_FEATURE_PROBE)) - return -EINVAL; - - /* GET & SET are mutually exclusive except with PROBE */ - if (!(feature.flags & VFIO_DEVICE_FEATURE_PROBE) && - (feature.flags & VFIO_DEVICE_FEATURE_SET) && - (feature.flags & VFIO_DEVICE_FEATURE_GET)) - return -EINVAL; - - switch (feature.flags & VFIO_DEVICE_FEATURE_MASK) { - case VFIO_DEVICE_FEATURE_MIGRATION: - return vfio_ioctl_device_feature_migration( - device, feature.flags, arg->data, - feature.argsz - minsz); - case VFIO_DEVICE_FEATURE_MIG_DEVICE_STATE: - return vfio_ioctl_device_feature_mig_device_state( - device, feature.flags, arg->data, - feature.argsz - minsz); - default: - if (unlikely(!device->ops->device_feature)) - return -EINVAL; - return device->ops->device_feature(device, feature.flags, - arg->data, - feature.argsz - minsz); - } -} - -static long vfio_device_fops_unl_ioctl(struct file *filep, - unsigned int cmd, unsigned long arg) -{ - struct vfio_device *device = filep->private_data; - - switch (cmd) { - case VFIO_DEVICE_FEATURE: - return vfio_ioctl_device_feature(device, (void __user *)arg); - default: - if (unlikely(!device->ops->ioctl)) - return -EINVAL; - return device->ops->ioctl(device, cmd, arg); - } -} - -static ssize_t vfio_device_fops_read(struct file *filep, char __user *buf, - size_t count, loff_t *ppos) -{ - struct vfio_device *device = filep->private_data; - - if (unlikely(!device->ops->read)) - return -EINVAL; - - return device->ops->read(device, buf, count, ppos); -} - -static ssize_t vfio_device_fops_write(struct file *filep, - const char __user *buf, - size_t count, loff_t *ppos) -{ - struct vfio_device *device = filep->private_data; - - if (unlikely(!device->ops->write)) - return -EINVAL; - - return device->ops->write(device, buf, count, ppos); -} - -static int vfio_device_fops_mmap(struct file *filep, struct vm_area_struct *vma) -{ - struct vfio_device *device = filep->private_data; - - if (unlikely(!device->ops->mmap)) - return -EINVAL; - - return device->ops->mmap(device, vma); -} - -static const struct file_operations vfio_device_fops = { - .owner = THIS_MODULE, - .release = vfio_device_fops_release, - .read = vfio_device_fops_read, - .write = vfio_device_fops_write, - .unlocked_ioctl = vfio_device_fops_unl_ioctl, - .compat_ioctl = compat_ptr_ioctl, - .mmap = vfio_device_fops_mmap, -}; - -/** - * vfio_file_iommu_group - Return the struct iommu_group for the vfio group file - * @file: VFIO group file - * - * The returned iommu_group is valid as long as a ref is held on the file. - */ -struct iommu_group *vfio_file_iommu_group(struct file *file) -{ - struct vfio_group *group = file->private_data; - - if (file->f_op != &vfio_group_fops) - return NULL; - return group->iommu_group; -} -EXPORT_SYMBOL_GPL(vfio_file_iommu_group); - -/** - * vfio_file_enforced_coherent - True if the DMA associated with the VFIO file - * is always CPU cache coherent - * @file: VFIO group file - * - * Enforced coherency means that the IOMMU ignores things like the PCIe no-snoop - * bit in DMA transactions. A return of false indicates that the user has - * rights to access additional instructions such as wbinvd on x86. - */ -bool vfio_file_enforced_coherent(struct file *file) -{ - struct vfio_group *group = file->private_data; - bool ret; - - if (file->f_op != &vfio_group_fops) - return true; - - down_read(&group->group_rwsem); - if (group->container) { - ret = vfio_ioctl_check_extension(group->container, - VFIO_DMA_CC_IOMMU); - } else { - /* - * Since the coherency state is determined only once a container - * is attached the user must do so before they can prove they - * have permission. - */ - ret = true; - } - up_read(&group->group_rwsem); - return ret; -} -EXPORT_SYMBOL_GPL(vfio_file_enforced_coherent); - -/** - * vfio_file_set_kvm - Link a kvm with VFIO drivers - * @file: VFIO group file - * @kvm: KVM to link - * - * When a VFIO device is first opened the KVM will be available in - * device->kvm if one was associated with the group. - */ -void vfio_file_set_kvm(struct file *file, struct kvm *kvm) -{ - struct vfio_group *group = file->private_data; - - if (file->f_op != &vfio_group_fops) - return; - - down_write(&group->group_rwsem); - group->kvm = kvm; - up_write(&group->group_rwsem); -} -EXPORT_SYMBOL_GPL(vfio_file_set_kvm); - -/** - * vfio_file_has_dev - True if the VFIO file is a handle for device - * @file: VFIO file to check - * @device: Device that must be part of the file - * - * Returns true if given file has permission to manipulate the given device. - */ -bool vfio_file_has_dev(struct file *file, struct vfio_device *device) -{ - struct vfio_group *group = file->private_data; - - if (file->f_op != &vfio_group_fops) - return false; - - return group == device->group; -} -EXPORT_SYMBOL_GPL(vfio_file_has_dev); - -/* - * Sub-module support - */ -/* - * Helper for managing a buffer of info chain capabilities, allocate or - * reallocate a buffer with additional @size, filling in @id and @version - * of the capability. A pointer to the new capability is returned. - * - * NB. The chain is based at the head of the buffer, so new entries are - * added to the tail, vfio_info_cap_shift() should be called to fixup the - * next offsets prior to copying to the user buffer. - */ -struct vfio_info_cap_header *vfio_info_cap_add(struct vfio_info_cap *caps, - size_t size, u16 id, u16 version) -{ - void *buf; - struct vfio_info_cap_header *header, *tmp; - - buf = krealloc(caps->buf, caps->size + size, GFP_KERNEL); - if (!buf) { - kfree(caps->buf); - caps->buf = NULL; - caps->size = 0; - return ERR_PTR(-ENOMEM); - } - - caps->buf = buf; - header = buf + caps->size; - - /* Eventually copied to user buffer, zero */ - memset(header, 0, size); - - header->id = id; - header->version = version; - - /* Add to the end of the capability chain */ - for (tmp = buf; tmp->next; tmp = buf + tmp->next) - ; /* nothing */ - - tmp->next = caps->size; - caps->size += size; - - return header; -} -EXPORT_SYMBOL_GPL(vfio_info_cap_add); - -void vfio_info_cap_shift(struct vfio_info_cap *caps, size_t offset) -{ - struct vfio_info_cap_header *tmp; - void *buf = (void *)caps->buf; - - for (tmp = buf; tmp->next; tmp = buf + tmp->next - offset) - tmp->next += offset; -} -EXPORT_SYMBOL(vfio_info_cap_shift); - -int vfio_info_add_capability(struct vfio_info_cap *caps, - struct vfio_info_cap_header *cap, size_t size) -{ - struct vfio_info_cap_header *header; - - header = vfio_info_cap_add(caps, size, cap->id, cap->version); - if (IS_ERR(header)) - return PTR_ERR(header); - - memcpy(header + 1, cap + 1, size - sizeof(*header)); - - return 0; -} -EXPORT_SYMBOL(vfio_info_add_capability); - -int vfio_set_irqs_validate_and_prepare(struct vfio_irq_set *hdr, int num_irqs, - int max_irq_type, size_t *data_size) -{ - unsigned long minsz; - size_t size; - - minsz = offsetofend(struct vfio_irq_set, count); - - if ((hdr->argsz < minsz) || (hdr->index >= max_irq_type) || - (hdr->count >= (U32_MAX - hdr->start)) || - (hdr->flags & ~(VFIO_IRQ_SET_DATA_TYPE_MASK | - VFIO_IRQ_SET_ACTION_TYPE_MASK))) - return -EINVAL; - - if (data_size) - *data_size = 0; - - if (hdr->start >= num_irqs || hdr->start + hdr->count > num_irqs) - return -EINVAL; - - switch (hdr->flags & VFIO_IRQ_SET_DATA_TYPE_MASK) { - case VFIO_IRQ_SET_DATA_NONE: - size = 0; - break; - case VFIO_IRQ_SET_DATA_BOOL: - size = sizeof(uint8_t); - break; - case VFIO_IRQ_SET_DATA_EVENTFD: - size = sizeof(int32_t); - break; - default: - return -EINVAL; - } - - if (size) { - if (hdr->argsz - minsz < hdr->count * size) - return -EINVAL; - - if (!data_size) - return -EINVAL; - - *data_size = hdr->count * size; - } - - return 0; -} -EXPORT_SYMBOL(vfio_set_irqs_validate_and_prepare); - -/* - * Pin contiguous user pages and return their associated host pages for local - * domain only. - * @device [in] : device - * @iova [in] : starting IOVA of user pages to be pinned. - * @npage [in] : count of pages to be pinned. This count should not - * be greater than VFIO_PIN_PAGES_MAX_ENTRIES. - * @prot [in] : protection flags - * @pages[out] : array of host pages - * Return error or number of pages pinned. - */ -int vfio_pin_pages(struct vfio_device *device, dma_addr_t iova, - int npage, int prot, struct page **pages) -{ - struct vfio_container *container; - struct vfio_group *group = device->group; - struct vfio_iommu_driver *driver; - int ret; - - if (!pages || !npage || !vfio_assert_device_open(device)) - return -EINVAL; - - if (npage > VFIO_PIN_PAGES_MAX_ENTRIES) - return -E2BIG; - - if (group->dev_counter > 1) - return -EINVAL; - - /* group->container cannot change while a vfio device is open */ - container = group->container; - driver = container->iommu_driver; - if (likely(driver && driver->ops->pin_pages)) - ret = driver->ops->pin_pages(container->iommu_data, - group->iommu_group, iova, - npage, prot, pages); - else - ret = -ENOTTY; - - return ret; -} -EXPORT_SYMBOL(vfio_pin_pages); - -/* - * Unpin contiguous host pages for local domain only. - * @device [in] : device - * @iova [in] : starting address of user pages to be unpinned. - * @npage [in] : count of pages to be unpinned. This count should not - * be greater than VFIO_PIN_PAGES_MAX_ENTRIES. - */ -void vfio_unpin_pages(struct vfio_device *device, dma_addr_t iova, int npage) -{ - struct vfio_container *container; - struct vfio_iommu_driver *driver; - - if (WARN_ON(npage <= 0 || npage > VFIO_PIN_PAGES_MAX_ENTRIES)) - return; - - if (WARN_ON(!vfio_assert_device_open(device))) - return; - - /* group->container cannot change while a vfio device is open */ - container = device->group->container; - driver = container->iommu_driver; - - driver->ops->unpin_pages(container->iommu_data, iova, npage); -} -EXPORT_SYMBOL(vfio_unpin_pages); - -/* - * This interface allows the CPUs to perform some sort of virtual DMA on - * behalf of the device. - * - * CPUs read/write from/into a range of IOVAs pointing to user space memory - * into/from a kernel buffer. - * - * As the read/write of user space memory is conducted via the CPUs and is - * not a real device DMA, it is not necessary to pin the user space memory. - * - * @device [in] : VFIO device - * @iova [in] : base IOVA of a user space buffer - * @data [in] : pointer to kernel buffer - * @len [in] : kernel buffer length - * @write : indicate read or write - * Return error code on failure or 0 on success. - */ -int vfio_dma_rw(struct vfio_device *device, dma_addr_t iova, void *data, - size_t len, bool write) -{ - struct vfio_container *container; - struct vfio_iommu_driver *driver; - int ret = 0; - - if (!data || len <= 0 || !vfio_assert_device_open(device)) - return -EINVAL; - - /* group->container cannot change while a vfio device is open */ - container = device->group->container; - driver = container->iommu_driver; - - if (likely(driver && driver->ops->dma_rw)) - ret = driver->ops->dma_rw(container->iommu_data, - iova, data, len, write); - else - ret = -ENOTTY; - return ret; -} -EXPORT_SYMBOL(vfio_dma_rw); - -/* - * Module/class support - */ -static char *vfio_devnode(struct device *dev, umode_t *mode) -{ - return kasprintf(GFP_KERNEL, "vfio/%s", dev_name(dev)); -} - -static struct miscdevice vfio_dev = { - .minor = VFIO_MINOR, - .name = "vfio", - .fops = &vfio_fops, - .nodename = "vfio/vfio", - .mode = S_IRUGO | S_IWUGO, -}; - -static int __init vfio_init(void) -{ - int ret; - - ida_init(&vfio.group_ida); - mutex_init(&vfio.group_lock); - mutex_init(&vfio.iommu_drivers_lock); - INIT_LIST_HEAD(&vfio.group_list); - INIT_LIST_HEAD(&vfio.iommu_drivers_list); - - ret = misc_register(&vfio_dev); - if (ret) { - pr_err("vfio: misc device register failed\n"); - return ret; - } - - /* /dev/vfio/$GROUP */ - vfio.class = class_create(THIS_MODULE, "vfio"); - if (IS_ERR(vfio.class)) { - ret = PTR_ERR(vfio.class); - goto err_class; - } - - vfio.class->devnode = vfio_devnode; - - ret = alloc_chrdev_region(&vfio.group_devt, 0, MINORMASK + 1, "vfio"); - if (ret) - goto err_alloc_chrdev; - -#ifdef CONFIG_VFIO_NOIOMMU - ret = vfio_register_iommu_driver(&vfio_noiommu_ops); -#endif - if (ret) - goto err_driver_register; - - pr_info(DRIVER_DESC " version: " DRIVER_VERSION "\n"); - return 0; - -err_driver_register: - unregister_chrdev_region(vfio.group_devt, MINORMASK + 1); -err_alloc_chrdev: - class_destroy(vfio.class); - vfio.class = NULL; -err_class: - misc_deregister(&vfio_dev); - return ret; -} - -static void __exit vfio_cleanup(void) -{ - WARN_ON(!list_empty(&vfio.group_list)); - -#ifdef CONFIG_VFIO_NOIOMMU - vfio_unregister_iommu_driver(&vfio_noiommu_ops); -#endif - ida_destroy(&vfio.group_ida); - unregister_chrdev_region(vfio.group_devt, MINORMASK + 1); - class_destroy(vfio.class); - vfio.class = NULL; - misc_deregister(&vfio_dev); - xa_destroy(&vfio_device_set_xa); -} - -module_init(vfio_init); -module_exit(vfio_cleanup); - -MODULE_VERSION(DRIVER_VERSION); -MODULE_LICENSE("GPL v2"); -MODULE_AUTHOR(DRIVER_AUTHOR); -MODULE_DESCRIPTION(DRIVER_DESC); -MODULE_ALIAS_MISCDEV(VFIO_MINOR); -MODULE_ALIAS("devname:vfio/vfio"); -MODULE_SOFTDEP("post: vfio_iommu_type1 vfio_iommu_spapr_tce"); diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c new file mode 100644 index 000000000000..7cb56c382c97 --- /dev/null +++ b/drivers/vfio/vfio_main.c @@ -0,0 +1,2135 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * VFIO core + * + * Copyright (C) 2012 Red Hat, Inc. All rights reserved. + * Author: Alex Williamson + * + * Derived from original vfio: + * Copyright 2010 Cisco Systems, Inc. All rights reserved. + * Author: Tom Lyon, pugs@cisco.com + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "vfio.h" + +#define DRIVER_VERSION "0.3" +#define DRIVER_AUTHOR "Alex Williamson " +#define DRIVER_DESC "VFIO - User Level meta-driver" + +static struct vfio { + struct class *class; + struct list_head iommu_drivers_list; + struct mutex iommu_drivers_lock; + struct list_head group_list; + struct mutex group_lock; /* locks group_list */ + struct ida group_ida; + dev_t group_devt; +} vfio; + +struct vfio_iommu_driver { + const struct vfio_iommu_driver_ops *ops; + struct list_head vfio_next; +}; + +struct vfio_container { + struct kref kref; + struct list_head group_list; + struct rw_semaphore group_lock; + struct vfio_iommu_driver *iommu_driver; + void *iommu_data; + bool noiommu; +}; + +struct vfio_group { + struct device dev; + struct cdev cdev; + refcount_t users; + unsigned int container_users; + struct iommu_group *iommu_group; + struct vfio_container *container; + struct list_head device_list; + struct mutex device_lock; + struct list_head vfio_next; + struct list_head container_next; + enum vfio_group_type type; + unsigned int dev_counter; + struct rw_semaphore group_rwsem; + struct kvm *kvm; + struct file *opened_file; + struct blocking_notifier_head notifier; +}; + +#ifdef CONFIG_VFIO_NOIOMMU +static bool noiommu __read_mostly; +module_param_named(enable_unsafe_noiommu_mode, + noiommu, bool, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(enable_unsafe_noiommu_mode, "Enable UNSAFE, no-IOMMU mode. This mode provides no device isolation, no DMA translation, no host kernel protection, cannot be used for device assignment to virtual machines, requires RAWIO permissions, and will taint the kernel. If you do not know what this is for, step away. (default: false)"); +#endif + +static DEFINE_XARRAY(vfio_device_set_xa); +static const struct file_operations vfio_group_fops; + +int vfio_assign_device_set(struct vfio_device *device, void *set_id) +{ + unsigned long idx = (unsigned long)set_id; + struct vfio_device_set *new_dev_set; + struct vfio_device_set *dev_set; + + if (WARN_ON(!set_id)) + return -EINVAL; + + /* + * Atomically acquire a singleton object in the xarray for this set_id + */ + xa_lock(&vfio_device_set_xa); + dev_set = xa_load(&vfio_device_set_xa, idx); + if (dev_set) + goto found_get_ref; + xa_unlock(&vfio_device_set_xa); + + new_dev_set = kzalloc(sizeof(*new_dev_set), GFP_KERNEL); + if (!new_dev_set) + return -ENOMEM; + mutex_init(&new_dev_set->lock); + INIT_LIST_HEAD(&new_dev_set->device_list); + new_dev_set->set_id = set_id; + + xa_lock(&vfio_device_set_xa); + dev_set = __xa_cmpxchg(&vfio_device_set_xa, idx, NULL, new_dev_set, + GFP_KERNEL); + if (!dev_set) { + dev_set = new_dev_set; + goto found_get_ref; + } + + kfree(new_dev_set); + if (xa_is_err(dev_set)) { + xa_unlock(&vfio_device_set_xa); + return xa_err(dev_set); + } + +found_get_ref: + dev_set->device_count++; + xa_unlock(&vfio_device_set_xa); + mutex_lock(&dev_set->lock); + device->dev_set = dev_set; + list_add_tail(&device->dev_set_list, &dev_set->device_list); + mutex_unlock(&dev_set->lock); + return 0; +} +EXPORT_SYMBOL_GPL(vfio_assign_device_set); + +static void vfio_release_device_set(struct vfio_device *device) +{ + struct vfio_device_set *dev_set = device->dev_set; + + if (!dev_set) + return; + + mutex_lock(&dev_set->lock); + list_del(&device->dev_set_list); + mutex_unlock(&dev_set->lock); + + xa_lock(&vfio_device_set_xa); + if (!--dev_set->device_count) { + __xa_erase(&vfio_device_set_xa, + (unsigned long)dev_set->set_id); + mutex_destroy(&dev_set->lock); + kfree(dev_set); + } + xa_unlock(&vfio_device_set_xa); +} + +#ifdef CONFIG_VFIO_NOIOMMU +static void *vfio_noiommu_open(unsigned long arg) +{ + if (arg != VFIO_NOIOMMU_IOMMU) + return ERR_PTR(-EINVAL); + if (!capable(CAP_SYS_RAWIO)) + return ERR_PTR(-EPERM); + + return NULL; +} + +static void vfio_noiommu_release(void *iommu_data) +{ +} + +static long vfio_noiommu_ioctl(void *iommu_data, + unsigned int cmd, unsigned long arg) +{ + if (cmd == VFIO_CHECK_EXTENSION) + return noiommu && (arg == VFIO_NOIOMMU_IOMMU) ? 1 : 0; + + return -ENOTTY; +} + +static int vfio_noiommu_attach_group(void *iommu_data, + struct iommu_group *iommu_group, enum vfio_group_type type) +{ + return 0; +} + +static void vfio_noiommu_detach_group(void *iommu_data, + struct iommu_group *iommu_group) +{ +} + +static const struct vfio_iommu_driver_ops vfio_noiommu_ops = { + .name = "vfio-noiommu", + .owner = THIS_MODULE, + .open = vfio_noiommu_open, + .release = vfio_noiommu_release, + .ioctl = vfio_noiommu_ioctl, + .attach_group = vfio_noiommu_attach_group, + .detach_group = vfio_noiommu_detach_group, +}; + +/* + * Only noiommu containers can use vfio-noiommu and noiommu containers can only + * use vfio-noiommu. + */ +static inline bool vfio_iommu_driver_allowed(struct vfio_container *container, + const struct vfio_iommu_driver *driver) +{ + return container->noiommu == (driver->ops == &vfio_noiommu_ops); +} +#else +static inline bool vfio_iommu_driver_allowed(struct vfio_container *container, + const struct vfio_iommu_driver *driver) +{ + return true; +} +#endif /* CONFIG_VFIO_NOIOMMU */ + +/* + * IOMMU driver registration + */ +int vfio_register_iommu_driver(const struct vfio_iommu_driver_ops *ops) +{ + struct vfio_iommu_driver *driver, *tmp; + + if (WARN_ON(!ops->register_device != !ops->unregister_device)) + return -EINVAL; + + driver = kzalloc(sizeof(*driver), GFP_KERNEL); + if (!driver) + return -ENOMEM; + + driver->ops = ops; + + mutex_lock(&vfio.iommu_drivers_lock); + + /* Check for duplicates */ + list_for_each_entry(tmp, &vfio.iommu_drivers_list, vfio_next) { + if (tmp->ops == ops) { + mutex_unlock(&vfio.iommu_drivers_lock); + kfree(driver); + return -EINVAL; + } + } + + list_add(&driver->vfio_next, &vfio.iommu_drivers_list); + + mutex_unlock(&vfio.iommu_drivers_lock); + + return 0; +} +EXPORT_SYMBOL_GPL(vfio_register_iommu_driver); + +void vfio_unregister_iommu_driver(const struct vfio_iommu_driver_ops *ops) +{ + struct vfio_iommu_driver *driver; + + mutex_lock(&vfio.iommu_drivers_lock); + list_for_each_entry(driver, &vfio.iommu_drivers_list, vfio_next) { + if (driver->ops == ops) { + list_del(&driver->vfio_next); + mutex_unlock(&vfio.iommu_drivers_lock); + kfree(driver); + return; + } + } + mutex_unlock(&vfio.iommu_drivers_lock); +} +EXPORT_SYMBOL_GPL(vfio_unregister_iommu_driver); + +static void vfio_group_get(struct vfio_group *group); + +/* + * Container objects - containers are created when /dev/vfio/vfio is + * opened, but their lifecycle extends until the last user is done, so + * it's freed via kref. Must support container/group/device being + * closed in any order. + */ +static void vfio_container_get(struct vfio_container *container) +{ + kref_get(&container->kref); +} + +static void vfio_container_release(struct kref *kref) +{ + struct vfio_container *container; + container = container_of(kref, struct vfio_container, kref); + + kfree(container); +} + +static void vfio_container_put(struct vfio_container *container) +{ + kref_put(&container->kref, vfio_container_release); +} + +/* + * Group objects - create, release, get, put, search + */ +static struct vfio_group * +__vfio_group_get_from_iommu(struct iommu_group *iommu_group) +{ + struct vfio_group *group; + + list_for_each_entry(group, &vfio.group_list, vfio_next) { + if (group->iommu_group == iommu_group) { + vfio_group_get(group); + return group; + } + } + return NULL; +} + +static struct vfio_group * +vfio_group_get_from_iommu(struct iommu_group *iommu_group) +{ + struct vfio_group *group; + + mutex_lock(&vfio.group_lock); + group = __vfio_group_get_from_iommu(iommu_group); + mutex_unlock(&vfio.group_lock); + return group; +} + +static void vfio_group_release(struct device *dev) +{ + struct vfio_group *group = container_of(dev, struct vfio_group, dev); + + mutex_destroy(&group->device_lock); + iommu_group_put(group->iommu_group); + ida_free(&vfio.group_ida, MINOR(group->dev.devt)); + kfree(group); +} + +static struct vfio_group *vfio_group_alloc(struct iommu_group *iommu_group, + enum vfio_group_type type) +{ + struct vfio_group *group; + int minor; + + group = kzalloc(sizeof(*group), GFP_KERNEL); + if (!group) + return ERR_PTR(-ENOMEM); + + minor = ida_alloc_max(&vfio.group_ida, MINORMASK, GFP_KERNEL); + if (minor < 0) { + kfree(group); + return ERR_PTR(minor); + } + + device_initialize(&group->dev); + group->dev.devt = MKDEV(MAJOR(vfio.group_devt), minor); + group->dev.class = vfio.class; + group->dev.release = vfio_group_release; + cdev_init(&group->cdev, &vfio_group_fops); + group->cdev.owner = THIS_MODULE; + + refcount_set(&group->users, 1); + init_rwsem(&group->group_rwsem); + INIT_LIST_HEAD(&group->device_list); + mutex_init(&group->device_lock); + group->iommu_group = iommu_group; + /* put in vfio_group_release() */ + iommu_group_ref_get(iommu_group); + group->type = type; + BLOCKING_INIT_NOTIFIER_HEAD(&group->notifier); + + return group; +} + +static struct vfio_group *vfio_create_group(struct iommu_group *iommu_group, + enum vfio_group_type type) +{ + struct vfio_group *group; + struct vfio_group *ret; + int err; + + group = vfio_group_alloc(iommu_group, type); + if (IS_ERR(group)) + return group; + + err = dev_set_name(&group->dev, "%s%d", + group->type == VFIO_NO_IOMMU ? "noiommu-" : "", + iommu_group_id(iommu_group)); + if (err) { + ret = ERR_PTR(err); + goto err_put; + } + + mutex_lock(&vfio.group_lock); + + /* Did we race creating this group? */ + ret = __vfio_group_get_from_iommu(iommu_group); + if (ret) + goto err_unlock; + + err = cdev_device_add(&group->cdev, &group->dev); + if (err) { + ret = ERR_PTR(err); + goto err_unlock; + } + + list_add(&group->vfio_next, &vfio.group_list); + + mutex_unlock(&vfio.group_lock); + return group; + +err_unlock: + mutex_unlock(&vfio.group_lock); +err_put: + put_device(&group->dev); + return ret; +} + +static void vfio_group_put(struct vfio_group *group) +{ + if (!refcount_dec_and_mutex_lock(&group->users, &vfio.group_lock)) + return; + + /* + * These data structures all have paired operations that can only be + * undone when the caller holds a live reference on the group. Since all + * pairs must be undone these WARN_ON's indicate some caller did not + * properly hold the group reference. + */ + WARN_ON(!list_empty(&group->device_list)); + WARN_ON(group->container || group->container_users); + WARN_ON(group->notifier.head); + + list_del(&group->vfio_next); + cdev_device_del(&group->cdev, &group->dev); + mutex_unlock(&vfio.group_lock); + + put_device(&group->dev); +} + +static void vfio_group_get(struct vfio_group *group) +{ + refcount_inc(&group->users); +} + +/* + * Device objects - create, release, get, put, search + */ +/* Device reference always implies a group reference */ +static void vfio_device_put(struct vfio_device *device) +{ + if (refcount_dec_and_test(&device->refcount)) + complete(&device->comp); +} + +static bool vfio_device_try_get(struct vfio_device *device) +{ + return refcount_inc_not_zero(&device->refcount); +} + +static struct vfio_device *vfio_group_get_device(struct vfio_group *group, + struct device *dev) +{ + struct vfio_device *device; + + mutex_lock(&group->device_lock); + list_for_each_entry(device, &group->device_list, group_next) { + if (device->dev == dev && vfio_device_try_get(device)) { + mutex_unlock(&group->device_lock); + return device; + } + } + mutex_unlock(&group->device_lock); + return NULL; +} + +/* + * VFIO driver API + */ +void vfio_init_group_dev(struct vfio_device *device, struct device *dev, + const struct vfio_device_ops *ops) +{ + init_completion(&device->comp); + device->dev = dev; + device->ops = ops; +} +EXPORT_SYMBOL_GPL(vfio_init_group_dev); + +void vfio_uninit_group_dev(struct vfio_device *device) +{ + vfio_release_device_set(device); +} +EXPORT_SYMBOL_GPL(vfio_uninit_group_dev); + +static struct vfio_group *vfio_noiommu_group_alloc(struct device *dev, + enum vfio_group_type type) +{ + struct iommu_group *iommu_group; + struct vfio_group *group; + int ret; + + iommu_group = iommu_group_alloc(); + if (IS_ERR(iommu_group)) + return ERR_CAST(iommu_group); + + ret = iommu_group_set_name(iommu_group, "vfio-noiommu"); + if (ret) + goto out_put_group; + ret = iommu_group_add_device(iommu_group, dev); + if (ret) + goto out_put_group; + + group = vfio_create_group(iommu_group, type); + if (IS_ERR(group)) { + ret = PTR_ERR(group); + goto out_remove_device; + } + iommu_group_put(iommu_group); + return group; + +out_remove_device: + iommu_group_remove_device(dev); +out_put_group: + iommu_group_put(iommu_group); + return ERR_PTR(ret); +} + +static struct vfio_group *vfio_group_find_or_alloc(struct device *dev) +{ + struct iommu_group *iommu_group; + struct vfio_group *group; + + iommu_group = iommu_group_get(dev); +#ifdef CONFIG_VFIO_NOIOMMU + if (!iommu_group && noiommu) { + /* + * With noiommu enabled, create an IOMMU group for devices that + * don't already have one, implying no IOMMU hardware/driver + * exists. Taint the kernel because we're about to give a DMA + * capable device to a user without IOMMU protection. + */ + group = vfio_noiommu_group_alloc(dev, VFIO_NO_IOMMU); + if (!IS_ERR(group)) { + add_taint(TAINT_USER, LOCKDEP_STILL_OK); + dev_warn(dev, "Adding kernel taint for vfio-noiommu group on device\n"); + } + return group; + } +#endif + if (!iommu_group) + return ERR_PTR(-EINVAL); + + /* + * VFIO always sets IOMMU_CACHE because we offer no way for userspace to + * restore cache coherency. It has to be checked here because it is only + * valid for cases where we are using iommu groups. + */ + if (!device_iommu_capable(dev, IOMMU_CAP_CACHE_COHERENCY)) { + iommu_group_put(iommu_group); + return ERR_PTR(-EINVAL); + } + + group = vfio_group_get_from_iommu(iommu_group); + if (!group) + group = vfio_create_group(iommu_group, VFIO_IOMMU); + + /* The vfio_group holds a reference to the iommu_group */ + iommu_group_put(iommu_group); + return group; +} + +static int __vfio_register_dev(struct vfio_device *device, + struct vfio_group *group) +{ + struct vfio_device *existing_device; + + if (IS_ERR(group)) + return PTR_ERR(group); + + /* + * If the driver doesn't specify a set then the device is added to a + * singleton set just for itself. + */ + if (!device->dev_set) + vfio_assign_device_set(device, device); + + existing_device = vfio_group_get_device(group, device->dev); + if (existing_device) { + dev_WARN(device->dev, "Device already exists on group %d\n", + iommu_group_id(group->iommu_group)); + vfio_device_put(existing_device); + if (group->type == VFIO_NO_IOMMU || + group->type == VFIO_EMULATED_IOMMU) + iommu_group_remove_device(device->dev); + vfio_group_put(group); + return -EBUSY; + } + + /* Our reference on group is moved to the device */ + device->group = group; + + /* Refcounting can't start until the driver calls register */ + refcount_set(&device->refcount, 1); + + mutex_lock(&group->device_lock); + list_add(&device->group_next, &group->device_list); + group->dev_counter++; + mutex_unlock(&group->device_lock); + + return 0; +} + +int vfio_register_group_dev(struct vfio_device *device) +{ + return __vfio_register_dev(device, + vfio_group_find_or_alloc(device->dev)); +} +EXPORT_SYMBOL_GPL(vfio_register_group_dev); + +/* + * Register a virtual device without IOMMU backing. The user of this + * device must not be able to directly trigger unmediated DMA. + */ +int vfio_register_emulated_iommu_dev(struct vfio_device *device) +{ + return __vfio_register_dev(device, + vfio_noiommu_group_alloc(device->dev, VFIO_EMULATED_IOMMU)); +} +EXPORT_SYMBOL_GPL(vfio_register_emulated_iommu_dev); + +static struct vfio_device *vfio_device_get_from_name(struct vfio_group *group, + char *buf) +{ + struct vfio_device *it, *device = ERR_PTR(-ENODEV); + + mutex_lock(&group->device_lock); + list_for_each_entry(it, &group->device_list, group_next) { + int ret; + + if (it->ops->match) { + ret = it->ops->match(it, buf); + if (ret < 0) { + device = ERR_PTR(ret); + break; + } + } else { + ret = !strcmp(dev_name(it->dev), buf); + } + + if (ret && vfio_device_try_get(it)) { + device = it; + break; + } + } + mutex_unlock(&group->device_lock); + + return device; +} + +/* + * Decrement the device reference count and wait for the device to be + * removed. Open file descriptors for the device... */ +void vfio_unregister_group_dev(struct vfio_device *device) +{ + struct vfio_group *group = device->group; + unsigned int i = 0; + bool interrupted = false; + long rc; + + vfio_device_put(device); + rc = try_wait_for_completion(&device->comp); + while (rc <= 0) { + if (device->ops->request) + device->ops->request(device, i++); + + if (interrupted) { + rc = wait_for_completion_timeout(&device->comp, + HZ * 10); + } else { + rc = wait_for_completion_interruptible_timeout( + &device->comp, HZ * 10); + if (rc < 0) { + interrupted = true; + dev_warn(device->dev, + "Device is currently in use, task" + " \"%s\" (%d) " + "blocked until device is released", + current->comm, task_pid_nr(current)); + } + } + } + + mutex_lock(&group->device_lock); + list_del(&device->group_next); + group->dev_counter--; + mutex_unlock(&group->device_lock); + + if (group->type == VFIO_NO_IOMMU || group->type == VFIO_EMULATED_IOMMU) + iommu_group_remove_device(device->dev); + + /* Matches the get in vfio_register_group_dev() */ + vfio_group_put(group); +} +EXPORT_SYMBOL_GPL(vfio_unregister_group_dev); + +/* + * VFIO base fd, /dev/vfio/vfio + */ +static long vfio_ioctl_check_extension(struct vfio_container *container, + unsigned long arg) +{ + struct vfio_iommu_driver *driver; + long ret = 0; + + down_read(&container->group_lock); + + driver = container->iommu_driver; + + switch (arg) { + /* No base extensions yet */ + default: + /* + * If no driver is set, poll all registered drivers for + * extensions and return the first positive result. If + * a driver is already set, further queries will be passed + * only to that driver. + */ + if (!driver) { + mutex_lock(&vfio.iommu_drivers_lock); + list_for_each_entry(driver, &vfio.iommu_drivers_list, + vfio_next) { + + if (!list_empty(&container->group_list) && + !vfio_iommu_driver_allowed(container, + driver)) + continue; + if (!try_module_get(driver->ops->owner)) + continue; + + ret = driver->ops->ioctl(NULL, + VFIO_CHECK_EXTENSION, + arg); + module_put(driver->ops->owner); + if (ret > 0) + break; + } + mutex_unlock(&vfio.iommu_drivers_lock); + } else + ret = driver->ops->ioctl(container->iommu_data, + VFIO_CHECK_EXTENSION, arg); + } + + up_read(&container->group_lock); + + return ret; +} + +/* hold write lock on container->group_lock */ +static int __vfio_container_attach_groups(struct vfio_container *container, + struct vfio_iommu_driver *driver, + void *data) +{ + struct vfio_group *group; + int ret = -ENODEV; + + list_for_each_entry(group, &container->group_list, container_next) { + ret = driver->ops->attach_group(data, group->iommu_group, + group->type); + if (ret) + goto unwind; + } + + return ret; + +unwind: + list_for_each_entry_continue_reverse(group, &container->group_list, + container_next) { + driver->ops->detach_group(data, group->iommu_group); + } + + return ret; +} + +static long vfio_ioctl_set_iommu(struct vfio_container *container, + unsigned long arg) +{ + struct vfio_iommu_driver *driver; + long ret = -ENODEV; + + down_write(&container->group_lock); + + /* + * The container is designed to be an unprivileged interface while + * the group can be assigned to specific users. Therefore, only by + * adding a group to a container does the user get the privilege of + * enabling the iommu, which may allocate finite resources. There + * is no unset_iommu, but by removing all the groups from a container, + * the container is deprivileged and returns to an unset state. + */ + if (list_empty(&container->group_list) || container->iommu_driver) { + up_write(&container->group_lock); + return -EINVAL; + } + + mutex_lock(&vfio.iommu_drivers_lock); + list_for_each_entry(driver, &vfio.iommu_drivers_list, vfio_next) { + void *data; + + if (!vfio_iommu_driver_allowed(container, driver)) + continue; + if (!try_module_get(driver->ops->owner)) + continue; + + /* + * The arg magic for SET_IOMMU is the same as CHECK_EXTENSION, + * so test which iommu driver reported support for this + * extension and call open on them. We also pass them the + * magic, allowing a single driver to support multiple + * interfaces if they'd like. + */ + if (driver->ops->ioctl(NULL, VFIO_CHECK_EXTENSION, arg) <= 0) { + module_put(driver->ops->owner); + continue; + } + + data = driver->ops->open(arg); + if (IS_ERR(data)) { + ret = PTR_ERR(data); + module_put(driver->ops->owner); + continue; + } + + ret = __vfio_container_attach_groups(container, driver, data); + if (ret) { + driver->ops->release(data); + module_put(driver->ops->owner); + continue; + } + + container->iommu_driver = driver; + container->iommu_data = data; + break; + } + + mutex_unlock(&vfio.iommu_drivers_lock); + up_write(&container->group_lock); + + return ret; +} + +static long vfio_fops_unl_ioctl(struct file *filep, + unsigned int cmd, unsigned long arg) +{ + struct vfio_container *container = filep->private_data; + struct vfio_iommu_driver *driver; + void *data; + long ret = -EINVAL; + + if (!container) + return ret; + + switch (cmd) { + case VFIO_GET_API_VERSION: + ret = VFIO_API_VERSION; + break; + case VFIO_CHECK_EXTENSION: + ret = vfio_ioctl_check_extension(container, arg); + break; + case VFIO_SET_IOMMU: + ret = vfio_ioctl_set_iommu(container, arg); + break; + default: + driver = container->iommu_driver; + data = container->iommu_data; + + if (driver) /* passthrough all unrecognized ioctls */ + ret = driver->ops->ioctl(data, cmd, arg); + } + + return ret; +} + +static int vfio_fops_open(struct inode *inode, struct file *filep) +{ + struct vfio_container *container; + + container = kzalloc(sizeof(*container), GFP_KERNEL); + if (!container) + return -ENOMEM; + + INIT_LIST_HEAD(&container->group_list); + init_rwsem(&container->group_lock); + kref_init(&container->kref); + + filep->private_data = container; + + return 0; +} + +static int vfio_fops_release(struct inode *inode, struct file *filep) +{ + struct vfio_container *container = filep->private_data; + struct vfio_iommu_driver *driver = container->iommu_driver; + + if (driver && driver->ops->notify) + driver->ops->notify(container->iommu_data, + VFIO_IOMMU_CONTAINER_CLOSE); + + filep->private_data = NULL; + + vfio_container_put(container); + + return 0; +} + +static const struct file_operations vfio_fops = { + .owner = THIS_MODULE, + .open = vfio_fops_open, + .release = vfio_fops_release, + .unlocked_ioctl = vfio_fops_unl_ioctl, + .compat_ioctl = compat_ptr_ioctl, +}; + +/* + * VFIO Group fd, /dev/vfio/$GROUP + */ +static void __vfio_group_unset_container(struct vfio_group *group) +{ + struct vfio_container *container = group->container; + struct vfio_iommu_driver *driver; + + lockdep_assert_held_write(&group->group_rwsem); + + down_write(&container->group_lock); + + driver = container->iommu_driver; + if (driver) + driver->ops->detach_group(container->iommu_data, + group->iommu_group); + + if (group->type == VFIO_IOMMU) + iommu_group_release_dma_owner(group->iommu_group); + + group->container = NULL; + group->container_users = 0; + list_del(&group->container_next); + + /* Detaching the last group deprivileges a container, remove iommu */ + if (driver && list_empty(&container->group_list)) { + driver->ops->release(container->iommu_data); + module_put(driver->ops->owner); + container->iommu_driver = NULL; + container->iommu_data = NULL; + } + + up_write(&container->group_lock); + + vfio_container_put(container); +} + +/* + * VFIO_GROUP_UNSET_CONTAINER should fail if there are other users or + * if there was no container to unset. Since the ioctl is called on + * the group, we know that still exists, therefore the only valid + * transition here is 1->0. + */ +static int vfio_group_unset_container(struct vfio_group *group) +{ + lockdep_assert_held_write(&group->group_rwsem); + + if (!group->container) + return -EINVAL; + if (group->container_users != 1) + return -EBUSY; + __vfio_group_unset_container(group); + return 0; +} + +static int vfio_group_set_container(struct vfio_group *group, int container_fd) +{ + struct fd f; + struct vfio_container *container; + struct vfio_iommu_driver *driver; + int ret = 0; + + lockdep_assert_held_write(&group->group_rwsem); + + if (group->container || WARN_ON(group->container_users)) + return -EINVAL; + + if (group->type == VFIO_NO_IOMMU && !capable(CAP_SYS_RAWIO)) + return -EPERM; + + f = fdget(container_fd); + if (!f.file) + return -EBADF; + + /* Sanity check, is this really our fd? */ + if (f.file->f_op != &vfio_fops) { + fdput(f); + return -EINVAL; + } + + container = f.file->private_data; + WARN_ON(!container); /* fget ensures we don't race vfio_release */ + + down_write(&container->group_lock); + + /* Real groups and fake groups cannot mix */ + if (!list_empty(&container->group_list) && + container->noiommu != (group->type == VFIO_NO_IOMMU)) { + ret = -EPERM; + goto unlock_out; + } + + if (group->type == VFIO_IOMMU) { + ret = iommu_group_claim_dma_owner(group->iommu_group, f.file); + if (ret) + goto unlock_out; + } + + driver = container->iommu_driver; + if (driver) { + ret = driver->ops->attach_group(container->iommu_data, + group->iommu_group, + group->type); + if (ret) { + if (group->type == VFIO_IOMMU) + iommu_group_release_dma_owner( + group->iommu_group); + goto unlock_out; + } + } + + group->container = container; + group->container_users = 1; + container->noiommu = (group->type == VFIO_NO_IOMMU); + list_add(&group->container_next, &container->group_list); + + /* Get a reference on the container and mark a user within the group */ + vfio_container_get(container); + +unlock_out: + up_write(&container->group_lock); + fdput(f); + return ret; +} + +static const struct file_operations vfio_device_fops; + +/* true if the vfio_device has open_device() called but not close_device() */ +static bool vfio_assert_device_open(struct vfio_device *device) +{ + return !WARN_ON_ONCE(!READ_ONCE(device->open_count)); +} + +static int vfio_device_assign_container(struct vfio_device *device) +{ + struct vfio_group *group = device->group; + + lockdep_assert_held_write(&group->group_rwsem); + + if (!group->container || !group->container->iommu_driver || + WARN_ON(!group->container_users)) + return -EINVAL; + + if (group->type == VFIO_NO_IOMMU && !capable(CAP_SYS_RAWIO)) + return -EPERM; + + get_file(group->opened_file); + group->container_users++; + return 0; +} + +static void vfio_device_unassign_container(struct vfio_device *device) +{ + down_write(&device->group->group_rwsem); + WARN_ON(device->group->container_users <= 1); + device->group->container_users--; + fput(device->group->opened_file); + up_write(&device->group->group_rwsem); +} + +static struct file *vfio_device_open(struct vfio_device *device) +{ + struct vfio_iommu_driver *iommu_driver; + struct file *filep; + int ret; + + down_write(&device->group->group_rwsem); + ret = vfio_device_assign_container(device); + up_write(&device->group->group_rwsem); + if (ret) + return ERR_PTR(ret); + + if (!try_module_get(device->dev->driver->owner)) { + ret = -ENODEV; + goto err_unassign_container; + } + + mutex_lock(&device->dev_set->lock); + device->open_count++; + if (device->open_count == 1) { + /* + * Here we pass the KVM pointer with the group under the read + * lock. If the device driver will use it, it must obtain a + * reference and release it during close_device. + */ + down_read(&device->group->group_rwsem); + device->kvm = device->group->kvm; + + if (device->ops->open_device) { + ret = device->ops->open_device(device); + if (ret) + goto err_undo_count; + } + + iommu_driver = device->group->container->iommu_driver; + if (iommu_driver && iommu_driver->ops->register_device) + iommu_driver->ops->register_device( + device->group->container->iommu_data, device); + + up_read(&device->group->group_rwsem); + } + mutex_unlock(&device->dev_set->lock); + + /* + * We can't use anon_inode_getfd() because we need to modify + * the f_mode flags directly to allow more than just ioctls + */ + filep = anon_inode_getfile("[vfio-device]", &vfio_device_fops, + device, O_RDWR); + if (IS_ERR(filep)) { + ret = PTR_ERR(filep); + goto err_close_device; + } + + /* + * TODO: add an anon_inode interface to do this. + * Appears to be missing by lack of need rather than + * explicitly prevented. Now there's need. + */ + filep->f_mode |= (FMODE_PREAD | FMODE_PWRITE); + + if (device->group->type == VFIO_NO_IOMMU) + dev_warn(device->dev, "vfio-noiommu device opened by user " + "(%s:%d)\n", current->comm, task_pid_nr(current)); + /* + * On success the ref of device is moved to the file and + * put in vfio_device_fops_release() + */ + return filep; + +err_close_device: + mutex_lock(&device->dev_set->lock); + down_read(&device->group->group_rwsem); + if (device->open_count == 1 && device->ops->close_device) { + device->ops->close_device(device); + + iommu_driver = device->group->container->iommu_driver; + if (iommu_driver && iommu_driver->ops->unregister_device) + iommu_driver->ops->unregister_device( + device->group->container->iommu_data, device); + } +err_undo_count: + up_read(&device->group->group_rwsem); + device->open_count--; + if (device->open_count == 0 && device->kvm) + device->kvm = NULL; + mutex_unlock(&device->dev_set->lock); + module_put(device->dev->driver->owner); +err_unassign_container: + vfio_device_unassign_container(device); + return ERR_PTR(ret); +} + +static int vfio_group_get_device_fd(struct vfio_group *group, char *buf) +{ + struct vfio_device *device; + struct file *filep; + int fdno; + int ret; + + device = vfio_device_get_from_name(group, buf); + if (IS_ERR(device)) + return PTR_ERR(device); + + fdno = get_unused_fd_flags(O_CLOEXEC); + if (fdno < 0) { + ret = fdno; + goto err_put_device; + } + + filep = vfio_device_open(device); + if (IS_ERR(filep)) { + ret = PTR_ERR(filep); + goto err_put_fdno; + } + + fd_install(fdno, filep); + return fdno; + +err_put_fdno: + put_unused_fd(fdno); +err_put_device: + vfio_device_put(device); + return ret; +} + +static long vfio_group_fops_unl_ioctl(struct file *filep, + unsigned int cmd, unsigned long arg) +{ + struct vfio_group *group = filep->private_data; + long ret = -ENOTTY; + + switch (cmd) { + case VFIO_GROUP_GET_STATUS: + { + struct vfio_group_status status; + unsigned long minsz; + + minsz = offsetofend(struct vfio_group_status, flags); + + if (copy_from_user(&status, (void __user *)arg, minsz)) + return -EFAULT; + + if (status.argsz < minsz) + return -EINVAL; + + status.flags = 0; + + down_read(&group->group_rwsem); + if (group->container) + status.flags |= VFIO_GROUP_FLAGS_CONTAINER_SET | + VFIO_GROUP_FLAGS_VIABLE; + else if (!iommu_group_dma_owner_claimed(group->iommu_group)) + status.flags |= VFIO_GROUP_FLAGS_VIABLE; + up_read(&group->group_rwsem); + + if (copy_to_user((void __user *)arg, &status, minsz)) + return -EFAULT; + + ret = 0; + break; + } + case VFIO_GROUP_SET_CONTAINER: + { + int fd; + + if (get_user(fd, (int __user *)arg)) + return -EFAULT; + + if (fd < 0) + return -EINVAL; + + down_write(&group->group_rwsem); + ret = vfio_group_set_container(group, fd); + up_write(&group->group_rwsem); + break; + } + case VFIO_GROUP_UNSET_CONTAINER: + down_write(&group->group_rwsem); + ret = vfio_group_unset_container(group); + up_write(&group->group_rwsem); + break; + case VFIO_GROUP_GET_DEVICE_FD: + { + char *buf; + + buf = strndup_user((const char __user *)arg, PAGE_SIZE); + if (IS_ERR(buf)) + return PTR_ERR(buf); + + ret = vfio_group_get_device_fd(group, buf); + kfree(buf); + break; + } + } + + return ret; +} + +static int vfio_group_fops_open(struct inode *inode, struct file *filep) +{ + struct vfio_group *group = + container_of(inode->i_cdev, struct vfio_group, cdev); + int ret; + + down_write(&group->group_rwsem); + + /* users can be zero if this races with vfio_group_put() */ + if (!refcount_inc_not_zero(&group->users)) { + ret = -ENODEV; + goto err_unlock; + } + + if (group->type == VFIO_NO_IOMMU && !capable(CAP_SYS_RAWIO)) { + ret = -EPERM; + goto err_put; + } + + /* + * Do we need multiple instances of the group open? Seems not. + */ + if (group->opened_file) { + ret = -EBUSY; + goto err_put; + } + group->opened_file = filep; + filep->private_data = group; + + up_write(&group->group_rwsem); + return 0; +err_put: + vfio_group_put(group); +err_unlock: + up_write(&group->group_rwsem); + return ret; +} + +static int vfio_group_fops_release(struct inode *inode, struct file *filep) +{ + struct vfio_group *group = filep->private_data; + + filep->private_data = NULL; + + down_write(&group->group_rwsem); + /* + * Device FDs hold a group file reference, therefore the group release + * is only called when there are no open devices. + */ + WARN_ON(group->notifier.head); + if (group->container) { + WARN_ON(group->container_users != 1); + __vfio_group_unset_container(group); + } + group->opened_file = NULL; + up_write(&group->group_rwsem); + + vfio_group_put(group); + + return 0; +} + +static const struct file_operations vfio_group_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = vfio_group_fops_unl_ioctl, + .compat_ioctl = compat_ptr_ioctl, + .open = vfio_group_fops_open, + .release = vfio_group_fops_release, +}; + +/* + * VFIO Device fd + */ +static int vfio_device_fops_release(struct inode *inode, struct file *filep) +{ + struct vfio_device *device = filep->private_data; + struct vfio_iommu_driver *iommu_driver; + + mutex_lock(&device->dev_set->lock); + vfio_assert_device_open(device); + down_read(&device->group->group_rwsem); + if (device->open_count == 1 && device->ops->close_device) + device->ops->close_device(device); + + iommu_driver = device->group->container->iommu_driver; + if (iommu_driver && iommu_driver->ops->unregister_device) + iommu_driver->ops->unregister_device( + device->group->container->iommu_data, device); + up_read(&device->group->group_rwsem); + device->open_count--; + if (device->open_count == 0) + device->kvm = NULL; + mutex_unlock(&device->dev_set->lock); + + module_put(device->dev->driver->owner); + + vfio_device_unassign_container(device); + + vfio_device_put(device); + + return 0; +} + +/* + * vfio_mig_get_next_state - Compute the next step in the FSM + * @cur_fsm - The current state the device is in + * @new_fsm - The target state to reach + * @next_fsm - Pointer to the next step to get to new_fsm + * + * Return 0 upon success, otherwise -errno + * Upon success the next step in the state progression between cur_fsm and + * new_fsm will be set in next_fsm. + * + * This breaks down requests for combination transitions into smaller steps and + * returns the next step to get to new_fsm. The function may need to be called + * multiple times before reaching new_fsm. + * + */ +int vfio_mig_get_next_state(struct vfio_device *device, + enum vfio_device_mig_state cur_fsm, + enum vfio_device_mig_state new_fsm, + enum vfio_device_mig_state *next_fsm) +{ + enum { VFIO_DEVICE_NUM_STATES = VFIO_DEVICE_STATE_RUNNING_P2P + 1 }; + /* + * The coding in this table requires the driver to implement the + * following FSM arcs: + * RESUMING -> STOP + * STOP -> RESUMING + * STOP -> STOP_COPY + * STOP_COPY -> STOP + * + * If P2P is supported then the driver must also implement these FSM + * arcs: + * RUNNING -> RUNNING_P2P + * RUNNING_P2P -> RUNNING + * RUNNING_P2P -> STOP + * STOP -> RUNNING_P2P + * Without P2P the driver must implement: + * RUNNING -> STOP + * STOP -> RUNNING + * + * The coding will step through multiple states for some combination + * transitions; if all optional features are supported, this means the + * following ones: + * RESUMING -> STOP -> RUNNING_P2P + * RESUMING -> STOP -> RUNNING_P2P -> RUNNING + * RESUMING -> STOP -> STOP_COPY + * RUNNING -> RUNNING_P2P -> STOP + * RUNNING -> RUNNING_P2P -> STOP -> RESUMING + * RUNNING -> RUNNING_P2P -> STOP -> STOP_COPY + * RUNNING_P2P -> STOP -> RESUMING + * RUNNING_P2P -> STOP -> STOP_COPY + * STOP -> RUNNING_P2P -> RUNNING + * STOP_COPY -> STOP -> RESUMING + * STOP_COPY -> STOP -> RUNNING_P2P + * STOP_COPY -> STOP -> RUNNING_P2P -> RUNNING + */ + static const u8 vfio_from_fsm_table[VFIO_DEVICE_NUM_STATES][VFIO_DEVICE_NUM_STATES] = { + [VFIO_DEVICE_STATE_STOP] = { + [VFIO_DEVICE_STATE_STOP] = VFIO_DEVICE_STATE_STOP, + [VFIO_DEVICE_STATE_RUNNING] = VFIO_DEVICE_STATE_RUNNING_P2P, + [VFIO_DEVICE_STATE_STOP_COPY] = VFIO_DEVICE_STATE_STOP_COPY, + [VFIO_DEVICE_STATE_RESUMING] = VFIO_DEVICE_STATE_RESUMING, + [VFIO_DEVICE_STATE_RUNNING_P2P] = VFIO_DEVICE_STATE_RUNNING_P2P, + [VFIO_DEVICE_STATE_ERROR] = VFIO_DEVICE_STATE_ERROR, + }, + [VFIO_DEVICE_STATE_RUNNING] = { + [VFIO_DEVICE_STATE_STOP] = VFIO_DEVICE_STATE_RUNNING_P2P, + [VFIO_DEVICE_STATE_RUNNING] = VFIO_DEVICE_STATE_RUNNING, + [VFIO_DEVICE_STATE_STOP_COPY] = VFIO_DEVICE_STATE_RUNNING_P2P, + [VFIO_DEVICE_STATE_RESUMING] = VFIO_DEVICE_STATE_RUNNING_P2P, + [VFIO_DEVICE_STATE_RUNNING_P2P] = VFIO_DEVICE_STATE_RUNNING_P2P, + [VFIO_DEVICE_STATE_ERROR] = VFIO_DEVICE_STATE_ERROR, + }, + [VFIO_DEVICE_STATE_STOP_COPY] = { + [VFIO_DEVICE_STATE_STOP] = VFIO_DEVICE_STATE_STOP, + [VFIO_DEVICE_STATE_RUNNING] = VFIO_DEVICE_STATE_STOP, + [VFIO_DEVICE_STATE_STOP_COPY] = VFIO_DEVICE_STATE_STOP_COPY, + [VFIO_DEVICE_STATE_RESUMING] = VFIO_DEVICE_STATE_STOP, + [VFIO_DEVICE_STATE_RUNNING_P2P] = VFIO_DEVICE_STATE_STOP, + [VFIO_DEVICE_STATE_ERROR] = VFIO_DEVICE_STATE_ERROR, + }, + [VFIO_DEVICE_STATE_RESUMING] = { + [VFIO_DEVICE_STATE_STOP] = VFIO_DEVICE_STATE_STOP, + [VFIO_DEVICE_STATE_RUNNING] = VFIO_DEVICE_STATE_STOP, + [VFIO_DEVICE_STATE_STOP_COPY] = VFIO_DEVICE_STATE_STOP, + [VFIO_DEVICE_STATE_RESUMING] = VFIO_DEVICE_STATE_RESUMING, + [VFIO_DEVICE_STATE_RUNNING_P2P] = VFIO_DEVICE_STATE_STOP, + [VFIO_DEVICE_STATE_ERROR] = VFIO_DEVICE_STATE_ERROR, + }, + [VFIO_DEVICE_STATE_RUNNING_P2P] = { + [VFIO_DEVICE_STATE_STOP] = VFIO_DEVICE_STATE_STOP, + [VFIO_DEVICE_STATE_RUNNING] = VFIO_DEVICE_STATE_RUNNING, + [VFIO_DEVICE_STATE_STOP_COPY] = VFIO_DEVICE_STATE_STOP, + [VFIO_DEVICE_STATE_RESUMING] = VFIO_DEVICE_STATE_STOP, + [VFIO_DEVICE_STATE_RUNNING_P2P] = VFIO_DEVICE_STATE_RUNNING_P2P, + [VFIO_DEVICE_STATE_ERROR] = VFIO_DEVICE_STATE_ERROR, + }, + [VFIO_DEVICE_STATE_ERROR] = { + [VFIO_DEVICE_STATE_STOP] = VFIO_DEVICE_STATE_ERROR, + [VFIO_DEVICE_STATE_RUNNING] = VFIO_DEVICE_STATE_ERROR, + [VFIO_DEVICE_STATE_STOP_COPY] = VFIO_DEVICE_STATE_ERROR, + [VFIO_DEVICE_STATE_RESUMING] = VFIO_DEVICE_STATE_ERROR, + [VFIO_DEVICE_STATE_RUNNING_P2P] = VFIO_DEVICE_STATE_ERROR, + [VFIO_DEVICE_STATE_ERROR] = VFIO_DEVICE_STATE_ERROR, + }, + }; + + static const unsigned int state_flags_table[VFIO_DEVICE_NUM_STATES] = { + [VFIO_DEVICE_STATE_STOP] = VFIO_MIGRATION_STOP_COPY, + [VFIO_DEVICE_STATE_RUNNING] = VFIO_MIGRATION_STOP_COPY, + [VFIO_DEVICE_STATE_STOP_COPY] = VFIO_MIGRATION_STOP_COPY, + [VFIO_DEVICE_STATE_RESUMING] = VFIO_MIGRATION_STOP_COPY, + [VFIO_DEVICE_STATE_RUNNING_P2P] = + VFIO_MIGRATION_STOP_COPY | VFIO_MIGRATION_P2P, + [VFIO_DEVICE_STATE_ERROR] = ~0U, + }; + + if (WARN_ON(cur_fsm >= ARRAY_SIZE(vfio_from_fsm_table) || + (state_flags_table[cur_fsm] & device->migration_flags) != + state_flags_table[cur_fsm])) + return -EINVAL; + + if (new_fsm >= ARRAY_SIZE(vfio_from_fsm_table) || + (state_flags_table[new_fsm] & device->migration_flags) != + state_flags_table[new_fsm]) + return -EINVAL; + + /* + * Arcs touching optional and unsupported states are skipped over. The + * driver will instead see an arc from the original state to the next + * logical state, as per the above comment. + */ + *next_fsm = vfio_from_fsm_table[cur_fsm][new_fsm]; + while ((state_flags_table[*next_fsm] & device->migration_flags) != + state_flags_table[*next_fsm]) + *next_fsm = vfio_from_fsm_table[*next_fsm][new_fsm]; + + return (*next_fsm != VFIO_DEVICE_STATE_ERROR) ? 0 : -EINVAL; +} +EXPORT_SYMBOL_GPL(vfio_mig_get_next_state); + +/* + * Convert the drivers's struct file into a FD number and return it to userspace + */ +static int vfio_ioct_mig_return_fd(struct file *filp, void __user *arg, + struct vfio_device_feature_mig_state *mig) +{ + int ret; + int fd; + + fd = get_unused_fd_flags(O_CLOEXEC); + if (fd < 0) { + ret = fd; + goto out_fput; + } + + mig->data_fd = fd; + if (copy_to_user(arg, mig, sizeof(*mig))) { + ret = -EFAULT; + goto out_put_unused; + } + fd_install(fd, filp); + return 0; + +out_put_unused: + put_unused_fd(fd); +out_fput: + fput(filp); + return ret; +} + +static int +vfio_ioctl_device_feature_mig_device_state(struct vfio_device *device, + u32 flags, void __user *arg, + size_t argsz) +{ + size_t minsz = + offsetofend(struct vfio_device_feature_mig_state, data_fd); + struct vfio_device_feature_mig_state mig; + struct file *filp = NULL; + int ret; + + if (!device->mig_ops) + return -ENOTTY; + + ret = vfio_check_feature(flags, argsz, + VFIO_DEVICE_FEATURE_SET | + VFIO_DEVICE_FEATURE_GET, + sizeof(mig)); + if (ret != 1) + return ret; + + if (copy_from_user(&mig, arg, minsz)) + return -EFAULT; + + if (flags & VFIO_DEVICE_FEATURE_GET) { + enum vfio_device_mig_state curr_state; + + ret = device->mig_ops->migration_get_state(device, + &curr_state); + if (ret) + return ret; + mig.device_state = curr_state; + goto out_copy; + } + + /* Handle the VFIO_DEVICE_FEATURE_SET */ + filp = device->mig_ops->migration_set_state(device, mig.device_state); + if (IS_ERR(filp) || !filp) + goto out_copy; + + return vfio_ioct_mig_return_fd(filp, arg, &mig); +out_copy: + mig.data_fd = -1; + if (copy_to_user(arg, &mig, sizeof(mig))) + return -EFAULT; + if (IS_ERR(filp)) + return PTR_ERR(filp); + return 0; +} + +static int vfio_ioctl_device_feature_migration(struct vfio_device *device, + u32 flags, void __user *arg, + size_t argsz) +{ + struct vfio_device_feature_migration mig = { + .flags = device->migration_flags, + }; + int ret; + + if (!device->mig_ops) + return -ENOTTY; + + ret = vfio_check_feature(flags, argsz, VFIO_DEVICE_FEATURE_GET, + sizeof(mig)); + if (ret != 1) + return ret; + if (copy_to_user(arg, &mig, sizeof(mig))) + return -EFAULT; + return 0; +} + +static int vfio_ioctl_device_feature(struct vfio_device *device, + struct vfio_device_feature __user *arg) +{ + size_t minsz = offsetofend(struct vfio_device_feature, flags); + struct vfio_device_feature feature; + + if (copy_from_user(&feature, arg, minsz)) + return -EFAULT; + + if (feature.argsz < minsz) + return -EINVAL; + + /* Check unknown flags */ + if (feature.flags & + ~(VFIO_DEVICE_FEATURE_MASK | VFIO_DEVICE_FEATURE_SET | + VFIO_DEVICE_FEATURE_GET | VFIO_DEVICE_FEATURE_PROBE)) + return -EINVAL; + + /* GET & SET are mutually exclusive except with PROBE */ + if (!(feature.flags & VFIO_DEVICE_FEATURE_PROBE) && + (feature.flags & VFIO_DEVICE_FEATURE_SET) && + (feature.flags & VFIO_DEVICE_FEATURE_GET)) + return -EINVAL; + + switch (feature.flags & VFIO_DEVICE_FEATURE_MASK) { + case VFIO_DEVICE_FEATURE_MIGRATION: + return vfio_ioctl_device_feature_migration( + device, feature.flags, arg->data, + feature.argsz - minsz); + case VFIO_DEVICE_FEATURE_MIG_DEVICE_STATE: + return vfio_ioctl_device_feature_mig_device_state( + device, feature.flags, arg->data, + feature.argsz - minsz); + default: + if (unlikely(!device->ops->device_feature)) + return -EINVAL; + return device->ops->device_feature(device, feature.flags, + arg->data, + feature.argsz - minsz); + } +} + +static long vfio_device_fops_unl_ioctl(struct file *filep, + unsigned int cmd, unsigned long arg) +{ + struct vfio_device *device = filep->private_data; + + switch (cmd) { + case VFIO_DEVICE_FEATURE: + return vfio_ioctl_device_feature(device, (void __user *)arg); + default: + if (unlikely(!device->ops->ioctl)) + return -EINVAL; + return device->ops->ioctl(device, cmd, arg); + } +} + +static ssize_t vfio_device_fops_read(struct file *filep, char __user *buf, + size_t count, loff_t *ppos) +{ + struct vfio_device *device = filep->private_data; + + if (unlikely(!device->ops->read)) + return -EINVAL; + + return device->ops->read(device, buf, count, ppos); +} + +static ssize_t vfio_device_fops_write(struct file *filep, + const char __user *buf, + size_t count, loff_t *ppos) +{ + struct vfio_device *device = filep->private_data; + + if (unlikely(!device->ops->write)) + return -EINVAL; + + return device->ops->write(device, buf, count, ppos); +} + +static int vfio_device_fops_mmap(struct file *filep, struct vm_area_struct *vma) +{ + struct vfio_device *device = filep->private_data; + + if (unlikely(!device->ops->mmap)) + return -EINVAL; + + return device->ops->mmap(device, vma); +} + +static const struct file_operations vfio_device_fops = { + .owner = THIS_MODULE, + .release = vfio_device_fops_release, + .read = vfio_device_fops_read, + .write = vfio_device_fops_write, + .unlocked_ioctl = vfio_device_fops_unl_ioctl, + .compat_ioctl = compat_ptr_ioctl, + .mmap = vfio_device_fops_mmap, +}; + +/** + * vfio_file_iommu_group - Return the struct iommu_group for the vfio group file + * @file: VFIO group file + * + * The returned iommu_group is valid as long as a ref is held on the file. + */ +struct iommu_group *vfio_file_iommu_group(struct file *file) +{ + struct vfio_group *group = file->private_data; + + if (file->f_op != &vfio_group_fops) + return NULL; + return group->iommu_group; +} +EXPORT_SYMBOL_GPL(vfio_file_iommu_group); + +/** + * vfio_file_enforced_coherent - True if the DMA associated with the VFIO file + * is always CPU cache coherent + * @file: VFIO group file + * + * Enforced coherency means that the IOMMU ignores things like the PCIe no-snoop + * bit in DMA transactions. A return of false indicates that the user has + * rights to access additional instructions such as wbinvd on x86. + */ +bool vfio_file_enforced_coherent(struct file *file) +{ + struct vfio_group *group = file->private_data; + bool ret; + + if (file->f_op != &vfio_group_fops) + return true; + + down_read(&group->group_rwsem); + if (group->container) { + ret = vfio_ioctl_check_extension(group->container, + VFIO_DMA_CC_IOMMU); + } else { + /* + * Since the coherency state is determined only once a container + * is attached the user must do so before they can prove they + * have permission. + */ + ret = true; + } + up_read(&group->group_rwsem); + return ret; +} +EXPORT_SYMBOL_GPL(vfio_file_enforced_coherent); + +/** + * vfio_file_set_kvm - Link a kvm with VFIO drivers + * @file: VFIO group file + * @kvm: KVM to link + * + * When a VFIO device is first opened the KVM will be available in + * device->kvm if one was associated with the group. + */ +void vfio_file_set_kvm(struct file *file, struct kvm *kvm) +{ + struct vfio_group *group = file->private_data; + + if (file->f_op != &vfio_group_fops) + return; + + down_write(&group->group_rwsem); + group->kvm = kvm; + up_write(&group->group_rwsem); +} +EXPORT_SYMBOL_GPL(vfio_file_set_kvm); + +/** + * vfio_file_has_dev - True if the VFIO file is a handle for device + * @file: VFIO file to check + * @device: Device that must be part of the file + * + * Returns true if given file has permission to manipulate the given device. + */ +bool vfio_file_has_dev(struct file *file, struct vfio_device *device) +{ + struct vfio_group *group = file->private_data; + + if (file->f_op != &vfio_group_fops) + return false; + + return group == device->group; +} +EXPORT_SYMBOL_GPL(vfio_file_has_dev); + +/* + * Sub-module support + */ +/* + * Helper for managing a buffer of info chain capabilities, allocate or + * reallocate a buffer with additional @size, filling in @id and @version + * of the capability. A pointer to the new capability is returned. + * + * NB. The chain is based at the head of the buffer, so new entries are + * added to the tail, vfio_info_cap_shift() should be called to fixup the + * next offsets prior to copying to the user buffer. + */ +struct vfio_info_cap_header *vfio_info_cap_add(struct vfio_info_cap *caps, + size_t size, u16 id, u16 version) +{ + void *buf; + struct vfio_info_cap_header *header, *tmp; + + buf = krealloc(caps->buf, caps->size + size, GFP_KERNEL); + if (!buf) { + kfree(caps->buf); + caps->buf = NULL; + caps->size = 0; + return ERR_PTR(-ENOMEM); + } + + caps->buf = buf; + header = buf + caps->size; + + /* Eventually copied to user buffer, zero */ + memset(header, 0, size); + + header->id = id; + header->version = version; + + /* Add to the end of the capability chain */ + for (tmp = buf; tmp->next; tmp = buf + tmp->next) + ; /* nothing */ + + tmp->next = caps->size; + caps->size += size; + + return header; +} +EXPORT_SYMBOL_GPL(vfio_info_cap_add); + +void vfio_info_cap_shift(struct vfio_info_cap *caps, size_t offset) +{ + struct vfio_info_cap_header *tmp; + void *buf = (void *)caps->buf; + + for (tmp = buf; tmp->next; tmp = buf + tmp->next - offset) + tmp->next += offset; +} +EXPORT_SYMBOL(vfio_info_cap_shift); + +int vfio_info_add_capability(struct vfio_info_cap *caps, + struct vfio_info_cap_header *cap, size_t size) +{ + struct vfio_info_cap_header *header; + + header = vfio_info_cap_add(caps, size, cap->id, cap->version); + if (IS_ERR(header)) + return PTR_ERR(header); + + memcpy(header + 1, cap + 1, size - sizeof(*header)); + + return 0; +} +EXPORT_SYMBOL(vfio_info_add_capability); + +int vfio_set_irqs_validate_and_prepare(struct vfio_irq_set *hdr, int num_irqs, + int max_irq_type, size_t *data_size) +{ + unsigned long minsz; + size_t size; + + minsz = offsetofend(struct vfio_irq_set, count); + + if ((hdr->argsz < minsz) || (hdr->index >= max_irq_type) || + (hdr->count >= (U32_MAX - hdr->start)) || + (hdr->flags & ~(VFIO_IRQ_SET_DATA_TYPE_MASK | + VFIO_IRQ_SET_ACTION_TYPE_MASK))) + return -EINVAL; + + if (data_size) + *data_size = 0; + + if (hdr->start >= num_irqs || hdr->start + hdr->count > num_irqs) + return -EINVAL; + + switch (hdr->flags & VFIO_IRQ_SET_DATA_TYPE_MASK) { + case VFIO_IRQ_SET_DATA_NONE: + size = 0; + break; + case VFIO_IRQ_SET_DATA_BOOL: + size = sizeof(uint8_t); + break; + case VFIO_IRQ_SET_DATA_EVENTFD: + size = sizeof(int32_t); + break; + default: + return -EINVAL; + } + + if (size) { + if (hdr->argsz - minsz < hdr->count * size) + return -EINVAL; + + if (!data_size) + return -EINVAL; + + *data_size = hdr->count * size; + } + + return 0; +} +EXPORT_SYMBOL(vfio_set_irqs_validate_and_prepare); + +/* + * Pin contiguous user pages and return their associated host pages for local + * domain only. + * @device [in] : device + * @iova [in] : starting IOVA of user pages to be pinned. + * @npage [in] : count of pages to be pinned. This count should not + * be greater than VFIO_PIN_PAGES_MAX_ENTRIES. + * @prot [in] : protection flags + * @pages[out] : array of host pages + * Return error or number of pages pinned. + */ +int vfio_pin_pages(struct vfio_device *device, dma_addr_t iova, + int npage, int prot, struct page **pages) +{ + struct vfio_container *container; + struct vfio_group *group = device->group; + struct vfio_iommu_driver *driver; + int ret; + + if (!pages || !npage || !vfio_assert_device_open(device)) + return -EINVAL; + + if (npage > VFIO_PIN_PAGES_MAX_ENTRIES) + return -E2BIG; + + if (group->dev_counter > 1) + return -EINVAL; + + /* group->container cannot change while a vfio device is open */ + container = group->container; + driver = container->iommu_driver; + if (likely(driver && driver->ops->pin_pages)) + ret = driver->ops->pin_pages(container->iommu_data, + group->iommu_group, iova, + npage, prot, pages); + else + ret = -ENOTTY; + + return ret; +} +EXPORT_SYMBOL(vfio_pin_pages); + +/* + * Unpin contiguous host pages for local domain only. + * @device [in] : device + * @iova [in] : starting address of user pages to be unpinned. + * @npage [in] : count of pages to be unpinned. This count should not + * be greater than VFIO_PIN_PAGES_MAX_ENTRIES. + */ +void vfio_unpin_pages(struct vfio_device *device, dma_addr_t iova, int npage) +{ + struct vfio_container *container; + struct vfio_iommu_driver *driver; + + if (WARN_ON(npage <= 0 || npage > VFIO_PIN_PAGES_MAX_ENTRIES)) + return; + + if (WARN_ON(!vfio_assert_device_open(device))) + return; + + /* group->container cannot change while a vfio device is open */ + container = device->group->container; + driver = container->iommu_driver; + + driver->ops->unpin_pages(container->iommu_data, iova, npage); +} +EXPORT_SYMBOL(vfio_unpin_pages); + +/* + * This interface allows the CPUs to perform some sort of virtual DMA on + * behalf of the device. + * + * CPUs read/write from/into a range of IOVAs pointing to user space memory + * into/from a kernel buffer. + * + * As the read/write of user space memory is conducted via the CPUs and is + * not a real device DMA, it is not necessary to pin the user space memory. + * + * @device [in] : VFIO device + * @iova [in] : base IOVA of a user space buffer + * @data [in] : pointer to kernel buffer + * @len [in] : kernel buffer length + * @write : indicate read or write + * Return error code on failure or 0 on success. + */ +int vfio_dma_rw(struct vfio_device *device, dma_addr_t iova, void *data, + size_t len, bool write) +{ + struct vfio_container *container; + struct vfio_iommu_driver *driver; + int ret = 0; + + if (!data || len <= 0 || !vfio_assert_device_open(device)) + return -EINVAL; + + /* group->container cannot change while a vfio device is open */ + container = device->group->container; + driver = container->iommu_driver; + + if (likely(driver && driver->ops->dma_rw)) + ret = driver->ops->dma_rw(container->iommu_data, + iova, data, len, write); + else + ret = -ENOTTY; + return ret; +} +EXPORT_SYMBOL(vfio_dma_rw); + +/* + * Module/class support + */ +static char *vfio_devnode(struct device *dev, umode_t *mode) +{ + return kasprintf(GFP_KERNEL, "vfio/%s", dev_name(dev)); +} + +static struct miscdevice vfio_dev = { + .minor = VFIO_MINOR, + .name = "vfio", + .fops = &vfio_fops, + .nodename = "vfio/vfio", + .mode = S_IRUGO | S_IWUGO, +}; + +static int __init vfio_init(void) +{ + int ret; + + ida_init(&vfio.group_ida); + mutex_init(&vfio.group_lock); + mutex_init(&vfio.iommu_drivers_lock); + INIT_LIST_HEAD(&vfio.group_list); + INIT_LIST_HEAD(&vfio.iommu_drivers_list); + + ret = misc_register(&vfio_dev); + if (ret) { + pr_err("vfio: misc device register failed\n"); + return ret; + } + + /* /dev/vfio/$GROUP */ + vfio.class = class_create(THIS_MODULE, "vfio"); + if (IS_ERR(vfio.class)) { + ret = PTR_ERR(vfio.class); + goto err_class; + } + + vfio.class->devnode = vfio_devnode; + + ret = alloc_chrdev_region(&vfio.group_devt, 0, MINORMASK + 1, "vfio"); + if (ret) + goto err_alloc_chrdev; + +#ifdef CONFIG_VFIO_NOIOMMU + ret = vfio_register_iommu_driver(&vfio_noiommu_ops); +#endif + if (ret) + goto err_driver_register; + + pr_info(DRIVER_DESC " version: " DRIVER_VERSION "\n"); + return 0; + +err_driver_register: + unregister_chrdev_region(vfio.group_devt, MINORMASK + 1); +err_alloc_chrdev: + class_destroy(vfio.class); + vfio.class = NULL; +err_class: + misc_deregister(&vfio_dev); + return ret; +} + +static void __exit vfio_cleanup(void) +{ + WARN_ON(!list_empty(&vfio.group_list)); + +#ifdef CONFIG_VFIO_NOIOMMU + vfio_unregister_iommu_driver(&vfio_noiommu_ops); +#endif + ida_destroy(&vfio.group_ida); + unregister_chrdev_region(vfio.group_devt, MINORMASK + 1); + class_destroy(vfio.class); + vfio.class = NULL; + misc_deregister(&vfio_dev); + xa_destroy(&vfio_device_set_xa); +} + +module_init(vfio_init); +module_exit(vfio_cleanup); + +MODULE_VERSION(DRIVER_VERSION); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_ALIAS_MISCDEV(VFIO_MINOR); +MODULE_ALIAS("devname:vfio/vfio"); +MODULE_SOFTDEP("post: vfio_iommu_type1 vfio_iommu_spapr_tce"); -- cgit v1.2.3 From 03c4cd6f89e074a51e289eb9129ac646f0f2bd29 Mon Sep 17 00:00:00 2001 From: Zeng Jingxiang Date: Thu, 28 Jul 2022 18:01:01 +0800 Subject: rtc: spear: set range max In the commit f395e1d3b28d7c2c67b73bd467c4fb79523e1c65 ("rtc: spear: set range"), the value of RTC_TIMESTAMP_END_9999 was incorrectly set to range_min. 390 config->rtc->range_min = RTC_TIMESTAMP_BEGIN_0000; 391 config->rtc->range_max = RTC_TIMESTAMP_END_9999; Fixes: f395e1d3b28d ("rtc: spear: set range") Signed-off-by: Zeng Jingxiang Acked-by: Viresh Kumar Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20220728100101.1906801-1-zengjx95@gmail.com --- drivers/rtc/rtc-spear.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/rtc/rtc-spear.c b/drivers/rtc/rtc-spear.c index d4777b01ab22..736fe535cd45 100644 --- a/drivers/rtc/rtc-spear.c +++ b/drivers/rtc/rtc-spear.c @@ -388,7 +388,7 @@ static int spear_rtc_probe(struct platform_device *pdev) config->rtc->ops = &spear_rtc_ops; config->rtc->range_min = RTC_TIMESTAMP_BEGIN_0000; - config->rtc->range_min = RTC_TIMESTAMP_END_9999; + config->rtc->range_max = RTC_TIMESTAMP_END_9999; status = devm_rtc_register_device(config->rtc); if (status) -- cgit v1.2.3 From f71c70df416f4d49a9cf11d6132f6aaba0e2f65c Mon Sep 17 00:00:00 2001 From: Christian Colglazier Date: Tue, 9 Aug 2022 14:02:41 +0930 Subject: ALSA: scarlett2: Add Focusrite Clarett+ 8Pre support The Focusrite Clarett+ 8Pre uses the same protocol as the Scarlett Gen 2 and Gen 3 product range. This patch adds support for the Clarett+ 8Pre by adding appropriate entries to the scarlett2 driver. The Clarett+ 2Pre and 4Pre, and the Clarett USB product line presumably use the same protocol as well, so support for them can easily be added if someone can test. Signed-off-by: Christian Colglazier Signed-off-by: Geoffrey D. Bennett Link: https://lore.kernel.org/r/20220809043241.GA2749152@m.b4.vu Signed-off-by: Takashi Iwai --- sound/usb/mixer_quirks.c | 1 + sound/usb/mixer_scarlett_gen2.c | 91 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 90 insertions(+), 2 deletions(-) diff --git a/sound/usb/mixer_quirks.c b/sound/usb/mixer_quirks.c index c06d6dfa8139..ab0d459f4271 100644 --- a/sound/usb/mixer_quirks.c +++ b/sound/usb/mixer_quirks.c @@ -3420,6 +3420,7 @@ int snd_usb_mixer_apply_create_quirk(struct usb_mixer_interface *mixer) case USB_ID(0x1235, 0x8213): /* Focusrite Scarlett 8i6 3rd Gen */ case USB_ID(0x1235, 0x8214): /* Focusrite Scarlett 18i8 3rd Gen */ case USB_ID(0x1235, 0x8215): /* Focusrite Scarlett 18i20 3rd Gen */ + case USB_ID(0x1235, 0x820c): /* Focusrite Clarett+ 8Pre */ err = snd_scarlett_gen2_init(mixer); break; diff --git a/sound/usb/mixer_scarlett_gen2.c b/sound/usb/mixer_scarlett_gen2.c index 69a2cd429ee2..9d11bb08667e 100644 --- a/sound/usb/mixer_scarlett_gen2.c +++ b/sound/usb/mixer_scarlett_gen2.c @@ -1,13 +1,15 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Focusrite Scarlett Gen 2/3 Driver for ALSA + * Focusrite Scarlett Gen 2/3 and Clarett+ Driver for ALSA * * Supported models: * - 6i6/18i8/18i20 Gen 2 * - Solo/2i2/4i4/8i6/18i8/18i20 Gen 3 + * - Clarett+ 8Pre * * Copyright (c) 2018-2022 by Geoffrey D. Bennett * Copyright (c) 2020-2021 by Vladimir Sadovnikov + * Copyright (c) 2022 by Christian Colglazier * * Based on the Scarlett (Gen 1) Driver for ALSA: * @@ -51,6 +53,9 @@ * Support for phantom power, direct monitoring, speaker switching, * and talkback added in May-June 2021. * + * Support for Clarett+ 8Pre added in Aug 2022 by Christian + * Colglazier. + * * This ALSA mixer gives access to (model-dependent): * - input, output, mixer-matrix muxes * - mixer-matrix gain stages @@ -203,7 +208,8 @@ enum { SCARLETT2_CONFIG_SET_NO_MIXER = 0, SCARLETT2_CONFIG_SET_GEN_2 = 1, SCARLETT2_CONFIG_SET_GEN_3 = 2, - SCARLETT2_CONFIG_SET_COUNT = 3 + SCARLETT2_CONFIG_SET_CLARETT = 3, + SCARLETT2_CONFIG_SET_COUNT = 4 }; /* Hardware port types: @@ -841,6 +847,61 @@ static const struct scarlett2_device_info s18i20_gen3_info = { } }, }; +static const struct scarlett2_device_info clarett_8pre_info = { + .usb_id = USB_ID(0x1235, 0x820c), + + .config_set = SCARLETT2_CONFIG_SET_CLARETT, + .line_out_hw_vol = 1, + .level_input_count = 2, + .air_input_count = 8, + + .line_out_descrs = { + "Monitor L", + "Monitor R", + NULL, + NULL, + NULL, + NULL, + "Headphones 1 L", + "Headphones 1 R", + "Headphones 2 L", + "Headphones 2 R", + }, + + .port_count = { + [SCARLETT2_PORT_TYPE_NONE] = { 1, 0 }, + [SCARLETT2_PORT_TYPE_ANALOGUE] = { 8, 10 }, + [SCARLETT2_PORT_TYPE_SPDIF] = { 2, 2 }, + [SCARLETT2_PORT_TYPE_ADAT] = { 8, 8 }, + [SCARLETT2_PORT_TYPE_MIX] = { 10, 18 }, + [SCARLETT2_PORT_TYPE_PCM] = { 20, 18 }, + }, + + .mux_assignment = { { + { SCARLETT2_PORT_TYPE_PCM, 0, 18 }, + { SCARLETT2_PORT_TYPE_ANALOGUE, 0, 10 }, + { SCARLETT2_PORT_TYPE_SPDIF, 0, 2 }, + { SCARLETT2_PORT_TYPE_ADAT, 0, 8 }, + { SCARLETT2_PORT_TYPE_MIX, 0, 18 }, + { SCARLETT2_PORT_TYPE_NONE, 0, 8 }, + { 0, 0, 0 }, + }, { + { SCARLETT2_PORT_TYPE_PCM, 0, 14 }, + { SCARLETT2_PORT_TYPE_ANALOGUE, 0, 10 }, + { SCARLETT2_PORT_TYPE_SPDIF, 0, 2 }, + { SCARLETT2_PORT_TYPE_ADAT, 0, 4 }, + { SCARLETT2_PORT_TYPE_MIX, 0, 18 }, + { SCARLETT2_PORT_TYPE_NONE, 0, 8 }, + { 0, 0, 0 }, + }, { + { SCARLETT2_PORT_TYPE_PCM, 0, 12 }, + { SCARLETT2_PORT_TYPE_ANALOGUE, 0, 10 }, + { SCARLETT2_PORT_TYPE_SPDIF, 0, 2 }, + { SCARLETT2_PORT_TYPE_NONE, 0, 22 }, + { 0, 0, 0 }, + } }, +}; + static const struct scarlett2_device_info *scarlett2_devices[] = { /* Supported Gen 2 devices */ &s6i6_gen2_info, @@ -855,6 +916,9 @@ static const struct scarlett2_device_info *scarlett2_devices[] = { &s18i8_gen3_info, &s18i20_gen3_info, + /* Supported Clarett+ devices */ + &clarett_8pre_info, + /* End of list */ NULL }; @@ -1047,6 +1111,29 @@ static const struct scarlett2_config [SCARLETT2_CONFIG_TALKBACK_MAP] = { .offset = 0xb0, .size = 16, .activate = 10 }, + +/* Clarett+ 8Pre */ +}, { + [SCARLETT2_CONFIG_DIM_MUTE] = { + .offset = 0x31, .size = 8, .activate = 2 }, + + [SCARLETT2_CONFIG_LINE_OUT_VOLUME] = { + .offset = 0x34, .size = 16, .activate = 1 }, + + [SCARLETT2_CONFIG_MUTE_SWITCH] = { + .offset = 0x5c, .size = 8, .activate = 1 }, + + [SCARLETT2_CONFIG_SW_HW_SWITCH] = { + .offset = 0x66, .size = 8, .activate = 3 }, + + [SCARLETT2_CONFIG_LEVEL_SWITCH] = { + .offset = 0x7c, .size = 8, .activate = 7 }, + + [SCARLETT2_CONFIG_AIR_SWITCH] = { + .offset = 0x95, .size = 8, .activate = 8 }, + + [SCARLETT2_CONFIG_STANDALONE_SWITCH] = { + .offset = 0x8d, .size = 8, .activate = 6 }, } }; /* proprietary request/response format */ -- cgit v1.2.3 From 6bc2906253e723d1ab1acc652b55b83e286bfec2 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Tue, 9 Aug 2022 09:32:59 +0200 Subject: ALSA: usb-audio: More comprehensive mixer map for ASUS ROG Zenith II ASUS ROG Zenith II has two USB interfaces, one for the front headphone and another for the rest I/O. Currently we provided the mixer mapping for the latter but with an incomplete form. This patch corrects and provides more comprehensive mixer mapping, as well as providing the proper device names for both the front headphone and main audio. BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=211005 Fixes: 2a48218f8e23 ("ALSA: usb-audio: Add mixer workaround for TRX40 and co") Link: https://lore.kernel.org/r/20220809073259.18849-1-tiwai@suse.de Signed-off-by: Takashi Iwai --- sound/usb/card.c | 8 ++++++++ sound/usb/mixer_maps.c | 34 +++++++++++++++++++++++++--------- 2 files changed, 33 insertions(+), 9 deletions(-) diff --git a/sound/usb/card.c b/sound/usb/card.c index 0fff96a5d3ab..d356743de2ff 100644 --- a/sound/usb/card.c +++ b/sound/usb/card.c @@ -387,6 +387,14 @@ static const struct usb_audio_device_name usb_audio_names[] = { DEVICE_NAME(0x05e1, 0x0408, "Syntek", "STK1160"), DEVICE_NAME(0x05e1, 0x0480, "Hauppauge", "Woodbury"), + /* ASUS ROG Zenith II: this machine has also two devices, one for + * the front headphone and another for the rest + */ + PROFILE_NAME(0x0b05, 0x1915, "ASUS", "Zenith II Front Headphone", + "Zenith-II-Front-Headphone"), + PROFILE_NAME(0x0b05, 0x1916, "ASUS", "Zenith II Main Audio", + "Zenith-II-Main-Audio"), + /* ASUS ROG Strix */ PROFILE_NAME(0x0b05, 0x1917, "Realtek", "ALC1220-VB-DT", "Realtek-ALC1220-VB-Desktop"), diff --git a/sound/usb/mixer_maps.c b/sound/usb/mixer_maps.c index 3c795675f048..f4bd1e8ae4b6 100644 --- a/sound/usb/mixer_maps.c +++ b/sound/usb/mixer_maps.c @@ -374,13 +374,28 @@ static const struct usbmix_name_map corsair_virtuoso_map[] = { { 0 } }; -/* Some mobos shipped with a dummy HD-audio show the invalid GET_MIN/GET_MAX - * response for Input Gain Pad (id=19, control=12) and the connector status - * for SPDIF terminal (id=18). Skip them. - */ -static const struct usbmix_name_map asus_rog_map[] = { - { 18, NULL }, /* OT, connector control */ - { 19, NULL, 12 }, /* FU, Input Gain Pad */ +/* ASUS ROG Zenith II with Realtek ALC1220-VB */ +static const struct usbmix_name_map asus_zenith_ii_map[] = { + { 19, NULL, 12 }, /* FU, Input Gain Pad - broken response, disabled */ + { 16, "Speaker" }, /* OT */ + { 22, "Speaker Playback" }, /* FU */ + { 7, "Line" }, /* IT */ + { 19, "Line Capture" }, /* FU */ + { 8, "Mic" }, /* IT */ + { 20, "Mic Capture" }, /* FU */ + { 9, "Front Mic" }, /* IT */ + { 21, "Front Mic Capture" }, /* FU */ + { 17, "IEC958" }, /* OT */ + { 23, "IEC958 Playback" }, /* FU */ + {} +}; + +static const struct usbmix_connector_map asus_zenith_ii_connector_map[] = { + { 10, 16 }, /* (Back) Speaker */ + { 11, 17 }, /* SPDIF */ + { 13, 7 }, /* Line */ + { 14, 8 }, /* Mic */ + { 15, 9 }, /* Front Mic */ {} }; @@ -611,9 +626,10 @@ static const struct usbmix_ctl_map usbmix_ctl_maps[] = { .map = gigabyte_b450_map, .connector_map = gigabyte_b450_connector_map, }, - { /* ASUS ROG Zenith II */ + { /* ASUS ROG Zenith II (main audio) */ .id = USB_ID(0x0b05, 0x1916), - .map = asus_rog_map, + .map = asus_zenith_ii_map, + .connector_map = asus_zenith_ii_connector_map, }, { /* ASUS ROG Strix */ .id = USB_ID(0x0b05, 0x1917), -- cgit v1.2.3 From 30267718fe2d4dbea49015b022f6f1fe16ca31ab Mon Sep 17 00:00:00 2001 From: Bedant Patnaik Date: Tue, 9 Aug 2022 19:54:55 +0530 Subject: ALSA: hda/realtek: Add a quirk for HP OMEN 15 (8786) mute LED Board ID 8786 seems to be another variant of the Omen 15 that needs ALC285_FIXUP_HP_MUTE_LED for working mute LED. Signed-off-by: Bedant Patnaik Cc: Link: https://lore.kernel.org/r/20220809142455.6473-1-bedant.patnaik@gmail.com Signed-off-by: Takashi Iwai --- sound/pci/hda/patch_realtek.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 4197567b6f26..fd630d62b5a0 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -9213,6 +9213,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = { ALC285_FIXUP_HP_GPIO_AMP_INIT), SND_PCI_QUIRK(0x103c, 0x8783, "HP ZBook Fury 15 G7 Mobile Workstation", ALC285_FIXUP_HP_GPIO_AMP_INIT), + SND_PCI_QUIRK(0x103c, 0x8786, "HP OMEN 15", ALC285_FIXUP_HP_MUTE_LED), SND_PCI_QUIRK(0x103c, 0x8787, "HP OMEN 15", ALC285_FIXUP_HP_MUTE_LED), SND_PCI_QUIRK(0x103c, 0x8788, "HP OMEN 15", ALC285_FIXUP_HP_MUTE_LED), SND_PCI_QUIRK(0x103c, 0x87c8, "HP", ALC287_FIXUP_HP_GPIO_LED), -- cgit v1.2.3 From a44252d5c3bbd76efa7b65819712f0e2b1de54c0 Mon Sep 17 00:00:00 2001 From: Justin Stitt Date: Mon, 11 Jul 2022 16:01:48 -0700 Subject: ntb: idt: fix clang -Wformat warnings When building with Clang we encounter these warnings: | drivers/ntb/hw/idt/ntb_hw_idt.c:2409:28: error: format specifies type | 'unsigned char' but the argument has type 'int' [-Werror,-Wformat] | "\t%hhu-%hhu.\t", idx + cnt - 1); - | drivers/ntb/hw/idt/ntb_hw_idt.c:2438:29: error: format specifies type | 'unsigned char' but the argument has type 'int' [-Werror,-Wformat] | "\t%hhu-%hhu.\t", idx + cnt - 1); - | drivers/ntb/hw/idt/ntb_hw_idt.c:2484:15: error: format specifies type | 'unsigned char' but the argument has type 'int' [-Werror,-Wformat], src); For the first two warnings the format specifier used is `%hhu` which describes a u8. Both `idx` and `cnt` are u8 as well. However, the expression as a whole is promoted to an int as you cannot get smaller-than-int from addition. Therefore, to fix the warning, use the promoted-to-type's format specifier -- in this case `%d`. example: `` uint8_t a = 4, b = 7; int size = sizeof(a + b - 1); printf("%d\n", size); // output: 4 ``` For the last warning, src is of type `int` while the format specifier describes a u8. The fix here is just to use the proper specifier `%d`. See more: (https://wiki.sei.cmu.edu/confluence/display/c/INT02-C.+Understand+integer+conversion+rules) "Integer types smaller than int are promoted when an operation is performed on them. If all values of the original type can be represented as an int, the value of the smaller type is converted to an int; otherwise, it is converted to an unsigned int." Link: https://github.com/ClangBuiltLinux/linux/issues/378 Signed-off-by: Justin Stitt Acked-by: Serge Semin Signed-off-by: Jon Mason --- drivers/ntb/hw/idt/ntb_hw_idt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/ntb/hw/idt/ntb_hw_idt.c b/drivers/ntb/hw/idt/ntb_hw_idt.c index 733557231ed0..0ed6f809ff2e 100644 --- a/drivers/ntb/hw/idt/ntb_hw_idt.c +++ b/drivers/ntb/hw/idt/ntb_hw_idt.c @@ -2406,7 +2406,7 @@ static ssize_t idt_dbgfs_info_read(struct file *filp, char __user *ubuf, "\t%hhu.\t", idx); else off += scnprintf(strbuf + off, size - off, - "\t%hhu-%hhu.\t", idx, idx + cnt - 1); + "\t%hhu-%d.\t", idx, idx + cnt - 1); off += scnprintf(strbuf + off, size - off, "%s BAR%hhu, ", idt_get_mw_name(data), ndev->mws[idx].bar); @@ -2435,7 +2435,7 @@ static ssize_t idt_dbgfs_info_read(struct file *filp, char __user *ubuf, "\t%hhu.\t", idx); else off += scnprintf(strbuf + off, size - off, - "\t%hhu-%hhu.\t", idx, idx + cnt - 1); + "\t%hhu-%d.\t", idx, idx + cnt - 1); off += scnprintf(strbuf + off, size - off, "%s BAR%hhu, ", idt_get_mw_name(data), @@ -2480,7 +2480,7 @@ static ssize_t idt_dbgfs_info_read(struct file *filp, char __user *ubuf, int src; data = idt_ntb_msg_read(&ndev->ntb, &src, idx); off += scnprintf(strbuf + off, size - off, - "\t%hhu. 0x%08x from peer %hhu (Port %hhu)\n", + "\t%hhu. 0x%08x from peer %d (Port %hhu)\n", idx, data, src, ndev->peers[src].port); } off += scnprintf(strbuf + off, size - off, "\n"); -- cgit v1.2.3 From 45e1058b77feade4e36402828bfe3e0d3363177b Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 20 Jul 2022 21:28:18 +0300 Subject: NTB: ntb_tool: uninitialized heap data in tool_fn_write() The call to: ret = simple_write_to_buffer(buf, size, offp, ubuf, size); will return success if it is able to write even one byte to "buf". The value of "*offp" controls which byte. This could result in reading uninitialized data when we do the sscanf() on the next line. This code is not really desigined to handle partial writes where *offp is non-zero and the "buf" is preserved and re-used between writes. Just ban partial writes and replace the simple_write_to_buffer() with copy_from_user(). Fixes: 578b881ba9c4 ("NTB: Add tool test client") Signed-off-by: Dan Carpenter Signed-off-by: Jon Mason --- drivers/ntb/test/ntb_tool.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/ntb/test/ntb_tool.c b/drivers/ntb/test/ntb_tool.c index b7bf3f863d79..5ee0afa621a9 100644 --- a/drivers/ntb/test/ntb_tool.c +++ b/drivers/ntb/test/ntb_tool.c @@ -367,14 +367,16 @@ static ssize_t tool_fn_write(struct tool_ctx *tc, u64 bits; int n; + if (*offp) + return 0; + buf = kmalloc(size + 1, GFP_KERNEL); if (!buf) return -ENOMEM; - ret = simple_write_to_buffer(buf, size, offp, ubuf, size); - if (ret < 0) { + if (copy_from_user(buf, ubuf, size)) { kfree(buf); - return ret; + return -EFAULT; } buf[size] = 0; -- cgit v1.2.3 From a914fc529f59dcd9f59633157cf7ee70822ebcac Mon Sep 17 00:00:00 2001 From: Dave Jiang Date: Tue, 2 Aug 2022 14:10:13 -0700 Subject: ntb: intel: add GNR support for Intel PCIe gen5 NTB Add Intel Granite Rapids NTB PCI device ID and related enabling. Expectation is same hardware interface as Saphire Rapids Xeon platforms. Signed-off-by: Dave Jiang Acked-by: Allen Hubbe Signed-off-by: Jon Mason --- drivers/ntb/hw/intel/ntb_hw_gen1.c | 12 ++++++++---- drivers/ntb/hw/intel/ntb_hw_gen4.c | 2 +- drivers/ntb/hw/intel/ntb_hw_intel.h | 7 +++++++ 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/ntb/hw/intel/ntb_hw_gen1.c b/drivers/ntb/hw/intel/ntb_hw_gen1.c index e5f14e20a9ff..84772013812b 100644 --- a/drivers/ntb/hw/intel/ntb_hw_gen1.c +++ b/drivers/ntb/hw/intel/ntb_hw_gen1.c @@ -763,7 +763,7 @@ static ssize_t ndev_debugfs_read(struct file *filp, char __user *ubuf, return ndev_ntb_debugfs_read(filp, ubuf, count, offp); else if (pdev_is_gen3(ndev->ntb.pdev)) return ndev_ntb3_debugfs_read(filp, ubuf, count, offp); - else if (pdev_is_gen4(ndev->ntb.pdev)) + else if (pdev_is_gen4(ndev->ntb.pdev) || pdev_is_gen5(ndev->ntb.pdev)) return ndev_ntb4_debugfs_read(filp, ubuf, count, offp); return -ENXIO; @@ -1874,7 +1874,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev, rc = gen3_init_dev(ndev); if (rc) goto err_init_dev; - } else if (pdev_is_gen4(pdev)) { + } else if (pdev_is_gen4(pdev) || pdev_is_gen5(pdev)) { ndev->ntb.ops = &intel_ntb4_ops; rc = intel_ntb_init_pci(ndev, pdev); if (rc) @@ -1904,7 +1904,8 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev, err_register: ndev_deinit_debugfs(ndev); - if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev) || pdev_is_gen4(pdev)) + if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev) || + pdev_is_gen4(pdev) || pdev_is_gen5(pdev)) xeon_deinit_dev(ndev); err_init_dev: intel_ntb_deinit_pci(ndev); @@ -1920,7 +1921,8 @@ static void intel_ntb_pci_remove(struct pci_dev *pdev) ntb_unregister_device(&ndev->ntb); ndev_deinit_debugfs(ndev); - if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev) || pdev_is_gen4(pdev)) + if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev) || + pdev_is_gen4(pdev) || pdev_is_gen5(pdev)) xeon_deinit_dev(ndev); intel_ntb_deinit_pci(ndev); kfree(ndev); @@ -2047,6 +2049,8 @@ static const struct pci_device_id intel_ntb_pci_tbl[] = { /* GEN4 */ {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)}, + /* GEN5 PCIe */ + {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_GNR)}, {0} }; MODULE_DEVICE_TABLE(pci, intel_ntb_pci_tbl); diff --git a/drivers/ntb/hw/intel/ntb_hw_gen4.c b/drivers/ntb/hw/intel/ntb_hw_gen4.c index 4081fc538ff4..22cac7975b3c 100644 --- a/drivers/ntb/hw/intel/ntb_hw_gen4.c +++ b/drivers/ntb/hw/intel/ntb_hw_gen4.c @@ -197,7 +197,7 @@ int gen4_init_dev(struct intel_ntb_dev *ndev) ppd1 = ioread32(ndev->self_mmio + GEN4_PPD1_OFFSET); if (pdev_is_ICX(pdev)) ndev->ntb.topo = gen4_ppd_topo(ndev, ppd1); - else if (pdev_is_SPR(pdev)) + else if (pdev_is_SPR(pdev) || pdev_is_gen5(pdev)) ndev->ntb.topo = spr_ppd_topo(ndev, ppd1); dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd1, ntb_topo_string(ndev->ntb.topo)); diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.h b/drivers/ntb/hw/intel/ntb_hw_intel.h index b233d1c6ba2d..da4d5fe55bab 100644 --- a/drivers/ntb/hw/intel/ntb_hw_intel.h +++ b/drivers/ntb/hw/intel/ntb_hw_intel.h @@ -70,6 +70,7 @@ #define PCI_DEVICE_ID_INTEL_NTB_SS_BDX 0x6F0F #define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX 0x201C #define PCI_DEVICE_ID_INTEL_NTB_B2B_ICX 0x347e +#define PCI_DEVICE_ID_INTEL_NTB_B2B_GNR 0x0db4 /* Ntb control and link status */ #define NTB_CTL_CFG_LOCK BIT(0) @@ -228,4 +229,10 @@ static inline int pdev_is_gen4(struct pci_dev *pdev) return 0; } + +static inline int pdev_is_gen5(struct pci_dev *pdev) +{ + return pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_GNR; +} + #endif -- cgit v1.2.3 From df4aaf015775221dde8a51ee09edb919981f091e Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Thu, 30 Jun 2022 23:00:57 +0300 Subject: drm/shmem-helper: Add missing vunmap on error The vmapping of dma-buf may succeed, but DRM SHMEM rejects the IOMEM mapping, and thus, drm_gem_shmem_vmap_locked() should unvmap the IOMEM before erroring out. Cc: stable@vger.kernel.org Fixes: 49a3f51dfeee ("drm/gem: Use struct dma_buf_map in GEM vmap ops and convert GEM backends") Signed-off-by: Dmitry Osipenko Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20220630200058.1883506-2-dmitry.osipenko@collabora.com --- drivers/gpu/drm/drm_gem_shmem_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c b/drivers/gpu/drm/drm_gem_shmem_helper.c index 8ad0e02991ca..904fc893c905 100644 --- a/drivers/gpu/drm/drm_gem_shmem_helper.c +++ b/drivers/gpu/drm/drm_gem_shmem_helper.c @@ -302,6 +302,7 @@ static int drm_gem_shmem_vmap_locked(struct drm_gem_shmem_object *shmem, ret = dma_buf_vmap(obj->import_attach->dmabuf, map); if (!ret) { if (WARN_ON(map->is_iomem)) { + dma_buf_vunmap(obj->import_attach->dmabuf, map); ret = -EIO; goto err_put_pages; } -- cgit v1.2.3 From 2939deac1fa220bc82b89235f146df1d9b52e876 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Thu, 30 Jun 2022 23:04:04 +0300 Subject: drm/gem: Properly annotate WW context on drm_gem_lock_reservations() error MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use ww_acquire_fini() in the error code paths. Otherwise lockdep thinks that lock is held when lock's memory is freed after the drm_gem_lock_reservations() error. The ww_acquire_context needs to be annotated as "released", which fixes the noisy "WARNING: held lock freed!" splat of VirtIO-GPU driver with CONFIG_DEBUG_MUTEXES=y and enabled lockdep. Cc: stable@vger.kernel.org Fixes: 7edc3e3b975b5 ("drm: Add helpers for locking an array of BO reservations.") Reviewed-by: Thomas Hellström Reviewed-by: Christian König Signed-off-by: Dmitry Osipenko Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20220630200405.1883897-2-dmitry.osipenko@collabora.com --- drivers/gpu/drm/drm_gem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c index eb0c2d041f13..86d670c71286 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c @@ -1226,7 +1226,7 @@ retry: ret = dma_resv_lock_slow_interruptible(obj->resv, acquire_ctx); if (ret) { - ww_acquire_done(acquire_ctx); + ww_acquire_fini(acquire_ctx); return ret; } } @@ -1251,7 +1251,7 @@ retry: goto retry; } - ww_acquire_done(acquire_ctx); + ww_acquire_fini(acquire_ctx); return ret; } } -- cgit v1.2.3 From 46dae32fe625a75f549c3a70edc77b778197bb05 Mon Sep 17 00:00:00 2001 From: Youngmin Nam Date: Tue, 12 Jul 2022 18:47:15 +0900 Subject: time: Correct the prototype of ns_to_kernel_old_timeval and ns_to_timespec64 In ns_to_kernel_old_timeval() definition, the function argument is defined with const identifier in kernel/time/time.c, but the prototype in include/linux/time32.h looks different. - The function is defined in kernel/time/time.c as below: struct __kernel_old_timeval ns_to_kernel_old_timeval(const s64 nsec) - The function is decalared in include/linux/time32.h as below: extern struct __kernel_old_timeval ns_to_kernel_old_timeval(s64 nsec); Because the variable of arithmethic types isn't modified in the calling scope, there's no need to mark arguments as const, which was already mentioned during review (Link[1) of the original patch. Likewise remove the "const" keyword in both definition and declaration of ns_to_timespec64() as requested by Arnd (Link[2]). Fixes: a84d1169164b ("y2038: Introduce struct __kernel_old_timeval") Signed-off-by: Youngmin Nam Signed-off-by: Thomas Gleixner Reviewed-by: Arnd Bergmann Link: https://lore.kernel.org/all/20220712094715.2918823-1-youngmin.nam@samsung.com Link[1]: https://lore.kernel.org/all/20180310081123.thin6wphgk7tongy@gmail.com/ Link[2]: https://lore.kernel.org/all/CAK8P3a3nknJgEDESGdJH91jMj6R_xydFqWASd8r5BbesdvMBgA@mail.gmail.com/ --- include/linux/time64.h | 2 +- kernel/time/time.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/linux/time64.h b/include/linux/time64.h index 2fb8232cff1d..f1bcea8c124a 100644 --- a/include/linux/time64.h +++ b/include/linux/time64.h @@ -145,7 +145,7 @@ static inline s64 timespec64_to_ns(const struct timespec64 *ts) * * Returns the timespec64 representation of the nsec parameter. */ -extern struct timespec64 ns_to_timespec64(const s64 nsec); +extern struct timespec64 ns_to_timespec64(s64 nsec); /** * timespec64_add_ns - Adds nanoseconds to a timespec64 diff --git a/kernel/time/time.c b/kernel/time/time.c index 29923b20e0e4..526257b3727c 100644 --- a/kernel/time/time.c +++ b/kernel/time/time.c @@ -449,7 +449,7 @@ time64_t mktime64(const unsigned int year0, const unsigned int mon0, } EXPORT_SYMBOL(mktime64); -struct __kernel_old_timeval ns_to_kernel_old_timeval(const s64 nsec) +struct __kernel_old_timeval ns_to_kernel_old_timeval(s64 nsec) { struct timespec64 ts = ns_to_timespec64(nsec); struct __kernel_old_timeval tv; @@ -503,7 +503,7 @@ EXPORT_SYMBOL(set_normalized_timespec64); * * Returns the timespec64 representation of the nsec parameter. */ -struct timespec64 ns_to_timespec64(const s64 nsec) +struct timespec64 ns_to_timespec64(s64 nsec) { struct timespec64 ts = { 0, 0 }; s32 rem; -- cgit v1.2.3 From e362359ace6f87c201531872486ff295df306d13 Mon Sep 17 00:00:00 2001 From: Thadeu Lima de Souza Cascardo Date: Tue, 9 Aug 2022 14:07:51 -0300 Subject: posix-cpu-timers: Cleanup CPU timers before freeing them during exec Commit 55e8c8eb2c7b ("posix-cpu-timers: Store a reference to a pid not a task") started looking up tasks by PID when deleting a CPU timer. When a non-leader thread calls execve, it will switch PIDs with the leader process. Then, as it calls exit_itimers, posix_cpu_timer_del cannot find the task because the timer still points out to the old PID. That means that armed timers won't be disarmed, that is, they won't be removed from the timerqueue_list. exit_itimers will still release their memory, and when that list is later processed, it leads to a use-after-free. Clean up the timers from the de-threaded task before freeing them. This prevents a reported use-after-free. Fixes: 55e8c8eb2c7b ("posix-cpu-timers: Store a reference to a pid not a task") Signed-off-by: Thadeu Lima de Souza Cascardo Signed-off-by: Thomas Gleixner Reviewed-by: Thomas Gleixner Cc: Link: https://lore.kernel.org/r/20220809170751.164716-1-cascardo@canonical.com --- fs/exec.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/fs/exec.c b/fs/exec.c index 5fd73915c62c..f793221f4eb6 100644 --- a/fs/exec.c +++ b/fs/exec.c @@ -1304,6 +1304,9 @@ int begin_new_exec(struct linux_binprm * bprm) bprm->mm = NULL; #ifdef CONFIG_POSIX_TIMERS + spin_lock_irq(&me->sighand->siglock); + posix_cpu_timers_exit(me); + spin_unlock_irq(&me->sighand->siglock); exit_itimers(me); flush_itimer_signals(); #endif -- cgit v1.2.3 From 0d22bbc2d557515bd51629408cada0fca681343a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 8 Aug 2022 13:15:26 +0300 Subject: dt-bindings: display: simple-framebuffer: Drop Bartlomiej Zolnierkiewicz Bartlomiej's Samsung email address is not working since around last year and there was no follow up patch take over of the drivers, so drop the email from maintainers. Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Krzysztof Kozlowski Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20220808101526.46556-3-krzysztof.kozlowski@linaro.org --- Documentation/devicetree/bindings/display/simple-framebuffer.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/simple-framebuffer.yaml b/Documentation/devicetree/bindings/display/simple-framebuffer.yaml index 27ba4323d221..1f905d85dd9c 100644 --- a/Documentation/devicetree/bindings/display/simple-framebuffer.yaml +++ b/Documentation/devicetree/bindings/display/simple-framebuffer.yaml @@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Simple Framebuffer Device Tree Bindings maintainers: - - Bartlomiej Zolnierkiewicz - Hans de Goede description: |+ -- cgit v1.2.3 From 331753ff3292d5ef987ad6106f737853c3a187ba Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 26 Jul 2022 01:57:09 +0530 Subject: dt-bindings: mmc: sdhci-msm: Fix 'operating-points-v2 was unexpected' issue As Rob reported in [1], there is one more issue present in the 'sdhci-msm' dt-binding which shows up when a fix for 'unevaluatedProperties' handling is applied: Documentation/devicetree/bindings/mmc/sdhci-msm.example.dtb: mmc@8804000: Unevaluated properties are not allowed ('operating-points-v2' was unexpected) Fix the same. [1]. https://lore.kernel.org/lkml/20220514220116.1008254-1-bhupesh.sharma@linaro.org/ Cc: Bjorn Andersson Cc: Rob Herring Cc: Ulf Hansson Signed-off-by: Bhupesh Sharma Acked-by: Rob Herring Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20220725202709.2861789-1-bhupesh.sharma@linaro.org --- Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index b00578ae1dea..fc0e81c2066c 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -137,6 +137,8 @@ properties: max-frequency: true + operating-points-v2: true + patternProperties: '^opp-table(-[a-z0-9]+)?$': if: -- cgit v1.2.3 From 4284c88fff0efc4e418abb53d78e02dc4f099d6c Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 22 Feb 2022 10:23:52 -0600 Subject: PCI: designware-ep: Allow pci_epc_set_bar() update inbound map address ntb_mw_set_trans() will set memory map window after endpoint function driver bind. The inbound map address need be updated dynamically when using NTB by PCIe Root Port and PCIe Endpoint connection. Checking if iatu already assigned to the BAR, if yes, using assigned iatu number to update inbound address map and skip set BAR's register. Signed-off-by: Frank Li Signed-off-by: Jon Mason --- drivers/pci/controller/dwc/pcie-designware-ep.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 0eda8236c125..b4cb65d851cd 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -162,7 +162,11 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, u32 free_win; struct dw_pcie *pci = to_dw_pcie_from_ep(ep); - free_win = find_first_zero_bit(ep->ib_window_map, pci->num_ib_windows); + if (!ep->bar_to_atu[bar]) + free_win = find_first_zero_bit(ep->ib_window_map, pci->num_ib_windows); + else + free_win = ep->bar_to_atu[bar]; + if (free_win >= pci->num_ib_windows) { dev_err(pci->dev, "No free inbound window\n"); return -EINVAL; @@ -216,6 +220,7 @@ static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND); clear_bit(atu_index, ep->ib_window_map); ep->epf_bar[bar] = NULL; + ep->bar_to_atu[bar] = 0; } static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, @@ -245,6 +250,9 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, if (ret) return ret; + if (ep->epf_bar[bar]) + return 0; + dw_pcie_dbi_ro_wr_en(pci); dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1)); -- cgit v1.2.3 From e75d5ae8ab88b7ffb3d1d56124b003f3555f74b4 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 22 Feb 2022 10:23:53 -0600 Subject: NTB: epf: Allow more flexibility in the memory BAR map method Support the below BAR configuration methods for epf NTB. BAR 0: config and scratchpad BAR 2: doorbell BAR 4: memory map windows Set difference BAR number information into struct ntb_epf_data. So difference VID/PID can choose different BAR configurations. There are difference BAR map method between epf NTB and epf vNTB Endpoint function. Signed-off-by: Frank Li Signed-off-by: Jon Mason --- drivers/ntb/hw/epf/ntb_hw_epf.c | 48 ++++++++++++++++++++++++++++++----------- 1 file changed, 35 insertions(+), 13 deletions(-) diff --git a/drivers/ntb/hw/epf/ntb_hw_epf.c b/drivers/ntb/hw/epf/ntb_hw_epf.c index b019755e4e21..3ece49cb18ff 100644 --- a/drivers/ntb/hw/epf/ntb_hw_epf.c +++ b/drivers/ntb/hw/epf/ntb_hw_epf.c @@ -45,7 +45,6 @@ #define NTB_EPF_MIN_DB_COUNT 3 #define NTB_EPF_MAX_DB_COUNT 31 -#define NTB_EPF_MW_OFFSET 2 #define NTB_EPF_COMMAND_TIMEOUT 1000 /* 1 Sec */ @@ -67,6 +66,7 @@ struct ntb_epf_dev { enum pci_barno ctrl_reg_bar; enum pci_barno peer_spad_reg_bar; enum pci_barno db_reg_bar; + enum pci_barno mw_bar; unsigned int mw_count; unsigned int spad_count; @@ -92,6 +92,8 @@ struct ntb_epf_data { enum pci_barno peer_spad_reg_bar; /* BAR that contains Doorbell region and Memory window '1' */ enum pci_barno db_reg_bar; + /* BAR that contains memory windows*/ + enum pci_barno mw_bar; }; static int ntb_epf_send_command(struct ntb_epf_dev *ndev, u32 command, @@ -411,7 +413,7 @@ static int ntb_epf_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx, return -EINVAL; } - bar = idx + NTB_EPF_MW_OFFSET; + bar = idx + ndev->mw_bar; mw_size = pci_resource_len(ntb->pdev, bar); @@ -453,7 +455,7 @@ static int ntb_epf_peer_mw_get_addr(struct ntb_dev *ntb, int idx, if (idx == 0) offset = readl(ndev->ctrl_reg + NTB_EPF_MW1_OFFSET); - bar = idx + NTB_EPF_MW_OFFSET; + bar = idx + ndev->mw_bar; if (base) *base = pci_resource_start(ndev->ntb.pdev, bar) + offset; @@ -565,6 +567,7 @@ static int ntb_epf_init_pci(struct ntb_epf_dev *ndev, struct pci_dev *pdev) { struct device *dev = ndev->dev; + size_t spad_sz, spad_off; int ret; pci_set_drvdata(pdev, ndev); @@ -599,10 +602,16 @@ static int ntb_epf_init_pci(struct ntb_epf_dev *ndev, goto err_dma_mask; } - ndev->peer_spad_reg = pci_iomap(pdev, ndev->peer_spad_reg_bar, 0); - if (!ndev->peer_spad_reg) { - ret = -EIO; - goto err_dma_mask; + if (ndev->peer_spad_reg_bar) { + ndev->peer_spad_reg = pci_iomap(pdev, ndev->peer_spad_reg_bar, 0); + if (!ndev->peer_spad_reg) { + ret = -EIO; + goto err_dma_mask; + } + } else { + spad_sz = 4 * readl(ndev->ctrl_reg + NTB_EPF_SPAD_COUNT); + spad_off = readl(ndev->ctrl_reg + NTB_EPF_SPAD_OFFSET); + ndev->peer_spad_reg = ndev->ctrl_reg + spad_off + spad_sz; } ndev->db_reg = pci_iomap(pdev, ndev->db_reg_bar, 0); @@ -657,6 +666,7 @@ static int ntb_epf_pci_probe(struct pci_dev *pdev, enum pci_barno peer_spad_reg_bar = BAR_1; enum pci_barno ctrl_reg_bar = BAR_0; enum pci_barno db_reg_bar = BAR_2; + enum pci_barno mw_bar = BAR_2; struct device *dev = &pdev->dev; struct ntb_epf_data *data; struct ntb_epf_dev *ndev; @@ -671,17 +681,16 @@ static int ntb_epf_pci_probe(struct pci_dev *pdev, data = (struct ntb_epf_data *)id->driver_data; if (data) { - if (data->peer_spad_reg_bar) - peer_spad_reg_bar = data->peer_spad_reg_bar; - if (data->ctrl_reg_bar) - ctrl_reg_bar = data->ctrl_reg_bar; - if (data->db_reg_bar) - db_reg_bar = data->db_reg_bar; + peer_spad_reg_bar = data->peer_spad_reg_bar; + ctrl_reg_bar = data->ctrl_reg_bar; + db_reg_bar = data->db_reg_bar; + mw_bar = data->mw_bar; } ndev->peer_spad_reg_bar = peer_spad_reg_bar; ndev->ctrl_reg_bar = ctrl_reg_bar; ndev->db_reg_bar = db_reg_bar; + ndev->mw_bar = mw_bar; ndev->dev = dev; ntb_epf_init_struct(ndev, pdev); @@ -729,6 +738,14 @@ static const struct ntb_epf_data j721e_data = { .ctrl_reg_bar = BAR_0, .peer_spad_reg_bar = BAR_1, .db_reg_bar = BAR_2, + .mw_bar = BAR_2, +}; + +static const struct ntb_epf_data mx8_data = { + .ctrl_reg_bar = BAR_0, + .peer_spad_reg_bar = BAR_0, + .db_reg_bar = BAR_2, + .mw_bar = BAR_4, }; static const struct pci_device_id ntb_epf_pci_tbl[] = { @@ -737,6 +754,11 @@ static const struct pci_device_id ntb_epf_pci_tbl[] = { .class = PCI_CLASS_MEMORY_RAM << 8, .class_mask = 0xffff00, .driver_data = (kernel_ulong_t)&j721e_data, }, + { + PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x0809), + .class = PCI_CLASS_MEMORY_RAM << 8, .class_mask = 0xffff00, + .driver_data = (kernel_ulong_t)&mx8_data, + }, { }, }; -- cgit v1.2.3 From e35f56bb03304abc92c928b641af41ca372966bb Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 22 Feb 2022 10:23:54 -0600 Subject: PCI: endpoint: Support NTB transfer between RC and EP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add NTB function driver and virtual PCI Bus and Virtual NTB driver to implement communication between PCIe Root Port and PCIe EP devices ┌────────────┐ ┌─────────────────────────────────────┐ │ │ │ │ ├────────────┤ │ ┌──────────────┤ │ NTB │ │ │ NTB │ │ NetDev │ │ │ NetDev │ ├────────────┤ │ ├──────────────┤ │ NTB │ │ │ NTB │ │ Transfer │ │ │ Transfer │ ├────────────┤ │ ├──────────────┤ │ │ │ │ │ │ PCI NTB │ │ │ │ │ EPF │ │ │ │ │ Driver │ │ │ PCI Virtual │ │ │ ├───────────────┐ │ NTB Driver │ │ │ │ PCI EP NTB │◄────►│ │ │ │ │ FN Driver │ │ │ ├────────────┤ ├───────────────┤ ├──────────────┤ │ │ │ │ │ │ │ PCI Bus │ ◄─────► │ PCI EP Bus │ │ Virtual PCI │ │ │ PCI │ │ │ Bus │ └────────────┘ └───────────────┴──────┴──────────────┘ PCIe Root Port PCI EP This driver includes 3 parts: 1 PCI EP NTB function driver 2 Virtual PCI bus 3 PCI virtual NTB driver, which is loaded only by above virtual PCI bus Signed-off-by: Frank Li Signed-off-by: Jon Mason --- drivers/pci/endpoint/functions/Kconfig | 11 + drivers/pci/endpoint/functions/Makefile | 1 + drivers/pci/endpoint/functions/pci-epf-vntb.c | 1424 +++++++++++++++++++++++++ 3 files changed, 1436 insertions(+) create mode 100644 drivers/pci/endpoint/functions/pci-epf-vntb.c diff --git a/drivers/pci/endpoint/functions/Kconfig b/drivers/pci/endpoint/functions/Kconfig index 5f1242ca2f4e..65217428d17b 100644 --- a/drivers/pci/endpoint/functions/Kconfig +++ b/drivers/pci/endpoint/functions/Kconfig @@ -25,3 +25,14 @@ config PCI_EPF_NTB device tree. If in doubt, say "N" to disable Endpoint NTB driver. + +config PCI_EPF_VNTB + tristate "PCI Endpoint NTB driver" + depends on PCI_ENDPOINT + select CONFIGFS_FS + help + Select this configuration option to enable the Non-Transparent + Bridge (NTB) driver for PCIe Endpoint. NTB driver implements NTB + between PCI Root Port and PCIe Endpoint. + + If in doubt, say "N" to disable Endpoint NTB driver. diff --git a/drivers/pci/endpoint/functions/Makefile b/drivers/pci/endpoint/functions/Makefile index 96ab932a537a..5c13001deaba 100644 --- a/drivers/pci/endpoint/functions/Makefile +++ b/drivers/pci/endpoint/functions/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_PCI_EPF_TEST) += pci-epf-test.o obj-$(CONFIG_PCI_EPF_NTB) += pci-epf-ntb.o +obj-$(CONFIG_PCI_EPF_VNTB) += pci-epf-vntb.o diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/endpoint/functions/pci-epf-vntb.c new file mode 100644 index 000000000000..1466dd190417 --- /dev/null +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c @@ -0,0 +1,1424 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Endpoint Function Driver to implement Non-Transparent Bridge functionality + * Between PCI RC and EP + * + * Copyright (C) 2020 Texas Instruments + * Copyright (C) 2022 NXP + * + * Based on pci-epf-ntb.c + * Author: Frank Li + * Author: Kishon Vijay Abraham I + */ + +/** + * +------------+ +---------------------------------------+ + * | | | | + * +------------+ | +--------------+ + * | NTB | | | NTB | + * | NetDev | | | NetDev | + * +------------+ | +--------------+ + * | NTB | | | NTB | + * | Transfer | | | Transfer | + * +------------+ | +--------------+ + * | | | | | + * | PCI NTB | | | | + * | EPF | | | | + * | Driver | | | PCI Virtual | + * | | +---------------+ | NTB Driver | + * | | | PCI EP NTB |<------>| | + * | | | FN Driver | | | + * +------------+ +---------------+ +--------------+ + * | | | | | | + * | PCI Bus | <-----> | PCI EP Bus | | Virtual PCI | + * | | PCI | | | Bus | + * +------------+ +---------------+--------+--------------+ + * PCIe Root Port PCI EP + */ + +#include +#include +#include +#include + +#include +#include +#include + +static struct workqueue_struct *kpcintb_workqueue; + +#define COMMAND_CONFIGURE_DOORBELL 1 +#define COMMAND_TEARDOWN_DOORBELL 2 +#define COMMAND_CONFIGURE_MW 3 +#define COMMAND_TEARDOWN_MW 4 +#define COMMAND_LINK_UP 5 +#define COMMAND_LINK_DOWN 6 + +#define COMMAND_STATUS_OK 1 +#define COMMAND_STATUS_ERROR 2 + +#define LINK_STATUS_UP BIT(0) + +#define SPAD_COUNT 64 +#define DB_COUNT 4 +#define NTB_MW_OFFSET 2 +#define DB_COUNT_MASK GENMASK(15, 0) +#define MSIX_ENABLE BIT(16) +#define MAX_DB_COUNT 32 +#define MAX_MW 4 + +enum epf_ntb_bar { + BAR_CONFIG, + BAR_DB, + BAR_MW0, + BAR_MW1, + BAR_MW2, +}; + +/* + * +--------------------------------------------------+ Base + * | | + * | | + * | | + * | Common Control Register | + * | | + * | | + * | | + * +-----------------------+--------------------------+ Base+span_offset + * | | | + * | Peer Span Space | Span Space | + * | | | + * | | | + * +-----------------------+--------------------------+ Base+span_offset + * | | | +span_count * 4 + * | | | + * | Span Space | Peer Span Space | + * | | | + * +-----------------------+--------------------------+ + * Virtual PCI PCIe Endpoint + * NTB Driver NTB Driver + */ +struct epf_ntb_ctrl { + u32 command; + u32 argument; + u16 command_status; + u16 link_status; + u32 topology; + u64 addr; + u64 size; + u32 num_mws; + u32 reserved; + u32 spad_offset; + u32 spad_count; + u32 db_entry_size; + u32 db_data[MAX_DB_COUNT]; + u32 db_offset[MAX_DB_COUNT]; +} __packed; + +struct epf_ntb { + struct ntb_dev ntb; + struct pci_epf *epf; + struct config_group group; + + u32 num_mws; + u32 db_count; + u32 spad_count; + u64 mws_size[MAX_MW]; + u64 db; + u32 vbus_number; + u16 vntb_pid; + u16 vntb_vid; + + bool linkup; + u32 spad_size; + + enum pci_barno epf_ntb_bar[6]; + + struct epf_ntb_ctrl *reg; + + phys_addr_t epf_db_phy; + void __iomem *epf_db; + + phys_addr_t vpci_mw_phy[MAX_MW]; + void __iomem *vpci_mw_addr[MAX_MW]; + + struct delayed_work cmd_handler; +}; + +#define to_epf_ntb(epf_group) container_of((epf_group), struct epf_ntb, group) +#define ntb_ndev(__ntb) container_of(__ntb, struct epf_ntb, ntb) + +static struct pci_epf_header epf_ntb_header = { + .vendorid = PCI_ANY_ID, + .deviceid = PCI_ANY_ID, + .baseclass_code = PCI_BASE_CLASS_MEMORY, + .interrupt_pin = PCI_INTERRUPT_INTA, +}; + +/** + * epf_ntb_link_up() - Raise link_up interrupt to Virtual Host + * @ntb: NTB device that facilitates communication between HOST and VHOST + * @link_up: true or false indicating Link is UP or Down + * + * Once NTB function in HOST invoke ntb_link_enable(), + * this NTB function driver will trigger a link event to vhost. + */ +static int epf_ntb_link_up(struct epf_ntb *ntb, bool link_up) +{ + if (link_up) + ntb->reg->link_status |= LINK_STATUS_UP; + else + ntb->reg->link_status &= ~LINK_STATUS_UP; + + ntb_link_event(&ntb->ntb); + return 0; +} + +/** + * epf_ntb_configure_mw() - Configure the Outbound Address Space for vhost + * to access the memory window of host + * @ntb: NTB device that facilitates communication between host and vhost + * @mw: Index of the memory window (either 0, 1, 2 or 3) + * + * EP Outbound Window + * +--------+ +-----------+ + * | | | | + * | | | | + * | | | | + * | | | | + * | | +-----------+ + * | Virtual| | Memory Win| + * | NTB | -----------> | | + * | Driver | | | + * | | +-----------+ + * | | | | + * | | | | + * +--------+ +-----------+ + * VHost PCI EP + */ +static int epf_ntb_configure_mw(struct epf_ntb *ntb, u32 mw) +{ + phys_addr_t phys_addr; + u8 func_no, vfunc_no; + u64 addr, size; + int ret = 0; + + phys_addr = ntb->vpci_mw_phy[mw]; + addr = ntb->reg->addr; + size = ntb->reg->size; + + func_no = ntb->epf->func_no; + vfunc_no = ntb->epf->vfunc_no; + + ret = pci_epc_map_addr(ntb->epf->epc, func_no, vfunc_no, phys_addr, addr, size); + if (ret) + dev_err(&ntb->epf->epc->dev, + "Failed to map memory window %d address\n", mw); + return ret; +} + +/** + * epf_ntb_teardown_mw() - Teardown the configured OB ATU + * @ntb: NTB device that facilitates communication between HOST and vHOST + * @mw: Index of the memory window (either 0, 1, 2 or 3) + * + * Teardown the configured OB ATU configured in epf_ntb_configure_mw() using + * pci_epc_unmap_addr() + */ +static void epf_ntb_teardown_mw(struct epf_ntb *ntb, u32 mw) +{ + pci_epc_unmap_addr(ntb->epf->epc, + ntb->epf->func_no, + ntb->epf->vfunc_no, + ntb->vpci_mw_phy[mw]); +} + +/** + * epf_ntb_cmd_handler() - Handle commands provided by the NTB Host + * @work: work_struct for the epf_ntb_epc + * + * Workqueue function that gets invoked for the two epf_ntb_epc + * periodically (once every 5ms) to see if it has received any commands + * from NTB host. The host can send commands to configure doorbell or + * configure memory window or to update link status. + */ +static void epf_ntb_cmd_handler(struct work_struct *work) +{ + struct epf_ntb_ctrl *ctrl; + u32 command, argument; + struct epf_ntb *ntb; + struct device *dev; + int ret; + int i; + + ntb = container_of(work, struct epf_ntb, cmd_handler.work); + + for (i = 1; i < ntb->db_count; i++) { + if (readl(ntb->epf_db + i * 4)) { + if (readl(ntb->epf_db + i * 4)) + ntb->db |= 1 << (i - 1); + + ntb_db_event(&ntb->ntb, i); + writel(0, ntb->epf_db + i * 4); + } + } + + ctrl = ntb->reg; + command = ctrl->command; + if (!command) + goto reset_handler; + argument = ctrl->argument; + + ctrl->command = 0; + ctrl->argument = 0; + + ctrl = ntb->reg; + dev = &ntb->epf->dev; + + switch (command) { + case COMMAND_CONFIGURE_DOORBELL: + ctrl->command_status = COMMAND_STATUS_OK; + break; + case COMMAND_TEARDOWN_DOORBELL: + ctrl->command_status = COMMAND_STATUS_OK; + break; + case COMMAND_CONFIGURE_MW: + ret = epf_ntb_configure_mw(ntb, argument); + if (ret < 0) + ctrl->command_status = COMMAND_STATUS_ERROR; + else + ctrl->command_status = COMMAND_STATUS_OK; + break; + case COMMAND_TEARDOWN_MW: + epf_ntb_teardown_mw(ntb, argument); + ctrl->command_status = COMMAND_STATUS_OK; + break; + case COMMAND_LINK_UP: + ntb->linkup = true; + ret = epf_ntb_link_up(ntb, true); + if (ret < 0) + ctrl->command_status = COMMAND_STATUS_ERROR; + else + ctrl->command_status = COMMAND_STATUS_OK; + goto reset_handler; + case COMMAND_LINK_DOWN: + ntb->linkup = false; + ret = epf_ntb_link_up(ntb, false); + if (ret < 0) + ctrl->command_status = COMMAND_STATUS_ERROR; + else + ctrl->command_status = COMMAND_STATUS_OK; + break; + default: + dev_err(dev, "UNKNOWN command: %d\n", command); + break; + } + +reset_handler: + queue_delayed_work(kpcintb_workqueue, &ntb->cmd_handler, + msecs_to_jiffies(5)); +} + +/** + * epf_ntb_config_sspad_bar_clear() - Clear Config + Self scratchpad BAR + * @ntb_epc: EPC associated with one of the HOST which holds peer's outbound + * address. + * + * Clear BAR0 of EP CONTROLLER 1 which contains the HOST1's config and + * self scratchpad region (removes inbound ATU configuration). While BAR0 is + * the default self scratchpad BAR, an NTB could have other BARs for self + * scratchpad (because of reserved BARs). This function can get the exact BAR + * used for self scratchpad from epf_ntb_bar[BAR_CONFIG]. + * + * Please note the self scratchpad region and config region is combined to + * a single region and mapped using the same BAR. Also note HOST2's peer + * scratchpad is HOST1's self scratchpad. + */ +static void epf_ntb_config_sspad_bar_clear(struct epf_ntb *ntb) +{ + struct pci_epf_bar *epf_bar; + enum pci_barno barno; + + barno = ntb->epf_ntb_bar[BAR_CONFIG]; + epf_bar = &ntb->epf->bar[barno]; + + pci_epc_clear_bar(ntb->epf->epc, ntb->epf->func_no, ntb->epf->vfunc_no, epf_bar); +} + +/** + * epf_ntb_config_sspad_bar_set() - Set Config + Self scratchpad BAR + * @ntb: NTB device that facilitates communication between HOST and vHOST + * + * Map BAR0 of EP CONTROLLER 1 which contains the HOST1's config and + * self scratchpad region. + * + * Please note the self scratchpad region and config region is combined to + * a single region and mapped using the same BAR. + */ +static int epf_ntb_config_sspad_bar_set(struct epf_ntb *ntb) +{ + struct pci_epf_bar *epf_bar; + enum pci_barno barno; + u8 func_no, vfunc_no; + struct device *dev; + int ret; + + dev = &ntb->epf->dev; + func_no = ntb->epf->func_no; + vfunc_no = ntb->epf->vfunc_no; + barno = ntb->epf_ntb_bar[BAR_CONFIG]; + epf_bar = &ntb->epf->bar[barno]; + + ret = pci_epc_set_bar(ntb->epf->epc, func_no, vfunc_no, epf_bar); + if (ret) { + dev_err(dev, "inft: Config/Status/SPAD BAR set failed\n"); + return ret; + } + return 0; +} + +/** + * epf_ntb_config_spad_bar_free() - Free the physical memory associated with + * config + scratchpad region + * @ntb: NTB device that facilitates communication between HOST and vHOST + */ +static void epf_ntb_config_spad_bar_free(struct epf_ntb *ntb) +{ + enum pci_barno barno; + + barno = ntb->epf_ntb_bar[BAR_CONFIG]; + pci_epf_free_space(ntb->epf, ntb->reg, barno, 0); +} + +/** + * epf_ntb_config_spad_bar_alloc() - Allocate memory for config + scratchpad + * region + * @ntb: NTB device that facilitates communication between HOST1 and HOST2 + * + * Allocate the Local Memory mentioned in the above diagram. The size of + * CONFIG REGION is sizeof(struct epf_ntb_ctrl) and size of SCRATCHPAD REGION + * is obtained from "spad-count" configfs entry. + */ +static int epf_ntb_config_spad_bar_alloc(struct epf_ntb *ntb) +{ + size_t align; + enum pci_barno barno; + struct epf_ntb_ctrl *ctrl; + u32 spad_size, ctrl_size; + u64 size; + struct pci_epf *epf = ntb->epf; + struct device *dev = &epf->dev; + u32 spad_count; + void *base; + int i; + const struct pci_epc_features *epc_features = pci_epc_get_features(epf->epc, + epf->func_no, + epf->vfunc_no); + barno = ntb->epf_ntb_bar[BAR_CONFIG]; + size = epc_features->bar_fixed_size[barno]; + align = epc_features->align; + + if ((!IS_ALIGNED(size, align))) + return -EINVAL; + + spad_count = ntb->spad_count; + + ctrl_size = sizeof(struct epf_ntb_ctrl); + spad_size = 2 * spad_count * 4; + + if (!align) { + ctrl_size = roundup_pow_of_two(ctrl_size); + spad_size = roundup_pow_of_two(spad_size); + } else { + ctrl_size = ALIGN(ctrl_size, align); + spad_size = ALIGN(spad_size, align); + } + + if (!size) + size = ctrl_size + spad_size; + else if (size < ctrl_size + spad_size) + return -EINVAL; + + base = pci_epf_alloc_space(epf, size, barno, align, 0); + if (!base) { + dev_err(dev, "Config/Status/SPAD alloc region fail\n"); + return -ENOMEM; + } + + ntb->reg = base; + + ctrl = ntb->reg; + ctrl->spad_offset = ctrl_size; + + ctrl->spad_count = spad_count; + ctrl->num_mws = ntb->num_mws; + ntb->spad_size = spad_size; + + ctrl->db_entry_size = 4; + + for (i = 0; i < ntb->db_count; i++) { + ntb->reg->db_data[i] = 1 + i; + ntb->reg->db_offset[i] = 0; + } + + return 0; +} + +/** + * epf_ntb_configure_interrupt() - Configure MSI/MSI-X capaiblity + * @ntb: NTB device that facilitates communication between HOST and vHOST + * + * Configure MSI/MSI-X capability for each interface with number of + * interrupts equal to "db_count" configfs entry. + */ +static int epf_ntb_configure_interrupt(struct epf_ntb *ntb) +{ + const struct pci_epc_features *epc_features; + struct device *dev; + u32 db_count; + int ret; + + dev = &ntb->epf->dev; + + epc_features = pci_epc_get_features(ntb->epf->epc, ntb->epf->func_no, ntb->epf->vfunc_no); + + if (!(epc_features->msix_capable || epc_features->msi_capable)) { + dev_err(dev, "MSI or MSI-X is required for doorbell\n"); + return -EINVAL; + } + + db_count = ntb->db_count; + if (db_count > MAX_DB_COUNT) { + dev_err(dev, "DB count cannot be more than %d\n", MAX_DB_COUNT); + return -EINVAL; + } + + ntb->db_count = db_count; + + if (epc_features->msi_capable) { + ret = pci_epc_set_msi(ntb->epf->epc, + ntb->epf->func_no, + ntb->epf->vfunc_no, + 16); + if (ret) { + dev_err(dev, "MSI configuration failed\n"); + return ret; + } + } + + return 0; +} + +/** + * epf_ntb_db_bar_init() - Configure Doorbell window BARs + * @ntb: NTB device that facilitates communication between HOST and vHOST + */ +static int epf_ntb_db_bar_init(struct epf_ntb *ntb) +{ + const struct pci_epc_features *epc_features; + u32 align; + struct device *dev = &ntb->epf->dev; + int ret; + struct pci_epf_bar *epf_bar; + void __iomem *mw_addr; + enum pci_barno barno; + size_t size = 4 * ntb->db_count; + + epc_features = pci_epc_get_features(ntb->epf->epc, + ntb->epf->func_no, + ntb->epf->vfunc_no); + align = epc_features->align; + + if (size < 128) + size = 128; + + if (align) + size = ALIGN(size, align); + else + size = roundup_pow_of_two(size); + + barno = ntb->epf_ntb_bar[BAR_DB]; + + mw_addr = pci_epf_alloc_space(ntb->epf, size, barno, align, 0); + if (!mw_addr) { + dev_err(dev, "Failed to allocate OB address\n"); + return -ENOMEM; + } + + ntb->epf_db = mw_addr; + + epf_bar = &ntb->epf->bar[barno]; + + ret = pci_epc_set_bar(ntb->epf->epc, ntb->epf->func_no, ntb->epf->vfunc_no, epf_bar); + if (ret) { + dev_err(dev, "Doorbell BAR set failed\n"); + goto err_alloc_peer_mem; + } + return ret; + +err_alloc_peer_mem: + pci_epc_mem_free_addr(ntb->epf->epc, epf_bar->phys_addr, mw_addr, epf_bar->size); + return -1; +} + +/** + * epf_ntb_db_bar_clear() - Clear doorbell BAR and free memory + * allocated in peer's outbound address space + * @ntb: NTB device that facilitates communication between HOST and vHOST + */ +static void epf_ntb_db_bar_clear(struct epf_ntb *ntb) +{ + enum pci_barno barno; + + barno = ntb->epf_ntb_bar[BAR_DB]; + pci_epf_free_space(ntb->epf, ntb->epf_db, barno, 0); + pci_epc_clear_bar(ntb->epf->epc, + ntb->epf->func_no, + ntb->epf->vfunc_no, + &ntb->epf->bar[barno]); +} + +/** + * epf_ntb_mw_bar_init() - Configure Memory window BARs + * @ntb: NTB device that facilitates communication between HOST and vHOST + * + */ +static int epf_ntb_mw_bar_init(struct epf_ntb *ntb) +{ + int ret = 0; + int i; + u64 size; + enum pci_barno barno; + struct device *dev = &ntb->epf->dev; + + for (i = 0; i < ntb->num_mws; i++) { + size = ntb->mws_size[i]; + barno = ntb->epf_ntb_bar[BAR_MW0 + i]; + + ntb->epf->bar[barno].barno = barno; + ntb->epf->bar[barno].size = size; + ntb->epf->bar[barno].addr = 0; + ntb->epf->bar[barno].phys_addr = 0; + ntb->epf->bar[barno].flags |= upper_32_bits(size) ? + PCI_BASE_ADDRESS_MEM_TYPE_64 : + PCI_BASE_ADDRESS_MEM_TYPE_32; + + ret = pci_epc_set_bar(ntb->epf->epc, + ntb->epf->func_no, + ntb->epf->vfunc_no, + &ntb->epf->bar[barno]); + if (ret) { + dev_err(dev, "MW set failed\n"); + goto err_alloc_mem; + } + + /* Allocate EPC outbound memory windows to vpci vntb device */ + ntb->vpci_mw_addr[i] = pci_epc_mem_alloc_addr(ntb->epf->epc, + &ntb->vpci_mw_phy[i], + size); + if (!ntb->vpci_mw_addr[i]) { + dev_err(dev, "Failed to allocate source address\n"); + goto err_alloc_mem; + } + } + + return ret; +err_alloc_mem: + return ret; +} + +/** + * epf_ntb_mw_bar_clear() - Clear Memory window BARs + * @ntb: NTB device that facilitates communication between HOST and vHOST + */ +static void epf_ntb_mw_bar_clear(struct epf_ntb *ntb) +{ + enum pci_barno barno; + int i; + + for (i = 0; i < ntb->num_mws; i++) { + barno = ntb->epf_ntb_bar[BAR_MW0 + i]; + pci_epc_clear_bar(ntb->epf->epc, + ntb->epf->func_no, + ntb->epf->vfunc_no, + &ntb->epf->bar[barno]); + + pci_epc_mem_free_addr(ntb->epf->epc, + ntb->vpci_mw_phy[i], + ntb->vpci_mw_addr[i], + ntb->mws_size[i]); + } +} + +/** + * epf_ntb_epc_destroy() - Cleanup NTB EPC interface + * @ntb: NTB device that facilitates communication between HOST and vHOST + * + * Wrapper for epf_ntb_epc_destroy_interface() to cleanup all the NTB interfaces + */ +static void epf_ntb_epc_destroy(struct epf_ntb *ntb) +{ + pci_epc_remove_epf(ntb->epf->epc, ntb->epf, 0); + pci_epc_put(ntb->epf->epc); +} + +/** + * epf_ntb_init_epc_bar() - Identify BARs to be used for each of the NTB + * constructs (scratchpad region, doorbell, memorywindow) + * @ntb: NTB device that facilitates communication between HOST and vHOST + */ +static int epf_ntb_init_epc_bar(struct epf_ntb *ntb) +{ + const struct pci_epc_features *epc_features; + enum pci_barno barno; + enum epf_ntb_bar bar; + struct device *dev; + u32 num_mws; + int i; + + barno = BAR_0; + num_mws = ntb->num_mws; + dev = &ntb->epf->dev; + epc_features = pci_epc_get_features(ntb->epf->epc, ntb->epf->func_no, ntb->epf->vfunc_no); + + /* These are required BARs which are mandatory for NTB functionality */ + for (bar = BAR_CONFIG; bar <= BAR_MW0; bar++, barno++) { + barno = pci_epc_get_next_free_bar(epc_features, barno); + if (barno < 0) { + dev_err(dev, "Fail to get NTB function BAR\n"); + return barno; + } + ntb->epf_ntb_bar[bar] = barno; + } + + /* These are optional BARs which don't impact NTB functionality */ + for (bar = BAR_MW1, i = 1; i < num_mws; bar++, barno++, i++) { + barno = pci_epc_get_next_free_bar(epc_features, barno); + if (barno < 0) { + ntb->num_mws = i; + dev_dbg(dev, "BAR not available for > MW%d\n", i + 1); + } + ntb->epf_ntb_bar[bar] = barno; + } + + return 0; +} + +/** + * epf_ntb_epc_init() - Initialize NTB interface + * @ntb: NTB device that facilitates communication between HOST and vHOST2 + * + * Wrapper to initialize a particular EPC interface and start the workqueue + * to check for commands from host. This function will write to the + * EP controller HW for configuring it. + */ +static int epf_ntb_epc_init(struct epf_ntb *ntb) +{ + u8 func_no, vfunc_no; + struct pci_epc *epc; + struct pci_epf *epf; + struct device *dev; + int ret; + + epf = ntb->epf; + dev = &epf->dev; + epc = epf->epc; + func_no = ntb->epf->func_no; + vfunc_no = ntb->epf->vfunc_no; + + ret = epf_ntb_config_sspad_bar_set(ntb); + if (ret) { + dev_err(dev, "Config/self SPAD BAR init failed"); + return ret; + } + + ret = epf_ntb_configure_interrupt(ntb); + if (ret) { + dev_err(dev, "Interrupt configuration failed\n"); + goto err_config_interrupt; + } + + ret = epf_ntb_db_bar_init(ntb); + if (ret) { + dev_err(dev, "DB BAR init failed\n"); + goto err_db_bar_init; + } + + ret = epf_ntb_mw_bar_init(ntb); + if (ret) { + dev_err(dev, "MW BAR init failed\n"); + goto err_mw_bar_init; + } + + if (vfunc_no <= 1) { + ret = pci_epc_write_header(epc, func_no, vfunc_no, epf->header); + if (ret) { + dev_err(dev, "Configuration header write failed\n"); + goto err_write_header; + } + } + + INIT_DELAYED_WORK(&ntb->cmd_handler, epf_ntb_cmd_handler); + queue_work(kpcintb_workqueue, &ntb->cmd_handler.work); + + return 0; + +err_write_header: + epf_ntb_mw_bar_clear(ntb); +err_mw_bar_init: + epf_ntb_db_bar_clear(ntb); +err_db_bar_init: +err_config_interrupt: + epf_ntb_config_sspad_bar_clear(ntb); + + return ret; +} + + +/** + * epf_ntb_epc_cleanup() - Cleanup all NTB interfaces + * @ntb: NTB device that facilitates communication between HOST1 and HOST2 + * + * Wrapper to cleanup all NTB interfaces. + */ +static void epf_ntb_epc_cleanup(struct epf_ntb *ntb) +{ + epf_ntb_db_bar_clear(ntb); + epf_ntb_mw_bar_clear(ntb); +} + +#define EPF_NTB_R(_name) \ +static ssize_t epf_ntb_##_name##_show(struct config_item *item, \ + char *page) \ +{ \ + struct config_group *group = to_config_group(item); \ + struct epf_ntb *ntb = to_epf_ntb(group); \ + \ + return sprintf(page, "%d\n", ntb->_name); \ +} + +#define EPF_NTB_W(_name) \ +static ssize_t epf_ntb_##_name##_store(struct config_item *item, \ + const char *page, size_t len) \ +{ \ + struct config_group *group = to_config_group(item); \ + struct epf_ntb *ntb = to_epf_ntb(group); \ + u32 val; \ + int ret; \ + \ + ret = kstrtou32(page, 0, &val); \ + if (ret) \ + return ret; \ + \ + ntb->_name = val; \ + \ + return len; \ +} + +#define EPF_NTB_MW_R(_name) \ +static ssize_t epf_ntb_##_name##_show(struct config_item *item, \ + char *page) \ +{ \ + struct config_group *group = to_config_group(item); \ + struct epf_ntb *ntb = to_epf_ntb(group); \ + int win_no; \ + \ + sscanf(#_name, "mw%d", &win_no); \ + \ + return sprintf(page, "%lld\n", ntb->mws_size[win_no - 1]); \ +} + +#define EPF_NTB_MW_W(_name) \ +static ssize_t epf_ntb_##_name##_store(struct config_item *item, \ + const char *page, size_t len) \ +{ \ + struct config_group *group = to_config_group(item); \ + struct epf_ntb *ntb = to_epf_ntb(group); \ + struct device *dev = &ntb->epf->dev; \ + int win_no; \ + u64 val; \ + int ret; \ + \ + ret = kstrtou64(page, 0, &val); \ + if (ret) \ + return ret; \ + \ + if (sscanf(#_name, "mw%d", &win_no) != 1) \ + return -EINVAL; \ + \ + if (ntb->num_mws < win_no) { \ + dev_err(dev, "Invalid num_nws: %d value\n", ntb->num_mws); \ + return -EINVAL; \ + } \ + \ + ntb->mws_size[win_no - 1] = val; \ + \ + return len; \ +} + +static ssize_t epf_ntb_num_mws_store(struct config_item *item, + const char *page, size_t len) +{ + struct config_group *group = to_config_group(item); + struct epf_ntb *ntb = to_epf_ntb(group); + u32 val; + int ret; + + ret = kstrtou32(page, 0, &val); + if (ret) + return ret; + + if (val > MAX_MW) + return -EINVAL; + + ntb->num_mws = val; + + return len; +} + +EPF_NTB_R(spad_count) +EPF_NTB_W(spad_count) +EPF_NTB_R(db_count) +EPF_NTB_W(db_count) +EPF_NTB_R(num_mws) +EPF_NTB_R(vbus_number) +EPF_NTB_W(vbus_number) +EPF_NTB_R(vntb_pid) +EPF_NTB_W(vntb_pid) +EPF_NTB_R(vntb_vid) +EPF_NTB_W(vntb_vid) +EPF_NTB_MW_R(mw1) +EPF_NTB_MW_W(mw1) +EPF_NTB_MW_R(mw2) +EPF_NTB_MW_W(mw2) +EPF_NTB_MW_R(mw3) +EPF_NTB_MW_W(mw3) +EPF_NTB_MW_R(mw4) +EPF_NTB_MW_W(mw4) + +CONFIGFS_ATTR(epf_ntb_, spad_count); +CONFIGFS_ATTR(epf_ntb_, db_count); +CONFIGFS_ATTR(epf_ntb_, num_mws); +CONFIGFS_ATTR(epf_ntb_, mw1); +CONFIGFS_ATTR(epf_ntb_, mw2); +CONFIGFS_ATTR(epf_ntb_, mw3); +CONFIGFS_ATTR(epf_ntb_, mw4); +CONFIGFS_ATTR(epf_ntb_, vbus_number); +CONFIGFS_ATTR(epf_ntb_, vntb_pid); +CONFIGFS_ATTR(epf_ntb_, vntb_vid); + +static struct configfs_attribute *epf_ntb_attrs[] = { + &epf_ntb_attr_spad_count, + &epf_ntb_attr_db_count, + &epf_ntb_attr_num_mws, + &epf_ntb_attr_mw1, + &epf_ntb_attr_mw2, + &epf_ntb_attr_mw3, + &epf_ntb_attr_mw4, + &epf_ntb_attr_vbus_number, + &epf_ntb_attr_vntb_pid, + &epf_ntb_attr_vntb_vid, + NULL, +}; + +static const struct config_item_type ntb_group_type = { + .ct_attrs = epf_ntb_attrs, + .ct_owner = THIS_MODULE, +}; + +/** + * epf_ntb_add_cfs() - Add configfs directory specific to NTB + * @epf: NTB endpoint function device + * @group: A pointer to the config_group structure referencing a group of + * config_items of a specific type that belong to a specific sub-system. + * + * Add configfs directory specific to NTB. This directory will hold + * NTB specific properties like db_count, spad_count, num_mws etc., + */ +static struct config_group *epf_ntb_add_cfs(struct pci_epf *epf, + struct config_group *group) +{ + struct epf_ntb *ntb = epf_get_drvdata(epf); + struct config_group *ntb_group = &ntb->group; + struct device *dev = &epf->dev; + + config_group_init_type_name(ntb_group, dev_name(dev), &ntb_group_type); + + return ntb_group; +} + +/*==== virtual PCI bus driver, which only load virtual NTB PCI driver ====*/ + +static u32 pci_space[] = { + 0xffffffff, /*DeviceID, Vendor ID*/ + 0, /*Status, Command*/ + 0xffffffff, /*Class code, subclass, prog if, revision id*/ + 0x40, /*bist, header type, latency Timer, cache line size*/ + 0, /*BAR 0*/ + 0, /*BAR 1*/ + 0, /*BAR 2*/ + 0, /*BAR 3*/ + 0, /*BAR 4*/ + 0, /*BAR 5*/ + 0, /*Cardbus cis point*/ + 0, /*Subsystem ID Subystem vendor id*/ + 0, /*ROM Base Address*/ + 0, /*Reserved, Cap. Point*/ + 0, /*Reserved,*/ + 0, /*Max Lat, Min Gnt, interrupt pin, interrupt line*/ +}; + +int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) +{ + if (devfn == 0) { + memcpy(val, ((u8 *)pci_space) + where, size); + return PCIBIOS_SUCCESSFUL; + } + return PCIBIOS_DEVICE_NOT_FOUND; +} + +int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) +{ + return 0; +} + +struct pci_ops vpci_ops = { + .read = pci_read, + .write = pci_write, +}; + +static int vpci_scan_bus(void *sysdata) +{ + struct pci_bus *vpci_bus; + struct epf_ntb *ndev = sysdata; + + vpci_bus = pci_scan_bus(ndev->vbus_number, &vpci_ops, sysdata); + if (vpci_bus) + pr_err("create pci bus\n"); + + pci_bus_add_devices(vpci_bus); + + return 0; +} + +/*==================== Virtual PCIe NTB driver ==========================*/ + +static int vntb_epf_mw_count(struct ntb_dev *ntb, int pidx) +{ + struct epf_ntb *ndev = ntb_ndev(ntb); + + return ndev->num_mws; +} + +static int vntb_epf_spad_count(struct ntb_dev *ntb) +{ + return ntb_ndev(ntb)->spad_count; +} + +static int vntb_epf_peer_mw_count(struct ntb_dev *ntb) +{ + return ntb_ndev(ntb)->num_mws; +} + +static u64 vntb_epf_db_valid_mask(struct ntb_dev *ntb) +{ + return BIT_ULL(ntb_ndev(ntb)->db_count) - 1; +} + +static int vntb_epf_db_set_mask(struct ntb_dev *ntb, u64 db_bits) +{ + return 0; +} + +static int vntb_epf_mw_set_trans(struct ntb_dev *ndev, int pidx, int idx, + dma_addr_t addr, resource_size_t size) +{ + struct epf_ntb *ntb = ntb_ndev(ndev); + struct pci_epf_bar *epf_bar; + enum pci_barno barno; + int ret; + struct device *dev; + + dev = &ntb->ntb.dev; + barno = ntb->epf_ntb_bar[BAR_MW0 + idx]; + epf_bar = &ntb->epf->bar[barno]; + epf_bar->phys_addr = addr; + epf_bar->barno = barno; + epf_bar->size = size; + + ret = pci_epc_set_bar(ntb->epf->epc, 0, 0, epf_bar); + if (ret) { + dev_err(dev, "failure set mw trans\n"); + return ret; + } + return 0; +} + +static int vntb_epf_mw_clear_trans(struct ntb_dev *ntb, int pidx, int idx) +{ + return 0; +} + +static int vntb_epf_peer_mw_get_addr(struct ntb_dev *ndev, int idx, + phys_addr_t *base, resource_size_t *size) +{ + + struct epf_ntb *ntb = ntb_ndev(ndev); + + if (base) + *base = ntb->vpci_mw_phy[idx]; + + if (size) + *size = ntb->mws_size[idx]; + + return 0; +} + +static int vntb_epf_link_enable(struct ntb_dev *ntb, + enum ntb_speed max_speed, + enum ntb_width max_width) +{ + return 0; +} + +static u32 vntb_epf_spad_read(struct ntb_dev *ndev, int idx) +{ + struct epf_ntb *ntb = ntb_ndev(ndev); + int off = ntb->reg->spad_offset, ct = ntb->reg->spad_count * 4; + u32 val; + void __iomem *base = ntb->reg; + + val = readl(base + off + ct + idx * 4); + return val; +} + +static int vntb_epf_spad_write(struct ntb_dev *ndev, int idx, u32 val) +{ + struct epf_ntb *ntb = ntb_ndev(ndev); + struct epf_ntb_ctrl *ctrl = ntb->reg; + int off = ctrl->spad_offset, ct = ctrl->spad_count * 4; + void __iomem *base = ntb->reg; + + writel(val, base + off + ct + idx * 4); + return 0; +} + +static u32 vntb_epf_peer_spad_read(struct ntb_dev *ndev, int pidx, int idx) +{ + struct epf_ntb *ntb = ntb_ndev(ndev); + struct epf_ntb_ctrl *ctrl = ntb->reg; + int off = ctrl->spad_offset; + void __iomem *base = ntb->reg; + u32 val; + + val = readl(base + off + idx * 4); + return val; +} + +static int vntb_epf_peer_spad_write(struct ntb_dev *ndev, int pidx, int idx, u32 val) +{ + struct epf_ntb *ntb = ntb_ndev(ndev); + struct epf_ntb_ctrl *ctrl = ntb->reg; + int off = ctrl->spad_offset; + void __iomem *base = ntb->reg; + + writel(val, base + off + idx * 4); + return 0; +} + +static int vntb_epf_peer_db_set(struct ntb_dev *ndev, u64 db_bits) +{ + u32 interrupt_num = ffs(db_bits) + 1; + struct epf_ntb *ntb = ntb_ndev(ndev); + u8 func_no, vfunc_no; + int ret; + + func_no = ntb->epf->func_no; + vfunc_no = ntb->epf->vfunc_no; + + ret = pci_epc_raise_irq(ntb->epf->epc, + func_no, + vfunc_no, + PCI_EPC_IRQ_MSI, + interrupt_num + 1); + if (ret) + dev_err(&ntb->ntb.dev, "Failed to raise IRQ\n"); + + return ret; +} + +static u64 vntb_epf_db_read(struct ntb_dev *ndev) +{ + struct epf_ntb *ntb = ntb_ndev(ndev); + + return ntb->db; +} + +static int vntb_epf_mw_get_align(struct ntb_dev *ndev, int pidx, int idx, + resource_size_t *addr_align, + resource_size_t *size_align, + resource_size_t *size_max) +{ + struct epf_ntb *ntb = ntb_ndev(ndev); + + if (addr_align) + *addr_align = SZ_4K; + + if (size_align) + *size_align = 1; + + if (size_max) + *size_max = ntb->mws_size[idx]; + + return 0; +} + +static u64 vntb_epf_link_is_up(struct ntb_dev *ndev, + enum ntb_speed *speed, + enum ntb_width *width) +{ + struct epf_ntb *ntb = ntb_ndev(ndev); + + return ntb->reg->link_status; +} + +static int vntb_epf_db_clear_mask(struct ntb_dev *ndev, u64 db_bits) +{ + return 0; +} + +static int vntb_epf_db_clear(struct ntb_dev *ndev, u64 db_bits) +{ + struct epf_ntb *ntb = ntb_ndev(ndev); + + ntb->db &= ~db_bits; + return 0; +} + +static int vntb_epf_link_disable(struct ntb_dev *ntb) +{ + return 0; +} + +static const struct ntb_dev_ops vntb_epf_ops = { + .mw_count = vntb_epf_mw_count, + .spad_count = vntb_epf_spad_count, + .peer_mw_count = vntb_epf_peer_mw_count, + .db_valid_mask = vntb_epf_db_valid_mask, + .db_set_mask = vntb_epf_db_set_mask, + .mw_set_trans = vntb_epf_mw_set_trans, + .mw_clear_trans = vntb_epf_mw_clear_trans, + .peer_mw_get_addr = vntb_epf_peer_mw_get_addr, + .link_enable = vntb_epf_link_enable, + .spad_read = vntb_epf_spad_read, + .spad_write = vntb_epf_spad_write, + .peer_spad_read = vntb_epf_peer_spad_read, + .peer_spad_write = vntb_epf_peer_spad_write, + .peer_db_set = vntb_epf_peer_db_set, + .db_read = vntb_epf_db_read, + .mw_get_align = vntb_epf_mw_get_align, + .link_is_up = vntb_epf_link_is_up, + .db_clear_mask = vntb_epf_db_clear_mask, + .db_clear = vntb_epf_db_clear, + .link_disable = vntb_epf_link_disable, +}; + +static int pci_vntb_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + int ret; + struct epf_ntb *ndev = (struct epf_ntb *)pdev->sysdata; + struct device *dev = &pdev->dev; + + ndev->ntb.pdev = pdev; + ndev->ntb.topo = NTB_TOPO_NONE; + ndev->ntb.ops = &vntb_epf_ops; + + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); + if (ret) { + dev_err(dev, "Cannot set DMA mask\n"); + return -EINVAL; + } + + ret = ntb_register_device(&ndev->ntb); + if (ret) { + dev_err(dev, "Failed to register NTB device\n"); + goto err_register_dev; + } + + dev_dbg(dev, "PCI Virtual NTB driver loaded\n"); + return 0; + +err_register_dev: + return -EINVAL; +} + +static struct pci_device_id pci_vntb_table[] = { + { + PCI_DEVICE(0xffff, 0xffff), + }, + {}, +}; + +static struct pci_driver vntb_pci_driver = { + .name = "pci-vntb", + .id_table = pci_vntb_table, + .probe = pci_vntb_probe, +}; + +/* ============ PCIe EPF Driver Bind ====================*/ + +/** + * epf_ntb_bind() - Initialize endpoint controller to provide NTB functionality + * @epf: NTB endpoint function device + * + * Initialize both the endpoint controllers associated with NTB function device. + * Invoked when a primary interface or secondary interface is bound to EPC + * device. This function will succeed only when EPC is bound to both the + * interfaces. + */ +static int epf_ntb_bind(struct pci_epf *epf) +{ + struct epf_ntb *ntb = epf_get_drvdata(epf); + struct device *dev = &epf->dev; + int ret; + + if (!epf->epc) { + dev_dbg(dev, "PRIMARY EPC interface not yet bound\n"); + return 0; + } + + ret = epf_ntb_init_epc_bar(ntb); + if (ret) { + dev_err(dev, "Failed to create NTB EPC\n"); + goto err_bar_init; + } + + ret = epf_ntb_config_spad_bar_alloc(ntb); + if (ret) { + dev_err(dev, "Failed to allocate BAR memory\n"); + goto err_bar_alloc; + } + + ret = epf_ntb_epc_init(ntb); + if (ret) { + dev_err(dev, "Failed to initialize EPC\n"); + goto err_bar_alloc; + } + + epf_set_drvdata(epf, ntb); + + pci_space[0] = (ntb->vntb_pid << 16) | ntb->vntb_vid; + pci_vntb_table[0].vendor = ntb->vntb_vid; + pci_vntb_table[0].device = ntb->vntb_pid; + + if (pci_register_driver(&vntb_pci_driver)) { + dev_err(dev, "failure register vntb pci driver\n"); + goto err_bar_alloc; + } + + vpci_scan_bus(ntb); + + return 0; + +err_bar_alloc: + epf_ntb_config_spad_bar_free(ntb); + +err_bar_init: + epf_ntb_epc_destroy(ntb); + + return ret; +} + +/** + * epf_ntb_unbind() - Cleanup the initialization from epf_ntb_bind() + * @epf: NTB endpoint function device + * + * Cleanup the initialization from epf_ntb_bind() + */ +static void epf_ntb_unbind(struct pci_epf *epf) +{ + struct epf_ntb *ntb = epf_get_drvdata(epf); + + epf_ntb_epc_cleanup(ntb); + epf_ntb_config_spad_bar_free(ntb); + epf_ntb_epc_destroy(ntb); + + pci_unregister_driver(&vntb_pci_driver); +} + +// EPF driver probe +static struct pci_epf_ops epf_ntb_ops = { + .bind = epf_ntb_bind, + .unbind = epf_ntb_unbind, + .add_cfs = epf_ntb_add_cfs, +}; + +/** + * epf_ntb_probe() - Probe NTB function driver + * @epf: NTB endpoint function device + * + * Probe NTB function driver when endpoint function bus detects a NTB + * endpoint function. + */ +static int epf_ntb_probe(struct pci_epf *epf) +{ + struct epf_ntb *ntb; + struct device *dev; + + dev = &epf->dev; + + ntb = devm_kzalloc(dev, sizeof(*ntb), GFP_KERNEL); + if (!ntb) + return -ENOMEM; + + epf->header = &epf_ntb_header; + ntb->epf = epf; + ntb->vbus_number = 0xff; + epf_set_drvdata(epf, ntb); + + dev_info(dev, "pci-ep epf driver loaded\n"); + return 0; +} + +static const struct pci_epf_device_id epf_ntb_ids[] = { + { + .name = "pci_epf_vntb", + }, + {}, +}; + +static struct pci_epf_driver epf_ntb_driver = { + .driver.name = "pci_epf_vntb", + .probe = epf_ntb_probe, + .id_table = epf_ntb_ids, + .ops = &epf_ntb_ops, + .owner = THIS_MODULE, +}; + +static int __init epf_ntb_init(void) +{ + int ret; + + kpcintb_workqueue = alloc_workqueue("kpcintb", WQ_MEM_RECLAIM | + WQ_HIGHPRI, 0); + ret = pci_epf_register_driver(&epf_ntb_driver); + if (ret) { + destroy_workqueue(kpcintb_workqueue); + pr_err("Failed to register pci epf ntb driver --> %d\n", ret); + return ret; + } + + return 0; +} +module_init(epf_ntb_init); + +static void __exit epf_ntb_exit(void) +{ + pci_epf_unregister_driver(&epf_ntb_driver); + destroy_workqueue(kpcintb_workqueue); +} +module_exit(epf_ntb_exit); + +MODULE_DESCRIPTION("PCI EPF NTB DRIVER"); +MODULE_AUTHOR("Frank Li "); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 4ac8c8e52cd915c7efbd60f1eab4afe855f2e7c4 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 22 Feb 2022 10:23:55 -0600 Subject: Documentation: PCI: Add specification for the PCI vNTB function device Add specification for the PCI vNTB function device. The endpoint function driver and the host PCI driver should be created based on this specification. Signed-off-by: Frank Li Signed-off-by: Jon Mason --- Documentation/PCI/endpoint/index.rst | 2 + Documentation/PCI/endpoint/pci-vntb-function.rst | 126 +++++++++++++++++ Documentation/PCI/endpoint/pci-vntb-howto.rst | 167 +++++++++++++++++++++++ 3 files changed, 295 insertions(+) create mode 100644 Documentation/PCI/endpoint/pci-vntb-function.rst create mode 100644 Documentation/PCI/endpoint/pci-vntb-howto.rst diff --git a/Documentation/PCI/endpoint/index.rst b/Documentation/PCI/endpoint/index.rst index 38ea1f604b6d..4d2333e7ae06 100644 --- a/Documentation/PCI/endpoint/index.rst +++ b/Documentation/PCI/endpoint/index.rst @@ -13,6 +13,8 @@ PCI Endpoint Framework pci-test-howto pci-ntb-function pci-ntb-howto + pci-vntb-function + pci-vntb-howto function/binding/pci-test function/binding/pci-ntb diff --git a/Documentation/PCI/endpoint/pci-vntb-function.rst b/Documentation/PCI/endpoint/pci-vntb-function.rst new file mode 100644 index 000000000000..cad8013e8839 --- /dev/null +++ b/Documentation/PCI/endpoint/pci-vntb-function.rst @@ -0,0 +1,126 @@ +.. SPDX-License-Identifier: GPL-2.0 + +================= +PCI vNTB Function +================= + +:Author: Frank Li + +The difference between PCI NTB function and PCI vNTB function is + +PCI NTB function need at two endpoint instances and connect HOST1 +and HOST2. + +PCI vNTB function only use one host and one endpoint(EP), use NTB +connect EP and PCI host + +.. code-block:: text + + + +------------+ +---------------------------------------+ + | | | | + +------------+ | +--------------+ + | NTB | | | NTB | + | NetDev | | | NetDev | + +------------+ | +--------------+ + | NTB | | | NTB | + | Transfer | | | Transfer | + +------------+ | +--------------+ + | | | | | + | PCI NTB | | | | + | EPF | | | | + | Driver | | | PCI Virtual | + | | +---------------+ | NTB Driver | + | | | PCI EP NTB |<------>| | + | | | FN Driver | | | + +------------+ +---------------+ +--------------+ + | | | | | | + | PCI BUS | <-----> | PCI EP BUS | | Virtual PCI | + | | PCI | | | BUS | + +------------+ +---------------+--------+--------------+ + PCI RC PCI EP + +Constructs used for Implementing vNTB +===================================== + + 1) Config Region + 2) Self Scratchpad Registers + 3) Peer Scratchpad Registers + 4) Doorbell (DB) Registers + 5) Memory Window (MW) + + +Config Region: +-------------- + +It is same as PCI NTB Function driver + +Scratchpad Registers: +--------------------- + + It is appended after Config region. + + +--------------------------------------------------+ Base + | | + | | + | | + | Common Config Register | + | | + | | + | | + +-----------------------+--------------------------+ Base + span_offset + | | | + | Peer Span Space | Span Space | + | | | + | | | + +-----------------------+--------------------------+ Base + span_offset + | | | + span_count * 4 + | | | + | Span Space | Peer Span Space | + | | | + +-----------------------+--------------------------+ + Virtual PCI Pcie Endpoint + NTB Driver NTB Driver + + +Doorbell Registers: +------------------- + + Doorbell Registers are used by the hosts to interrupt each other. + +Memory Window: +-------------- + + Actual transfer of data between the two hosts will happen using the + memory window. + +Modeling Constructs: +==================== + +32-bit BARs. + +====== =============== +BAR NO CONSTRUCTS USED +====== =============== +BAR0 Config Region +BAR1 Doorbell +BAR2 Memory Window 1 +BAR3 Memory Window 2 +BAR4 Memory Window 3 +BAR5 Memory Window 4 +====== =============== + +64-bit BARs. + +====== =============================== +BAR NO CONSTRUCTS USED +====== =============================== +BAR0 Config Region + Scratchpad +BAR1 +BAR2 Doorbell +BAR3 +BAR4 Memory Window 1 +BAR5 +====== =============================== + + diff --git a/Documentation/PCI/endpoint/pci-vntb-howto.rst b/Documentation/PCI/endpoint/pci-vntb-howto.rst new file mode 100644 index 000000000000..524cd487e184 --- /dev/null +++ b/Documentation/PCI/endpoint/pci-vntb-howto.rst @@ -0,0 +1,167 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=================================================================== +PCI Non-Transparent Bridge (NTB) Endpoint Function (EPF) User Guide +=================================================================== + +:Author: Frank Li + +This document is a guide to help users use pci-epf-vntb function driver +and ntb_hw_epf host driver for NTB functionality. The list of steps to +be followed in the host side and EP side is given below. For the hardware +configuration and internals of NTB using configurable endpoints see +Documentation/PCI/endpoint/pci-vntb-function.rst + +Endpoint Device +=============== + +Endpoint Controller Devices +--------------------------- + +To find the list of endpoint controller devices in the system:: + + # ls /sys/class/pci_epc/ + 5f010000.pcie_ep + +If PCI_ENDPOINT_CONFIGFS is enabled:: + + # ls /sys/kernel/config/pci_ep/controllers + 5f010000.pcie_ep + +Endpoint Function Drivers +------------------------- + +To find the list of endpoint function drivers in the system:: + + # ls /sys/bus/pci-epf/drivers + pci_epf_ntb pci_epf_test pci_epf_vntb + +If PCI_ENDPOINT_CONFIGFS is enabled:: + + # ls /sys/kernel/config/pci_ep/functions + pci_epf_ntb pci_epf_test pci_epf_vntb + + +Creating pci-epf-vntb Device +---------------------------- + +PCI endpoint function device can be created using the configfs. To create +pci-epf-vntb device, the following commands can be used:: + + # mount -t configfs none /sys/kernel/config + # cd /sys/kernel/config/pci_ep/ + # mkdir functions/pci_epf_vntb/func1 + +The "mkdir func1" above creates the pci-epf-ntb function device that will +be probed by pci_epf_vntb driver. + +The PCI endpoint framework populates the directory with the following +configurable fields:: + + # ls functions/pci_epf_ntb/func1 + baseclass_code deviceid msi_interrupts pci-epf-ntb.0 + progif_code secondary subsys_id vendorid + cache_line_size interrupt_pin msix_interrupts primary + revid subclass_code subsys_vendor_id + +The PCI endpoint function driver populates these entries with default values +when the device is bound to the driver. The pci-epf-vntb driver populates +vendorid with 0xffff and interrupt_pin with 0x0001:: + + # cat functions/pci_epf_vntb/func1/vendorid + 0xffff + # cat functions/pci_epf_vntb/func1/interrupt_pin + 0x0001 + + +Configuring pci-epf-vntb Device +------------------------------- + +The user can configure the pci-epf-vntb device using its configfs entry. In order +to change the vendorid and the deviceid, the following +commands can be used:: + + # echo 0x1957 > functions/pci_epf_vntb/func1/vendorid + # echo 0x0809 > functions/pci_epf_vntb/func1/deviceid + +In order to configure NTB specific attributes, a new sub-directory to func1 +should be created:: + + # mkdir functions/pci_epf_vntb/func1/pci_epf_vntb.0/ + +The NTB function driver will populate this directory with various attributes +that can be configured by the user:: + + # ls functions/pci_epf_vntb/func1/pci_epf_vntb.0/ + db_count mw1 mw2 mw3 mw4 num_mws + spad_count + +A sample configuration for NTB function is given below:: + + # echo 4 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/db_count + # echo 128 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/spad_count + # echo 1 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/num_mws + # echo 0x100000 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/mw1 + +A sample configuration for virtual NTB driver for virutal PCI bus:: + + # echo 0x1957 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/vntb_vid + # echo 0x080A > functions/pci_epf_vntb/func1/pci_epf_vntb.0/vntb_pid + # echo 0x10 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/vbus_number + +Binding pci-epf-ntb Device to EP Controller +-------------------------------------------- + +NTB function device should be attached to PCI endpoint controllers +connected to the host. + + # ln -s controllers/5f010000.pcie_ep functions/pci-epf-ntb/func1/primary + +Once the above step is completed, the PCI endpoint controllers are ready to +establish a link with the host. + + +Start the Link +-------------- + +In order for the endpoint device to establish a link with the host, the _start_ +field should be populated with '1'. For NTB, both the PCI endpoint controllers +should establish link with the host (imx8 don't need this steps):: + + # echo 1 > controllers/5f010000.pcie_ep/start + +RootComplex Device +================== + +lspci Output at Host side +------------------------ + +Note that the devices listed here correspond to the values populated in +"Creating pci-epf-ntb Device" section above:: + + # lspci + 00:00.0 PCI bridge: Freescale Semiconductor Inc Device 0000 (rev 01) + 01:00.0 RAM memory: Freescale Semiconductor Inc Device 0809 + +Endpoint Device / Virtual PCI bus +================================= + +lspci Output at EP Side / Virtual PCI bus +----------------------------------------- + +Note that the devices listed here correspond to the values populated in +"Creating pci-epf-ntb Device" section above:: + + # lspci + 10:00.0 Unassigned class [ffff]: Dawicontrol Computersysteme GmbH Device 1234 (rev ff) + +Using ntb_hw_epf Device +----------------------- + +The host side software follows the standard NTB software architecture in Linux. +All the existing client side NTB utilities like NTB Transport Client and NTB +Netdev, NTB Ping Pong Test Client and NTB Tool Test Client can be used with NTB +function device. + +For more information on NTB see +:doc:`Non-Transparent Bridge <../../driver-api/ntb>` -- cgit v1.2.3 From e9ac6e335dc72cd1296d06e20a7c8bbff8ca19d3 Mon Sep 17 00:00:00 2001 From: Bagas Sanjaya Date: Wed, 22 Jun 2022 16:53:44 +0700 Subject: Documentation: PCI: Use code-block block for scratchpad registers diagram MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The diagram in "Scratchpad Registers" isn't formatted inside code block, hence triggers indentation warning: Documentation/PCI/endpoint/pci-vntb-function.rst:82: WARNING: Unexpected indentation. Fix the warning by using code-block directive to format the diagram inside code block, as in other diagrams in Documentation/. While at it, unindent the preceeding text. Link: https://lore.kernel.org/linux-next/20220621200235.211b2e32@canb.auug.org.au/ Fixes: 0c4b285d9636cc ("Documentation: PCI: Add specification for the PCI vNTB function device") Reported-by: Stephen Rothwell Cc: Kishon Vijay Abraham I Cc: Lorenzo Pieralisi Cc: "Krzysztof Wilczyński" Cc: Bjorn Helgaas Cc: Jonathan Corbet Cc: Frank Li Cc: linux-pci@vger.kernel.org Cc: linux-next@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bagas Sanjaya Signed-off-by: Jon Mason --- Documentation/PCI/endpoint/pci-vntb-function.rst | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/PCI/endpoint/pci-vntb-function.rst b/Documentation/PCI/endpoint/pci-vntb-function.rst index cad8013e8839..0c51f53ab972 100644 --- a/Documentation/PCI/endpoint/pci-vntb-function.rst +++ b/Documentation/PCI/endpoint/pci-vntb-function.rst @@ -58,7 +58,10 @@ It is same as PCI NTB Function driver Scratchpad Registers: --------------------- - It is appended after Config region. +It is appended after Config region. + +.. code-block:: text + +--------------------------------------------------+ Base | | -- cgit v1.2.3 From 9458c27a67e37a574938e9637afe393c3c2a50af Mon Sep 17 00:00:00 2001 From: Bagas Sanjaya Date: Wed, 22 Jun 2022 16:53:45 +0700 Subject: Documentation: PCI: extend subheading underline for "lspci output" section MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The underline syntax for "lspci output..." section is off-by-one less than the section heading's length, hence triggers the warning: Documentation/PCI/endpoint/pci-vntb-howto.rst:131: WARNING: Title underline too short. Extend the underline by one to match the heading length. Link: https://lore.kernel.org/linux-next/20220621200235.211b2e32@canb.auug.org.au/ Fixes: 0c4b285d9636cc ("Documentation: PCI: Add specification for the PCI vNTB function device") Reported-by: Stephen Rothwell Cc: Kishon Vijay Abraham I Cc: Lorenzo Pieralisi Cc: "Krzysztof Wilczyński" Cc: Bjorn Helgaas Cc: Jonathan Corbet Cc: Frank Li Cc: linux-pci@vger.kernel.org Cc: linux-next@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bagas Sanjaya Signed-off-by: Jon Mason --- Documentation/PCI/endpoint/pci-vntb-howto.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/PCI/endpoint/pci-vntb-howto.rst b/Documentation/PCI/endpoint/pci-vntb-howto.rst index 524cd487e184..4ab8e4a26d4b 100644 --- a/Documentation/PCI/endpoint/pci-vntb-howto.rst +++ b/Documentation/PCI/endpoint/pci-vntb-howto.rst @@ -134,7 +134,7 @@ RootComplex Device ================== lspci Output at Host side ------------------------- +------------------------- Note that the devices listed here correspond to the values populated in "Creating pci-epf-ntb Device" section above:: -- cgit v1.2.3 From 7b14a5e96128ec467ea9ced36a32f28ee7892e1f Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Thu, 23 Jun 2022 17:57:09 +0100 Subject: NTB: EPF: set pointer addr to null using NULL rather than 0 The pointer addr is being set to null using 0. Use NULL instead. Cleans up sparse warning: warning: Using plain integer as NULL pointer Signed-off-by: Colin Ian King Signed-off-by: Jon Mason --- drivers/pci/endpoint/functions/pci-epf-vntb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/endpoint/functions/pci-epf-vntb.c index 1466dd190417..599538cd554c 100644 --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c @@ -597,7 +597,7 @@ static int epf_ntb_mw_bar_init(struct epf_ntb *ntb) ntb->epf->bar[barno].barno = barno; ntb->epf->bar[barno].size = size; - ntb->epf->bar[barno].addr = 0; + ntb->epf->bar[barno].addr = NULL; ntb->epf->bar[barno].phys_addr = 0; ntb->epf->bar[barno].flags |= upper_32_bits(size) ? PCI_BASE_ADDRESS_MEM_TYPE_64 : -- cgit v1.2.3 From 556a2c7dca337954040ffdf0c544aa8bbb75583b Mon Sep 17 00:00:00 2001 From: Ren Zhijie Date: Fri, 24 Jun 2022 09:19:11 +0800 Subject: PCI: endpoint: Fix Kconfig dependency If CONFIG_NTB is not set and CONFIG_PCI_EPF_VNTB is y. make ARCH=x86_64 CROSS_COMPILE=x86_64-linux-gnu-, will be failed, like this: drivers/pci/endpoint/functions/pci-epf-vntb.o: In function `epf_ntb_cmd_handler': pci-epf-vntb.c:(.text+0x95e): undefined reference to `ntb_db_event' pci-epf-vntb.c:(.text+0xa1f): undefined reference to `ntb_link_event' pci-epf-vntb.c:(.text+0xa42): undefined reference to `ntb_link_event' drivers/pci/endpoint/functions/pci-epf-vntb.o: In function `pci_vntb_probe': pci-epf-vntb.c:(.text+0x1250): undefined reference to `ntb_register_device' The functions ntb_*() are defined in drivers/ntb/core.c, which need CONFIG_NTB setting y to be build-in. To fix this build error, add depends on NTB. Reported-by: Hulk Robot Fixes: ff32fac00d97("NTB: EPF: support NTB transfer between PCI RC and EP connection") Signed-off-by: Ren Zhijie Acked-by: Frank Li Acked-by: Randy Dunlap Tested-by: Randy Dunlap # build-tested Reported-by: Randy Dunlap Signed-off-by: Jon Mason --- drivers/pci/endpoint/functions/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/endpoint/functions/Kconfig b/drivers/pci/endpoint/functions/Kconfig index 65217428d17b..295a033ee9a2 100644 --- a/drivers/pci/endpoint/functions/Kconfig +++ b/drivers/pci/endpoint/functions/Kconfig @@ -29,6 +29,7 @@ config PCI_EPF_NTB config PCI_EPF_VNTB tristate "PCI Endpoint NTB driver" depends on PCI_ENDPOINT + depends on NTB select CONFIGFS_FS help Select this configuration option to enable the Non-Transparent -- cgit v1.2.3 From 8e4bfbe644a6b804a72fd4575d89507a6e1d9476 Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Sat, 25 Jun 2022 10:15:16 +0800 Subject: PCI: endpoint: pci-epf-vntb: fix error handle in epf_ntb_mw_bar_init() In error case of epf_ntb_mw_bar_init(), memory window BARs should be cleared, so add 'num_mws' parameter in epf_ntb_mw_bar_clear() and calling it in error path to clear the BARs. Also add missing error code when pci_epc_mem_alloc_addr() fails. Fixes: ff32fac00d97 ("NTB: EPF: support NTB transfer between PCI RC and EP connection") Reported-by: Hulk Robot Signed-off-by: Yang Yingliang Signed-off-by: Jon Mason --- drivers/pci/endpoint/functions/pci-epf-vntb.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/endpoint/functions/pci-epf-vntb.c index 599538cd554c..b069c84ec172 100644 --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c @@ -561,6 +561,8 @@ err_alloc_peer_mem: return -1; } +static void epf_ntb_mw_bar_clear(struct epf_ntb *ntb, int num_mws); + /** * epf_ntb_db_bar_clear() - Clear doorbell BAR and free memory * allocated in peer's outbound address space @@ -617,13 +619,21 @@ static int epf_ntb_mw_bar_init(struct epf_ntb *ntb) &ntb->vpci_mw_phy[i], size); if (!ntb->vpci_mw_addr[i]) { + ret = -ENOMEM; dev_err(dev, "Failed to allocate source address\n"); - goto err_alloc_mem; + goto err_set_bar; } } return ret; + +err_set_bar: + pci_epc_clear_bar(ntb->epf->epc, + ntb->epf->func_no, + ntb->epf->vfunc_no, + &ntb->epf->bar[barno]); err_alloc_mem: + epf_ntb_mw_bar_clear(ntb, i); return ret; } @@ -631,12 +641,12 @@ err_alloc_mem: * epf_ntb_mw_bar_clear() - Clear Memory window BARs * @ntb: NTB device that facilitates communication between HOST and vHOST */ -static void epf_ntb_mw_bar_clear(struct epf_ntb *ntb) +static void epf_ntb_mw_bar_clear(struct epf_ntb *ntb, int num_mws) { enum pci_barno barno; int i; - for (i = 0; i < ntb->num_mws; i++) { + for (i = 0; i < num_mws; i++) { barno = ntb->epf_ntb_bar[BAR_MW0 + i]; pci_epc_clear_bar(ntb->epf->epc, ntb->epf->func_no, @@ -764,7 +774,7 @@ static int epf_ntb_epc_init(struct epf_ntb *ntb) return 0; err_write_header: - epf_ntb_mw_bar_clear(ntb); + epf_ntb_mw_bar_clear(ntb, ntb->num_mws); err_mw_bar_init: epf_ntb_db_bar_clear(ntb); err_db_bar_init: @@ -784,7 +794,7 @@ err_config_interrupt: static void epf_ntb_epc_cleanup(struct epf_ntb *ntb) { epf_ntb_db_bar_clear(ntb); - epf_ntb_mw_bar_clear(ntb); + epf_ntb_mw_bar_clear(ntb, ntb->num_mws); } #define EPF_NTB_R(_name) \ -- cgit v1.2.3 From ae9f38adac261e4ca83559c7df21b18dd66aa986 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Mon, 4 Jul 2022 09:25:59 -0400 Subject: PCI: endpoint: pci-epf-vntb: reduce several globals to statics sparse reports drivers/pci/endpoint/functions/pci-epf-vntb.c:975:5: warning: symbol 'pci_read' was not declared. Should it be static? drivers/pci/endpoint/functions/pci-epf-vntb.c:984:5: warning: symbol 'pci_write' was not declared. Should it be static? drivers/pci/endpoint/functions/pci-epf-vntb.c:989:16: warning: symbol 'vpci_ops' was not declared. Should it be static? These functions and variables are only used in pci-epf-vntb.c, so their storage class specifiers should be static. Fixes: ff32fac00d97 ("NTB: EPF: support NTB transfer between PCI RC and EP connection") Signed-off-by: Tom Rix Acked-by: Frank Li Signed-off-by: Jon Mason --- drivers/pci/endpoint/functions/pci-epf-vntb.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/endpoint/functions/pci-epf-vntb.c index b069c84ec172..2aee789a370c 100644 --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c @@ -978,7 +978,7 @@ static u32 pci_space[] = { 0, /*Max Lat, Min Gnt, interrupt pin, interrupt line*/ }; -int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) +static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) { if (devfn == 0) { memcpy(val, ((u8 *)pci_space) + where, size); @@ -987,12 +987,12 @@ int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * return PCIBIOS_DEVICE_NOT_FOUND; } -int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) +static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) { return 0; } -struct pci_ops vpci_ops = { +static struct pci_ops vpci_ops = { .read = pci_read, .write = pci_write, }; -- cgit v1.2.3 From 3305f43cb6a8f1653c31463597d37216d03717c1 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 1 Aug 2022 13:15:25 +0300 Subject: NTB: EPF: Fix error code in epf_ntb_bind() Return an error code if pci_register_driver() fails. Don't return success. Fixes: da51fd247424 ("NTB: EPF: support NTB transfer between PCI RC and EP connection") Signed-off-by: Dan Carpenter Acked-by: Souptick Joarder (HPE) Signed-off-by: Jon Mason --- drivers/pci/endpoint/functions/pci-epf-vntb.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/endpoint/functions/pci-epf-vntb.c index 2aee789a370c..a5fa32eab39c 100644 --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c @@ -1321,7 +1321,8 @@ static int epf_ntb_bind(struct pci_epf *epf) pci_vntb_table[0].vendor = ntb->vntb_vid; pci_vntb_table[0].device = ntb->vntb_pid; - if (pci_register_driver(&vntb_pci_driver)) { + ret = pci_register_driver(&vntb_pci_driver); + if (ret) { dev_err(dev, "failure register vntb pci driver\n"); goto err_bar_alloc; } -- cgit v1.2.3 From b8c0aa9b16bb2f4d5966b87fbf1f36f3280e1f60 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 1 Aug 2022 13:17:32 +0300 Subject: NTB: EPF: Tidy up some bounds checks This sscanf() is reading from the filename which was set by the kernel so it should be trust worthy. Although the data is likely trust worthy there is some bounds checking but unfortunately, it is not complete or consistent. Additionally, the Smatch static checker marks everything that comes from sscanf() as tainted and so Smatch complains that this code can lead to an out of bounds issue. Let's clean things up and make Smatch happy. The first problem is that there is no bounds checking in the _show() functions. The _store() and _show() functions are very similar so make the bounds checking the same in both. The second issue is that if "win_no" is zero it leads to an array underflow so add an if (win_no <= 0) check for that. Signed-off-by: Dan Carpenter Acked-by: Souptick Joarder (HPE) Signed-off-by: Jon Mason --- drivers/pci/endpoint/functions/pci-epf-vntb.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/endpoint/functions/pci-epf-vntb.c index a5fa32eab39c..0ea85e1d292e 100644 --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c @@ -831,9 +831,16 @@ static ssize_t epf_ntb_##_name##_show(struct config_item *item, \ { \ struct config_group *group = to_config_group(item); \ struct epf_ntb *ntb = to_epf_ntb(group); \ + struct device *dev = &ntb->epf->dev; \ int win_no; \ \ - sscanf(#_name, "mw%d", &win_no); \ + if (sscanf(#_name, "mw%d", &win_no) != 1) \ + return -EINVAL; \ + \ + if (win_no <= 0 || win_no > ntb->num_mws) { \ + dev_err(dev, "Invalid num_nws: %d value\n", ntb->num_mws); \ + return -EINVAL; \ + } \ \ return sprintf(page, "%lld\n", ntb->mws_size[win_no - 1]); \ } @@ -856,7 +863,7 @@ static ssize_t epf_ntb_##_name##_store(struct config_item *item, \ if (sscanf(#_name, "mw%d", &win_no) != 1) \ return -EINVAL; \ \ - if (ntb->num_mws < win_no) { \ + if (win_no <= 0 || win_no > ntb->num_mws) { \ dev_err(dev, "Invalid num_nws: %d value\n", ntb->num_mws); \ return -EINVAL; \ } \ -- cgit v1.2.3 From b33b6fdca3f0380c101e2adae5644777d6530fe5 Mon Sep 17 00:00:00 2001 From: Mike Snitzer Date: Fri, 5 Aug 2022 22:58:33 -0400 Subject: dm bufio: simplify DM_BUFIO_CLIENT_NO_SLEEP locking Historically none of the bufio code runs in interrupt context but with the use of DM_BUFIO_CLIENT_NO_SLEEP a bufio client can, see: commit 5721d4e5a9cd ("dm verity: Add optional "try_verify_in_tasklet" feature") That said, the new tasklet usecase still doesn't require interrupts be disabled by bufio (let alone conditionally restore them). Yet with PREEMPT_RT, and falling back from tasklet to workqueue, care must be taken to properly synchronize between softirq and process context, otherwise ABBA deadlock may occur. While it is unnecessary to disable bottom-half preemption within a tasklet, we must consistently do so in process context to ensure locking is in the proper order. Fix these issues by switching from spin_lock_irq{save,restore} to using spin_{lock,unlock}_bh instead. Also remove the 'spinlock_flags' member in dm_bufio_client struct (that can be used unsafely if bufio must recurse on behalf of some caller, e.g. block layer's submit_bio). Fixes: 5721d4e5a9cd ("dm verity: Add optional "try_verify_in_tasklet" feature") Reported-by: Jens Axboe Signed-off-by: Mike Snitzer --- drivers/md/dm-bufio.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/md/dm-bufio.c b/drivers/md/dm-bufio.c index 0a38a7aef49c..bef8c6eb5bdb 100644 --- a/drivers/md/dm-bufio.c +++ b/drivers/md/dm-bufio.c @@ -83,7 +83,7 @@ struct dm_bufio_client { struct mutex lock; spinlock_t spinlock; - unsigned long spinlock_flags; + bool no_sleep; struct list_head lru[LIST_SIZE]; unsigned long n_buffers[LIST_SIZE]; @@ -93,8 +93,6 @@ struct dm_bufio_client { s8 sectors_per_block_bits; void (*alloc_callback)(struct dm_buffer *); void (*write_callback)(struct dm_buffer *); - bool no_sleep; - struct kmem_cache *slab_buffer; struct kmem_cache *slab_cache; struct dm_io_client *dm_io; @@ -174,7 +172,7 @@ static DEFINE_STATIC_KEY_FALSE(no_sleep_enabled); static void dm_bufio_lock(struct dm_bufio_client *c) { if (static_branch_unlikely(&no_sleep_enabled) && c->no_sleep) - spin_lock_irqsave_nested(&c->spinlock, c->spinlock_flags, dm_bufio_in_request()); + spin_lock_bh(&c->spinlock); else mutex_lock_nested(&c->lock, dm_bufio_in_request()); } @@ -182,7 +180,7 @@ static void dm_bufio_lock(struct dm_bufio_client *c) static int dm_bufio_trylock(struct dm_bufio_client *c) { if (static_branch_unlikely(&no_sleep_enabled) && c->no_sleep) - return spin_trylock_irqsave(&c->spinlock, c->spinlock_flags); + return spin_trylock_bh(&c->spinlock); else return mutex_trylock(&c->lock); } @@ -190,7 +188,7 @@ static int dm_bufio_trylock(struct dm_bufio_client *c) static void dm_bufio_unlock(struct dm_bufio_client *c) { if (static_branch_unlikely(&no_sleep_enabled) && c->no_sleep) - spin_unlock_irqrestore(&c->spinlock, c->spinlock_flags); + spin_unlock_bh(&c->spinlock); else mutex_unlock(&c->lock); } -- cgit v1.2.3 From 8c22816dbc8733ea761c3b74ec62d9463e242c56 Mon Sep 17 00:00:00 2001 From: Mike Snitzer Date: Tue, 9 Aug 2022 17:33:12 -0400 Subject: dm verity: fix DM_VERITY_OPTS_MAX value yet again Must account for the possibility that "try_verify_in_tasklet" is used. This is the same issue that was fixed with commit 160f99db94322 -- it is far too easy to miss that additional a new argument(s) require bumping DM_VERITY_OPTS_MAX accordingly. Fixes: 5721d4e5a9cd ("dm verity: Add optional "try_verify_in_tasklet" feature") Signed-off-by: Mike Snitzer --- drivers/md/dm-verity-target.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/md/dm-verity-target.c b/drivers/md/dm-verity-target.c index 981821f18a18..5b9062e5167b 100644 --- a/drivers/md/dm-verity-target.c +++ b/drivers/md/dm-verity-target.c @@ -37,7 +37,7 @@ #define DM_VERITY_OPT_AT_MOST_ONCE "check_at_most_once" #define DM_VERITY_OPT_TASKLET_VERIFY "try_verify_in_tasklet" -#define DM_VERITY_OPTS_MAX (3 + DM_VERITY_OPTS_FEC + \ +#define DM_VERITY_OPTS_MAX (4 + DM_VERITY_OPTS_FEC + \ DM_VERITY_ROOT_HASH_VERIFICATION_OPTS) static unsigned dm_verity_prefetch_cluster = DM_VERITY_DEFAULT_PREFETCH_SIZE; -- cgit v1.2.3 From f876df9f12cda68e68995b33b36491d78fd3ecce Mon Sep 17 00:00:00 2001 From: Mike Snitzer Date: Tue, 9 Aug 2022 18:07:28 -0400 Subject: dm verity: fix verity_parse_opt_args parsing Commit df326e7a0699 ("dm verity: allow optional args to alter primary args handling") introduced a bug where verity_parse_opt_args() wouldn't properly shift past an optional argument's additional params (by ignoring them). Fix this by avoiding returning with error if an unknown argument is encountered when @only_modifier_opts=true is passed to verity_parse_opt_args(). In practice this regressed the cryptsetup testsuite's FEC testing because unknown optional arguments were encountered, wherey short-circuiting ever testing FEC mode. With this fix all of the cryptsetup testsuite's verity FEC tests pass. Fixes: df326e7a0699 ("dm verity: allow optional args to alter primary args handling") Reported-by: Milan Broz > Signed-off-by: Mike Snitzer --- drivers/md/dm-verity-target.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/md/dm-verity-target.c b/drivers/md/dm-verity-target.c index 5b9062e5167b..0d70c9c60d46 100644 --- a/drivers/md/dm-verity-target.c +++ b/drivers/md/dm-verity-target.c @@ -1052,7 +1052,7 @@ static int verity_parse_opt_args(struct dm_arg_set *as, struct dm_verity *v, struct dm_verity_sig_opts *verify_args, bool only_modifier_opts) { - int r; + int r = 0; unsigned argc; struct dm_target *ti = v->ti; const char *arg_name; @@ -1122,8 +1122,18 @@ static int verity_parse_opt_args(struct dm_arg_set *as, struct dm_verity *v, if (r) return r; continue; + + } else if (only_modifier_opts) { + /* + * Ignore unrecognized opt, could easily be an extra + * argument to an option whose parsing was skipped. + * Normal parsing (@only_modifier_opts=false) will + * properly parse all options (and their extra args). + */ + continue; } + DMERR("Unrecognized verity feature request: %s", arg_name); ti->error = "Unrecognized verity feature request"; return -EINVAL; } while (argc && !r); -- cgit v1.2.3 From b7f362d6413ebd0167ac5a9f09ad5dca5490ac1a Mon Sep 17 00:00:00 2001 From: Mikulas Patocka Date: Mon, 8 Aug 2022 10:50:10 -0400 Subject: dm writecache: fix smatch warning about invalid return from writecache_map There's a smatch warning "inconsistent returns '&wc->lock'" in dm-writecache. The reason for the warning is that writecache_map() doesn't drop the lock on the impossible path. Fix this warning by adding wc_unlock() after the BUG statement (so that it will be compiled-away anyway). Fixes: df699cc16ea5e ("dm writecache: report invalid return from writecache_map helpers") Reported-by: kernel test robot Reported-by: Dan Carpenter Signed-off-by: Mikulas Patocka Signed-off-by: Mike Snitzer --- drivers/md/dm-writecache.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/md/dm-writecache.c b/drivers/md/dm-writecache.c index ead008ea38f2..03fe2c5d5e32 100644 --- a/drivers/md/dm-writecache.c +++ b/drivers/md/dm-writecache.c @@ -1598,7 +1598,8 @@ done: default: BUG(); - return -1; + wc_unlock(wc); + return DM_MAPIO_KILL; } } -- cgit v1.2.3 From 3f5117be95843950f31862be05e947b77a3cd77c Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sun, 26 Jun 2022 21:16:30 +0200 Subject: dt-bindings: mfd: convert to yaml Qualcomm SPMI PMIC Convert Qualcomm SPMI PMIC binding to yaml format. Additional changes: - filled many missing compatibles Co-developed-by: Caleb Connolly Signed-off-by: David Heidelberg Reviewed-by: Rob Herring Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20220626191630.176835-1-david@ixit.cz --- .../devicetree/bindings/mfd/qcom,spmi-pmic.txt | 94 ---------- .../devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 190 +++++++++++++++++++++ 2 files changed, 190 insertions(+), 94 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt create mode 100644 Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt deleted file mode 100644 index eb78e3ae7703..000000000000 --- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt +++ /dev/null @@ -1,94 +0,0 @@ - Qualcomm SPMI PMICs multi-function device bindings - -The Qualcomm SPMI series presently includes PM8941, PM8841 and PMA8084 -PMICs. These PMICs use a QPNP scheme through SPMI interface. -QPNP is effectively a partitioning scheme for dividing the SPMI extended -register space up into logical pieces, and set of fixed register -locations/definitions within these regions, with some of these regions -specifically used for interrupt handling. - -The QPNP PMICs are used with the Qualcomm Snapdragon series SoCs, and are -interfaced to the chip via the SPMI (System Power Management Interface) bus. -Support for multiple independent functions are implemented by splitting the -16-bit SPMI slave address space into 256 smaller fixed-size regions, 256 bytes -each. A function can consume one or more of these fixed-size register regions. - -Required properties: -- compatible: Should contain one of: - "qcom,pm660", - "qcom,pm660l", - "qcom,pm7325", - "qcom,pm8004", - "qcom,pm8005", - "qcom,pm8019", - "qcom,pm8028", - "qcom,pm8110", - "qcom,pm8150", - "qcom,pm8150b", - "qcom,pm8150c", - "qcom,pm8150l", - "qcom,pm8226", - "qcom,pm8350c", - "qcom,pm8841", - "qcom,pm8901", - "qcom,pm8909", - "qcom,pm8916", - "qcom,pm8941", - "qcom,pm8950", - "qcom,pm8953", - "qcom,pm8994", - "qcom,pm8998", - "qcom,pma8084", - "qcom,pmd9635", - "qcom,pmi8950", - "qcom,pmi8962", - "qcom,pmi8994", - "qcom,pmi8998", - "qcom,pmk8002", - "qcom,pmk8350", - "qcom,pmr735a", - "qcom,smb2351", - or generalized "qcom,spmi-pmic". -- reg: Specifies the SPMI USID slave address for this device. - For more information see: - Documentation/devicetree/bindings/spmi/spmi.yaml - -Required properties for peripheral child nodes: -- compatible: Should contain "qcom,xxx", where "xxx" is a peripheral name. - -Optional properties for peripheral child nodes: -- interrupts: Interrupts are specified as a 4-tuple. For more information - see: - Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml -- interrupt-names: Corresponding interrupt name to the interrupts property - -Each child node of SPMI slave id represents a function of the PMIC. In the -example below the rtc device node represents a peripheral of pm8941 -SID = 0. The regulator device node represents a peripheral of pm8941 SID = 1. - -Example: - - spmi { - compatible = "qcom,spmi-pmic-arb"; - - pm8941@0 { - compatible = "qcom,pm8941", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - - rtc { - compatible = "qcom,rtc"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "alarm"; - }; - }; - - pm8941@1 { - compatible = "qcom,pm8941", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - - regulator { - compatible = "qcom,regulator"; - regulator-name = "8941_boost"; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml new file mode 100644 index 000000000000..65cbc6dee545 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml @@ -0,0 +1,190 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SPMI PMICs multi-function device + +description: | + Some Qualcomm PMICs used with the Snapdragon series SoCs are interfaced + to the chip via the SPMI (System Power Management Interface) bus. + Support for multiple independent functions are implemented by splitting the + 16-bit SPMI peripheral address space into 256 smaller fixed-size regions, 256 bytes + each. A function can consume one or more of these fixed-size register regions. + + The Qualcomm SPMI series includes the PM8941, PM8841, PMA8084, PM8998 and other + PMICs. These PMICs use a "QPNP" scheme through SPMI interface. + QPNP is effectively a partitioning scheme for dividing the SPMI extended + register space up into logical pieces, and set of fixed register + locations/definitions within these regions, with some of these regions + specifically used for interrupt handling. + +maintainers: + - Stephen Boyd + +properties: + $nodename: + oneOf: + - pattern: '^pmic@.*$' + - pattern: '^pm(a|s)?[0-9]*@.*$' + deprecated: true + + compatible: + items: + - enum: + - qcom,pm660 + - qcom,pm660l + - qcom,pm6150 + - qcom,pm6150l + - qcom,pm6350 + - qcom,pm7325 + - qcom,pm8004 + - qcom,pm8005 + - qcom,pm8009 + - qcom,pm8019 + - qcom,pm8110 + - qcom,pm8150 + - qcom,pm8150b + - qcom,pm8150l + - qcom,pm8226 + - qcom,pm8350 + - qcom,pm8350b + - qcom,pm8350c + - qcom,pm8841 + - qcom,pm8909 + - qcom,pm8916 + - qcom,pm8941 + - qcom,pm8950 + - qcom,pm8994 + - qcom,pm8998 + - qcom,pma8084 + - qcom,pmd9635 + - qcom,pmi8950 + - qcom,pmi8962 + - qcom,pmi8994 + - qcom,pmi8998 + - qcom,pmk8350 + - qcom,pmm8155au + - qcom,pmr735a + - qcom,pmr735b + - qcom,pms405 + - qcom,pmx55 + - qcom,pmx65 + - qcom,smb2351 + - const: qcom,spmi-pmic + + reg: + minItems: 1 + maxItems: 2 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + labibb: + type: object + $ref: /schemas/regulator/qcom-labibb-regulator.yaml# + + regulators: + type: object + $ref: /schemas/regulator/regulator.yaml# + +patternProperties: + "^adc@[0-9a-f]+$": + type: object + $ref: /schemas/iio/adc/qcom,spmi-vadc.yaml# + + "^adc-tm@[0-9a-f]+$": + type: object + $ref: /schemas/thermal/qcom-spmi-adc-tm5.yaml# + + "^audio-codec@[0-9a-f]+$": + type: object + additionalProperties: true # FIXME qcom,pm8916-wcd-analog-codec binding not converted yet + + "extcon@[0-9a-f]+$": + type: object + $ref: /schemas/extcon/qcom,pm8941-misc.yaml# + + "gpio(s)?@[0-9a-f]+$": + type: object + $ref: /schemas/pinctrl/qcom,pmic-gpio.yaml# + + "pon@[0-9a-f]+$": + type: object + $ref: /schemas/power/reset/qcom,pon.yaml# + + "pwm@[0-9a-f]+$": + type: object + $ref: /schemas/leds/leds-qcom-lpg.yaml# + + "^rtc@[0-9a-f]+$": + type: object + $ref: /schemas/rtc/qcom-pm8xxx-rtc.yaml# + + "^temp-alarm@[0-9a-f]+$": + type: object + $ref: /schemas/thermal/qcom,spmi-temp-alarm.yaml# + + "^vibrator@[0-9a-f]+$": + type: object + additionalProperties: true # FIXME qcom,pm8916-vib binding not converted yet + + "^mpps@[0-9a-f]+$": + type: object + $ref: /schemas/pinctrl/qcom,pmic-mpp.yaml# + + "(.*)?(wled|leds)@[0-9a-f]+$": + type: object + $ref: /schemas/leds/backlight/qcom-wled.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + #include + #include + + spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0c440000 0x1100>, + <0x0c600000 0x2000000>, + <0x0e600000 0x100000>, + <0x0e700000 0xa0000>, + <0x0c40a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + pmi8998_lsid0: pmic@2 { + compatible = "qcom,pmi8998", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmi8998_gpio: gpios@c000 { + compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pmi8998_gpio 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + }; -- cgit v1.2.3 From 18db466a9a306406dab3b134014d9f6ed642471c Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Tue, 2 Aug 2022 11:02:36 +0200 Subject: powerpc: Fix eh field when calling lwarx on PPC32 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 9401f4e46cf6 ("powerpc: Use lwarx/ldarx directly instead of PPC_LWARX/LDARX macros") properly handled the eh field of lwarx in asm/bitops.h but failed to clear it for PPC32 in asm/simple_spinlock.h So, do as in arch_atomic_try_cmpxchg_lock(), set it to 1 if PPC64 but set it to 0 if PPC32. For that use IS_ENABLED(CONFIG_PPC64) which returns 1 when CONFIG_PPC64 is set and 0 otherwise. Fixes: 9401f4e46cf6 ("powerpc: Use lwarx/ldarx directly instead of PPC_LWARX/LDARX macros") Cc: stable@vger.kernel.org # v5.15+ Reported-by: Pali Rohár Signed-off-by: Christophe Leroy Tested-by: Pali Rohár Reviewed-by: Segher Boessenkool [mpe: Use symbolic names, use 'n' constraint per Segher] Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/a1176e19e627dd6a1b8d24c6c457a8ab874b7d12.1659430931.git.christophe.leroy@csgroup.eu --- arch/powerpc/include/asm/simple_spinlock.h | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/include/asm/simple_spinlock.h b/arch/powerpc/include/asm/simple_spinlock.h index 7ae6aeef8464..9dcc7e9993b9 100644 --- a/arch/powerpc/include/asm/simple_spinlock.h +++ b/arch/powerpc/include/asm/simple_spinlock.h @@ -48,10 +48,11 @@ static inline int arch_spin_is_locked(arch_spinlock_t *lock) static inline unsigned long __arch_spin_trylock(arch_spinlock_t *lock) { unsigned long tmp, token; + unsigned int eh = IS_ENABLED(CONFIG_PPC64); token = LOCK_TOKEN; __asm__ __volatile__( -"1: lwarx %0,0,%2,1\n\ +"1: lwarx %0,0,%2,%[eh]\n\ cmpwi 0,%0,0\n\ bne- 2f\n\ stwcx. %1,0,%2\n\ @@ -59,7 +60,7 @@ static inline unsigned long __arch_spin_trylock(arch_spinlock_t *lock) PPC_ACQUIRE_BARRIER "2:" : "=&r" (tmp) - : "r" (token), "r" (&lock->slock) + : "r" (token), "r" (&lock->slock), [eh] "n" (eh) : "cr0", "memory"); return tmp; @@ -156,9 +157,10 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock) static inline long __arch_read_trylock(arch_rwlock_t *rw) { long tmp; + unsigned int eh = IS_ENABLED(CONFIG_PPC64); __asm__ __volatile__( -"1: lwarx %0,0,%1,1\n" +"1: lwarx %0,0,%1,%[eh]\n" __DO_SIGN_EXTEND " addic. %0,%0,1\n\ ble- 2f\n" @@ -166,7 +168,7 @@ static inline long __arch_read_trylock(arch_rwlock_t *rw) bne- 1b\n" PPC_ACQUIRE_BARRIER "2:" : "=&r" (tmp) - : "r" (&rw->lock) + : "r" (&rw->lock), [eh] "n" (eh) : "cr0", "xer", "memory"); return tmp; @@ -179,17 +181,18 @@ static inline long __arch_read_trylock(arch_rwlock_t *rw) static inline long __arch_write_trylock(arch_rwlock_t *rw) { long tmp, token; + unsigned int eh = IS_ENABLED(CONFIG_PPC64); token = WRLOCK_TOKEN; __asm__ __volatile__( -"1: lwarx %0,0,%2,1\n\ +"1: lwarx %0,0,%2,%[eh]\n\ cmpwi 0,%0,0\n\ bne- 2f\n" " stwcx. %1,0,%2\n\ bne- 1b\n" PPC_ACQUIRE_BARRIER "2:" : "=&r" (tmp) - : "r" (token), "r" (&rw->lock) + : "r" (token), "r" (&rw->lock), [eh] "n" (eh) : "cr0", "memory"); return tmp; -- cgit v1.2.3 From eb5a33ea31190c189ca4a59de4687b0877662c06 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Tue, 2 Aug 2022 11:02:37 +0200 Subject: powerpc: Don't hide eh field of lwarx behind a macro The eh field must remain 0 for PPC32 and is only used by PPC64. Don't hide that behind a macro, just leave the responsibility to the user. At the time being, the only users of PPC_RAW_L{WDQ}ARX are setting the eh field to 0, so the special handling of __PPC_EH is useless. Just take the value given by the caller. Same for DEFINE_TESTOP(), don't do special handling in that macro, ensure the caller hands over the proper eh value. Signed-off-by: Christophe Leroy [mpe: Use 'n' constraint per Segher] Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/8b9c8a1a14f9143552a85fcbf96698224a8c2469.1659430931.git.christophe.leroy@csgroup.eu --- arch/powerpc/include/asm/bitops.h | 4 ++-- arch/powerpc/include/asm/ppc-opcode.h | 11 +---------- 2 files changed, 3 insertions(+), 12 deletions(-) diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h index 344fba3b16eb..7e0f0322912b 100644 --- a/arch/powerpc/include/asm/bitops.h +++ b/arch/powerpc/include/asm/bitops.h @@ -163,7 +163,7 @@ static inline unsigned long fn( \ "bne- 1b\n" \ postfix \ : "=&r" (old), "=&r" (t) \ - : "rK" (mask), "r" (p), "i" (IS_ENABLED(CONFIG_PPC64) ? eh : 0) \ + : "rK" (mask), "r" (p), "n" (eh) \ : "cc", "memory"); \ return (old & mask); \ } @@ -171,7 +171,7 @@ static inline unsigned long fn( \ DEFINE_TESTOP(test_and_set_bits, or, PPC_ATOMIC_ENTRY_BARRIER, PPC_ATOMIC_EXIT_BARRIER, 0) DEFINE_TESTOP(test_and_set_bits_lock, or, "", - PPC_ACQUIRE_BARRIER, 1) + PPC_ACQUIRE_BARRIER, IS_ENABLED(CONFIG_PPC64)) DEFINE_TESTOP(test_and_change_bits, xor, PPC_ATOMIC_ENTRY_BARRIER, PPC_ATOMIC_EXIT_BARRIER, 0) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 7b81b37a191e..d9703c5fd713 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -343,6 +343,7 @@ #define __PPC_SPR(r) ((((r) & 0x1f) << 16) | ((((r) >> 5) & 0x1f) << 11)) #define __PPC_RC21 (0x1 << 10) #define __PPC_PRFX_R(r) (((r) & 0x1) << 20) +#define __PPC_EH(eh) (((eh) & 0x1) << 0) /* * Both low and high 16 bits are added as SIGNED additions, so if low 16 bits @@ -359,16 +360,6 @@ #define PPC_LI_MASK 0x03fffffc #define PPC_LI(v) ((v) & PPC_LI_MASK) -/* - * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a - * larx with EH set as an illegal instruction. - */ -#ifdef CONFIG_PPC64 -#define __PPC_EH(eh) (((eh) & 0x1) << 0) -#else -#define __PPC_EH(eh) 0 -#endif - /* Base instruction encoding */ #define PPC_RAW_CP_ABORT (0x7c00068c) #define PPC_RAW_COPY(a, b) (PPC_INST_COPY | ___PPC_RA(a) | ___PPC_RB(b)) -- cgit v1.2.3 From 5cccf7a5215d12027e55e247907817631b413c28 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Tue, 2 Aug 2022 11:02:38 +0200 Subject: powerpc: Make eh value more explicit when using lwarx Just like the first patch of this series, define a local 'eh' in order to make the code clearer. And IS_ENABLED() returns either 1 or 0 so no need to do IS_ENABLED(CONFIG_PPC64) ? 1 : 0. Signed-off-by: Christophe Leroy [mpe: Use symbolic names, use 'n' constraint per Segher] Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/629befaa2d05e2922346e58a383886510d6af55a.1659430931.git.christophe.leroy@csgroup.eu --- arch/powerpc/include/asm/atomic.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h index 853dc86864f4..486ab7889121 100644 --- a/arch/powerpc/include/asm/atomic.h +++ b/arch/powerpc/include/asm/atomic.h @@ -140,9 +140,10 @@ static __always_inline bool arch_atomic_try_cmpxchg_lock(atomic_t *v, int *old, int new) { int r, o = *old; + unsigned int eh = IS_ENABLED(CONFIG_PPC64); __asm__ __volatile__ ( -"1: lwarx %0,0,%2,%5 # atomic_try_cmpxchg_acquire \n" +"1: lwarx %0,0,%2,%[eh] # atomic_try_cmpxchg_acquire \n" " cmpw 0,%0,%3 \n" " bne- 2f \n" " stwcx. %4,0,%2 \n" @@ -150,7 +151,7 @@ arch_atomic_try_cmpxchg_lock(atomic_t *v, int *old, int new) "\t" PPC_ACQUIRE_BARRIER " \n" "2: \n" : "=&r" (r), "+m" (v->counter) - : "r" (&v->counter), "r" (o), "r" (new), "i" (IS_ENABLED(CONFIG_PPC64) ? 1 : 0) + : "r" (&v->counter), "r" (o), "r" (new), [eh] "n" (eh) : "cr0", "memory"); if (unlikely(r != o)) -- cgit v1.2.3 From cb928ac192128c842f4c1cfc8b6780b95719d65f Mon Sep 17 00:00:00 2001 From: "Naveen N. Rao" Date: Tue, 9 Aug 2022 15:29:07 +0530 Subject: powerpc64/ftrace: Fix ftrace for clang builds Clang doesn't support -mprofile-kernel ABI, so guard the checks against CONFIG_DYNAMIC_FTRACE_WITH_REGS, rather than the elf ABI version. Fixes: 23b44fc248f4 ("powerpc/ftrace: Make __ftrace_make_{nop/call}() common to PPC32 and PPC64") Cc: stable@vger.kernel.org # v5.19+ Reported-by: Nick Desaulniers Reported-by: Ondrej Mosnacek Signed-off-by: Naveen N. Rao Tested-by: Ondrej Mosnacek Acked-by: Nick Desaulniers Signed-off-by: Michael Ellerman Link: https://github.com/llvm/llvm-project/issues/57031 Link: https://github.com/ClangBuiltLinux/linux/issues/1682 Link: https://lore.kernel.org/r/20220809095907.418764-1-naveen.n.rao@linux.vnet.ibm.com --- arch/powerpc/kernel/trace/ftrace.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/kernel/trace/ftrace.c b/arch/powerpc/kernel/trace/ftrace.c index cb158c32b50b..7b85c3b460a3 100644 --- a/arch/powerpc/kernel/trace/ftrace.c +++ b/arch/powerpc/kernel/trace/ftrace.c @@ -393,11 +393,11 @@ int ftrace_make_nop(struct module *mod, */ static bool expected_nop_sequence(void *ip, ppc_inst_t op0, ppc_inst_t op1) { - if (IS_ENABLED(CONFIG_PPC64_ELF_ABI_V1)) + if (IS_ENABLED(CONFIG_DYNAMIC_FTRACE_WITH_REGS)) + return ppc_inst_equal(op0, ppc_inst(PPC_RAW_NOP())); + else return ppc_inst_equal(op0, ppc_inst(PPC_RAW_BRANCH(8))) && ppc_inst_equal(op1, ppc_inst(PPC_INST_LD_TOC)); - else - return ppc_inst_equal(op0, ppc_inst(PPC_RAW_NOP())); } static int @@ -412,7 +412,7 @@ __ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) if (copy_inst_from_kernel_nofault(op, ip)) return -EFAULT; - if (IS_ENABLED(CONFIG_PPC64_ELF_ABI_V1) && + if (!IS_ENABLED(CONFIG_DYNAMIC_FTRACE_WITH_REGS) && copy_inst_from_kernel_nofault(op + 1, ip + 4)) return -EFAULT; -- cgit v1.2.3 From 59bab33a4f57f886c5f8a4d1f2bed728ec185d16 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Wed, 3 Aug 2022 13:47:33 +0200 Subject: powerpc/ppc-opcode: Fix PPC_RAW_TW() PPC_RAW_TW() is erroneously defined with base code 0x7f000008 instead of 0x7c000008. That's invisible because its only user is PPC_RAW_TRAP() which is 0x7fe00008, but fix it anyway to avoid any risk of future bug. Fixes: d00d762daf12 ("powerpc/ppc-opcode: Define and use PPC_RAW_TRAP() and PPC_RAW_TW()") Reported-by: Naveen N. Rao Signed-off-by: Christophe Leroy Reviewed-by: Naveen N. Rao Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/eca9251f1e1f82c4c46ec6380ddb28356ab3fdfe.1659527244.git.christophe.leroy@csgroup.eu --- arch/powerpc/include/asm/ppc-opcode.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index d9703c5fd713..c6d724104ed1 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -571,7 +571,7 @@ #define PPC_RAW_BRANCH(offset) (0x48000000 | PPC_LI(offset)) #define PPC_RAW_BL(offset) (0x48000001 | PPC_LI(offset)) -#define PPC_RAW_TW(t0, a, b) (0x7f000008 | ___PPC_RS(t0) | ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_TW(t0, a, b) (0x7c000008 | ___PPC_RS(t0) | ___PPC_RA(a) | ___PPC_RB(b)) #define PPC_RAW_TRAP() PPC_RAW_TW(31, 0, 0) #define PPC_RAW_SETB(t, bfa) (0x7c000100 | ___PPC_RT(t) | ___PPC_RA((bfa) << 2)) -- cgit v1.2.3 From 83ee9f23763a432a4077bf20624ee35de87bce99 Mon Sep 17 00:00:00 2001 From: Russell Currey Date: Wed, 10 Aug 2022 15:43:31 +1000 Subject: powerpc/kexec: Fix build failure from uninitialised variable clang 14 won't build because ret is uninitialised and can be returned if both prop and fdtprop are NULL. Drop the ret variable and return an error in that failure case. Fixes: b1fc44eaa9ba ("pseries/iommu/ddw: Fix kdump to work in absence of ibm,dma-window") Suggested-by: Christophe Leroy Signed-off-by: Russell Currey Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220810054331.373761-1-ruscur@russell.cc --- arch/powerpc/kexec/file_load_64.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/kexec/file_load_64.c b/arch/powerpc/kexec/file_load_64.c index 683462e4556b..349a781cea0b 100644 --- a/arch/powerpc/kexec/file_load_64.c +++ b/arch/powerpc/kexec/file_load_64.c @@ -1043,17 +1043,17 @@ static int copy_property(void *fdt, int node_offset, const struct device_node *d const char *propname) { const void *prop, *fdtprop; - int len = 0, fdtlen = 0, ret; + int len = 0, fdtlen = 0; prop = of_get_property(dn, propname, &len); fdtprop = fdt_getprop(fdt, node_offset, propname, &fdtlen); if (fdtprop && !prop) - ret = fdt_delprop(fdt, node_offset, propname); + return fdt_delprop(fdt, node_offset, propname); else if (prop) - ret = fdt_setprop(fdt, node_offset, propname, prop, len); - - return ret; + return fdt_setprop(fdt, node_offset, propname, prop, len); + else + return -FDT_ERR_NOTFOUND; } static int update_pci_dma_nodes(void *fdt, const char *dmapropname) -- cgit v1.2.3 From 6b2394bad503bfada6f677ad2574b2ef8178b1bf Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Tue, 9 Aug 2022 19:15:44 +0100 Subject: ALSA: usb-audio: make read-only array marker static const Don't populate the read-only array marker on the stack but instead make it static const. Also makes the object code a little smaller. Signed-off-by: Colin Ian King Link: https://lore.kernel.org/r/20220809181544.3046429-1-colin.i.king@gmail.com Signed-off-by: Takashi Iwai --- sound/usb/pcm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/usb/pcm.c b/sound/usb/pcm.c index e692ae04436a..d45d1d7e6664 100644 --- a/sound/usb/pcm.c +++ b/sound/usb/pcm.c @@ -1269,7 +1269,7 @@ static inline void fill_playback_urb_dsd_dop(struct snd_usb_substream *subs, unsigned int wrap = subs->buffer_bytes; u8 *dst = urb->transfer_buffer; u8 *src = runtime->dma_area; - u8 marker[] = { 0x05, 0xfa }; + static const u8 marker[] = { 0x05, 0xfa }; unsigned int queued = 0; /* -- cgit v1.2.3 From df936cadfb58ba93601ac351ab6fc2e2650cf591 Mon Sep 17 00:00:00 2001 From: Claire Jensen Date: Fri, 5 Aug 2022 13:01:04 -0700 Subject: perf stat: Add JSON output option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CSV output is tricky to format and column layout changes are susceptible to breaking parsers. New JSON-formatted output has variable names to identify fields that are consistent and informative, making the output parseable. CSV output example: 1.20,msec,task-clock:u,1204272,100.00,0.697,CPUs utilized 0,,context-switches:u,1204272,100.00,0.000,/sec 0,,cpu-migrations:u,1204272,100.00,0.000,/sec 70,,page-faults:u,1204272,100.00,58.126,K/sec JSON output example: {"counter-value" : "3805.723968", "unit" : "msec", "event" : "cpu-clock", "event-runtime" : 3805731510100.00, "pcnt-running" : 100.00, "metric-value" : 4.007571, "metric-unit" : "CPUs utilized"} {"counter-value" : "6166.000000", "unit" : "", "event" : "context-switches", "event-runtime" : 3805723045100.00, "pcnt-running" : 100.00, "metric-value" : 1.620191, "metric-unit" : "K/sec"} {"counter-value" : "466.000000", "unit" : "", "event" : "cpu-migrations", "event-runtime" : 3805727613100.00, "pcnt-running" : 100.00, "metric-value" : 122.447136, "metric-unit" : "/sec"} {"counter-value" : "208.000000", "unit" : "", "event" : "page-faults", "event-runtime" : 3805726799100.00, "pcnt-running" : 100.00, "metric-value" : 54.654516, "metric-unit" : "/sec"} Also added documentation for JSON option. There is some tidy up of CSV code including a potential memory over run in the os.nfields set up. To facilitate this an AGGR_MAX value is added. Committer notes: Fixed up using PRIu64 to format u64 values, not %lu. Committer testing: ⬢[acme@toolbox perf]$ perf stat -j sleep 1 {"counter-value" : "0.731750", "unit" : "msec", "event" : "task-clock:u", "event-runtime" : 731750, "pcnt-running" : 100.00, "metric-value" : 0.000731, "metric-unit" : "CPUs utilized"} {"counter-value" : "0.000000", "unit" : "", "event" : "context-switches:u", "event-runtime" : 731750, "pcnt-running" : 100.00, "metric-value" : 0.000000, "metric-unit" : "/sec"} {"counter-value" : "0.000000", "unit" : "", "event" : "cpu-migrations:u", "event-runtime" : 731750, "pcnt-running" : 100.00, "metric-value" : 0.000000, "metric-unit" : "/sec"} {"counter-value" : "75.000000", "unit" : "", "event" : "page-faults:u", "event-runtime" : 731750, "pcnt-running" : 100.00, "metric-value" : 102.494021, "metric-unit" : "K/sec"} {"counter-value" : "578765.000000", "unit" : "", "event" : "cycles:u", "event-runtime" : 379366, "pcnt-running" : 49.00, "metric-value" : 0.790933, "metric-unit" : "GHz"} {"counter-value" : "1298.000000", "unit" : "", "event" : "stalled-cycles-frontend:u", "event-runtime" : 768020, "pcnt-running" : 100.00, "metric-value" : 0.224271, "metric-unit" : "frontend cycles idle"} {"counter-value" : "21984.000000", "unit" : "", "event" : "stalled-cycles-backend:u", "event-runtime" : 768020, "pcnt-running" : 100.00, "metric-value" : 3.798433, "metric-unit" : "backend cycles idle"} {"counter-value" : "468197.000000", "unit" : "", "event" : "instructions:u", "event-runtime" : 768020, "pcnt-running" : 100.00, "metric-value" : 0.808959, "metric-unit" : "insn per cycle"} {"metric-value" : 0.046955, "metric-unit" : "stalled cycles per insn"} {"counter-value" : "103335.000000", "unit" : "", "event" : "branches:u", "event-runtime" : 768020, "pcnt-running" : 100.00, "metric-value" : 141.216262, "metric-unit" : "M/sec"} {"counter-value" : "2381.000000", "unit" : "", "event" : "branch-misses:u", "event-runtime" : 388654, "pcnt-running" : 50.00, "metric-value" : 2.304156, "metric-unit" : "of all branches"} ⬢[acme@toolbox perf]$ Signed-off-by: Claire Jensen Acked-by: Namhyung Kim Tested-by: Arnaldo Carvalho de Melo Cc: Alexander Shishkin Cc: Alyssa Ross Cc: Claire Jensen Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: Kan Liang Cc: Like Xu Cc: Mark Rutland Cc: Peter Zijlstra Cc: Sandipan Das Cc: Stephane Eranian Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20220805200105.2020995-2-irogers@google.com Signed-off-by: Ian Rogers Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Documentation/perf-stat.txt | 21 ++ tools/perf/builtin-stat.c | 6 + tools/perf/util/stat-display.c | 383 ++++++++++++++++++++++++--------- tools/perf/util/stat.c | 1 + tools/perf/util/stat.h | 2 + 5 files changed, 307 insertions(+), 106 deletions(-) diff --git a/tools/perf/Documentation/perf-stat.txt b/tools/perf/Documentation/perf-stat.txt index d8a33f4a47c5..d7ff1867feda 100644 --- a/tools/perf/Documentation/perf-stat.txt +++ b/tools/perf/Documentation/perf-stat.txt @@ -570,6 +570,27 @@ Additional metrics may be printed with all earlier fields being empty. include::intel-hybrid.txt[] +JSON FORMAT +----------- + +With -j, perf stat is able to print out a JSON format output +that can be used for parsing. + +- timestamp : optional usec time stamp in fractions of second (with -I) +- optional aggregate options: + - core : core identifier (with --per-core) + - die : die identifier (with --per-die) + - socket : socket identifier (with --per-socket) + - node : node identifier (with --per-node) + - thread : thread identifier (with --per-thread) +- counter-value : counter value +- unit : unit of the counter value or empty +- event : event name +- variance : optional variance if multiple values are collected (with -r) +- runtime : run time of counter +- metric-value : optional metric value +- metric-unit : optional unit of metric + SEE ALSO -------- linkperf:perf-top[1], linkperf:perf-list[1] diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index b5ce07c5738a..0d9fec377071 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -1250,6 +1250,8 @@ static struct option stat_options[] = { "Merge identical named hybrid events"), OPT_STRING('x', "field-separator", &stat_config.csv_sep, "separator", "print counts with custom separator"), + OPT_BOOLEAN('j', "json-output", &stat_config.json_output, + "print counts in JSON format"), OPT_CALLBACK('G', "cgroup", &evsel_list, "name", "monitor event in cgroup name only", parse_stat_cgroups), OPT_STRING(0, "for-each-cgroup", &stat_config.cgroup_list, "name", @@ -1436,6 +1438,7 @@ static aggr_cpu_id_get_t aggr_mode__get_aggr(enum aggr_mode aggr_mode) case AGGR_GLOBAL: case AGGR_THREAD: case AGGR_UNSET: + case AGGR_MAX: default: return NULL; } @@ -1460,6 +1463,7 @@ static aggr_get_id_t aggr_mode__get_id(enum aggr_mode aggr_mode) case AGGR_GLOBAL: case AGGR_THREAD: case AGGR_UNSET: + case AGGR_MAX: default: return NULL; } @@ -1610,6 +1614,7 @@ static aggr_cpu_id_get_t aggr_mode__get_aggr_file(enum aggr_mode aggr_mode) case AGGR_GLOBAL: case AGGR_THREAD: case AGGR_UNSET: + case AGGR_MAX: default: return NULL; } @@ -1630,6 +1635,7 @@ static aggr_get_id_t aggr_mode__get_id_file(enum aggr_mode aggr_mode) case AGGR_GLOBAL: case AGGR_THREAD: case AGGR_UNSET: + case AGGR_MAX: default: return NULL; } diff --git a/tools/perf/util/stat-display.c b/tools/perf/util/stat-display.c index 44045565c8f8..b82844cb0ce7 100644 --- a/tools/perf/util/stat-display.c +++ b/tools/perf/util/stat-display.c @@ -28,15 +28,21 @@ static void print_running(struct perf_stat_config *config, u64 run, u64 ena) { - if (config->csv_output) { - fprintf(config->output, "%s%" PRIu64 "%s%.2f", - config->csv_sep, - run, - config->csv_sep, - ena ? 100.0 * run / ena : 100.0); - } else if (run != ena) { + + double enabled_percent = 100; + + if (run != ena) + enabled_percent = 100 * run / ena; + if (config->json_output) + fprintf(config->output, + "\"event-runtime\" : %" PRIu64 ", \"pcnt-running\" : %.2f, ", + run, enabled_percent); + else if (config->csv_output) + fprintf(config->output, + "%s%" PRIu64 "%s%.2f", config->csv_sep, + run, config->csv_sep, enabled_percent); + else if (run != ena) fprintf(config->output, " (%.2f%%)", 100.0 * run / ena); - } } static void print_noise_pct(struct perf_stat_config *config, @@ -44,7 +50,9 @@ static void print_noise_pct(struct perf_stat_config *config, { double pct = rel_stddev_stats(total, avg); - if (config->csv_output) + if (config->json_output) + fprintf(config->output, "\"variance\" : %.2f, ", pct); + else if (config->csv_output) fprintf(config->output, "%s%.2f%%", config->csv_sep, pct); else if (pct) fprintf(config->output, " ( +-%6.2f%% )", pct); @@ -66,7 +74,11 @@ static void print_cgroup(struct perf_stat_config *config, struct evsel *evsel) { if (nr_cgroups) { const char *cgrp_name = evsel->cgrp ? evsel->cgrp->name : ""; - fprintf(config->output, "%s%s", config->csv_sep, cgrp_name); + + if (config->json_output) + fprintf(config->output, "\"cgroup\" : \"%s\", ", cgrp_name); + else + fprintf(config->output, "%s%s", config->csv_sep, cgrp_name); } } @@ -74,69 +86,123 @@ static void print_cgroup(struct perf_stat_config *config, struct evsel *evsel) static void aggr_printout(struct perf_stat_config *config, struct evsel *evsel, struct aggr_cpu_id id, int nr) { + + + if (config->json_output && !config->interval) + fprintf(config->output, "{"); + switch (config->aggr_mode) { case AGGR_CORE: - fprintf(config->output, "S%d-D%d-C%*d%s%*d%s", - id.socket, - id.die, - config->csv_output ? 0 : -8, - id.core, - config->csv_sep, - config->csv_output ? 0 : 4, - nr, - config->csv_sep); + if (config->json_output) { + fprintf(config->output, + "\"core\" : \"S%d-D%d-C%d\", \"aggregate-number\" : %d, ", + id.socket, + id.die, + id.core, + nr); + } else { + fprintf(config->output, "S%d-D%d-C%*d%s%*d%s", + id.socket, + id.die, + config->csv_output ? 0 : -8, + id.core, + config->csv_sep, + config->csv_output ? 0 : 4, + nr, + config->csv_sep); + } break; case AGGR_DIE: - fprintf(config->output, "S%d-D%*d%s%*d%s", - id.socket, - config->csv_output ? 0 : -8, - id.die, - config->csv_sep, - config->csv_output ? 0 : 4, - nr, - config->csv_sep); + if (config->json_output) { + fprintf(config->output, + "\"die\" : \"S%d-D%d\", \"aggregate-number\" : %d, ", + id.socket, + id.die, + nr); + } else { + fprintf(config->output, "S%d-D%*d%s%*d%s", + id.socket, + config->csv_output ? 0 : -8, + id.die, + config->csv_sep, + config->csv_output ? 0 : 4, + nr, + config->csv_sep); + } break; case AGGR_SOCKET: - fprintf(config->output, "S%*d%s%*d%s", - config->csv_output ? 0 : -5, - id.socket, - config->csv_sep, - config->csv_output ? 0 : 4, - nr, - config->csv_sep); - break; + if (config->json_output) { + fprintf(config->output, + "\"socket\" : \"S%d\", \"aggregate-number\" : %d, ", + id.socket, + nr); + } else { + fprintf(config->output, "S%*d%s%*d%s", + config->csv_output ? 0 : -5, + id.socket, + config->csv_sep, + config->csv_output ? 0 : 4, + nr, + config->csv_sep); + } + break; case AGGR_NODE: - fprintf(config->output, "N%*d%s%*d%s", - config->csv_output ? 0 : -5, - id.node, - config->csv_sep, - config->csv_output ? 0 : 4, - nr, - config->csv_sep); - break; + if (config->json_output) { + fprintf(config->output, "\"node\" : \"N%d\", \"aggregate-number\" : %d, ", + id.node, + nr); + } else { + fprintf(config->output, "N%*d%s%*d%s", + config->csv_output ? 0 : -5, + id.node, + config->csv_sep, + config->csv_output ? 0 : 4, + nr, + config->csv_sep); + } + break; case AGGR_NONE: - if (evsel->percore && !config->percore_show_thread) { - fprintf(config->output, "S%d-D%d-C%*d%s", - id.socket, - id.die, - config->csv_output ? 0 : -3, - id.core, config->csv_sep); - } else if (id.cpu.cpu > -1) { - fprintf(config->output, "CPU%*d%s", - config->csv_output ? 0 : -7, - id.cpu.cpu, config->csv_sep); + if (config->json_output) { + if (evsel->percore && !config->percore_show_thread) { + fprintf(config->output, "\"core\" : \"S%d-D%d-C%d\"", + id.socket, + id.die, + id.core); + } else if (id.core > -1) { + fprintf(config->output, "\"cpu\" : \"%d\", ", + id.cpu.cpu); + } + } else { + if (evsel->percore && !config->percore_show_thread) { + fprintf(config->output, "S%d-D%d-C%*d%s", + id.socket, + id.die, + config->csv_output ? 0 : -3, + id.core, config->csv_sep); + } else if (id.core > -1) { + fprintf(config->output, "CPU%*d%s", + config->csv_output ? 0 : -7, + id.cpu.cpu, config->csv_sep); + } } break; case AGGR_THREAD: - fprintf(config->output, "%*s-%*d%s", - config->csv_output ? 0 : 16, - perf_thread_map__comm(evsel->core.threads, id.thread), - config->csv_output ? 0 : -8, - perf_thread_map__pid(evsel->core.threads, id.thread), - config->csv_sep); + if (config->json_output) { + fprintf(config->output, "\"thread\" : \"%s-%d\", ", + perf_thread_map__comm(evsel->core.threads, id.thread), + perf_thread_map__pid(evsel->core.threads, id.thread)); + } else { + fprintf(config->output, "%*s-%*d%s", + config->csv_output ? 0 : 16, + perf_thread_map__comm(evsel->core.threads, id.thread), + config->csv_output ? 0 : -8, + perf_thread_map__pid(evsel->core.threads, id.thread), + config->csv_sep); + } break; case AGGR_GLOBAL: case AGGR_UNSET: + case AGGR_MAX: default: break; } @@ -234,6 +300,31 @@ static void print_metric_csv(struct perf_stat_config *config __maybe_unused, fprintf(out, "%s%s%s%s", config->csv_sep, vals, config->csv_sep, skip_spaces(unit)); } +static void print_metric_json(struct perf_stat_config *config __maybe_unused, + void *ctx, + const char *color __maybe_unused, + const char *fmt __maybe_unused, + const char *unit, double val) +{ + struct outstate *os = ctx; + FILE *out = os->fh; + + fprintf(out, "\"metric-value\" : %f, ", val); + fprintf(out, "\"metric-unit\" : \"%s\"", unit); + if (!config->metric_only) + fprintf(out, "}"); +} + +static void new_line_json(struct perf_stat_config *config, void *ctx) +{ + struct outstate *os = ctx; + + fputc('\n', os->fh); + if (os->prefix) + fprintf(os->fh, "%s", os->prefix); + aggr_printout(config, os->evsel, os->id, os->nr); +} + /* Filter out some columns that don't work well in metrics only mode */ static bool valid_only_metric(const char *unit) @@ -300,6 +391,27 @@ static void print_metric_only_csv(struct perf_stat_config *config __maybe_unused fprintf(out, "%s%s", vals, config->csv_sep); } +static void print_metric_only_json(struct perf_stat_config *config __maybe_unused, + void *ctx, const char *color __maybe_unused, + const char *fmt, + const char *unit, double val) +{ + struct outstate *os = ctx; + FILE *out = os->fh; + char buf[64], *vals, *ends; + char tbuf[1024]; + + if (!valid_only_metric(unit)) + return; + unit = fixunit(tbuf, os->evsel, unit); + snprintf(buf, sizeof(buf), fmt, val); + ends = vals = skip_spaces(buf); + while (isdigit(*ends) || *ends == '.') + ends++; + *ends = 0; + fprintf(out, "{\"metric-value\" : \"%s\"}", vals); +} + static void new_line_metric(struct perf_stat_config *config __maybe_unused, void *ctx __maybe_unused) { @@ -318,10 +430,13 @@ static void print_metric_header(struct perf_stat_config *config, os->evsel->priv != os->evsel->evlist->selected->priv) return; - if (!valid_only_metric(unit)) + if (!valid_only_metric(unit) && !config->json_output) return; unit = fixunit(tbuf, os->evsel, unit); - if (config->csv_output) + + if (config->json_output) + fprintf(os->fh, "\"unit\" : \"%s\"", unit); + else if (config->csv_output) fprintf(os->fh, "%s%s", unit, config->csv_sep); else fprintf(os->fh, "%*s ", config->metric_only_len, unit); @@ -367,14 +482,27 @@ static void abs_printout(struct perf_stat_config *config, aggr_printout(config, evsel, id, nr); - fprintf(output, fmt, avg, config->csv_sep); + if (config->json_output) + fprintf(output, "\"counter-value\" : \"%f\", ", avg); + else + fprintf(output, fmt, avg, config->csv_sep); - if (evsel->unit) - fprintf(output, "%-*s%s", - config->csv_output ? 0 : config->unit_width, - evsel->unit, config->csv_sep); + if (config->json_output) { + if (evsel->unit) { + fprintf(output, "\"unit\" : \"%s\", ", + evsel->unit); + } + } else { + if (evsel->unit) + fprintf(output, "%-*s%s", + config->csv_output ? 0 : config->unit_width, + evsel->unit, config->csv_sep); + } - fprintf(output, "%-*s", config->csv_output ? 0 : 32, evsel__name(evsel)); + if (config->json_output) + fprintf(output, "\"event\" : \"%s\", ", evsel__name(evsel)); + else + fprintf(output, "%-*s", config->csv_output ? 0 : 32, evsel__name(evsel)); print_cgroup(config, evsel); } @@ -416,34 +544,30 @@ static void printout(struct perf_stat_config *config, struct aggr_cpu_id id, int .nr = nr, .evsel = counter, }; - print_metric_t pm = print_metric_std; + print_metric_t pm; new_line_t nl; - if (config->metric_only) { - nl = new_line_metric; - if (config->csv_output) - pm = print_metric_only_csv; - else - pm = print_metric_only; - } else - nl = new_line_std; - - if (config->csv_output && !config->metric_only) { - static int aggr_fields[] = { - [AGGR_GLOBAL] = 0, - [AGGR_THREAD] = 1, + if (config->csv_output) { + static const int aggr_fields[AGGR_MAX] = { [AGGR_NONE] = 1, + [AGGR_GLOBAL] = 0, [AGGR_SOCKET] = 2, [AGGR_DIE] = 2, [AGGR_CORE] = 2, + [AGGR_THREAD] = 1, + [AGGR_UNSET] = 0, + [AGGR_NODE] = 0, }; - pm = print_metric_csv; - nl = new_line_csv; - os.nfields = 3; - os.nfields += aggr_fields[config->aggr_mode]; - if (counter->cgrp) - os.nfields++; + pm = config->metric_only ? print_metric_only_csv : print_metric_csv; + nl = config->metric_only ? new_line_metric : new_line_csv; + os.nfields = 3 + aggr_fields[config->aggr_mode] + (counter->cgrp ? 1 : 0); + } else if (config->json_output) { + pm = config->metric_only ? print_metric_only_json : print_metric_json; + nl = config->metric_only ? new_line_metric : new_line_json; + } else { + pm = config->metric_only ? print_metric_only : print_metric_std; + nl = config->metric_only ? new_line_metric : new_line_std; } if (!config->no_csv_summary && config->csv_output && @@ -458,10 +582,15 @@ static void printout(struct perf_stat_config *config, struct aggr_cpu_id id, int } aggr_printout(config, counter, id, nr); - fprintf(config->output, "%*s%s", - config->csv_output ? 0 : 18, - counter->supported ? CNTR_NOT_COUNTED : CNTR_NOT_SUPPORTED, - config->csv_sep); + if (config->json_output) { + fprintf(config->output, "\"counter-value\" : \"%s\", ", + counter->supported ? CNTR_NOT_COUNTED : CNTR_NOT_SUPPORTED); + } else { + fprintf(config->output, "%*s%s", + config->csv_output ? 0 : 18, + counter->supported ? CNTR_NOT_COUNTED : CNTR_NOT_SUPPORTED, + config->csv_sep); + } if (counter->supported) { if (!evlist__has_hybrid(counter->evlist)) { @@ -471,21 +600,32 @@ static void printout(struct perf_stat_config *config, struct aggr_cpu_id id, int } } - fprintf(config->output, "%-*s%s", - config->csv_output ? 0 : config->unit_width, - counter->unit, config->csv_sep); + if (config->json_output) { + fprintf(config->output, "\"unit\" : \"%s\", ", counter->unit); + } else { + fprintf(config->output, "%-*s%s", + config->csv_output ? 0 : config->unit_width, + counter->unit, config->csv_sep); + } - fprintf(config->output, "%*s", - config->csv_output ? 0 : -25, evsel__name(counter)); + if (config->json_output) { + fprintf(config->output, "\"event\" : \"%s\", ", + evsel__name(counter)); + } else { + fprintf(config->output, "%*s", + config->csv_output ? 0 : -25, evsel__name(counter)); + } print_cgroup(config, counter); - if (!config->csv_output) + if (!config->csv_output && !config->json_output) pm(config, &os, NULL, NULL, "", 0); print_noise(config, counter, noise); print_running(config, run, ena); if (config->csv_output) pm(config, &os, NULL, NULL, "", 0); + else if (config->json_output) + pm(config, &os, NULL, NULL, "", 0); return; } @@ -500,12 +640,15 @@ static void printout(struct perf_stat_config *config, struct aggr_cpu_id id, int if (config->csv_output && !config->metric_only) { print_noise(config, counter, noise); print_running(config, run, ena); + } else if (config->json_output && !config->metric_only) { + print_noise(config, counter, noise); + print_running(config, run, ena); } perf_stat__print_shadow_stats(config, counter, uval, first_shadow_cpu_map_idx(config, counter, &id), &out, &config->metric_events, st); - if (!config->csv_output && !config->metric_only) { + if (!config->csv_output && !config->metric_only && !config->json_output) { print_noise(config, counter, noise); print_running(config, run, ena); } @@ -1004,8 +1147,12 @@ static void print_metric_headers(struct perf_stat_config *config, struct outstate os = { .fh = config->output }; + bool first = true; + + if (config->json_output && !config->interval) + fprintf(config->output, "{"); - if (prefix) + if (prefix && !config->json_output) fprintf(config->output, "%s", prefix); if (!config->csv_output && !no_indent) @@ -1025,6 +1172,9 @@ static void print_metric_headers(struct perf_stat_config *config, os.evsel = counter; out.ctx = &os; out.print_metric = print_metric_header; + if (!first && config->json_output) + fprintf(config->output, ", "); + first = false; out.new_line = new_line_metric; out.force_header = true; perf_stat__print_shadow_stats(config, counter, 0, @@ -1033,6 +1183,8 @@ static void print_metric_headers(struct perf_stat_config *config, &config->metric_events, &rt_stat); } + if (config->json_output) + fprintf(config->output, "}"); fputc('\n', config->output); } @@ -1048,10 +1200,18 @@ static void print_interval(struct perf_stat_config *config, if (config->interval_clear) puts(CONSOLE_CLEAR); - if (!config->iostat_run) - sprintf(prefix, "%6lu.%09lu%s", (unsigned long) ts->tv_sec, ts->tv_nsec, config->csv_sep); - - if ((num_print_interval == 0 && !config->csv_output) || config->interval_clear) { + if (!config->iostat_run && !config->json_output) + sprintf(prefix, "%6lu.%09lu%s", (unsigned long) ts->tv_sec, + ts->tv_nsec, config->csv_sep); + if (!config->iostat_run && config->json_output && !config->metric_only) + sprintf(prefix, "{\"interval\" : %lu.%09lu, ", (unsigned long) + ts->tv_sec, ts->tv_nsec); + if (!config->iostat_run && config->json_output && config->metric_only) + sprintf(prefix, "{\"interval\" : %lu.%09lu}", (unsigned long) + ts->tv_sec, ts->tv_nsec); + + if ((num_print_interval == 0 && !config->csv_output && !config->json_output) + || config->interval_clear) { switch (config->aggr_mode) { case AGGR_NODE: fprintf(output, "# time node cpus"); @@ -1091,12 +1251,19 @@ static void print_interval(struct perf_stat_config *config, fprintf(output, " counts %*s events\n", unit_width, "unit"); } case AGGR_UNSET: + case AGGR_MAX: break; } } - if ((num_print_interval == 0 || config->interval_clear) && metric_only) + if ((num_print_interval == 0 || config->interval_clear) + && metric_only && !config->json_output) print_metric_headers(config, evlist, " ", true); + if ((num_print_interval == 0 || config->interval_clear) + && metric_only && config->json_output) { + fprintf(output, "{"); + print_metric_headers(config, evlist, " ", true); + } if (++num_print_interval == 25) num_print_interval = 0; } @@ -1110,7 +1277,7 @@ static void print_header(struct perf_stat_config *config, fflush(stdout); - if (!config->csv_output) { + if (!config->csv_output && !config->json_output) { fprintf(output, "\n"); fprintf(output, " Performance counter stats for "); if (_target->bpf_str) @@ -1303,6 +1470,9 @@ void evlist__print_counters(struct evlist *evlist, struct perf_stat_config *conf num_print_iv = 0; if (config->aggr_mode == AGGR_GLOBAL && prefix && !config->iostat_run) fprintf(config->output, "%s", prefix); + + if (config->json_output && !config->metric_only) + fprintf(config->output, "}"); } switch (config->aggr_mode) { @@ -1341,12 +1511,13 @@ void evlist__print_counters(struct evlist *evlist, struct perf_stat_config *conf } } break; + case AGGR_MAX: case AGGR_UNSET: default: break; } - if (!interval && !config->csv_output) + if (!interval && !config->csv_output && !config->json_output) print_footer(config); fflush(config->output); diff --git a/tools/perf/util/stat.c b/tools/perf/util/stat.c index 37ea2d044708..0882b4754fcf 100644 --- a/tools/perf/util/stat.c +++ b/tools/perf/util/stat.c @@ -401,6 +401,7 @@ process_counter_values(struct perf_stat_config *config, struct evsel *evsel, aggr->ena += count->ena; aggr->run += count->run; case AGGR_UNSET: + case AGGR_MAX: default: break; } diff --git a/tools/perf/util/stat.h b/tools/perf/util/stat.h index b5aeb8e6d34b..668250022f8c 100644 --- a/tools/perf/util/stat.h +++ b/tools/perf/util/stat.h @@ -57,6 +57,7 @@ enum aggr_mode { AGGR_THREAD, AGGR_UNSET, AGGR_NODE, + AGGR_MAX }; enum { @@ -121,6 +122,7 @@ struct perf_stat_config { bool no_inherit; bool identifier; bool csv_output; + bool json_output; bool interval_clear; bool metric_only; bool null_run; -- cgit v1.2.3 From 0c343af2a2f82844d03e5e30dc09a331421cd0c3 Mon Sep 17 00:00:00 2001 From: Claire Jensen Date: Fri, 5 Aug 2022 13:01:05 -0700 Subject: perf test: JSON format checking Add field checking tests for perf stat JSON output. Sanity checks the expected number of fields are present, that the expected keys are present and they have the correct values. Committer notes: Had to fix this: - $(INSTALL) tests/shell/lib/*.sh '$(DESTDIR_SQ)$(perfexec_instdir_SQ)/tests/shell/lib' \ + $(INSTALL) tests/shell/lib/*.sh '$(DESTDIR_SQ)$(perfexec_instdir_SQ)/tests/shell/lib'; \ Committer testing: [root@quaco ~]# perf test json 90: perf stat JSON output linter : Ok [root@quaco ~]# set -o vi [root@quaco ~]# perf test -v json 90: perf stat JSON output linter : --- start --- test child forked, pid 560794 Checking json output: no args [Success] Checking json output: system wide [Success] Checking json output: system wide Checking json output: system wide no aggregation [Success] Checking json output: interval [Success] Checking json output: event [Success] Checking json output: per core [Success] Checking json output: per thread [Success] Checking json output: per die [Success] Checking json output: per node [Success] Checking json output: per socket [Success] test child finished with 0 ---- end ---- perf stat JSON output linter: Ok [root@quaco ~]# Signed-off-by: Claire Jensen Acked-by: Namhyung Kim Tested-by: Arnaldo Carvalho de Melo Cc: Alexander Shishkin Cc: Alyssa Ross Cc: Claire Jensen Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: Kan Liang Cc: Like Xu Cc: Mark Rutland Cc: Peter Zijlstra Cc: Sandipan Das Cc: Stephane Eranian Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20220805200105.2020995-3-irogers@google.com Signed-off-by: Ian Rogers Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.perf | 3 +- .../perf/tests/shell/lib/perf_json_output_lint.py | 96 ++++++++++++++ tools/perf/tests/shell/stat+json_output.sh | 147 +++++++++++++++++++++ 3 files changed, 245 insertions(+), 1 deletion(-) create mode 100644 tools/perf/tests/shell/lib/perf_json_output_lint.py create mode 100755 tools/perf/tests/shell/stat+json_output.sh diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf index 5053b563bf9c..e5921b347153 100644 --- a/tools/perf/Makefile.perf +++ b/tools/perf/Makefile.perf @@ -1005,7 +1005,8 @@ install-tests: all install-gtk $(INSTALL) -d -m 755 '$(DESTDIR_SQ)$(perfexec_instdir_SQ)/tests/shell'; \ $(INSTALL) tests/shell/*.sh '$(DESTDIR_SQ)$(perfexec_instdir_SQ)/tests/shell'; \ $(INSTALL) -d -m 755 '$(DESTDIR_SQ)$(perfexec_instdir_SQ)/tests/shell/lib'; \ - $(INSTALL) tests/shell/lib/*.sh '$(DESTDIR_SQ)$(perfexec_instdir_SQ)/tests/shell/lib' + $(INSTALL) tests/shell/lib/*.sh '$(DESTDIR_SQ)$(perfexec_instdir_SQ)/tests/shell/lib'; \ + $(INSTALL) tests/shell/lib/*.py '$(DESTDIR_SQ)$(perfexec_instdir_SQ)/tests/shell/lib' install-bin: install-tools install-tests install-traceevent-plugins diff --git a/tools/perf/tests/shell/lib/perf_json_output_lint.py b/tools/perf/tests/shell/lib/perf_json_output_lint.py new file mode 100644 index 000000000000..d90f8d102eb9 --- /dev/null +++ b/tools/perf/tests/shell/lib/perf_json_output_lint.py @@ -0,0 +1,96 @@ +#!/usr/bin/python +# SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) +# Basic sanity check of perf JSON output as specified in the man page. + +import argparse +import sys +import json + +ap = argparse.ArgumentParser() +ap.add_argument('--no-args', action='store_true') +ap.add_argument('--interval', action='store_true') +ap.add_argument('--system-wide-no-aggr', action='store_true') +ap.add_argument('--system-wide', action='store_true') +ap.add_argument('--event', action='store_true') +ap.add_argument('--per-core', action='store_true') +ap.add_argument('--per-thread', action='store_true') +ap.add_argument('--per-die', action='store_true') +ap.add_argument('--per-node', action='store_true') +ap.add_argument('--per-socket', action='store_true') +args = ap.parse_args() + +Lines = sys.stdin.readlines() + +def isfloat(num): + try: + float(num) + return True + except ValueError: + return False + + +def isint(num): + try: + int(num) + return True + except ValueError: + return False + +def is_counter_value(num): + return isfloat(num) or num == '' or num == '' + +def check_json_output(expected_items): + if expected_items != -1: + for line in Lines: + if 'failed' not in line: + count = 0 + count = line.count(',') + if count != expected_items and count >= 1 and count <= 3 and 'metric-value' in line: + # Events that generate >1 metric may have isolated metric + # values and possibly other prefixes like interval, core and + # aggregate-number. + continue + if count != expected_items: + raise RuntimeError(f'wrong number of fields. counted {count} expected {expected_items}' + f' in \'{line}\'') + checks = { + 'aggregate-number': lambda x: isfloat(x), + 'core': lambda x: True, + 'counter-value': lambda x: is_counter_value(x), + 'cgroup': lambda x: True, + 'cpu': lambda x: isint(x), + 'die': lambda x: True, + 'event': lambda x: True, + 'event-runtime': lambda x: isfloat(x), + 'interval': lambda x: isfloat(x), + 'metric-unit': lambda x: True, + 'metric-value': lambda x: isfloat(x), + 'node': lambda x: True, + 'pcnt-running': lambda x: isfloat(x), + 'socket': lambda x: True, + 'thread': lambda x: True, + 'unit': lambda x: True, + } + input = '[\n' + ','.join(Lines) + '\n]' + for item in json.loads(input): + for key, value in item.items(): + if key not in checks: + raise RuntimeError(f'Unexpected key: key={key} value={value}') + if not checks[key](value): + raise RuntimeError(f'Check failed for: key={key} value={value}') + + +try: + if args.no_args or args.system_wide or args.event: + expected_items = 6 + elif args.interval or args.per_thread or args.system_wide_no_aggr: + expected_items = 7 + elif args.per_core or args.per_socket or args.per_node or args.per_die: + expected_items = 8 + else: + # If no option is specified, don't check the number of items. + expected_items = -1 + check_json_output(expected_items) +except: + print('Test failed for input:\n' + '\n'.join(Lines)) + raise diff --git a/tools/perf/tests/shell/stat+json_output.sh b/tools/perf/tests/shell/stat+json_output.sh new file mode 100755 index 000000000000..ea8714a36051 --- /dev/null +++ b/tools/perf/tests/shell/stat+json_output.sh @@ -0,0 +1,147 @@ +#!/bin/bash +# perf stat JSON output linter +# SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) +# Checks various perf stat JSON output commands for the +# correct number of fields. + +set -e + +pythonchecker=$(dirname $0)/lib/perf_json_output_lint.py +if [ "x$PYTHON" == "x" ] +then + if which python3 > /dev/null + then + PYTHON=python3 + elif which python > /dev/null + then + PYTHON=python + else + echo Skipping test, python not detected please set environment variable PYTHON. + exit 2 + fi +fi + +# Return true if perf_event_paranoid is > $1 and not running as root. +function ParanoidAndNotRoot() +{ + [ $(id -u) != 0 ] && [ $(cat /proc/sys/kernel/perf_event_paranoid) -gt $1 ] +} + +check_no_args() +{ + echo -n "Checking json output: no args " + perf stat -j true 2>&1 | $PYTHON $pythonchecker --no-args + echo "[Success]" +} + +check_system_wide() +{ + echo -n "Checking json output: system wide " + if ParanoidAndNotRoot 0 + then + echo "[Skip] paranoia and not root" + return + fi + perf stat -j -a true 2>&1 | $PYTHON $pythonchecker --system-wide + echo "[Success]" +} + +check_system_wide_no_aggr() +{ + echo -n "Checking json output: system wide " + if ParanoidAndNotRoot 0 + then + echo "[Skip] paranoia and not root" + return + fi + echo -n "Checking json output: system wide no aggregation " + perf stat -j -A -a --no-merge true 2>&1 | $PYTHON $pythonchecker --system-wide-no-aggr + echo "[Success]" +} + +check_interval() +{ + echo -n "Checking json output: interval " + perf stat -j -I 1000 true 2>&1 | $PYTHON $pythonchecker --interval + echo "[Success]" +} + + +check_event() +{ + echo -n "Checking json output: event " + perf stat -j -e cpu-clock true 2>&1 | $PYTHON $pythonchecker --event + echo "[Success]" +} + +check_per_core() +{ + echo -n "Checking json output: per core " + if ParanoidAndNotRoot 0 + then + echo "[Skip] paranoia and not root" + return + fi + perf stat -j --per-core -a true 2>&1 | $PYTHON $pythonchecker --per-core + echo "[Success]" +} + +check_per_thread() +{ + echo -n "Checking json output: per thread " + if ParanoidAndNotRoot 0 + then + echo "[Skip] paranoia and not root" + return + fi + perf stat -j --per-thread -a true 2>&1 | $PYTHON $pythonchecker --per-thread + echo "[Success]" +} + +check_per_die() +{ + echo -n "Checking json output: per die " + if ParanoidAndNotRoot 0 + then + echo "[Skip] paranoia and not root" + return + fi + perf stat -j --per-die -a true 2>&1 | $PYTHON $pythonchecker --per-die + echo "[Success]" +} + +check_per_node() +{ + echo -n "Checking json output: per node " + if ParanoidAndNotRoot 0 + then + echo "[Skip] paranoia and not root" + return + fi + perf stat -j --per-node -a true 2>&1 | $PYTHON $pythonchecker --per-node + echo "[Success]" +} + +check_per_socket() +{ + echo -n "Checking json output: per socket " + if ParanoidAndNotRoot 0 + then + echo "[Skip] paranoia and not root" + return + fi + perf stat -j --per-socket -a true 2>&1 | $PYTHON $pythonchecker --per-socket + echo "[Success]" +} + +check_no_args +check_system_wide +check_system_wide_no_aggr +check_interval +check_event +check_per_core +check_per_thread +check_per_die +check_per_node +check_per_socket +exit 0 -- cgit v1.2.3 From 629b98e2b1c6efcfa44ce144fce744819f0258f5 Mon Sep 17 00:00:00 2001 From: Roberto Sassu Date: Tue, 19 Jul 2022 19:05:52 +0200 Subject: tools, build: Retry detection of bfd-related features While separate features have been defined to determine which linking flags are required to use libbfd depending on the distribution (libbfd, libbfd-liberty and libbfd-liberty-z), the same has not been done for other features requiring linking to libbfd. For example, disassembler-four-args requires linking to libbfd too, but it should use the right linking flags. If not all the required ones are specified, e.g. -liberty, detection will always fail even if the feature is available. Instead of creating new features, similarly to libbfd, simply retry detection with the different set of flags until detection succeeds (or fails, if the libraries are missing). In this way, feature detection is transparent for the users of this building mechanism (e.g. perf), and those users don't have for example to set an appropriate value for the FEATURE_CHECK_LDFLAGS-disassembler-four-args variable. The number of retries and features for which the retry mechanism is implemented is low enough to make the increase in the complexity of Makefile negligible. Tested with perf and bpftool on Ubuntu 20.04.4 LTS, Fedora 36 and openSUSE Tumbleweed. Committer notes: Do the retry for disassembler-init-styled as well. Signed-off-by: Roberto Sassu Cc: Alexei Starovoitov Cc: Andres Freund Cc: Andrii Nakryiko Cc: Daniel Borkmann Cc: Ingo Molnar Cc: John Fastabend Cc: KP Singh Cc: Martin KaFai Lau Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Nick Terrell Cc: Peter Zijlstra Cc: Quentin Monnet Cc: Song Liu Cc: Stanislav Fomichev Cc: bpf@vger.kernel.org Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20220719170555.2576993-1-roberto.sassu@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/build/feature/Makefile | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/tools/build/feature/Makefile b/tools/build/feature/Makefile index c3059739318a..04b07ff88234 100644 --- a/tools/build/feature/Makefile +++ b/tools/build/feature/Makefile @@ -90,6 +90,8 @@ all: $(FILES) __BUILD = $(CC) $(CFLAGS) -MD -Wall -Werror -o $@ $(patsubst %.bin,%.c,$(@F)) $(LDFLAGS) BUILD = $(__BUILD) > $(@:.bin=.make.output) 2>&1 + BUILD_BFD = $(BUILD) -DPACKAGE='"perf"' -lbfd -ldl + BUILD_ALL = $(BUILD) -fstack-protector-all -O2 -D_FORTIFY_SOURCE=2 -ldw -lelf -lnuma -lelf -lslang $(FLAGS_PERL_EMBED) $(FLAGS_PYTHON_EMBED) -DPACKAGE='"perf"' -lbfd -ldl -lz -llzma -lzstd -lcap __BUILDXX = $(CXX) $(CXXFLAGS) -MD -Wall -Werror -o $@ $(patsubst %.bin,%.cpp,$(@F)) $(LDFLAGS) BUILDXX = $(__BUILDXX) > $(@:.bin=.make.output) 2>&1 @@ -97,7 +99,7 @@ __BUILDXX = $(CXX) $(CXXFLAGS) -MD -Wall -Werror -o $@ $(patsubst %.bin,%.cpp,$( ############################### $(OUTPUT)test-all.bin: - $(BUILD) -fstack-protector-all -O2 -D_FORTIFY_SOURCE=2 -ldw -lelf -lnuma -lelf -lslang $(FLAGS_PERL_EMBED) $(FLAGS_PYTHON_EMBED) -DPACKAGE='"perf"' -lbfd -ldl -lz -llzma -lzstd -lcap + $(BUILD_ALL) || $(BUILD_ALL) -lopcodes -liberty $(OUTPUT)test-hello.bin: $(BUILD) @@ -241,16 +243,18 @@ $(OUTPUT)test-libpython.bin: $(BUILD) $(FLAGS_PYTHON_EMBED) $(OUTPUT)test-libbfd.bin: - $(BUILD) -DPACKAGE='"perf"' -lbfd -ldl + $(BUILD_BFD) $(OUTPUT)test-libbfd-buildid.bin: - $(BUILD) -DPACKAGE='"perf"' -lbfd -ldl + $(BUILD_BFD) || $(BUILD_BFD) -liberty || $(BUILD_BFD) -liberty -lz $(OUTPUT)test-disassembler-four-args.bin: - $(BUILD) -DPACKAGE='"perf"' -lbfd -lopcodes + $(BUILD_BFD) -lopcodes || $(BUILD_BFD) -lopcodes -liberty || \ + $(BUILD_BFD) -lopcodes -liberty -lz $(OUTPUT)test-disassembler-init-styled.bin: - $(BUILD) -DPACKAGE='"perf"' -lbfd -lopcodes + $(BUILD_BFD) -lopcodes || $(BUILD_BFD) -lopcodes -liberty || \ + $(BUILD_BFD) -lopcodes -liberty -lz $(OUTPUT)test-reallocarray.bin: $(BUILD) -- cgit v1.2.3 From 13e6f53a7692ac239241e6bc5c82c58c18c4f1ab Mon Sep 17 00:00:00 2001 From: Roberto Sassu Date: Tue, 19 Jul 2022 19:05:53 +0200 Subject: bpftool: Complete libbfd feature detection Commit 6e8ccb4f624a7 ("tools/bpf: properly account for libbfd variations") sets the linking flags depending on which flavor of the libbfd feature was detected. However, the flavors except libbfd cannot be detected, as they are not in the feature list. Complete the list of features to detect by adding libbfd-liberty and libbfd-liberty-z. Committer notes: Adjust conflict with with: 1e1613f64cc8a09d ("tools bpftool: Don't display disassembler-four-args feature test") 600b7b26c07a070d ("tools bpftool: Fix compilation error with new binutils") Fixes: 6e8ccb4f624a73c5 ("tools/bpf: properly account for libbfd variations") Signed-off-by: Roberto Sassu Cc: Alexei Starovoitov Cc: Andres Freund Cc: Andrii Nakryiko Cc: bpf@vger.kernel.org Cc: Daniel Borkmann Cc: Ingo Molnar Cc: John Fastabend Cc: KP Singh Cc: llvm@lists.linux.dev Cc: Martin KaFai Lau Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Nick Terrell Cc: Peter Zijlstra Cc: Quentin Monnet Cc: Song Liu Cc: Stanislav Fomichev Link: https://lore.kernel.org/r/20220719170555.2576993-2-roberto.sassu@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/bpf/bpftool/Makefile | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tools/bpf/bpftool/Makefile b/tools/bpf/bpftool/Makefile index 04d733e98bff..4a95c017ad4c 100644 --- a/tools/bpf/bpftool/Makefile +++ b/tools/bpf/bpftool/Makefile @@ -93,9 +93,11 @@ INSTALL ?= install RM ?= rm -f FEATURE_USER = .bpftool -FEATURE_TESTS = libbfd disassembler-four-args disassembler-init-styled libcap \ +FEATURE_TESTS = libbfd libbfd-liberty libbfd-liberty-z \ + disassembler-four-args disassembler-init-styled libcap \ clang-bpf-co-re -FEATURE_DISPLAY = libbfd libcap clang-bpf-co-re +FEATURE_DISPLAY = libbfd libbfd-liberty libbfd-liberty-z \ + libcap clang-bpf-co-re check_feat := 1 NON_CHECK_FEAT_TARGETS := clean uninstall doc doc-clean doc-install doc-uninstall -- cgit v1.2.3 From dd6775f986144a9e0563dab70ef0398768227113 Mon Sep 17 00:00:00 2001 From: Roberto Sassu Date: Tue, 19 Jul 2022 19:05:54 +0200 Subject: perf build: Remove FEATURE_CHECK_LDFLAGS-disassembler-{four-args,init-styled} setting As the building mechanism is now able to retry detection with different combinations of linking flags, setting FEATURE_CHECK_LDFLAGS-disassembler-four-args and FEATURE_CHECK_LDFLAGS-disassembler-init-styled is not necessary anymore, so remove it. Committer notes: Use the same technique to find the set of bfd-related libraries to link as in: 3308ffc5016e6136 ("tools, build: Retry detection of bfd-related features") Signed-off-by: Roberto Sassu Cc: Alexei Starovoitov Cc: Andres Freund Cc: Andrii Nakryiko Cc: Daniel Borkmann Cc: Ingo Molnar Cc: John Fastabend Cc: KP Singh Cc: Martin KaFai Lau Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Nick Terrell Cc: Peter Zijlstra Cc: Quentin Monnet Cc: Song Liu Cc: Stanislav Fomichev Cc: bpf@vger.kernel.org Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20220719170555.2576993-3-roberto.sassu@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.config | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index 23648ea54e8d..0661a1cf9855 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -297,9 +297,6 @@ FEATURE_CHECK_LDFLAGS-libpython := $(PYTHON_EMBED_LDOPTS) FEATURE_CHECK_LDFLAGS-libaio = -lrt -FEATURE_CHECK_LDFLAGS-disassembler-four-args = -lbfd -lopcodes -ldl -FEATURE_CHECK_LDFLAGS-disassembler-init-styled = -lbfd -lopcodes -ldl - CORE_CFLAGS += -fno-omit-frame-pointer CORE_CFLAGS += -ggdb3 CORE_CFLAGS += -funwind-tables @@ -329,8 +326,8 @@ ifneq ($(TCMALLOC),) endif ifeq ($(FEATURES_DUMP),) -# We will display at the end of this Makefile.config, using $(call feature_display_entries) -# As we may retry some feature detection here, see the disassembler-four-args case, for instance +# We will display at the end of this Makefile.config, using $(call feature_display_entries), +# as we may retry some feature detection here. FEATURE_DISPLAY_DEFERRED := 1 include $(srctree)/tools/build/Makefile.feature else @@ -924,13 +921,9 @@ ifndef NO_LIBBFD ifeq ($(feature-libbfd-liberty), 1) EXTLIBS += -lbfd -lopcodes -liberty - FEATURE_CHECK_LDFLAGS-disassembler-four-args += -liberty -ldl - FEATURE_CHECK_LDFLAGS-disassembler-init-styled += -liberty -ldl else ifeq ($(feature-libbfd-liberty-z), 1) EXTLIBS += -lbfd -lopcodes -liberty -lz - FEATURE_CHECK_LDFLAGS-disassembler-four-args += -liberty -lz -ldl - FEATURE_CHECK_LDFLAGS-disassembler-init-styled += -liberty -lz -ldl endif endif $(call feature_check,disassembler-four-args) @@ -1356,7 +1349,7 @@ endif # re-generate FEATURE-DUMP as we may have called feature_check, found out # extra libraries to add to LDFLAGS of some other test and then redo those -# tests, see the block about libbfd, disassembler-four-args, for instance. +# tests. $(shell rm -f $(FEATURE_DUMP_FILENAME)) $(foreach feat,$(FEATURE_TESTS),$(shell echo "$(call feature_assign,$(feat))" >> $(FEATURE_DUMP_FILENAME))) -- cgit v1.2.3 From 73f8ec5992d17a5431b7a2d123097981dbaa4769 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Tue, 9 Aug 2022 16:23:53 -0300 Subject: Revert "perf build: Suppress openssl v3 deprecation warnings in libcrypto feature test" This reverts commit 10fef869a58e37ec649b61eddab545f2da57a79b. Because a proper fix was submitted. Signed-off-by: Arnaldo Carvalho de Melo --- tools/build/feature/test-libcrypto.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/tools/build/feature/test-libcrypto.c b/tools/build/feature/test-libcrypto.c index 31afff093d0b..a98174e0569c 100644 --- a/tools/build/feature/test-libcrypto.c +++ b/tools/build/feature/test-libcrypto.c @@ -2,12 +2,6 @@ #include #include -/* - * The MD5_* API have been deprecated since OpenSSL 3.0, which causes the - * feature test to fail silently. This is a workaround. - */ -#pragma GCC diagnostic ignored "-Wdeprecated-declarations" - int main(void) { MD5_CTX context; -- cgit v1.2.3 From 5b245985a6de5ac18b5088c37068816d413fb8ed Mon Sep 17 00:00:00 2001 From: Roberto Sassu Date: Tue, 19 Jul 2022 19:05:55 +0200 Subject: tools build: Switch to new openssl API for test-libcrypto Switch to new EVP API for detecting libcrypto, as Fedora 36 returns an error when it encounters the deprecated function MD5_Init() and the others. The error would be interpreted as missing libcrypto, while in reality it is not. Fixes: 6e8ccb4f624a73c5 ("tools/bpf: properly account for libbfd variations") Signed-off-by: Roberto Sassu Cc: Alexei Starovoitov Cc: Andrii Nakryiko Cc: bpf@vger.kernel.org Cc: Daniel Borkmann Cc: Ingo Molnar Cc: John Fastabend Cc: KP Singh Cc: llvm@lists.linux.dev Cc: Martin KaFai Lau Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Nick Terrell Cc: Peter Zijlstra Cc: Quentin Monnet Cc: Song Liu Cc: Stanislav Fomichev Link: https://lore.kernel.org/r/20220719170555.2576993-4-roberto.sassu@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/build/feature/test-libcrypto.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/tools/build/feature/test-libcrypto.c b/tools/build/feature/test-libcrypto.c index a98174e0569c..bc34a5bbb504 100644 --- a/tools/build/feature/test-libcrypto.c +++ b/tools/build/feature/test-libcrypto.c @@ -1,16 +1,23 @@ // SPDX-License-Identifier: GPL-2.0 +#include #include #include int main(void) { - MD5_CTX context; + EVP_MD_CTX *mdctx; unsigned char md[MD5_DIGEST_LENGTH + SHA_DIGEST_LENGTH]; unsigned char dat[] = "12345"; + unsigned int digest_len; - MD5_Init(&context); - MD5_Update(&context, &dat[0], sizeof(dat)); - MD5_Final(&md[0], &context); + mdctx = EVP_MD_CTX_new(); + if (!mdctx) + return 0; + + EVP_DigestInit_ex(mdctx, EVP_md5(), NULL); + EVP_DigestUpdate(mdctx, &dat[0], sizeof(dat)); + EVP_DigestFinal_ex(mdctx, &md[0], &digest_len); + EVP_MD_CTX_free(mdctx); SHA1(&dat[0], sizeof(dat), &md[0]); -- cgit v1.2.3 From e1e19d0545563f6684a68adc1995c6307105b19f Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 4 Aug 2022 15:18:00 -0700 Subject: perf jevents: Clean up pytype warnings Improve type hints to clean up pytype warnings. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Stephane Eranian Cc: Will Deacon Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Link: http://lore.kernel.org/lkml/20220804221816.1802790-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/jevents.py | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index 83e0dcbeac9a..5b72048d50da 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -6,8 +6,7 @@ import csv import json import os import sys -from typing import Callable -from typing import Sequence +from typing import (Callable, Optional, Sequence) # Global command line arguments. _args = None @@ -57,7 +56,7 @@ class JsonEvent: '. '), '.').replace('\n', '\\n').replace( '\"', '\\"').replace('\r', '\\r') - def convert_aggr_mode(aggr_mode: str) -> str: + def convert_aggr_mode(aggr_mode: str) -> Optional[str]: """Returns the aggr_mode_class enum value associated with the JSON string.""" if not aggr_mode: return None @@ -67,7 +66,7 @@ class JsonEvent: } return aggr_mode_to_enum[aggr_mode] - def lookup_msr(num: str) -> str: + def lookup_msr(num: str) -> Optional[str]: """Converts the msr number, or first in a list to the appropriate event field.""" if not num: return None @@ -79,7 +78,7 @@ class JsonEvent: } return msrmap[int(num.split(',', 1)[0], 0)] - def real_event(name: str, event: str) -> str: + def real_event(name: str, event: str) -> Optional[str]: """Convert well known event names to an event string otherwise use the event argument.""" fixed = { 'inst_retired.any': 'event=0xc0,period=2000003', @@ -95,7 +94,7 @@ class JsonEvent: return fixed[name.lower()] return event - def unit_to_pmu(unit: str) -> str: + def unit_to_pmu(unit: str) -> Optional[str]: """Convert a JSON Unit to Linux PMU name.""" if not unit: return None @@ -154,7 +153,7 @@ class JsonEvent: if self.metric_expr: self.metric_expr = self.metric_expr.replace('\\', '\\\\') arch_std = jd.get('ArchStdEvent') - if precise and self.desc and not '(Precise Event)' in self.desc: + if precise and self.desc and '(Precise Event)' not in self.desc: extra_desc += ' (Must be precise)' if precise == '2' else (' (Precise ' 'event)') event = f'config={llx(configcode)}' if configcode is not None else f'event={llx(eventcode)}' -- cgit v1.2.3 From 46acb311c6c6b47b2b1e43fb13a09beb70f870eb Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 4 Aug 2022 15:18:01 -0700 Subject: perf jevents: Simplify generation of C-string Previous implementation wanted variable order and '(null)' string output to match the C implementation. The '(null)' string output was a quirk/bug and so there is no need to carry it forward. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Stephane Eranian Cc: Will Deacon Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Link: http://lore.kernel.org/lkml/20220804221816.1802790-3-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/jevents.py | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index 5b72048d50da..cdfa4e0e7557 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -203,7 +203,7 @@ class JsonEvent: """Representation of the event as a C struct initializer.""" def attr_string(attr: str, value: str) -> str: - return '\t.%s = \"%s\",\n' % (attr, value) + return f'\t.{attr} = \"{value}\",\n' def str_if_present(self, attr: str) -> str: if not getattr(self, attr): @@ -211,17 +211,11 @@ class JsonEvent: return attr_string(attr, getattr(self, attr)) s = '{\n' - for attr in ['name', 'event']: - s += str_if_present(self, attr) - if self.desc is not None: - s += attr_string('desc', self.desc) - else: - s += attr_string('desc', '(null)') - s += str_if_present(self, 'compat') s += f'\t.topic = "{topic_local}",\n' for attr in [ - 'long_desc', 'pmu', 'unit', 'perpkg', 'aggr_mode', 'metric_expr', - 'metric_name', 'metric_group', 'deprecated', 'metric_constraint' + 'aggr_mode', 'compat', 'deprecated', 'desc', 'event', 'long_desc', + 'metric_constraint', 'metric_expr', 'metric_group', 'metric_name', + 'name', 'perpkg', 'pmu', 'unit' ]: s += str_if_present(self, attr) s += '},\n' -- cgit v1.2.3 From b4f0466082fc073507bd1a52f560b718f4b26a5a Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 4 Aug 2022 15:18:02 -0700 Subject: perf jevents: Add JEVENTS_ARCH make option Allow the architecture built into pmu-events.c to be set on the make command line with JEVENTS_ARCH. Reviewed-by: John Garry Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: James Clark Cc: Jiri Olsa Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Stephane Eranian Cc: Will Deacon Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Link: http://lore.kernel.org/lkml/20220804221816.1802790-4-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/Build | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/Build b/tools/perf/pmu-events/Build index 28a9d01b08af..04ef95174660 100644 --- a/tools/perf/pmu-events/Build +++ b/tools/perf/pmu-events/Build @@ -7,6 +7,10 @@ JSON_TEST = $(shell [ -d $(JDIR_TEST) ] && \ find $(JDIR_TEST) -name '*.json') JEVENTS_PY = pmu-events/jevents.py +ifeq ($(JEVENTS_ARCH),) +JEVENTS_ARCH=$(SRCARCH) +endif + # # Locate/process JSON files in pmu-events/arch/ # directory and create tables in pmu-events.c. @@ -19,5 +23,5 @@ $(OUTPUT)pmu-events/pmu-events.c: pmu-events/empty-pmu-events.c else $(OUTPUT)pmu-events/pmu-events.c: $(JSON) $(JSON_TEST) $(JEVENTS_PY) $(call rule_mkdir) - $(Q)$(call echo-cmd,gen)$(PYTHON) $(JEVENTS_PY) $(SRCARCH) pmu-events/arch $@ + $(Q)$(call echo-cmd,gen)$(PYTHON) $(JEVENTS_PY) $(JEVENTS_ARCH) pmu-events/arch $@ endif -- cgit v1.2.3 From 2c98bacfd7a7d6d8b7ff3ce24264cb142306e591 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 4 Aug 2022 18:38:54 -0700 Subject: perf vendor events: Remove bad broadwellde uncore events The event converter scripts at: https://github.com/intel/event-converter-for-linux-perf passes Filter values from data on 01.org that is bogus in a perf command line and can cause perf to infinitely recurse in parse events. Remove such events or filters using the updated patch: https://github.com/intel/event-converter-for-linux-perf/pull/15/commits/afd779df99ee41aac646eae1ae5ae651cda3394d Fixes: ef908a192512bf45 ("perf vendor events: Update Intel broadwellde") Reviewed-by: Kan Liang Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Andi Kleen Cc: Caleb Biggers Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kshipra Bopardikar Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20220805013856.1842878-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/broadwellde/uncore-cache.json | 97 ---------------------- .../arch/x86/broadwellde/uncore-other.json | 13 --- 2 files changed, 110 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json index caadbca1b15b..c4d154944ab6 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json @@ -37,7 +37,6 @@ "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.ANY", - "Filter": "CBoFilter0[23:17]", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", "UMask": "0x11", @@ -48,7 +47,6 @@ "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.DATA_READ", - "Filter": "CBoFilter0[23:17]", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions", "UMask": "0x3", @@ -59,7 +57,6 @@ "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.NID", - "Filter": "CBoFilter0[23:17]", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x41", @@ -70,7 +67,6 @@ "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.READ", - "Filter": "CBoFilter0[22:18]", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions", "UMask": "0x21", @@ -81,7 +77,6 @@ "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP", - "Filter": "CBoFilter0[23:17]", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.", "UMask": "0x9", @@ -92,7 +87,6 @@ "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.WRITE", - "Filter": "CBoFilter0[23:17]", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cachable and UC.", "UMask": "0x5", @@ -153,7 +147,6 @@ "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.NID", - "Filter": "CBoFilter1[17:10]", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x40", @@ -794,7 +787,6 @@ "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_C_RxR_IPQ_RETRY2.TARGET", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.", "UMask": "0x40", @@ -845,7 +837,6 @@ "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.NID", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.", "UMask": "0x40", @@ -896,7 +887,6 @@ "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_C_RxR_IRQ_RETRY2.TARGET", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.", "UMask": "0x40", @@ -937,7 +927,6 @@ "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.NID", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.", "UMask": "0x40", @@ -968,7 +957,6 @@ "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.", "UMask": "0x80", @@ -999,7 +987,6 @@ "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_C_RxR_ISMQ_RETRY2.TARGET", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the ISMQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.", "UMask": "0x40", @@ -1114,7 +1101,6 @@ "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory.", "UMask": "0x21", @@ -1135,7 +1121,6 @@ "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory.", "UMask": "0x23", @@ -1146,7 +1131,6 @@ "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "UMask": "0x3", @@ -1167,7 +1151,6 @@ "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by remote caches or remote memory.", "UMask": "0x83", @@ -1178,7 +1161,6 @@ "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_ALL", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x48", @@ -1189,7 +1171,6 @@ "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction transactions inserted into the TOR.", "UMask": "0x44", @@ -1200,7 +1181,6 @@ "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.", "UMask": "0x4A", @@ -1211,7 +1191,6 @@ "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE", - "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode.", "UMask": "0x43", @@ -1222,7 +1201,6 @@ "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE", - "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode.", "UMask": "0x41", @@ -1233,7 +1211,6 @@ "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_WB", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transactions inserted into the TOR.", "UMask": "0x50", @@ -1244,7 +1221,6 @@ "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "UMask": "0x1", @@ -1265,7 +1241,6 @@ "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisifed by an opcode, inserted into the TOR that are satisifed by remote caches or remote memory.", "UMask": "0x81", @@ -1312,7 +1287,6 @@ "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisifed by an opcode, in the TOR that are satisifed by locally HOMed memory.", "UMask": "0x21", @@ -1340,7 +1314,6 @@ "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcode Matched", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by locally HOMed memory.", "UMask": "0x23", @@ -1350,7 +1323,6 @@ "BriefDescription": "TOR Occupancy; Miss Opcode Match", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.", "UMask": "0x3", @@ -1369,7 +1341,6 @@ "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opcode Matched", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by remote caches or remote memory.", "UMask": "0x83", @@ -1379,7 +1350,6 @@ "BriefDescription": "TOR Occupancy; NID Matched", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NID matched outstanding requests in the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x48", @@ -1389,7 +1359,6 @@ "BriefDescription": "TOR Occupancy; NID Matched Evictions", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding NID matched eviction transactions in the TOR .", "UMask": "0x44", @@ -1399,7 +1368,6 @@ "BriefDescription": "TOR Occupancy; NID Matched", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID.", "UMask": "0x4A", @@ -1409,7 +1377,6 @@ "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE", - "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID and an opcode.", "UMask": "0x43", @@ -1419,7 +1386,6 @@ "BriefDescription": "TOR Occupancy; NID and Opcode Matched", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE", - "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match a NID and an opcode.", "UMask": "0x41", @@ -1429,7 +1395,6 @@ "BriefDescription": "TOR Occupancy; NID Matched Writebacks", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched write transactions int the TOR.", "UMask": "0x50", @@ -1439,7 +1404,6 @@ "BriefDescription": "TOR Occupancy; Opcode Match", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc).", "UMask": "0x1", @@ -1458,7 +1422,6 @@ "BriefDescription": "TOR Occupancy; Remote Memory - Opcode Matched", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisifed by an opcode, in the TOR that are satisifed by remote caches or remote memory.", "UMask": "0x81", @@ -1610,66 +1573,6 @@ "UMask": "0x8", "Unit": "CBO" }, - { - "BriefDescription": "QPI Address/Opcode Match; AD Opcodes", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_H_ADDR_OPC_MATCH.AD", - "Filter": "HA_OpcodeMatch[5:0]", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "HA" - }, - { - "BriefDescription": "QPI Address/Opcode Match; Address", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_H_ADDR_OPC_MATCH.ADDR", - "Filter": "HA_AddrMatch0[31:6], HA_AddrMatch1[13:0]", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "HA" - }, - { - "BriefDescription": "QPI Address/Opcode Match; AK Opcodes", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_H_ADDR_OPC_MATCH.AK", - "Filter": "HA_OpcodeMatch[5:0]", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "HA" - }, - { - "BriefDescription": "QPI Address/Opcode Match; BL Opcodes", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_H_ADDR_OPC_MATCH.BL", - "Filter": "HA_OpcodeMatch[5:0]", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "HA" - }, - { - "BriefDescription": "QPI Address/Opcode Match; Address & Opcode Match", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_H_ADDR_OPC_MATCH.FILT", - "Filter": "HA_AddrMatch0[31:6], HA_AddrMatch1[13:0], HA_OpcodeMatch[5:0]", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "HA" - }, - { - "BriefDescription": "QPI Address/Opcode Match; Opcode", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_H_ADDR_OPC_MATCH.OPC", - "Filter": "HA_OpcodeMatch[5:0]", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "HA" - }, { "BriefDescription": "BT Cycles Not Empty", "Counter": "0,1,2,3", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json index 71bdf75d8016..fc7e0867fcc5 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json @@ -416,17 +416,6 @@ "UMask": "0x10", "Unit": "IRP" }, - { - "BriefDescription": "Inbound Transaction Count; Select Source", - "Counter": "0,1", - "EventCode": "0x16", - "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ", - "Filter": "IRPFilter[4:0]", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time. If this bit is not set, then requests from all sources will be counted.", - "UMask": "0x40", - "Unit": "IRP" - }, { "BriefDescription": "Inbound Transaction Count; Other", "Counter": "0,1", @@ -1117,7 +1106,6 @@ "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.ENABLE", - "Filter": "UBoxFilter[3:0]", "PerPkg": "1", "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", "UMask": "0x1", @@ -1138,7 +1126,6 @@ "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE", - "Filter": "UBoxFilter[3:0]", "PerPkg": "1", "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", "UMask": "0x4", -- cgit v1.2.3 From 22de36ff2cf16f1ebaa93fc6eb483c65cc79c856 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 4 Aug 2022 18:38:55 -0700 Subject: perf vendor events: Remove bad ivytown uncore events The event converter scripts at: https://github.com/intel/event-converter-for-linux-perf passes Filter values from data on 01.org that is bogus in a perf command line and can cause perf to infinitely recurse in parse events. Remove such events or filters using the updated patch: https://github.com/intel/event-converter-for-linux-perf/pull/15/commits/afd779df99ee41aac646eae1ae5ae651cda3394d Fixes: 6220136831e34615 ("perf vendor events: Update Intel ivytown") Reviewed-by: Kan Liang Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Andi Kleen Cc: Caleb Biggers Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kshipra Bopardikar Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20220805013856.1842878-3-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/ivytown/uncore-cache.json | 90 ---------------------- .../arch/x86/ivytown/uncore-interconnect.json | 1 - .../pmu-events/arch/x86/ivytown/uncore-other.json | 13 ---- .../pmu-events/arch/x86/ivytown/uncore-power.json | 19 ----- 4 files changed, 123 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json b/tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json index 1e53bee8af5c..93e07385eeec 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json @@ -20,7 +20,6 @@ "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.ANY", - "Filter": "CBoFilter0[23:17]", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", "UMask": "0x11", @@ -31,7 +30,6 @@ "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.DATA_READ", - "Filter": "CBoFilter0[23:17]", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Read transactions", "UMask": "0x3", @@ -42,7 +40,6 @@ "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.NID", - "Filter": "CBoFilter0[23:17]", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x41", @@ -53,7 +50,6 @@ "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP", - "Filter": "CBoFilter0[23:17]", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.", "UMask": "0x9", @@ -64,7 +60,6 @@ "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.WRITE", - "Filter": "CBoFilter0[23:17]", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cachable and UC.", "UMask": "0x5", @@ -105,7 +100,6 @@ "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.NID", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x40", @@ -1034,7 +1028,6 @@ "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory.", "UMask": "0x21", @@ -1055,7 +1048,6 @@ "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory.", "UMask": "0x23", @@ -1066,7 +1058,6 @@ "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "UMask": "0x3", @@ -1087,7 +1078,6 @@ "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by remote caches or remote memory.", "UMask": "0x83", @@ -1098,7 +1088,6 @@ "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_ALL", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x48", @@ -1109,7 +1098,6 @@ "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction transactions inserted into the TOR.", "UMask": "0x44", @@ -1120,7 +1108,6 @@ "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.", "UMask": "0x4A", @@ -1131,7 +1118,6 @@ "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE", - "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode.", "UMask": "0x43", @@ -1142,7 +1128,6 @@ "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE", - "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode.", "UMask": "0x41", @@ -1153,7 +1138,6 @@ "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_WB", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transactions inserted into the TOR.", "UMask": "0x50", @@ -1164,7 +1148,6 @@ "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "UMask": "0x1", @@ -1185,7 +1168,6 @@ "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisifed by an opcode, inserted into the TOR that are satisifed by remote caches or remote memory.", "UMask": "0x81", @@ -1232,7 +1214,6 @@ "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisifed by an opcode, in the TOR that are satisifed by locally HOMed memory.", "UMask": "0x21", @@ -1260,7 +1241,6 @@ "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcode Matched", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by locally HOMed memory.", "UMask": "0x23", @@ -1270,7 +1250,6 @@ "BriefDescription": "TOR Occupancy; Miss Opcode Match", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.", "UMask": "0x3", @@ -1289,7 +1268,6 @@ "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opcode Matched", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by remote caches or remote memory.", "UMask": "0x83", @@ -1299,7 +1277,6 @@ "BriefDescription": "TOR Occupancy; NID Matched", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NID matched outstanding requests in the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x48", @@ -1309,7 +1286,6 @@ "BriefDescription": "TOR Occupancy; NID Matched Evictions", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding NID matched eviction transactions in the TOR .", "UMask": "0x44", @@ -1319,7 +1295,6 @@ "BriefDescription": "TOR Occupancy; NID Matched", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID.", "UMask": "0x4A", @@ -1329,7 +1304,6 @@ "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE", - "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID and an opcode.", "UMask": "0x43", @@ -1339,7 +1313,6 @@ "BriefDescription": "TOR Occupancy; NID and Opcode Matched", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE", - "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match a NID and an opcode.", "UMask": "0x41", @@ -1349,7 +1322,6 @@ "BriefDescription": "TOR Occupancy; NID Matched Writebacks", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB", - "Filter": "CBoFilter1[15:0]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched write transactions int the TOR.", "UMask": "0x50", @@ -1359,7 +1331,6 @@ "BriefDescription": "TOR Occupancy; Opcode Match", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc).", "UMask": "0x1", @@ -1378,7 +1349,6 @@ "BriefDescription": "TOR Occupancy; Remote Memory - Opcode Matched", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE", - "Filter": "CBoFilter1[28:20]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisifed by an opcode, in the TOR that are satisifed by remote caches or remote memory.", "UMask": "0x81", @@ -1520,66 +1490,6 @@ "UMask": "0x8", "Unit": "CBO" }, - { - "BriefDescription": "QPI Address/Opcode Match; AD Opcodes", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_H_ADDR_OPC_MATCH.AD", - "Filter": "HA_OpcodeMatch[5:0]", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "HA" - }, - { - "BriefDescription": "QPI Address/Opcode Match; Address", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_H_ADDR_OPC_MATCH.ADDR", - "Filter": "HA_AddrMatch0[31:6], HA_AddrMatch1[13:0]", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "HA" - }, - { - "BriefDescription": "QPI Address/Opcode Match; AK Opcodes", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_H_ADDR_OPC_MATCH.AK", - "Filter": "HA_OpcodeMatch[5:0]", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "HA" - }, - { - "BriefDescription": "QPI Address/Opcode Match; BL Opcodes", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_H_ADDR_OPC_MATCH.BL", - "Filter": "HA_OpcodeMatch[5:0]", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "HA" - }, - { - "BriefDescription": "QPI Address/Opcode Match; Address & Opcode Match", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_H_ADDR_OPC_MATCH.FILT", - "Filter": "HA_AddrMatch0[31:6], HA_AddrMatch1[13:0], HA_OpcodeMatch[5:0]", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "HA" - }, - { - "BriefDescription": "QPI Address/Opcode Match; Opcode", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_H_ADDR_OPC_MATCH.OPC", - "Filter": "HA_OpcodeMatch[5:0]", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "HA" - }, { "BriefDescription": "BT Bypass", "Counter": "0,1,2,3", diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json index b50685fbde12..b3b1a08d4acf 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json @@ -14,7 +14,6 @@ "EventCode": "0x38", "EventName": "UNC_Q_CTO_COUNT", "ExtSel": "1", - "Filter": "QPIMask0[17:0],QPIMatch0[17:0],QPIMask1[19:16],QPIMatch1[19:16]", "PerPkg": "1", "PublicDescription": "Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots. If both slots trigger in a given cycle, the event will increment by 2. You can use edge detect to count the number of cases when both events triggered.", "Unit": "QPI LL" diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-other.json b/tools/perf/pmu-events/arch/x86/ivytown/uncore-other.json index aa7a5059d79f..af289aa6c98e 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-other.json @@ -247,17 +247,6 @@ "UMask": "0x2", "Unit": "IRP" }, - { - "BriefDescription": "Inbound Transaction Count; Select Source", - "Counter": "0,1", - "EventCode": "0x15", - "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ", - "Filter": "IRPFilter[4:0]", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time. If this bit is not set, then requests from all sources will be counted.", - "UMask": "0x8", - "Unit": "IRP" - }, { "BriefDescription": "Inbound Transaction Count: Read Prefetches", "Counter": "0,1", @@ -2274,7 +2263,6 @@ "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.ENABLE", - "Filter": "UBoxFilter[3:0]", "PerPkg": "1", "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", "UMask": "0x1", @@ -2295,7 +2283,6 @@ "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE", - "Filter": "UBoxFilter[3:0]", "PerPkg": "1", "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", "UMask": "0x4", diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-power.json b/tools/perf/pmu-events/arch/x86/ivytown/uncore-power.json index 304d861c368f..0ba63a97ddfa 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-power.json @@ -297,7 +297,6 @@ "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_P_DEMOTIONS_CORE0", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion", "Unit": "PCU" @@ -307,7 +306,6 @@ "Counter": "0,1,2,3", "EventCode": "0x1f", "EventName": "UNC_P_DEMOTIONS_CORE1", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion", "Unit": "PCU" @@ -317,7 +315,6 @@ "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_P_DEMOTIONS_CORE10", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion", "Unit": "PCU" @@ -327,7 +324,6 @@ "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_P_DEMOTIONS_CORE11", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion", "Unit": "PCU" @@ -337,7 +333,6 @@ "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_P_DEMOTIONS_CORE12", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion", "Unit": "PCU" @@ -347,7 +342,6 @@ "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_P_DEMOTIONS_CORE13", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion", "Unit": "PCU" @@ -357,7 +351,6 @@ "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_P_DEMOTIONS_CORE14", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion", "Unit": "PCU" @@ -367,7 +360,6 @@ "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_P_DEMOTIONS_CORE2", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion", "Unit": "PCU" @@ -377,7 +369,6 @@ "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_P_DEMOTIONS_CORE3", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion", "Unit": "PCU" @@ -387,7 +378,6 @@ "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_P_DEMOTIONS_CORE4", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion", "Unit": "PCU" @@ -397,7 +387,6 @@ "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_P_DEMOTIONS_CORE5", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion", "Unit": "PCU" @@ -407,7 +396,6 @@ "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_P_DEMOTIONS_CORE6", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion", "Unit": "PCU" @@ -417,7 +405,6 @@ "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_P_DEMOTIONS_CORE7", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion", "Unit": "PCU" @@ -427,7 +414,6 @@ "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_P_DEMOTIONS_CORE8", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion", "Unit": "PCU" @@ -437,7 +423,6 @@ "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_P_DEMOTIONS_CORE9", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion", "Unit": "PCU" @@ -447,7 +432,6 @@ "Counter": "0,1,2,3", "EventCode": "0xb", "EventName": "UNC_P_FREQ_BAND0_CYCLES", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.", "Unit": "PCU" @@ -457,7 +441,6 @@ "Counter": "0,1,2,3", "EventCode": "0xc", "EventName": "UNC_P_FREQ_BAND1_CYCLES", - "Filter": "PCUFilter[15:8]", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.", "Unit": "PCU" @@ -467,7 +450,6 @@ "Counter": "0,1,2,3", "EventCode": "0xd", "EventName": "UNC_P_FREQ_BAND2_CYCLES", - "Filter": "PCUFilter[23:16]", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.", "Unit": "PCU" @@ -477,7 +459,6 @@ "Counter": "0,1,2,3", "EventCode": "0xe", "EventName": "UNC_P_FREQ_BAND3_CYCLES", - "Filter": "PCUFilter[31:24]", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.", "Unit": "PCU" -- cgit v1.2.3 From b48ddbbb99986de85878a34c23ecebac22a59b79 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 4 Aug 2022 18:38:56 -0700 Subject: perf vendor events: Remove bad jaketown uncore events The event converter scripts at: https://github.com/intel/event-converter-for-linux-perf passes Filter values from data on 01.org that is bogus in a perf command line and can cause perf to infinitely recurse in parse events. Remove such events or filters using the updated patch: https://github.com/intel/event-converter-for-linux-perf/pull/15/commits/afd779df99ee41aac646eae1ae5ae651cda3394d Fixes: 376d8b581b7639c9 ("perf vendor events: Update Intel jaketown") Reviewed-by: Kan Liang Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Andi Kleen Cc: Caleb Biggers Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kshipra Bopardikar Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20220805013856.1842878-4-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/jaketown/uncore-cache.json | 30 ---------------------- .../pmu-events/arch/x86/jaketown/uncore-other.json | 13 ---------- .../pmu-events/arch/x86/jaketown/uncore-power.json | 11 -------- 3 files changed, 54 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json index cf28ffa778ba..351f8b040ed1 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json @@ -20,7 +20,6 @@ "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.DATA_READ", - "Filter": "CBoFilter[22:18]", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.", "UMask": "0x3", @@ -31,7 +30,6 @@ "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.NID", - "Filter": "CBoFilter[22:18], CBoFilter[17:10]", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.", "UMask": "0x41", @@ -42,7 +40,6 @@ "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP", - "Filter": "CBoFilter[22:18]", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.", "UMask": "0x9", @@ -53,7 +50,6 @@ "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.WRITE", - "Filter": "CBoFilter[22:18]", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.", "UMask": "0x5", @@ -94,7 +90,6 @@ "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.NID", - "Filter": "CBoFilter[17:10]", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x40", @@ -613,7 +608,6 @@ "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", - "Filter": "CBoFilter[31:23]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x3", @@ -624,7 +618,6 @@ "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_ALL", - "Filter": "CBoFilter[17:10]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x48", @@ -635,7 +628,6 @@ "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION", - "Filter": "CBoFilter[17:10]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x44", @@ -646,7 +638,6 @@ "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL", - "Filter": "CBoFilter[17:10]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x4a", @@ -657,7 +648,6 @@ "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE", - "Filter": "CBoFilter[31:23], CBoFilter[17:10]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x43", @@ -668,7 +658,6 @@ "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE", - "Filter": "CBoFilter[31:23], CBoFilter[17:10]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x41", @@ -679,7 +668,6 @@ "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_WB", - "Filter": "CBoFilter[17:10]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x50", @@ -690,7 +678,6 @@ "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.OPCODE", - "Filter": "CBoFilter[31:23]", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x1", @@ -737,7 +724,6 @@ "BriefDescription": "TOR Occupancy; Miss Opcode Match", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE", - "Filter": "CBoFilter[31:23]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x3", @@ -747,7 +733,6 @@ "BriefDescription": "TOR Occupancy; NID Matched", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL", - "Filter": "CBoFilter[17:10]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x48", @@ -757,7 +742,6 @@ "BriefDescription": "TOR Occupancy; NID Matched Evictions", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION", - "Filter": "CBoFilter[17:10]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x44", @@ -767,7 +751,6 @@ "BriefDescription": "TOR Occupancy; NID Matched", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL", - "Filter": "CBoFilter[17:10]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x4a", @@ -777,7 +760,6 @@ "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE", - "Filter": "CBoFilter[31:23], CBoFilter[17:10]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x43", @@ -787,7 +769,6 @@ "BriefDescription": "TOR Occupancy; NID and Opcode Matched", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE", - "Filter": "CBoFilter[31:23], CBoFilter[17:10]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x41", @@ -797,7 +778,6 @@ "BriefDescription": "TOR Occupancy; Opcode Match", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE", - "Filter": "CBoFilter[31:23]", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x1", @@ -893,16 +873,6 @@ "UMask": "0x4", "Unit": "CBO" }, - { - "BriefDescription": "QPI Address/Opcode Match; Address & Opcode Match", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_H_ADDR_OPC_MATCH.FILT", - "Filter": "HA_AddrMatch0[31:6], HA_AddrMatch1[13:0], HA_OpcodeMatch[5:0]", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "HA" - }, { "BriefDescription": "HA to iMC Bypass; Not Taken", "Counter": "0,1,2,3", diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json index 99fc673c59e9..588549a668bd 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json @@ -247,17 +247,6 @@ "UMask": "0x2", "Unit": "IRP" }, - { - "BriefDescription": "Inbound Transaction Count; Select Source", - "Counter": "0,1", - "EventCode": "0x15", - "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ", - "Filter": "IRPFilter[4:0]", - "PerPkg": "1", - "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.", - "UMask": "0x8", - "Unit": "IRP" - }, { "BriefDescription": "Inbound Transaction Count; Read Prefetches", "Counter": "0,1", @@ -1378,7 +1367,6 @@ "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.ENABLE", - "Filter": "UBoxFilter[3:0]", "PerPkg": "1", "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", "UMask": "0x1", @@ -1399,7 +1387,6 @@ "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE", - "Filter": "UBoxFilter[3:0]", "PerPkg": "1", "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", "UMask": "0x4", diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json index 04228344cb9c..817ea6d7f785 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json @@ -92,7 +92,6 @@ "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_P_DEMOTIONS_CORE0", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion", "Unit": "PCU" @@ -102,7 +101,6 @@ "Counter": "0,1,2,3", "EventCode": "0x1f", "EventName": "UNC_P_DEMOTIONS_CORE1", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion", "Unit": "PCU" @@ -121,7 +119,6 @@ "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_P_DEMOTIONS_CORE3", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion", "Unit": "PCU" @@ -131,7 +128,6 @@ "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_P_DEMOTIONS_CORE4", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion", "Unit": "PCU" @@ -141,7 +137,6 @@ "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_P_DEMOTIONS_CORE5", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion", "Unit": "PCU" @@ -151,7 +146,6 @@ "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_P_DEMOTIONS_CORE6", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion", "Unit": "PCU" @@ -161,7 +155,6 @@ "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_P_DEMOTIONS_CORE7", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion", "Unit": "PCU" @@ -171,7 +164,6 @@ "Counter": "0,1,2,3", "EventCode": "0xb", "EventName": "UNC_P_FREQ_BAND0_CYCLES", - "Filter": "PCUFilter[7:0]", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.", "Unit": "PCU" @@ -181,7 +173,6 @@ "Counter": "0,1,2,3", "EventCode": "0xc", "EventName": "UNC_P_FREQ_BAND1_CYCLES", - "Filter": "PCUFilter[15:8]", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.", "Unit": "PCU" @@ -191,7 +182,6 @@ "Counter": "0,1,2,3", "EventCode": "0xd", "EventName": "UNC_P_FREQ_BAND2_CYCLES", - "Filter": "PCUFilter[23:16]", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.", "Unit": "PCU" @@ -201,7 +191,6 @@ "Counter": "0,1,2,3", "EventCode": "0xe", "EventName": "UNC_P_FREQ_BAND3_CYCLES", - "Filter": "PCUFilter[31:24]", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.", "Unit": "PCU" -- cgit v1.2.3 From e0b23af82d6f454c0bad6fb48d378e0099069b44 Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Thu, 4 Aug 2022 09:52:21 +0200 Subject: perf list: Add PMU pai_crypto event description for IBM z16 Add the event description for the IBM z16 pai_crypto PMU released with commit 1bf54f32f525 ("s390/pai: Add support for cryptography counters") The document SA22-7832-13 "z/Architecture Principles of Operation", published May, 2022, contains the description of the Processor Activity Instrumentation Facility and the cryptography counter set., See Pages 5-110 to 5-113. Patch reworked to fit for the converted jevents processing. Committer notes: Couldn't find 1bf54f32f525 ("s390/pai: Add support for cryptography counters") in torvalds/master, in what tree is that cset? Signed-off-by: Thomas Richter Acked-by: Sumanth Korikkar Cc: Heiko Carstens Cc: Sven Schnelle Cc: Vasily Gorbik Link: https://lore.kernel.org/r/20220804075221.1132849-1-tmricht@linux.ibm.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/s390/cf_z16/pai.json | 1101 +++++++++++++++++++++++ tools/perf/pmu-events/jevents.py | 1 + 2 files changed, 1102 insertions(+) create mode 100644 tools/perf/pmu-events/arch/s390/cf_z16/pai.json diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/pai.json b/tools/perf/pmu-events/arch/s390/cf_z16/pai.json new file mode 100644 index 000000000000..cf8563d059b9 --- /dev/null +++ b/tools/perf/pmu-events/arch/s390/cf_z16/pai.json @@ -0,0 +1,1101 @@ +[ + { + "Unit": "PAI-CRYPTO", + "EventCode": "4096", + "EventName": "CRYPTO_ALL", + "BriefDescription": "CRYPTO ALL", + "PublicDescription": "Sums of all non zero cryptography counters" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4097", + "EventName": "KM_DEA", + "BriefDescription": "KM DEA", + "PublicDescription": "KM-DEA function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4098", + "EventName": "KM_TDEA_128", + "BriefDescription": "KM TDEA 128", + "PublicDescription": "KM-TDEA-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4099", + "EventName": "KM_TDEA_192", + "BriefDescription": "KM TDEA 192", + "PublicDescription": "KM-TDEA-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4100", + "EventName": "KM_ENCRYPTED_DEA", + "BriefDescription": "KM ENCRYPTED DEA", + "PublicDescription": "KM-Encrypted-DEA function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4101", + "EventName": "KM_ENCRYPTED_TDEA_128", + "BriefDescription": "KM ENCRYPTED TDEA 128", + "PublicDescription": "KM-Encrypted-TDEA-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4102", + "EventName": "KM_ENCRYPTED_TDEA_192", + "BriefDescription": "KM ENCRYPTED TDEA 192", + "PublicDescription": "KM-Encrypted-TDEA-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4103", + "EventName": "KM_AES_128", + "BriefDescription": "KM AES 128", + "PublicDescription": "KM-AES-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4104", + "EventName": "KM_AES_192", + "BriefDescription": "KM AES 192", + "PublicDescription": "KM-AES-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4105", + "EventName": "KM_AES_256", + "BriefDescription": "KM AES 256", + "PublicDescription": "KM-AES-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4106", + "EventName": "KM_ENCRYPTED_AES_128", + "BriefDescription": "KM ENCRYPTED AES 128", + "PublicDescription": "KM-Encrypted-AES-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4107", + "EventName": "KM_ENCRYPTED_AES_192", + "BriefDescription": "KM ENCRYPTED AES 192", + "PublicDescription": "KM-Encrypted-AES-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4108", + "EventName": "KM_ENCRYPTED_AES_256", + "BriefDescription": "KM ENCRYPTED AES 256", + "PublicDescription": "KM-Encrypted-AES-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4109", + "EventName": "KM_XTS_AES_128", + "BriefDescription": "KM XTS AES 128", + "PublicDescription": "KM-XTS-AES-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4110", + "EventName": "KM_XTS_AES_256", + "BriefDescription": "KM XTS AES 256", + "PublicDescription": "KM-XTS-AES-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4111", + "EventName": "KM_XTS_ENCRYPTED_AES_128", + "BriefDescription": "KM XTS ENCRYPTED AES 128", + "PublicDescription": "KM-XTS-Encrypted-AES-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4112", + "EventName": "KM_XTS_ENCRYPTED_AES_256", + "BriefDescription": "KM XTS ENCRYPTED AES 256", + "PublicDescription": "KM-XTS-Encrypted-AES-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4113", + "EventName": "KMC_DEA", + "BriefDescription": "KMC DEA", + "PublicDescription": "KMC-DEA function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4114", + "EventName": "KMC_TDEA_128", + "BriefDescription": "KMC TDEA 128", + "PublicDescription": "KMC-TDEA-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4115", + "EventName": "KMC_TDEA_192", + "BriefDescription": "KMC TDEA 192", + "PublicDescription": "KMC-TDEA-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4116", + "EventName": "KMC_ENCRYPTED_DEA", + "BriefDescription": "KMC ENCRYPTED DEA", + "PublicDescription": "KMC-Encrypted-DEA function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4117", + "EventName": "KMC_ENCRYPTED_TDEA_128", + "BriefDescription": "KMC ENCRYPTED TDEA 128", + "PublicDescription": "KMC-Encrypted-TDEA-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4118", + "EventName": "KMC_ENCRYPTED_TDEA_192", + "BriefDescription": "KMC ENCRYPTED TDEA 192", + "PublicDescription": "KMC-Encrypted-TDEA-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4119", + "EventName": "KMC_AES_128", + "BriefDescription": "KMC AES 128", + "PublicDescription": "KMC-AES-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4120", + "EventName": "KMC_AES_192", + "BriefDescription": "KMC AES 192", + "PublicDescription": "KMC-AES-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4121", + "EventName": "KMC_AES_256", + "BriefDescription": "KMC AES 256", + "PublicDescription": "KMC-AES-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4122", + "EventName": "KMC_ENCRYPTED_AES_128", + "BriefDescription": "KMC ENCRYPTED AES 128", + "PublicDescription": "KMC-Encrypted-AES-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4123", + "EventName": "KMC_ENCRYPTED_AES_192", + "BriefDescription": "KMC ENCRYPTED AES 192", + "PublicDescription": "KMC-Encrypted-AES-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4124", + "EventName": "KMC_ENCRYPTED_AES_256", + "BriefDescription": "KMC ENCRYPTED AES 256", + "PublicDescription": "KMC-Encrypted-AES-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4125", + "EventName": "KMC_PRNG", + "BriefDescription": "KMC PRNG", + "PublicDescription": "KMC-PRNG function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4126", + "EventName": "KMA_GCM_AES_128", + "BriefDescription": "KMA GCM AES 128", + "PublicDescription": "KMA-GCM-AES-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4127", + "EventName": "KMA_GCM_AES_192", + "BriefDescription": "KMA GCM AES 192", + "PublicDescription": "KMA-GCM-AES-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4128", + "EventName": "KMA_GCM_AES_256", + "BriefDescription": "KMA GCM AES 256", + "PublicDescription": "KMA-GCM-AES-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4129", + "EventName": "KMA_GCM_ENCRYPTED_AES_128", + "BriefDescription": "KMA GCM ENCRYPTED AES 128", + "PublicDescription": "KMA-GCM-Encrypted-AES-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4130", + "EventName": "KMA_GCM_ENCRYPTED_AES_192", + "BriefDescription": "KMA GCM ENCRYPTED AES 192", + "PublicDescription": "KMA-GCM-Encrypted-AES-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4131", + "EventName": "KMA_GCM_ENCRYPTED_AES_256", + "BriefDescription": "KMA GCM ENCRYPTED AES 256", + "PublicDescription": "KMA-GCM-Encrypted-AES-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4132", + "EventName": "KMF_DEA", + "BriefDescription": "KMF DEA", + "PublicDescription": "KMF-DEA function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4133", + "EventName": "KMF_TDEA_128", + "BriefDescription": "KMF TDEA 128", + "PublicDescription": "KMF-TDEA-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4134", + "EventName": "KMF_TDEA_192", + "BriefDescription": "KMF TDEA 192", + "PublicDescription": "KMF-TDEA-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4135", + "EventName": "KMF_ENCRYPTED_DEA", + "BriefDescription": "KMF ENCRYPTED DEA", + "PublicDescription": "KMF-Encrypted-DEA function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4136", + "EventName": "KMF_ENCRYPTED_TDEA_128", + "BriefDescription": "KMF ENCRYPTED TDEA 128", + "PublicDescription": "KMF-Encrypted-TDEA-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4137", + "EventName": "KMF_ENCRYPTED_TDEA_192", + "BriefDescription": "KMF ENCRYPTED TDEA 192", + "PublicDescription": "KMF-Encrypted-TDEA-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4138", + "EventName": "KMF_AES_128", + "BriefDescription": "KMF AES 128", + "PublicDescription": "KMF-AES-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4139", + "EventName": "KMF_AES_192", + "BriefDescription": "KMF AES 192", + "PublicDescription": "KMF-AES-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4140", + "EventName": "KMF_AES_256", + "BriefDescription": "KMF AES 256", + "PublicDescription": "KMF-AES-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4141", + "EventName": "KMF_ENCRYPTED_AES_128", + "BriefDescription": "KMF ENCRYPTED AES 128", + "PublicDescription": "KMF-Encrypted-AES-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4142", + "EventName": "KMF_ENCRYPTED_AES_192", + "BriefDescription": "KMF ENCRYPTED AES 192", + "PublicDescription": "KMF-Encrypted-AES-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4143", + "EventName": "KMF_ENCRYPTED_AES_256", + "BriefDescription": "KMF ENCRYPTED AES 256", + "PublicDescription": "KMF-Encrypted-AES-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4144", + "EventName": "KMCTR_DEA", + "BriefDescription": "KMCTR DEA", + "PublicDescription": "KMCTR-DEA function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4145", + "EventName": "KMCTR_TDEA_128", + "BriefDescription": "KMCTR TDEA 128", + "PublicDescription": "KMCTR-TDEA-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4146", + "EventName": "KMCTR_TDEA_192", + "BriefDescription": "KMCTR TDEA 192", + "PublicDescription": "KMCTR-TDEA-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4147", + "EventName": "KMCTR_ENCRYPTED_DEA", + "BriefDescription": "KMCTR ENCRYPTED DEA", + "PublicDescription": "KMCTR-Encrypted-DEA function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4148", + "EventName": "KMCTR_ENCRYPTED_TDEA_128", + "BriefDescription": "KMCTR ENCRYPTED TDEA 128", + "PublicDescription": "KMCTR-Encrypted-TDEA-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4149", + "EventName": "KMCTR_ENCRYPTED_TDEA_192", + "BriefDescription": "KMCTR ENCRYPTED TDEA 192", + "PublicDescription": "KMCTR-Encrypted-TDEA-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4150", + "EventName": "KMCTR_AES_128", + "BriefDescription": "KMCTR AES 128", + "PublicDescription": "KMCTR-AES-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4151", + "EventName": "KMCTR_AES_192", + "BriefDescription": "KMCTR AES 192", + "PublicDescription": "KMCTR-AES-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4152", + "EventName": "KMCTR_AES_256", + "BriefDescription": "KMCTR AES 256", + "PublicDescription": "KMCTR-AES-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4153", + "EventName": "KMCTR_ENCRYPTED_AES_128", + "BriefDescription": "KMCTR ENCRYPTED AES 128", + "PublicDescription": "KMCTR-Encrypted-AES-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4154", + "EventName": "KMCTR_ENCRYPTED_AES_192", + "BriefDescription": "KMCTR ENCRYPTED AES 192", + "PublicDescription": "KMCTR-Encrypted-AES-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4155", + "EventName": "KMCTR_ENCRYPTED_AES_256", + "BriefDescription": "KMCTR ENCRYPTED AES 256", + "PublicDescription": "KMCTR-Encrypted-AES-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4156", + "EventName": "KMO_DEA", + "BriefDescription": "KMO DEA", + "PublicDescription": "KMO-DEA function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4157", + "EventName": "KMO_TDEA_128", + "BriefDescription": "KMO TDEA 128", + "PublicDescription": "KMO-TDEA-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4158", + "EventName": "KMO_TDEA_192", + "BriefDescription": "KMO TDEA 192", + "PublicDescription": "KMO-TDEA-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4159", + "EventName": "KMO_ENCRYPTED_DEA", + "BriefDescription": "KMO ENCRYPTED DEA", + "PublicDescription": "KMO-Encrypted-DEA function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4160", + "EventName": "KMO_ENCRYPTED_TDEA_128", + "BriefDescription": "KMO ENCRYPTED TDEA 128", + "PublicDescription": "KMO-Encrypted-TDEA-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4161", + "EventName": "KMO_ENCRYPTED_TDEA_192", + "BriefDescription": "KMO ENCRYPTED TDEA 192", + "PublicDescription": "KMO-Encrypted-TDEA-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4162", + "EventName": "KMO_AES_128", + "BriefDescription": "KMO AES 128", + "PublicDescription": "KMO-AES-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4163", + "EventName": "KMO_AES_192", + "BriefDescription": "KMO AES 192", + "PublicDescription": "KMO-AES-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4164", + "EventName": "KMO_AES_256", + "BriefDescription": "KMO AES 256", + "PublicDescription": "KMO-AES-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4165", + "EventName": "KMO_ENCRYPTED_AES_128", + "BriefDescription": "KMO ENCRYPTED AES 128", + "PublicDescription": "KMO-Encrypted-AES-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4166", + "EventName": "KMO_ENCRYPTED_AES_192", + "BriefDescription": "KMO ENCRYPTED AES 192", + "PublicDescription": "KMO-Encrypted-AES-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4167", + "EventName": "KMO_ENCRYPTED_AES_256", + "BriefDescription": "KMO ENCRYPTED AES 256", + "PublicDescription": "KMO-Encrypted-AES-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4168", + "EventName": "KIMD_SHA_1", + "BriefDescription": "KIMD SHA 1", + "PublicDescription": "KIMD-SHA-1 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4169", + "EventName": "KIMD_SHA_256", + "BriefDescription": "KIMD SHA 256", + "PublicDescription": "KIMD-SHA-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4170", + "EventName": "KIMD_SHA_512", + "BriefDescription": "KIMD SHA 512", + "PublicDescription": "KIMD-SHA-512 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4171", + "EventName": "KIMD_SHA3_224", + "BriefDescription": "KIMD SHA3 224", + "PublicDescription": "KIMD-SHA3-224 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4172", + "EventName": "KIMD_SHA3_256", + "BriefDescription": "KIMD SHA3 256", + "PublicDescription": "KIMD-SHA3-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4173", + "EventName": "KIMD_SHA3_384", + "BriefDescription": "KIMD SHA3 384", + "PublicDescription": "KIMD-SHA3-384 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4174", + "EventName": "KIMD_SHA3_512", + "BriefDescription": "KIMD SHA3 512", + "PublicDescription": "KIMD-SHA3-512 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4175", + "EventName": "KIMD_SHAKE_128", + "BriefDescription": "KIMD SHAKE 128", + "PublicDescription": "KIMD-SHAKE-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4176", + "EventName": "KIMD_SHAKE_256", + "BriefDescription": "KIMD SHAKE 256", + "PublicDescription": "KIMD-SHAKE-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4177", + "EventName": "KIMD_GHASH", + "BriefDescription": "KIMD GHASH", + "PublicDescription": "KIMD-GHASH function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4178", + "EventName": "KLMD_SHA_1", + "BriefDescription": "KLMD SHA 1", + "PublicDescription": "KLMD-SHA-1 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4179", + "EventName": "KLMD_SHA_256", + "BriefDescription": "KLMD SHA 256", + "PublicDescription": "KLMD-SHA-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4180", + "EventName": "KLMD_SHA_512", + "BriefDescription": "KLMD SHA 512", + "PublicDescription": "KLMD-SHA-512 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4181", + "EventName": "KLMD_SHA3_224", + "BriefDescription": "KLMD SHA3 224", + "PublicDescription": "KLMD-SHA3-224 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4182", + "EventName": "KLMD_SHA3_256", + "BriefDescription": "KLMD SHA3 256", + "PublicDescription": "KLMD-SHA3-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4183", + "EventName": "KLMD_SHA3_384", + "BriefDescription": "KLMD SHA3 384", + "PublicDescription": "KLMD-SHA3-384 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4184", + "EventName": "KLMD_SHA3_512", + "BriefDescription": "KLMD SHA3 512", + "PublicDescription": "KLMD-SHA3-512 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4185", + "EventName": "KLMD_SHAKE_128", + "BriefDescription": "KLMD SHAKE 128", + "PublicDescription": "KLMD-SHAKE-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4186", + "EventName": "KLMD_SHAKE_256", + "BriefDescription": "KLMD SHAKE 256", + "PublicDescription": "KLMD-SHAKE-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4187", + "EventName": "KMAC_DEA", + "BriefDescription": "KMAC DEA", + "PublicDescription": "KMAC-DEA function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4188", + "EventName": "KMAC_TDEA_128", + "BriefDescription": "KMAC TDEA 128", + "PublicDescription": "KMAC-TDEA-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4189", + "EventName": "KMAC_TDEA_192", + "BriefDescription": "KMAC TDEA 192", + "PublicDescription": "KMAC-TDEA-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4190", + "EventName": "KMAC_ENCRYPTED_DEA", + "BriefDescription": "KMAC ENCRYPTED DEA", + "PublicDescription": "KMAC-Encrypted-DEA function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4191", + "EventName": "KMAC_ENCRYPTED_TDEA_128", + "BriefDescription": "KMAC ENCRYPTED TDEA 128", + "PublicDescription": "KMAC-Encrypted-TDEA-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4192", + "EventName": "KMAC_ENCRYPTED_TDEA_192", + "BriefDescription": "KMAC ENCRYPTED TDEA 192", + "PublicDescription": "KMAC-Encrypted-TDEA-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4193", + "EventName": "KMAC_AES_128", + "BriefDescription": "KMAC AES 128", + "PublicDescription": "KMAC-AES-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4194", + "EventName": "KMAC_AES_192", + "BriefDescription": "KMAC AES 192", + "PublicDescription": "KMAC-AES-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4195", + "EventName": "KMAC_AES_256", + "BriefDescription": "KMAC AES 256", + "PublicDescription": "KMAC-AES-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4196", + "EventName": "KMAC_ENCRYPTED_AES_128", + "BriefDescription": "KMAC ENCRYPTED AES 128", + "PublicDescription": "KMAC-Encrypted-AES-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4197", + "EventName": "KMAC_ENCRYPTED_AES_192", + "BriefDescription": "KMAC ENCRYPTED AES 192", + "PublicDescription": "KMAC-Encrypted-AES-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4198", + "EventName": "KMAC_ENCRYPTED_AES_256", + "BriefDescription": "KMAC ENCRYPTED AES 256", + "PublicDescription": "KMAC-Encrypted-AES-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4199", + "EventName": "PCC_COMPUTE_LAST_BLOCK_CMAC_USING_DEA", + "BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING DEA", + "PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-DEA function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4200", + "EventName": "PCC_COMPUTE_LAST_BLOCK_CMAC_USING_TDEA_128", + "BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING TDEA 128", + "PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-TDEA-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4201", + "EventName": "PCC_COMPUTE_LAST_BLOCK_CMAC_USING_TDEA_192", + "BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING TDEA 192", + "PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-TDEA-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4202", + "EventName": "PCC_COMPUTE_LAST_BLOCK_CMAC_USING_ENCRYPTED_DEA", + "BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING ENCRYPTED DEA", + "PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-Encrypted-DEA function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4203", + "EventName": "PCC_COMPUTE_LAST_BLOCK_CMAC_USING_ENCRYPTED_TDEA_128", + "BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING ENCRYPTED TDEA 128", + "PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-Encrypted-TDEA- 128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4204", + "EventName": "PCC_COMPUTE_LAST_BLOCK_CMAC_USING_ENCRYPTED_TDEA_192", + "BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING ENCRYPTED TDEA 192", + "PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-Encrypted-TDEA- 192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4205", + "EventName": "PCC_COMPUTE_LAST_BLOCK_CMAC_USING_AES_128", + "BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING AES 128", + "PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-AES-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4206", + "EventName": "PCC_COMPUTE_LAST_BLOCK_CMAC_USING_AES_192", + "BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING AES 192", + "PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-AES-192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4207", + "EventName": "PCC_COMPUTE_LAST_BLOCK_CMAC_USING_AES_256", + "BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING AES 256", + "PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-AES-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4208", + "EventName": "PCC_COMPUTE_LAST_BLOCK_CMAC_USING_ENCRYPTED_AES_128", + "BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING ENCRYPTED AES 128", + "PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-Encrypted-AES- 128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4209", + "EventName": "PCC_COMPUTE_LAST_BLOCK_CMAC_USING_ENCRYPTED_AES_192", + "BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING ENCRYPTED AES 192", + "PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-Encrypted-AES- 192 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4210", + "EventName": "PCC_COMPUTE_LAST_BLOCK_CMAC_USING_ENCRYPTED_AES_256A", + "BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING ENCRYPTED AES 256A", + "PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-Encrypted-AES- 256A function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4211", + "EventName": "PCC_COMPUTE_XTS_PARAMETER_USING_AES_128", + "BriefDescription": "PCC COMPUTE XTS PARAMETER USING AES 128", + "PublicDescription": "PCC-Compute-XTS-Parameter-Using-AES-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4212", + "EventName": "PCC_COMPUTE_XTS_PARAMETER_USING_AES_256", + "BriefDescription": "PCC COMPUTE XTS PARAMETER USING AES 256", + "PublicDescription": "PCC-Compute-XTS-Parameter-Using-AES-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4213", + "EventName": "PCC_COMPUTE_XTS_PARAMETER_USING_ENCRYPTED_AES_128", + "BriefDescription": "PCC COMPUTE XTS PARAMETER USING ENCRYPTED AES 128", + "PublicDescription": "PCC-Compute-XTS-Parameter-Using-Encrypted-AES-128 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4214", + "EventName": "PCC_COMPUTE_XTS_PARAMETER_USING_ENCRYPTED_AES_256", + "BriefDescription": "PCC COMPUTE XTS PARAMETER USING ENCRYPTED AES 256", + "PublicDescription": "PCC-Compute-XTS-Parameter-Using-Encrypted-AES-256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4215", + "EventName": "PCC_SCALAR_MULTIPLY_P256", + "BriefDescription": "PCC SCALAR MULTIPLY P256", + "PublicDescription": "PCC-Scalar-Multiply-P256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4216", + "EventName": "PCC_SCALAR_MULTIPLY_P384", + "BriefDescription": "PCC SCALAR MULTIPLY P384", + "PublicDescription": "PCC-Scalar-Multiply-P384 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4217", + "EventName": "PCC_SCALAR_MULTIPLY_P521", + "BriefDescription": "PCC SCALAR MULTIPLY P521", + "PublicDescription": "PCC-Scalar-Multiply-P521 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4218", + "EventName": "PCC_SCALAR_MULTIPLY_ED25519", + "BriefDescription": "PCC SCALAR MULTIPLY ED25519", + "PublicDescription": "PCC-Scalar-Multiply-Ed25519 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4219", + "EventName": "PCC_SCALAR_MULTIPLY_ED448", + "BriefDescription": "PCC SCALAR MULTIPLY ED448", + "PublicDescription": "PCC-Scalar-Multiply-Ed448 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4220", + "EventName": "PCC_SCALAR_MULTIPLY_X25519", + "BriefDescription": "PCC SCALAR MULTIPLY X25519", + "PublicDescription": "PCC-Scalar-Multiply-X25519 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4221", + "EventName": "PCC_SCALAR_MULTIPLY_X448", + "BriefDescription": "PCC SCALAR MULTIPLY X448", + "PublicDescription": "PCC-Scalar-Multiply-X448 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4222", + "EventName": "PRNO_SHA_512_DRNG", + "BriefDescription": "PRNO SHA 512 DRNG", + "PublicDescription": "PRNO-SHA-512-DRNG function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4223", + "EventName": "PRNO_TRNG_QUERY_RAW_TO_CONDITIONED_RATIO", + "BriefDescription": "PRNO TRNG QUERY RAW TO CONDITIONED RATIO", + "PublicDescription": "PRNO-TRNG-Query-Raw-to-Conditioned-Ratio function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4224", + "EventName": "PRNO_TRNG", + "BriefDescription": "PRNO TRNG", + "PublicDescription": "PRNO-TRNG function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4225", + "EventName": "KDSA_ECDSA_VERIFY_P256", + "BriefDescription": "KDSA ECDSA VERIFY P256", + "PublicDescription": "KDSA-ECDSA-Verify-P256 function ending with CC=0 or CC=2" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4226", + "EventName": "KDSA_ECDSA_VERIFY_P384", + "BriefDescription": "KDSA ECDSA VERIFY P384", + "PublicDescription": "KDSA-ECDSA-Verify-P384 function ending with CC=0 or CC=2" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4227", + "EventName": "KDSA_ECDSA_VERIFY_P521", + "BriefDescription": "KDSA ECDSA VERIFY P521", + "PublicDescription": "KDSA-ECDSA-Verify-P521 function ending with CC=0 or CC=2" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4228", + "EventName": "KDSA_ECDSA_SIGN_P256", + "BriefDescription": "KDSA ECDSA SIGN P256", + "PublicDescription": "KDSA-ECDSA-Sign-P256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4229", + "EventName": "KDSA_ECDSA_SIGN_P384", + "BriefDescription": "KDSA ECDSA SIGN P384", + "PublicDescription": "KDSA-ECDSA-Sign-P384 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4230", + "EventName": "KDSA_ECDSA_SIGN_P521", + "BriefDescription": "KDSA ECDSA SIGN P521", + "PublicDescription": "KDSA-ECDSA-Sign-P521 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4231", + "EventName": "KDSA_ENCRYPTED_ECDSA_SIGN_P256", + "BriefDescription": "KDSA ENCRYPTED ECDSA SIGN P256", + "PublicDescription": "KDSA-Encrypted-ECDSA-Sign-P256 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4232", + "EventName": "KDSA_ENCRYPTED_ECDSA_SIGN_P384", + "BriefDescription": "KDSA ENCRYPTED ECDSA SIGN P384", + "PublicDescription": "KDSA-Encrypted-ECDSA-Sign-P384 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4233", + "EventName": "KDSA_ENCRYPTED_ECDSA_SIGN_P521", + "BriefDescription": "KDSA ENCRYPTED ECDSA SIGN P521", + "PublicDescription": "KDSA-Encrypted-ECDSA-Sign-P521 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4234", + "EventName": "KDSA_EDDSA_VERIFY_ED25519", + "BriefDescription": "KDSA EDDSA VERIFY ED25519", + "PublicDescription": "KDSA-EdDSA-Verify-Ed25519 function ending with CC=0 or CC=2" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4235", + "EventName": "KDSA_EDDSA_VERIFY_ED448", + "BriefDescription": "KDSA EDDSA VERIFY ED448", + "PublicDescription": "KDSA-EdDSA-Verify-Ed448 function ending with CC=0 or CC=2" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4236", + "EventName": "KDSA_EDDSA_SIGN_ED25519", + "BriefDescription": "KDSA EDDSA SIGN ED25519", + "PublicDescription": "KDSA-EdDSA-Sign-Ed25519 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4237", + "EventName": "KDSA_EDDSA_SIGN_ED448", + "BriefDescription": "KDSA EDDSA SIGN ED448", + "PublicDescription": "KDSA-EdDSA-Sign-Ed448 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4238", + "EventName": "KDSA_ENCRYPTED_EDDSA_SIGN_ED25519", + "BriefDescription": "KDSA ENCRYPTED EDDSA SIGN ED25519", + "PublicDescription": "KDSA-Encrypted-EdDSA-Sign-Ed25519 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4239", + "EventName": "KDSA_ENCRYPTED_EDDSA_SIGN_ED448", + "BriefDescription": "KDSA ENCRYPTED EDDSA SIGN ED448", + "PublicDescription": "KDSA-Encrypted-EdDSA-Sign-Ed448 function ending with CC=0" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4240", + "EventName": "PCKMO_ENCRYPT_DEA_KEY", + "BriefDescription": "PCKMO ENCRYPT DEA KEY", + "PublicDescription": "PCKMO-Encrypt-DEA-key function" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4241", + "EventName": "PCKMO_ENCRYPT_TDEA_128_KEY", + "BriefDescription": "PCKMO ENCRYPT TDEA 128 KEY", + "PublicDescription": "PCKMO-Encrypt-TDEA-128-key function" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4242", + "EventName": "PCKMO_ENCRYPT_TDEA_192_KEY", + "BriefDescription": "PCKMO ENCRYPT TDEA 192 KEY", + "PublicDescription": "PCKMO-Encrypt-TDEA-192-key function" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4243", + "EventName": "PCKMO_ENCRYPT_AES_128_KEY", + "BriefDescription": "PCKMO ENCRYPT AES 128 KEY", + "PublicDescription": "PCKMO-Encrypt-AES-128-key function" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4244", + "EventName": "PCKMO_ENCRYPT_AES_192_KEY", + "BriefDescription": "PCKMO ENCRYPT AES 192 KEY", + "PublicDescription": "PCKMO-Encrypt-AES-192-key function" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4245", + "EventName": "PCKMO_ENCRYPT_AES_256_KEY", + "BriefDescription": "PCKMO ENCRYPT AES 256 KEY", + "PublicDescription": "PCKMO-Encrypt-AES-256-key function" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4246", + "EventName": "PCKMO_ENCRYPT_ECC_P256_KEY", + "BriefDescription": "PCKMO ENCRYPT ECC P256 KEY", + "PublicDescription": "PCKMO-Encrypt-ECC-P256-key function" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4247", + "EventName": "PCKMO_ENCRYPT_ECC_P384_KEY", + "BriefDescription": "PCKMO ENCRYPT ECC P384 KEY", + "PublicDescription": "PCKMO-Encrypt-ECC-P384-key function" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4248", + "EventName": "PCKMO_ENCRYPT_ECC_P521_KEY", + "BriefDescription": "PCKMO ENCRYPT ECC P521 KEY", + "PublicDescription": "PCKMO-Encrypt-ECC-P521-key function" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4249", + "EventName": "PCKMO_ENCRYPT_ECC_ED25519_KEY", + "BriefDescription": "PCKMO ENCRYPT ECC ED25519 KEY", + "PublicDescription": "PCKMO-Encrypt-ECC-Ed25519-key function" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4250", + "EventName": "PCKMO_ENCRYPT_ECC_ED448_KEY", + "BriefDescription": "PCKMO ENCRYPT ECC ED448 KEY", + "PublicDescription": "PCKMO-Encrypt-ECC-Ed448-key function" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4251", + "EventName": "IBM_RESERVED_155", + "BriefDescription": "IBM RESERVED_155", + "PublicDescription": "Reserved for IBM use" + }, + { + "Unit": "PAI-CRYPTO", + "EventCode": "4252", + "EventName": "IBM_RESERVED_156", + "BriefDescription": "IBM RESERVED_156", + "PublicDescription": "Reserved for IBM use" + } +] diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index cdfa4e0e7557..c5c9bb186abd 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -107,6 +107,7 @@ class JsonEvent: 'iMPH-U': 'uncore_arb', 'CPU-M-CF': 'cpum_cf', 'CPU-M-SF': 'cpum_sf', + 'PAI-CRYPTO' : 'pai_crypto', 'UPI LL': 'uncore_upi', 'hisi_sicl,cpa': 'hisi_sicl,cpa', 'hisi_sccl,ddrc': 'hisi_sccl,ddrc', -- cgit v1.2.3 From 46f7bd5e1b5732acb9b95037afd052a4d2eebb1a Mon Sep 17 00:00:00 2001 From: Brian Robbins Date: Fri, 5 Aug 2022 15:06:45 -0700 Subject: perf inject jit: Ignore memfd and anonymous mmap events if jitdump present Some processes store jitted code in memfd mappings to avoid having rwx mappings. These processes map the code with a writeable mapping and a read-execute mapping. They write the code using the writeable mapping and then unmap the writeable mapping. All subsequent execution is through the read-execute mapping. perf inject --jit ignores //anon* mappings for each process where a jitdump is present because it expects to inject mmap events for each jitted code range, and said jitted code ranges will overlap with the //anon* mappings. Ignore /memfd: and [anon:* mappings so that jitted code contained in /memfd: and [anon:* mappings is treated the same way as jitted code contained in //anon* mappings. Signed-off-by: Brian Robbins Acked-by: Ian Rogers Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20220805220645.95855-1-brianrob@linux.microsoft.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/jitdump.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/jitdump.c b/tools/perf/util/jitdump.c index a23255773c60..4e6632203704 100644 --- a/tools/perf/util/jitdump.c +++ b/tools/perf/util/jitdump.c @@ -845,8 +845,13 @@ jit_process(struct perf_session *session, if (jit_detect(filename, pid, nsi)) { nsinfo__put(nsi); - // Strip //anon* mmaps if we processed a jitdump for this pid - if (jit_has_pid(machine, pid) && (strncmp(filename, "//anon", 6) == 0)) + /* + * Strip //anon*, [anon:* and /memfd:* mmaps if we processed a jitdump for this pid + */ + if (jit_has_pid(machine, pid) && + ((strncmp(filename, "//anon", 6) == 0) || + (strncmp(filename, "[anon:", 6) == 0) || + (strncmp(filename, "/memfd:", 7) == 0))) return 1; return 0; -- cgit v1.2.3 From 4bf6dcaa93bcd083a13c278a91418fe10e6d23a0 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sat, 6 Aug 2022 16:51:26 +0200 Subject: perf probe: Fix an error handling path in 'parse_perf_probe_command()' If a memory allocation fail, we should branch to the error handling path in order to free some resources allocated a few lines above. Fixes: 15354d54698648e2 ("perf probe: Generate event name with line number") Signed-off-by: Christophe JAILLET Acked-by: Masami Hiramatsu Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: kernel-janitors@vger.kernel.org Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/b71bcb01fa0c7b9778647235c3ab490f699ba278.1659797452.git.christophe.jaillet@wanadoo.fr Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/probe-event.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/probe-event.c b/tools/perf/util/probe-event.c index 67c12d5303e7..785246ff4179 100644 --- a/tools/perf/util/probe-event.c +++ b/tools/perf/util/probe-event.c @@ -1775,8 +1775,10 @@ int parse_perf_probe_command(const char *cmd, struct perf_probe_event *pev) if (!pev->event && pev->point.function && pev->point.line && !pev->point.lazy_line && !pev->point.offset) { if (asprintf(&pev->event, "%s_L%d", pev->point.function, - pev->point.line) < 0) - return -ENOMEM; + pev->point.line) < 0) { + ret = -ENOMEM; + goto out; + } } /* Copy arguments and ensure return probe has no C argument */ -- cgit v1.2.3 From d2f30b793e59d7c95822ef9b46d2416efddef583 Mon Sep 17 00:00:00 2001 From: Yang Jihong Date: Mon, 8 Aug 2022 17:24:07 +0800 Subject: perf kvm: Fix subcommand matching error Currently the 'diff', 'top', 'buildid-list' and 'stat' perf commands use strncmp() to match subcommands. As a result, matching does not meet expectation. For example: # perf kvm diff1234 # Event 'cycles' # # Baseline Delta Abs Shared Object Symbol # ........ ......... ............. ...... # # Event 'dummy:HG' # # Baseline Delta Abs Shared Object Symbol # ........ ......... ............. ...... # # echo $? 0 # Invalid information should be returned, but success is actually returned. Solution: Use strstarts() to match subcommands. After: # perf kvm diff1234 Usage: perf kvm [] {top|record|report|diff|buildid-list|stat} -i, --input Input file name -o, --output Output file name -v, --verbose be more verbose (show counter open errors, etc) --guest Collect guest os data --guest-code Guest code can be found in hypervisor process --guestkallsyms file saving guest os /proc/kallsyms --guestmodules file saving guest os /proc/modules --guestmount guest mount directory under which every guest os instance has a subdir --guestvmlinux file saving guest os vmlinux --host Collect host os data # echo $? 129 # Signed-off-by: Yang Jihong Acked-by: Namhyung Kim Tested-by: Arnaldo Carvalho de Melo Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20220808092408.107399-2-yangjihong1@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-kvm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c index 3696ae97f149..7d9ec1bac1a2 100644 --- a/tools/perf/builtin-kvm.c +++ b/tools/perf/builtin-kvm.c @@ -1638,14 +1638,14 @@ int cmd_kvm(int argc, const char **argv) return __cmd_record(file_name, argc, argv); else if (strlen(argv[0]) > 2 && strstarts("report", argv[0])) return __cmd_report(file_name, argc, argv); - else if (!strncmp(argv[0], "diff", 4)) + else if (strlen(argv[0]) > 2 && strstarts("diff", argv[0])) return cmd_diff(argc, argv); - else if (!strncmp(argv[0], "top", 3)) + else if (!strcmp(argv[0], "top")) return cmd_top(argc, argv); - else if (!strncmp(argv[0], "buildid-list", 12)) + else if (strlen(argv[0]) > 2 && strstarts("buildid-list", argv[0])) return __cmd_buildid_list(file_name, argc, argv); #ifdef HAVE_KVM_STAT_SUPPORT - else if (!strncmp(argv[0], "stat", 4)) + else if (strlen(argv[0]) > 2 && strstarts("stat", argv[0])) return kvm_cmd_stat(file_name, argc, argv); #endif else -- cgit v1.2.3 From 628881ee06cb41a3c2c4e4e3f04ff3dc6779cd12 Mon Sep 17 00:00:00 2001 From: Yang Jihong Date: Mon, 8 Aug 2022 17:24:08 +0800 Subject: perf sched latency: Fix subcommand matching error perf sched latency use strncmp to match subcommands which matching does not meet expectation. Before: # perf sched lat1234 >/dev/null # echo $? 0 # Solution: Use strstarts to match subcommand. After: # perf sched lat1234 Usage: perf sched [] {record|latency|map|replay|script|timehist} -D, --dump-raw-trace dump raw trace in ASCII -f, --force don't complain, do it -i, --input input file name -v, --verbose be more verbose (show symbol address, etc) # echo $? 129 # # perf sched lat >/dev/null # echo $? 0 # Signed-off-by: Yang Jihong Acked-by: Namhyung Kim Tested-by: Arnaldo Carvalho de Melo Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20220808092408.107399-3-yangjihong1@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-sched.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/builtin-sched.c b/tools/perf/builtin-sched.c index 646bd938927a..2f6cd1b8b662 100644 --- a/tools/perf/builtin-sched.c +++ b/tools/perf/builtin-sched.c @@ -3563,7 +3563,7 @@ int cmd_sched(int argc, const char **argv) if (strlen(argv[0]) > 2 && strstarts("record", argv[0])) { return __cmd_record(argc, argv); - } else if (!strncmp(argv[0], "lat", 3)) { + } else if (strlen(argv[0]) > 2 && strstarts("latency", argv[0])) { sched.tp_handler = &lat_ops; if (argc > 1) { argc = parse_options(argc, argv, latency_options, latency_usage, 0); -- cgit v1.2.3 From 0c39f147145e5ebb2a867a1b50afdbfee0ae66c8 Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Tue, 9 Aug 2022 15:32:58 +0300 Subject: perf script: Fix reference to perf insert instead of perf inject Amend "perf insert" to "perf inject". Fixes: e28fb159f1163e76 ("perf script: Add machine_pid and vcpu") Signed-off-by: Adrian Hunter Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Jiri Olsa Cc: Namhyung Kim Link: https://lore.kernel.org/r/20220809123258.9086-1-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Documentation/perf-script.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/Documentation/perf-script.txt b/tools/perf/Documentation/perf-script.txt index c09cc44e50ee..4c95e79e2c39 100644 --- a/tools/perf/Documentation/perf-script.txt +++ b/tools/perf/Documentation/perf-script.txt @@ -228,7 +228,7 @@ OPTIONS Instruction Trace decoding. The machine_pid and vcpu fields are derived from data resulting from using - perf insert to insert a perf.data file recorded inside a virtual machine into + perf inject to insert a perf.data file recorded inside a virtual machine into a perf.data file recorded on the host at the same time. Finally, a user may not set fields to none for all event types. -- cgit v1.2.3 From b39c9e1b101d2992de9981673919ae55a088792c Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Tue, 9 Aug 2022 16:07:58 +0300 Subject: perf machine: Fix missing free of machine->kallsyms_filename Add missing free of machine->kallsyms_filename to machine__exit(). Fixes: a5367ecb5353fbf2 ("perf tools: Automatically use guest kcore_dir if present") Signed-off-by: Adrian Hunter Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Jiri Olsa Cc: Namhyung Kim Link: https://lore.kernel.org/r/20220809130758.12800-1-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/machine.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c index facc13fbf16e..2a16cae28407 100644 --- a/tools/perf/util/machine.c +++ b/tools/perf/util/machine.c @@ -236,6 +236,7 @@ void machine__exit(struct machine *machine) zfree(&machine->root_dir); zfree(&machine->mmap_name); zfree(&machine->current_tid); + zfree(&machine->kallsyms_filename); for (i = 0; i < THREADS__TABLE_SIZE; i++) { struct threads *threads = &machine->threads[i]; -- cgit v1.2.3 From d511e8a7e850db567cd7f633288aa96a19508e5b Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Tue, 9 Aug 2022 14:27:45 -0700 Subject: regulator: core: Fix missing error return from regulator_bulk_get() In commit 6eabfc018e8d ("regulator: core: Allow specifying an initial load w/ the bulk API") I changed the error handling but had a subtle that caused us to always return no error even if there was an error. Fix it. Fixes: 6eabfc018e8d ("regulator: core: Allow specifying an initial load w/ the bulk API") Signed-off-by: Douglas Anderson Link: https://lore.kernel.org/r/20220809142738.1.I91625242f137c707bb345c51c80c5ecee02eeff3@changeid Signed-off-by: Mark Brown --- drivers/regulator/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index 7150b1d0159e..d8373cb04f90 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -4784,10 +4784,10 @@ int regulator_bulk_get(struct device *dev, int num_consumers, consumers[i].consumer = regulator_get(dev, consumers[i].supply); if (IS_ERR(consumers[i].consumer)) { - consumers[i].consumer = NULL; ret = dev_err_probe(dev, PTR_ERR(consumers[i].consumer), "Failed to get supply '%s'", consumers[i].supply); + consumers[i].consumer = NULL; goto err; } -- cgit v1.2.3 From 6fb271f1bc4ebc59bac0ff835c2e5197eac4b075 Mon Sep 17 00:00:00 2001 From: Ming Lei Date: Thu, 21 Jul 2022 08:33:58 +0800 Subject: nvme-fc: restart admin queue if the caller needs to restart queue Without restarting admin queue in __nvme_fc_abort_outstanding_ios(), it leaves controller not capable of handling admin pt request, and causes io hang. Fixes it by restarting admin queue if the caller of __nvme_fc_abort_outstanding_ios requires to restart queue. Signed-off-by: Ming Lei Reviewed-by: Sagi Grimberg Reviewed-by: James Smart Tested-by: Ewan D. Milne Signed-off-by: Christoph Hellwig --- drivers/nvme/host/fc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/nvme/host/fc.c b/drivers/nvme/host/fc.c index 9987797620b6..8d14df8eeab8 100644 --- a/drivers/nvme/host/fc.c +++ b/drivers/nvme/host/fc.c @@ -2533,6 +2533,8 @@ __nvme_fc_abort_outstanding_ios(struct nvme_fc_ctrl *ctrl, bool start_queues) blk_mq_tagset_busy_iter(&ctrl->admin_tag_set, nvme_fc_terminate_exchange, &ctrl->ctrl); blk_mq_tagset_wait_completed_request(&ctrl->admin_tag_set); + if (start_queues) + nvme_start_admin_queue(&ctrl->ctrl); } static void -- cgit v1.2.3 From 9317d0014499182c77a03cd095e83bcfb0f53750 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Sat, 6 Aug 2022 10:29:55 +0200 Subject: nvme-fc: fix the fc_appid_store return value "nvme-fc: fold t fc_update_appid into fc_appid_store" accidentally changed the userspace interface for the appid attribute, because the code that decrements "count" to remove a trailing '\n' in the parsing results in the decremented value being incorrectly be returned from the sysfs write. Fix this by keeping an orig_count variable for the full length of the write. Fixes: c814153c83a8 ("nvme-fc: fold t fc_update_appid into fc_appid_store") Signed-off-by: Christoph Hellwig Reviewed-by: Chaitanya Kulkarni Reviewed-by: Ewan D. Milne Reviewed-by: James Smart Tested-by: Muneendra Kumar M --- drivers/nvme/host/fc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/nvme/host/fc.c b/drivers/nvme/host/fc.c index 8d14df8eeab8..127abaf9ba5d 100644 --- a/drivers/nvme/host/fc.c +++ b/drivers/nvme/host/fc.c @@ -3880,6 +3880,7 @@ static int fc_parse_cgrpid(const char *buf, u64 *id) static ssize_t fc_appid_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { + size_t orig_count = count; u64 cgrp_id; int appid_len = 0; int cgrpid_len = 0; @@ -3904,7 +3905,7 @@ static ssize_t fc_appid_store(struct device *dev, ret = blkcg_set_fc_appid(app_id, cgrp_id, sizeof(app_id)); if (ret < 0) return ret; - return count; + return orig_count; } static DEVICE_ATTR(appid_store, 0200, NULL, fc_appid_store); #endif /* CONFIG_BLK_CGROUP_FC_APPID */ -- cgit v1.2.3 From 14446f9abd609791064d222ccf3c7b3af1772358 Mon Sep 17 00:00:00 2001 From: Zhang Xiaoxu Date: Tue, 26 Jul 2022 10:56:32 +0800 Subject: nvmet-auth: use kmemdup instead of kmalloc + memcpy For code neat purpose, we can use kmemdup to replace kmalloc + memcpy. Signed-off-by: Zhang Xiaoxu Signed-off-by: Christoph Hellwig --- drivers/nvme/target/fabrics-cmd-auth.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/nvme/target/fabrics-cmd-auth.c b/drivers/nvme/target/fabrics-cmd-auth.c index c851814d6cb0..ebdf9aa81041 100644 --- a/drivers/nvme/target/fabrics-cmd-auth.c +++ b/drivers/nvme/target/fabrics-cmd-auth.c @@ -160,10 +160,10 @@ static u16 nvmet_auth_reply(struct nvmet_req *req, void *d) pr_debug("%s: ctrl %d qid %d host authenticated\n", __func__, ctrl->cntlid, req->sq->qid); if (data->cvalid) { - req->sq->dhchap_c2 = kmalloc(data->hl, GFP_KERNEL); + req->sq->dhchap_c2 = kmemdup(data->rval + data->hl, data->hl, + GFP_KERNEL); if (!req->sq->dhchap_c2) return NVME_AUTH_DHCHAP_FAILURE_FAILED; - memcpy(req->sq->dhchap_c2, data->rval + data->hl, data->hl); pr_debug("%s: ctrl %d qid %d challenge %*ph\n", __func__, ctrl->cntlid, req->sq->qid, data->hl, -- cgit v1.2.3 From ec9e96b5230148294c7abcaf3a4c592d3720b62d Mon Sep 17 00:00:00 2001 From: Amit Engel Date: Mon, 1 Aug 2022 21:40:39 +0300 Subject: nvme-fabrics: parse nvme connect Linux error codes This fixes the assumption that errval is an unsigned nvme error Signed-off-by: Amit Engel Signed-off-by: Christoph Hellwig --- drivers/nvme/host/fabrics.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/nvme/host/fabrics.c b/drivers/nvme/host/fabrics.c index 5207a2348257..83b505358859 100644 --- a/drivers/nvme/host/fabrics.c +++ b/drivers/nvme/host/fabrics.c @@ -270,6 +270,12 @@ static void nvmf_log_connect_error(struct nvme_ctrl *ctrl, { int err_sctype = errval & ~NVME_SC_DNR; + if (errval < 0) { + dev_err(ctrl->device, + "Connect command failed, errno: %d\n", errval); + return; + } + switch (err_sctype) { case NVME_SC_CONNECT_INVALID_PARAM: if (offset >> 16) { -- cgit v1.2.3 From c50cd03dbebd1d5d34a2eb361f315b0bd833d6c1 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sat, 6 Aug 2022 22:15:01 +0200 Subject: nvme-fabrics: Fix a typo in an error message A 'c' is missing. s/fabris/fabrics/ Signed-off-by: Christophe JAILLET Reviewed-by: Chaitanya Kulkarni Signed-off-by: Christoph Hellwig --- drivers/nvme/host/fabrics.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/nvme/host/fabrics.c b/drivers/nvme/host/fabrics.c index 83b505358859..10cc4a814602 100644 --- a/drivers/nvme/host/fabrics.c +++ b/drivers/nvme/host/fabrics.c @@ -1236,7 +1236,7 @@ static int __init nvmf_init(void) nvmf_device = device_create(nvmf_class, NULL, MKDEV(0, 0), NULL, "ctl"); if (IS_ERR(nvmf_device)) { - pr_err("couldn't create nvme-fabris device!\n"); + pr_err("couldn't create nvme-fabrics device!\n"); ret = PTR_ERR(nvmf_device); goto out_destroy_class; } -- cgit v1.2.3 From 2bff487f9a9085c9c877b55579b153691f0e5245 Mon Sep 17 00:00:00 2001 From: Maurizio Lombardi Date: Mon, 1 Aug 2022 10:09:00 +0200 Subject: nvme-tcp: check if the queue is allocated before stopping it When an error is detected and the host reconnects, the nvme_tcp_error_recovery_work() function is called and starts tearing down the io queues and de-allocating them; If at the same time the "nvme" process deletes the controller via sysfs, the nvme_tcp_delete_ctrl() gets called and waits until the nvme_tcp_error_recovery_work() finishes its job; then starts tearing down the io queues, but at this point they have already been freed and the mutexes are destroyed. Calling mutex_lock() against a destroyed mutex triggers a warning: [ 1299.025575] nvme nvme1: Reconnecting in 10 seconds... [ 1299.636449] nvme nvme1: Removing ctrl: NQN "blktests-subsystem-1" [ 1299.645262] ------------[ cut here ]------------ [ 1299.649949] DEBUG_LOCKS_WARN_ON(lock->magic != lock) [ 1299.649971] WARNING: CPU: 4 PID: 104150 at kernel/locking/mutex.c:579 __mutex_lock+0x2d0/0x7dc [ 1299.717934] CPU: 4 PID: 104150 Comm: nvme [ 1299.828075] Call trace: [ 1299.830526] __mutex_lock+0x2d0/0x7dc [ 1299.834203] mutex_lock_nested+0x64/0xd4 [ 1299.838139] nvme_tcp_stop_queue+0x54/0xe0 [nvme_tcp] [ 1299.843211] nvme_tcp_teardown_io_queues.part.0+0x90/0x280 [nvme_tcp] [ 1299.849672] nvme_tcp_delete_ctrl+0x6c/0xf0 [nvme_tcp] [ 1299.854831] nvme_do_delete_ctrl+0x108/0x120 [nvme_core] [ 1299.860181] nvme_sysfs_delete+0xec/0xf0 [nvme_core] [ 1299.865179] dev_attr_store+0x40/0x70 Fix the warning by checking if the queues are allocated in the nvme_tcp_stop_queue(). If they are not, it makes no sense to try to stop them. Signed-off-by: Maurizio Lombardi Reviewed-by: Sagi Grimberg Signed-off-by: Christoph Hellwig --- drivers/nvme/host/tcp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/nvme/host/tcp.c b/drivers/nvme/host/tcp.c index e82dcfcda29b..044da18c06f5 100644 --- a/drivers/nvme/host/tcp.c +++ b/drivers/nvme/host/tcp.c @@ -1660,6 +1660,9 @@ static void nvme_tcp_stop_queue(struct nvme_ctrl *nctrl, int qid) struct nvme_tcp_ctrl *ctrl = to_tcp_ctrl(nctrl); struct nvme_tcp_queue *queue = &ctrl->queues[qid]; + if (!test_bit(NVME_TCP_Q_ALLOCATED, &queue->flags)) + return; + mutex_lock(&queue->queue_lock); if (test_and_clear_bit(NVME_TCP_Q_LIVE, &queue->flags)) __nvme_tcp_stop_queue(queue); -- cgit v1.2.3 From 3400278328285a8c2f121904496aff5e7b610a01 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Tue, 9 Aug 2022 13:22:01 +0200 Subject: netfilter: nf_tables: use READ_ONCE and WRITE_ONCE for shared generation id access The generation ID is bumped from the commit path while holding the mutex, however, netlink dump operations rely on RCU. This patch also adds missing cb->base_eq initialization in nf_tables_dump_set(). Fixes: 38e029f14a97 ("netfilter: nf_tables: set NLM_F_DUMP_INTR if netlink dumping is stale") Signed-off-by: Pablo Neira Ayuso --- net/netfilter/nf_tables_api.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index 3cc88998b879..8b084cd669ab 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -889,7 +889,7 @@ static int nf_tables_dump_tables(struct sk_buff *skb, rcu_read_lock(); nft_net = nft_pernet(net); - cb->seq = nft_net->base_seq; + cb->seq = READ_ONCE(nft_net->base_seq); list_for_each_entry_rcu(table, &nft_net->tables, list) { if (family != NFPROTO_UNSPEC && family != table->family) @@ -1705,7 +1705,7 @@ static int nf_tables_dump_chains(struct sk_buff *skb, rcu_read_lock(); nft_net = nft_pernet(net); - cb->seq = nft_net->base_seq; + cb->seq = READ_ONCE(nft_net->base_seq); list_for_each_entry_rcu(table, &nft_net->tables, list) { if (family != NFPROTO_UNSPEC && family != table->family) @@ -3149,7 +3149,7 @@ static int nf_tables_dump_rules(struct sk_buff *skb, rcu_read_lock(); nft_net = nft_pernet(net); - cb->seq = nft_net->base_seq; + cb->seq = READ_ONCE(nft_net->base_seq); list_for_each_entry_rcu(table, &nft_net->tables, list) { if (family != NFPROTO_UNSPEC && family != table->family) @@ -4133,7 +4133,7 @@ static int nf_tables_dump_sets(struct sk_buff *skb, struct netlink_callback *cb) rcu_read_lock(); nft_net = nft_pernet(net); - cb->seq = nft_net->base_seq; + cb->seq = READ_ONCE(nft_net->base_seq); list_for_each_entry_rcu(table, &nft_net->tables, list) { if (ctx->family != NFPROTO_UNSPEC && @@ -5061,6 +5061,8 @@ static int nf_tables_dump_set(struct sk_buff *skb, struct netlink_callback *cb) rcu_read_lock(); nft_net = nft_pernet(net); + cb->seq = READ_ONCE(nft_net->base_seq); + list_for_each_entry_rcu(table, &nft_net->tables, list) { if (dump_ctx->ctx.family != NFPROTO_UNSPEC && dump_ctx->ctx.family != table->family) @@ -6941,7 +6943,7 @@ static int nf_tables_dump_obj(struct sk_buff *skb, struct netlink_callback *cb) rcu_read_lock(); nft_net = nft_pernet(net); - cb->seq = nft_net->base_seq; + cb->seq = READ_ONCE(nft_net->base_seq); list_for_each_entry_rcu(table, &nft_net->tables, list) { if (family != NFPROTO_UNSPEC && family != table->family) @@ -7873,7 +7875,7 @@ static int nf_tables_dump_flowtable(struct sk_buff *skb, rcu_read_lock(); nft_net = nft_pernet(net); - cb->seq = nft_net->base_seq; + cb->seq = READ_ONCE(nft_net->base_seq); list_for_each_entry_rcu(table, &nft_net->tables, list) { if (family != NFPROTO_UNSPEC && family != table->family) @@ -8806,6 +8808,7 @@ static int nf_tables_commit(struct net *net, struct sk_buff *skb) struct nft_trans_elem *te; struct nft_chain *chain; struct nft_table *table; + unsigned int base_seq; LIST_HEAD(adl); int err; @@ -8855,9 +8858,12 @@ static int nf_tables_commit(struct net *net, struct sk_buff *skb) * Bump generation counter, invalidate any dump in progress. * Cannot fail after this point. */ - while (++nft_net->base_seq == 0) + base_seq = READ_ONCE(nft_net->base_seq); + while (++base_seq == 0) ; + WRITE_ONCE(nft_net->base_seq, base_seq); + /* step 3. Start new generation, rules_gen_X now in use. */ net->nft.gencursor = nft_gencursor_next(net); -- cgit v1.2.3 From 4963674c2e71fc062f8f089f0f58ffbb5533060b Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Tue, 9 Aug 2022 13:39:18 +0200 Subject: netfilter: nf_tables: disallow NFTA_SET_ELEM_KEY_END with NFT_SET_ELEM_INTERVAL_END flag These are mutually exclusive, actually NFTA_SET_ELEM_KEY_END replaces the flag notation. Fixes: 7b225d0b5c6d ("netfilter: nf_tables: add NFTA_SET_ELEM_KEY_END attribute") Signed-off-by: Pablo Neira Ayuso --- net/netfilter/nf_tables_api.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index 8b084cd669ab..ac549c5b88c2 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -5901,6 +5901,7 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, nla[NFTA_SET_ELEM_EXPIRATION] || nla[NFTA_SET_ELEM_USERDATA] || nla[NFTA_SET_ELEM_EXPR] || + nla[NFTA_SET_ELEM_KEY_END] || nla[NFTA_SET_ELEM_EXPRESSIONS])) return -EINVAL; -- cgit v1.2.3 From c485c35ff6783ccd12c160fcac6a0e504e83e0bf Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Tue, 9 Aug 2022 17:23:52 +0200 Subject: netfilter: nf_tables: possible module reference underflow in error path dst->ops is set on when nft_expr_clone() fails, but module refcount has not been bumped yet, therefore nft_expr_destroy() leads to module reference underflow. Fixes: 8cfd9b0f8515 ("netfilter: nftables: generalize set expressions support") Signed-off-by: Pablo Neira Ayuso --- net/netfilter/nf_tables_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index ac549c5b88c2..989c9782ecc3 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -5601,7 +5601,7 @@ int nft_set_elem_expr_clone(const struct nft_ctx *ctx, struct nft_set *set, err = nft_expr_clone(expr, set->exprs[i]); if (err < 0) { - nft_expr_destroy(ctx, expr); + kfree(expr); goto err_expr; } expr_array[i] = expr; -- cgit v1.2.3 From dcc2ed3912ae32fd6646264d1aa296ea3d2aa07c Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 27 Jul 2022 15:10:59 -0600 Subject: dt-bindings: Drop DT_MK_SCHEMA_FLAGS conditional selecting schema files Since commit ef8795f3f1ce ("dt-bindings: kbuild: Use DTB files for validation"), dt-mk-schema always needs a complete list of schemas, so the conditional using DT_MK_SCHEMA_FLAGS should be removed. Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20220727211100.3249417-1-robh@kernel.org --- Documentation/devicetree/bindings/Makefile | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/Makefile b/Documentation/devicetree/bindings/Makefile index c9953f86b19d..1eaccf135b30 100644 --- a/Documentation/devicetree/bindings/Makefile +++ b/Documentation/devicetree/bindings/Makefile @@ -42,9 +42,7 @@ quiet_cmd_chk_bindings = CHKDT $@ quiet_cmd_mk_schema = SCHEMA $@ cmd_mk_schema = f=$$(mktemp) ; \ - $(if $(DT_MK_SCHEMA_FLAGS), \ - printf '%s\n' $(real-prereqs), \ - $(find_all_cmd)) > $$f ; \ + $(find_all_cmd) > $$f ; \ $(DT_MK_SCHEMA) -j $(DT_MK_SCHEMA_FLAGS) @$$f > $@ ; \ rm -f $$f -- cgit v1.2.3 From f1432cd24c240cedf78c0d026631e3b10052c8e1 Mon Sep 17 00:00:00 2001 From: Alexandre Vicenzi Date: Mon, 8 Aug 2022 20:03:43 +0200 Subject: rtla: Fix tracer name The correct tracer name is timerlat and not timelat. Link: https://lore.kernel.org/linux-trace-devel/20220808180343.22262-1-alexandre.vicenzi@suse.com Signed-off-by: Alexandre Vicenzi Signed-off-by: Steven Rostedt (Google) --- Documentation/tools/rtla/rtla-timerlat-hist.rst | 2 +- tools/tracing/rtla/src/timerlat_hist.c | 2 +- tools/tracing/rtla/src/timerlat_top.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/tools/rtla/rtla-timerlat-hist.rst b/Documentation/tools/rtla/rtla-timerlat-hist.rst index e12eae1f3301..6bf7f0ca4556 100644 --- a/Documentation/tools/rtla/rtla-timerlat-hist.rst +++ b/Documentation/tools/rtla/rtla-timerlat-hist.rst @@ -33,7 +33,7 @@ EXAMPLE ======= In the example below, **rtla timerlat hist** is set to run for *10* minutes, in the cpus *0-4*, *skipping zero* only lines. Moreover, **rtla timerlat -hist** will change the priority of the *timelat* threads to run under +hist** will change the priority of the *timerlat* threads to run under *SCHED_DEADLINE* priority, with a *10us* runtime every *1ms* period. The *1ms* period is also passed to the *timerlat* tracer:: diff --git a/tools/tracing/rtla/src/timerlat_hist.c b/tools/tracing/rtla/src/timerlat_hist.c index f3ec628f5e51..4b48af8a8309 100644 --- a/tools/tracing/rtla/src/timerlat_hist.c +++ b/tools/tracing/rtla/src/timerlat_hist.c @@ -892,7 +892,7 @@ int timerlat_hist_main(int argc, char *argv[]) return_value = 0; if (trace_is_off(&tool->trace, &record->trace)) { - printf("rtla timelat hit stop tracing\n"); + printf("rtla timerlat hit stop tracing\n"); if (params->trace_output) { printf(" Saving trace to %s\n", params->trace_output); save_trace_to_file(record->trace.inst, params->trace_output); diff --git a/tools/tracing/rtla/src/timerlat_top.c b/tools/tracing/rtla/src/timerlat_top.c index 35452a1d45e9..334271935222 100644 --- a/tools/tracing/rtla/src/timerlat_top.c +++ b/tools/tracing/rtla/src/timerlat_top.c @@ -687,7 +687,7 @@ int timerlat_top_main(int argc, char *argv[]) return_value = 0; if (trace_is_off(&top->trace, &record->trace)) { - printf("rtla timelat hit stop tracing\n"); + printf("rtla timerlat hit stop tracing\n"); if (params->trace_output) { printf(" Saving trace to %s\n", params->trace_output); save_trace_to_file(record->trace.inst, params->trace_output); -- cgit v1.2.3 From ff5a55dcdb343e3db9b9fb08795b78544b032773 Mon Sep 17 00:00:00 2001 From: Ben Hutchings Date: Sat, 16 Jul 2022 15:47:08 +0200 Subject: tools/rtla: Fix command symlinks "ln -s" stores the next argument directly as the symlink target, so it needs to be a relative path. In this case, just "rtla". Link: https://lore.kernel.org/linux-trace-devel/YtLBXMI6Ui4HLIF1@decadent.org.uk Fixes: 0605bf009f18 ("rtla: Add osnoise tool") Fixes: a828cd18bc4a ("rtla: Add timerlat tool and timelart top mode") Signed-off-by: Ben Hutchings Acked-by: Daniel Bristot de Oliveira Signed-off-by: Steven Rostedt (Google) --- tools/tracing/rtla/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/tracing/rtla/Makefile b/tools/tracing/rtla/Makefile index 1bea2d16d4c1..b8fe10d941ce 100644 --- a/tools/tracing/rtla/Makefile +++ b/tools/tracing/rtla/Makefile @@ -108,9 +108,9 @@ install: doc_install $(INSTALL) rtla -m 755 $(DESTDIR)$(BINDIR) $(STRIP) $(DESTDIR)$(BINDIR)/rtla @test ! -f $(DESTDIR)$(BINDIR)/osnoise || rm $(DESTDIR)$(BINDIR)/osnoise - ln -s $(DESTDIR)$(BINDIR)/rtla $(DESTDIR)$(BINDIR)/osnoise + ln -s rtla $(DESTDIR)$(BINDIR)/osnoise @test ! -f $(DESTDIR)$(BINDIR)/timerlat || rm $(DESTDIR)$(BINDIR)/timerlat - ln -s $(DESTDIR)$(BINDIR)/rtla $(DESTDIR)$(BINDIR)/timerlat + ln -s rtla $(DESTDIR)$(BINDIR)/timerlat .PHONY: clean tarball clean: doc_clean -- cgit v1.2.3 From 1a7b22ab15ebf643e10e54ae5387afee06e39ad0 Mon Sep 17 00:00:00 2001 From: Ben Hutchings Date: Sat, 16 Jul 2022 15:48:34 +0200 Subject: tools/rtla: Build with EXTRA_{C,LD}FLAGS To allow for distributions and other builders to apply hardening policy and other customisation, append EXTRA_CFLAGS and EXTRA_LDFLAGS to the corresponding variables. Link: https://lore.kernel.org/linux-trace-devel/YtLBshz0nMQ7530H@decadent.org.uk Signed-off-by: Ben Hutchings Acked-by: Daniel Bristot de Oliveira Signed-off-by: Steven Rostedt (Google) --- tools/tracing/rtla/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/tracing/rtla/Makefile b/tools/tracing/rtla/Makefile index b8fe10d941ce..f392708c7a1e 100644 --- a/tools/tracing/rtla/Makefile +++ b/tools/tracing/rtla/Makefile @@ -30,8 +30,8 @@ WOPTS := -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2 -Wp,-D_GLIBCXX_A TRACEFS_HEADERS := $$($(PKG_CONFIG) --cflags libtracefs) -CFLAGS := -O -g -DVERSION=\"$(VERSION)\" $(FOPTS) $(MOPTS) $(WOPTS) $(TRACEFS_HEADERS) -LDFLAGS := -ggdb +CFLAGS := -O -g -DVERSION=\"$(VERSION)\" $(FOPTS) $(MOPTS) $(WOPTS) $(TRACEFS_HEADERS) $(EXTRA_CFLAGS) +LDFLAGS := -ggdb $(EXTRA_LDFLAGS) LIBS := $$($(PKG_CONFIG) --libs libtracefs) SRC := $(wildcard src/*.c) -- cgit v1.2.3 From 20aec89aac7761e3c096004f5c819aacc86fc542 Mon Sep 17 00:00:00 2001 From: "Steven Rostedt (Google)" Date: Wed, 10 Aug 2022 11:39:18 -0400 Subject: rtla: Consolidate and show all necessary libraries that failed for building When building rtla tools, if the necessary libraries are not installed (libtraceevent and libtracefs), show the ones that are missing in one consolidated output, and also show how to install them (at least for Fedora). Link: https://lore.kernel.org/all/CAHk-=wh+e1qcCnEYJ3JRDVLNCYbJ=0u+Ts5bOYZnY3mX_k-hFA@mail.gmail.com/ Link: https://lkml.kernel.org/r/20220810113918.5d19ce59@gandalf.local.home Suggested-by: Linus Torvalds Signed-off-by: Steven Rostedt (Google) --- tools/tracing/rtla/Makefile | 62 ++++++++++++++++++++++++++------------------- 1 file changed, 36 insertions(+), 26 deletions(-) diff --git a/tools/tracing/rtla/Makefile b/tools/tracing/rtla/Makefile index f392708c7a1e..22e28b76f800 100644 --- a/tools/tracing/rtla/Makefile +++ b/tools/tracing/rtla/Makefile @@ -61,40 +61,50 @@ endif LIBTRACEEVENT_MIN_VERSION = 1.5 LIBTRACEFS_MIN_VERSION = 1.3 +.PHONY: all warnings show_warnings +all: warnings rtla + TEST_LIBTRACEEVENT = $(shell sh -c "$(PKG_CONFIG) --atleast-version $(LIBTRACEEVENT_MIN_VERSION) libtraceevent > /dev/null 2>&1 || echo n") ifeq ("$(TEST_LIBTRACEEVENT)", "n") -.PHONY: warning_traceevent -warning_traceevent: - @echo "********************************************" - @echo "** NOTICE: libtraceevent version $(LIBTRACEEVENT_MIN_VERSION) or higher not found" - @echo "**" - @echo "** Consider installing the latest libtraceevent from your" - @echo "** distribution, e.g., 'dnf install libtraceevent' on Fedora," - @echo "** or from source:" - @echo "**" - @echo "** https://git.kernel.org/pub/scm/libs/libtrace/libtraceevent.git/ " - @echo "**" - @echo "********************************************" +WARNINGS = show_warnings +MISSING_LIBS += echo "** libtraceevent version $(LIBTRACEEVENT_MIN_VERSION) or higher"; +MISSING_PACKAGES += "libtraceevent-devel" +MISSING_SOURCE += echo "** https://git.kernel.org/pub/scm/libs/libtrace/libtraceevent.git/ "; endif TEST_LIBTRACEFS = $(shell sh -c "$(PKG_CONFIG) --atleast-version $(LIBTRACEFS_MIN_VERSION) libtracefs > /dev/null 2>&1 || echo n") ifeq ("$(TEST_LIBTRACEFS)", "n") -.PHONY: warning_tracefs -warning_tracefs: - @echo "********************************************" - @echo "** NOTICE: libtracefs version $(LIBTRACEFS_MIN_VERSION) or higher not found" - @echo "**" - @echo "** Consider installing the latest libtracefs from your" - @echo "** distribution, e.g., 'dnf install libtracefs' on Fedora," - @echo "** or from source:" - @echo "**" - @echo "** https://git.kernel.org/pub/scm/libs/libtrace/libtracefs.git/ " - @echo "**" - @echo "********************************************" +WARNINGS = show_warnings +MISSING_LIBS += echo "** libtracefs version $(LIBTRACEFS_MIN_VERSION) or higher"; +MISSING_PACKAGES += "libtracefs-devel" +MISSING_SOURCE += echo "** https://git.kernel.org/pub/scm/libs/libtrace/libtracefs.git/ "; endif -.PHONY: all -all: rtla +define show_dependencies + @echo "********************************************"; \ + echo "** NOTICE: Failed build dependencies"; \ + echo "**"; \ + echo "** Required Libraries:"; \ + $(MISSING_LIBS) \ + echo "**"; \ + echo "** Consider installing the latest libtracefs from your"; \ + echo "** distribution, e.g., 'dnf install $(MISSING_PACKAGES)' on Fedora,"; \ + echo "** or from source:"; \ + echo "**"; \ + $(MISSING_SOURCE) \ + echo "**"; \ + echo "********************************************" +endef + +show_warnings: + $(call show_dependencies); + +ifneq ("$(WARNINGS)", "") +ERROR_OUT = $(error Please add the necessary dependencies) + +warnings: $(WARNINGS) + $(ERROR_OUT) +endif rtla: $(OBJ) $(CC) -o rtla $(LDFLAGS) $(OBJ) $(LIBS) -- cgit v1.2.3 From 96964352e21962f5e51ecad87527ae9b6fec9670 Mon Sep 17 00:00:00 2001 From: Jiapeng Chong Date: Thu, 21 Jul 2022 11:18:41 +0800 Subject: fs/ntfs3: Remove unused function wnd_bits Since the function wnd_bits is defined but not called in any file, it is a useless function, and we delete it in view of the brevity of the code. Remove some warnings found by running scripts/kernel-doc, which is caused by using 'make W=1'. fs/ntfs3/bitmap.c:54:19: warning: unused function 'wnd_bits' [-Wunused-function]. Reported-by: Abaci Robot Signed-off-by: Jiapeng Chong Signed-off-by: Konstantin Komarov --- fs/ntfs3/bitmap.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/fs/ntfs3/bitmap.c b/fs/ntfs3/bitmap.c index bb9ebb160227..5d44ceac855b 100644 --- a/fs/ntfs3/bitmap.c +++ b/fs/ntfs3/bitmap.c @@ -51,11 +51,6 @@ void ntfs3_exit_bitmap(void) kmem_cache_destroy(ntfs_enode_cachep); } -static inline u32 wnd_bits(const struct wnd_bitmap *wnd, size_t i) -{ - return i + 1 == wnd->nwnd ? wnd->bits_last : wnd->sb->s_blocksize * 8; -} - /* * wnd_scan * -- cgit v1.2.3 From d4073595d0c61463ec3a87411b19e2a90f76d3f8 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 8 Aug 2022 11:34:41 +0300 Subject: fs/ntfs3: uninitialized variable in ntfs_set_acl_ex() The goto out calls kfree(value) on an uninitialized pointer. Just return directly as the other error paths do. Fixes: 460bbf2990b3 ("fs/ntfs3: Do not change mode if ntfs_set_ea failed") Signed-off-by: Dan Carpenter Signed-off-by: Konstantin Komarov --- fs/ntfs3/xattr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/ntfs3/xattr.c b/fs/ntfs3/xattr.c index 02f6a933ee79..5bdff12a1232 100644 --- a/fs/ntfs3/xattr.c +++ b/fs/ntfs3/xattr.c @@ -568,7 +568,7 @@ static noinline int ntfs_set_acl_ex(struct user_namespace *mnt_userns, err = posix_acl_update_mode(mnt_userns, inode, &mode, &acl); if (err) - goto out; + return err; } name = XATTR_NAME_POSIX_ACL_ACCESS; name_len = sizeof(XATTR_NAME_POSIX_ACL_ACCESS) - 1; -- cgit v1.2.3 From 2e828582b81f5bc76a4fe8e7812df259ab208302 Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Tue, 9 Aug 2022 11:07:00 +0300 Subject: perf parse-events: Fix segfault when event parser gets an error parse_events() is often called with parse_events_error set to NULL. Make parse_events_error__handle() not segfault in that case. A subsequent patch changes to avoid passing NULL in the first place. Fixes: 43eb05d066795bdf ("perf tests: Support 'Track with sched_switch' test for hybrid") Signed-off-by: Adrian Hunter Cc: Ian Rogers Cc: Jin Yao Cc: Jiri Olsa Cc: Namhyung Kim Link: https://lore.kernel.org/r/20220809080702.6921-2-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/parse-events.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 206c76623c06..dfc7d7a0ec4e 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -2256,9 +2256,12 @@ void parse_events_error__exit(struct parse_events_error *err) void parse_events_error__handle(struct parse_events_error *err, int idx, char *str, char *help) { - if (WARN(!str, "WARNING: failed to provide error string\n")) { - free(help); - return; + if (WARN(!str, "WARNING: failed to provide error string\n")) + goto out_free; + if (!err) { + /* Assume caller does not want message printed */ + pr_debug("event syntax error: %s\n", str); + goto out_free; } switch (err->num_errors) { case 0: @@ -2284,6 +2287,11 @@ void parse_events_error__handle(struct parse_events_error *err, int idx, break; } err->num_errors++; + return; + +out_free: + free(str); + free(help); } #define MAX_WIDTH 1000 -- cgit v1.2.3 From 1da1d60774014137d776d0400fdf2f1779d8d4d5 Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Tue, 9 Aug 2022 11:07:01 +0300 Subject: perf tests: Fix Track with sched_switch test for hybrid case If cpu_core PMU event fails to parse, try also cpu_atom PMU event when parsing cycles event. Fixes: 43eb05d066795bdf ("perf tests: Support 'Track with sched_switch' test for hybrid") Signed-off-by: Adrian Hunter Cc: Ian Rogers Cc: Jin Yao Cc: Jiri Olsa Cc: Namhyung Kim Link: https://lore.kernel.org/r/20220809080702.6921-3-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/switch-tracking.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/tools/perf/tests/switch-tracking.c b/tools/perf/tests/switch-tracking.c index 0c0c2328bf4e..6f53bee33f7c 100644 --- a/tools/perf/tests/switch-tracking.c +++ b/tools/perf/tests/switch-tracking.c @@ -324,6 +324,7 @@ out_free_nodes: static int test__switch_tracking(struct test_suite *test __maybe_unused, int subtest __maybe_unused) { const char *sched_switch = "sched:sched_switch"; + const char *cycles = "cycles:u"; struct switch_tracking switch_tracking = { .tids = NULL, }; struct record_opts opts = { .mmap_pages = UINT_MAX, @@ -372,12 +373,19 @@ static int test__switch_tracking(struct test_suite *test __maybe_unused, int sub cpu_clocks_evsel = evlist__last(evlist); /* Second event */ - if (perf_pmu__has_hybrid()) - err = parse_events(evlist, "cpu_core/cycles/u", NULL); - else - err = parse_events(evlist, "cycles:u", NULL); + if (perf_pmu__has_hybrid()) { + cycles = "cpu_core/cycles/u"; + err = parse_events(evlist, cycles, NULL); + if (err) { + cycles = "cpu_atom/cycles/u"; + pr_debug("Trying %s\n", cycles); + err = parse_events(evlist, cycles, NULL); + } + } else { + err = parse_events(evlist, cycles, NULL); + } if (err) { - pr_debug("Failed to parse event cycles:u\n"); + pr_debug("Failed to parse event %s\n", cycles); goto out_err; } -- cgit v1.2.3 From 806731a9465b42aaf887cbaf8bfee7eccc9417de Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Tue, 9 Aug 2022 11:07:02 +0300 Subject: perf tools: Do not pass NULL to parse_events() Many cases do not use the extra error information provided by parse_events and instead pass NULL as the struct parse_events_error pointer. Add a wrapper for those cases so that the pointer is never NULL. Signed-off-by: Adrian Hunter Cc: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Link: https://lore.kernel.org/r/20220809080702.6921-4-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/arm/util/cs-etm.c | 2 +- tools/perf/arch/arm64/util/arm-spe.c | 2 +- tools/perf/arch/x86/tests/intel-cqm.c | 2 +- tools/perf/arch/x86/util/intel-bts.c | 2 +- tools/perf/arch/x86/util/intel-pt.c | 2 +- tools/perf/arch/x86/util/iostat.c | 2 +- tools/perf/arch/x86/util/topdown.c | 2 +- tools/perf/tests/code-reading.c | 2 +- tools/perf/tests/event-times.c | 2 +- tools/perf/tests/evsel-roundtrip-name.c | 4 ++-- tools/perf/tests/hists_cumulate.c | 2 +- tools/perf/tests/hists_filter.c | 4 ++-- tools/perf/tests/hists_link.c | 4 ++-- tools/perf/tests/hists_output.c | 2 +- tools/perf/tests/keep-tracking.c | 4 ++-- tools/perf/tests/perf-time-to-tsc.c | 2 +- tools/perf/tests/switch-tracking.c | 12 ++++++------ tools/perf/util/bpf-loader.c | 2 +- tools/perf/util/parse-events.c | 18 ++++++++++++------ tools/perf/util/parse-events.h | 4 ++++ tools/perf/util/perf_api_probe.c | 2 +- tools/perf/util/record.c | 2 +- 22 files changed, 45 insertions(+), 35 deletions(-) diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c index 1b54638d53b0..a346d5f3dafa 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -438,7 +438,7 @@ static int cs_etm_recording_options(struct auxtrace_record *itr, if (opts->full_auxtrace) { struct evsel *tracking_evsel; - err = parse_events(evlist, "dummy:u", NULL); + err = parse_event(evlist, "dummy:u"); if (err) goto out; diff --git a/tools/perf/arch/arm64/util/arm-spe.c b/tools/perf/arch/arm64/util/arm-spe.c index 6f4db2ac5420..d4c234076541 100644 --- a/tools/perf/arch/arm64/util/arm-spe.c +++ b/tools/perf/arch/arm64/util/arm-spe.c @@ -257,7 +257,7 @@ static int arm_spe_recording_options(struct auxtrace_record *itr, evsel__set_sample_bit(arm_spe_evsel, PHYS_ADDR); /* Add dummy event to keep tracking */ - err = parse_events(evlist, "dummy:u", NULL); + err = parse_event(evlist, "dummy:u"); if (err) return err; diff --git a/tools/perf/arch/x86/tests/intel-cqm.c b/tools/perf/arch/x86/tests/intel-cqm.c index cb5b2c6c3b3b..360a082fc928 100644 --- a/tools/perf/arch/x86/tests/intel-cqm.c +++ b/tools/perf/arch/x86/tests/intel-cqm.c @@ -56,7 +56,7 @@ int test__intel_cqm_count_nmi_context(struct test_suite *test __maybe_unused, in return TEST_FAIL; } - ret = parse_events(evlist, "intel_cqm/llc_occupancy/", NULL); + ret = parse_event(evlist, "intel_cqm/llc_occupancy/"); if (ret) { pr_debug("parse_events failed, is \"intel_cqm/llc_occupancy/\" available?\n"); err = TEST_SKIP; diff --git a/tools/perf/arch/x86/util/intel-bts.c b/tools/perf/arch/x86/util/intel-bts.c index bcccfbade5c6..439c2956f3e7 100644 --- a/tools/perf/arch/x86/util/intel-bts.c +++ b/tools/perf/arch/x86/util/intel-bts.c @@ -233,7 +233,7 @@ static int intel_bts_recording_options(struct auxtrace_record *itr, struct evsel *tracking_evsel; int err; - err = parse_events(evlist, "dummy:u", NULL); + err = parse_event(evlist, "dummy:u"); if (err) return err; diff --git a/tools/perf/arch/x86/util/intel-pt.c b/tools/perf/arch/x86/util/intel-pt.c index 06c2cdfd8f2f..13933020a79e 100644 --- a/tools/perf/arch/x86/util/intel-pt.c +++ b/tools/perf/arch/x86/util/intel-pt.c @@ -426,7 +426,7 @@ static int intel_pt_track_switches(struct evlist *evlist) if (!evlist__can_select_event(evlist, sched_switch)) return -EPERM; - err = parse_events(evlist, sched_switch, NULL); + err = parse_event(evlist, sched_switch); if (err) { pr_debug2("%s: failed to parse %s, error %d\n", __func__, sched_switch, err); diff --git a/tools/perf/arch/x86/util/iostat.c b/tools/perf/arch/x86/util/iostat.c index 792cd75ade33..404de795ec0b 100644 --- a/tools/perf/arch/x86/util/iostat.c +++ b/tools/perf/arch/x86/util/iostat.c @@ -316,7 +316,7 @@ static int iostat_event_group(struct evlist *evl, sprintf(iostat_cmd, iostat_cmd_template, list->rps[idx]->pmu_idx, list->rps[idx]->pmu_idx, list->rps[idx]->pmu_idx, list->rps[idx]->pmu_idx); - ret = parse_events(evl, iostat_cmd, NULL); + ret = parse_event(evl, iostat_cmd); if (ret) goto err; } diff --git a/tools/perf/arch/x86/util/topdown.c b/tools/perf/arch/x86/util/topdown.c index 67c524324125..54810f9acd6f 100644 --- a/tools/perf/arch/x86/util/topdown.c +++ b/tools/perf/arch/x86/util/topdown.c @@ -122,5 +122,5 @@ int topdown_parse_events(struct evlist *evlist) topdown_events = TOPDOWN_L1_EVENTS; } - return parse_events(evlist, topdown_events, NULL); + return parse_event(evlist, topdown_events); } diff --git a/tools/perf/tests/code-reading.c b/tools/perf/tests/code-reading.c index 5610767b407f..95feb6ef34a0 100644 --- a/tools/perf/tests/code-reading.c +++ b/tools/perf/tests/code-reading.c @@ -638,7 +638,7 @@ static int do_test_code_reading(bool try_kcore) str = do_determine_event(excl_kernel); pr_debug("Parsing event '%s'\n", str); - ret = parse_events(evlist, str, NULL); + ret = parse_event(evlist, str); if (ret < 0) { pr_debug("parse_events failed\n"); goto out_put; diff --git a/tools/perf/tests/event-times.c b/tools/perf/tests/event-times.c index 7606eb3df92f..e155f0e0e04d 100644 --- a/tools/perf/tests/event-times.c +++ b/tools/perf/tests/event-times.c @@ -174,7 +174,7 @@ static int test_times(int (attach)(struct evlist *), goto out_err; } - err = parse_events(evlist, "cpu-clock:u", NULL); + err = parse_event(evlist, "cpu-clock:u"); if (err) { pr_debug("failed to parse event cpu-clock:u\n"); goto out_err; diff --git a/tools/perf/tests/evsel-roundtrip-name.c b/tools/perf/tests/evsel-roundtrip-name.c index 9d3c64974f77..e94fed901992 100644 --- a/tools/perf/tests/evsel-roundtrip-name.c +++ b/tools/perf/tests/evsel-roundtrip-name.c @@ -27,7 +27,7 @@ static int perf_evsel__roundtrip_cache_name_test(void) for (i = 0; i < PERF_COUNT_HW_CACHE_RESULT_MAX; i++) { __evsel__hw_cache_type_op_res_name(type, op, i, name, sizeof(name)); - err = parse_events(evlist, name, NULL); + err = parse_event(evlist, name); if (err) ret = err; } @@ -75,7 +75,7 @@ static int __perf_evsel__name_array_test(const char *const names[], int nr_names return -ENOMEM; for (i = 0; i < nr_names; ++i) { - err = parse_events(evlist, names[i], NULL); + err = parse_event(evlist, names[i]); if (err) { pr_debug("failed to parse event '%s', err %d\n", names[i], err); diff --git a/tools/perf/tests/hists_cumulate.c b/tools/perf/tests/hists_cumulate.c index 17f4fcd6bdce..b42d37ff2399 100644 --- a/tools/perf/tests/hists_cumulate.c +++ b/tools/perf/tests/hists_cumulate.c @@ -706,7 +706,7 @@ static int test__hists_cumulate(struct test_suite *test __maybe_unused, int subt TEST_ASSERT_VAL("No memory", evlist); - err = parse_events(evlist, "cpu-clock", NULL); + err = parse_event(evlist, "cpu-clock"); if (err) goto out; err = TEST_FAIL; diff --git a/tools/perf/tests/hists_filter.c b/tools/perf/tests/hists_filter.c index 08cbeb9e39ae..8e1ceeb9b7b6 100644 --- a/tools/perf/tests/hists_filter.c +++ b/tools/perf/tests/hists_filter.c @@ -111,10 +111,10 @@ static int test__hists_filter(struct test_suite *test __maybe_unused, int subtes TEST_ASSERT_VAL("No memory", evlist); - err = parse_events(evlist, "cpu-clock", NULL); + err = parse_event(evlist, "cpu-clock"); if (err) goto out; - err = parse_events(evlist, "task-clock", NULL); + err = parse_event(evlist, "task-clock"); if (err) goto out; err = TEST_FAIL; diff --git a/tools/perf/tests/hists_link.c b/tools/perf/tests/hists_link.c index c575e13a850d..14b2ff808b5e 100644 --- a/tools/perf/tests/hists_link.c +++ b/tools/perf/tests/hists_link.c @@ -276,10 +276,10 @@ static int test__hists_link(struct test_suite *test __maybe_unused, int subtest if (evlist == NULL) return -ENOMEM; - err = parse_events(evlist, "cpu-clock", NULL); + err = parse_event(evlist, "cpu-clock"); if (err) goto out; - err = parse_events(evlist, "task-clock", NULL); + err = parse_event(evlist, "task-clock"); if (err) goto out; diff --git a/tools/perf/tests/hists_output.c b/tools/perf/tests/hists_output.c index 0bde4a768c15..62b0093253e3 100644 --- a/tools/perf/tests/hists_output.c +++ b/tools/perf/tests/hists_output.c @@ -593,7 +593,7 @@ static int test__hists_output(struct test_suite *test __maybe_unused, int subtes TEST_ASSERT_VAL("No memory", evlist); - err = parse_events(evlist, "cpu-clock", NULL); + err = parse_event(evlist, "cpu-clock"); if (err) goto out; err = TEST_FAIL; diff --git a/tools/perf/tests/keep-tracking.c b/tools/perf/tests/keep-tracking.c index dd2067312452..8f4f9b632e1e 100644 --- a/tools/perf/tests/keep-tracking.c +++ b/tools/perf/tests/keep-tracking.c @@ -89,8 +89,8 @@ static int test__keep_tracking(struct test_suite *test __maybe_unused, int subte perf_evlist__set_maps(&evlist->core, cpus, threads); - CHECK__(parse_events(evlist, "dummy:u", NULL)); - CHECK__(parse_events(evlist, "cycles:u", NULL)); + CHECK__(parse_event(evlist, "dummy:u")); + CHECK__(parse_event(evlist, "cycles:u")); evlist__config(evlist, &opts, NULL); diff --git a/tools/perf/tests/perf-time-to-tsc.c b/tools/perf/tests/perf-time-to-tsc.c index 7c7d20fc503a..26ce30a35191 100644 --- a/tools/perf/tests/perf-time-to-tsc.c +++ b/tools/perf/tests/perf-time-to-tsc.c @@ -100,7 +100,7 @@ static int test__perf_time_to_tsc(struct test_suite *test __maybe_unused, int su perf_evlist__set_maps(&evlist->core, cpus, threads); - CHECK__(parse_events(evlist, "cycles:u", NULL)); + CHECK__(parse_event(evlist, "cycles:u")); evlist__config(evlist, &opts, NULL); diff --git a/tools/perf/tests/switch-tracking.c b/tools/perf/tests/switch-tracking.c index 6f53bee33f7c..2d46af9ef935 100644 --- a/tools/perf/tests/switch-tracking.c +++ b/tools/perf/tests/switch-tracking.c @@ -364,7 +364,7 @@ static int test__switch_tracking(struct test_suite *test __maybe_unused, int sub perf_evlist__set_maps(&evlist->core, cpus, threads); /* First event */ - err = parse_events(evlist, "cpu-clock:u", NULL); + err = parse_event(evlist, "cpu-clock:u"); if (err) { pr_debug("Failed to parse event dummy:u\n"); goto out_err; @@ -375,14 +375,14 @@ static int test__switch_tracking(struct test_suite *test __maybe_unused, int sub /* Second event */ if (perf_pmu__has_hybrid()) { cycles = "cpu_core/cycles/u"; - err = parse_events(evlist, cycles, NULL); + err = parse_event(evlist, cycles); if (err) { cycles = "cpu_atom/cycles/u"; pr_debug("Trying %s\n", cycles); - err = parse_events(evlist, cycles, NULL); + err = parse_event(evlist, cycles); } } else { - err = parse_events(evlist, cycles, NULL); + err = parse_event(evlist, cycles); } if (err) { pr_debug("Failed to parse event %s\n", cycles); @@ -398,7 +398,7 @@ static int test__switch_tracking(struct test_suite *test __maybe_unused, int sub goto out; } - err = parse_events(evlist, sched_switch, NULL); + err = parse_event(evlist, sched_switch); if (err) { pr_debug("Failed to parse event %s\n", sched_switch); goto out_err; @@ -428,7 +428,7 @@ static int test__switch_tracking(struct test_suite *test __maybe_unused, int sub evsel__set_sample_bit(cycles_evsel, TIME); /* Fourth event */ - err = parse_events(evlist, "dummy:u", NULL); + err = parse_event(evlist, "dummy:u"); if (err) { pr_debug("Failed to parse event dummy:u\n"); goto out_err; diff --git a/tools/perf/util/bpf-loader.c b/tools/perf/util/bpf-loader.c index d2c9b09ddb48..e2052f4fed33 100644 --- a/tools/perf/util/bpf-loader.c +++ b/tools/perf/util/bpf-loader.c @@ -1879,7 +1879,7 @@ struct evsel *bpf__setup_output_event(struct evlist *evlist, const char *name) if (asprintf(&event_definition, "bpf-output/no-inherit=1,name=%s/", name) < 0) return ERR_PTR(-ENOMEM); - err = parse_events(evlist, event_definition, NULL); + err = parse_event(evlist, event_definition); free(event_definition); if (err) { diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index dfc7d7a0ec4e..f05e15acd33f 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -2240,6 +2240,17 @@ int __parse_events(struct evlist *evlist, const char *str, return ret; } +int parse_event(struct evlist *evlist, const char *str) +{ + struct parse_events_error err; + int ret; + + parse_events_error__init(&err); + ret = parse_events(evlist, str, &err); + parse_events_error__exit(&err); + return ret; +} + void parse_events_error__init(struct parse_events_error *err) { bzero(err, sizeof(*err)); @@ -2256,13 +2267,8 @@ void parse_events_error__exit(struct parse_events_error *err) void parse_events_error__handle(struct parse_events_error *err, int idx, char *str, char *help) { - if (WARN(!str, "WARNING: failed to provide error string\n")) - goto out_free; - if (!err) { - /* Assume caller does not want message printed */ - pr_debug("event syntax error: %s\n", str); + if (WARN(!str || !err, "WARNING: failed to provide error string or struct\n")) goto out_free; - } switch (err->num_errors) { case 0: err->idx = idx; diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index ba9fa3ddaf6e..7e6a601d9cd0 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -24,15 +24,19 @@ const char *event_type(int type); int parse_events_option(const struct option *opt, const char *str, int unset); int parse_events_option_new_evlist(const struct option *opt, const char *str, int unset); +__attribute__((nonnull(1, 2, 3))) int __parse_events(struct evlist *evlist, const char *str, struct parse_events_error *error, struct perf_pmu *fake_pmu); +__attribute__((nonnull)) static inline int parse_events(struct evlist *evlist, const char *str, struct parse_events_error *err) { return __parse_events(evlist, str, err, NULL); } +int parse_event(struct evlist *evlist, const char *str); + int parse_events_terms(struct list_head *terms, const char *str); int parse_filter(const struct option *opt, const char *str, int unset); int exclude_perf(const struct option *opt, const char *arg, int unset); diff --git a/tools/perf/util/perf_api_probe.c b/tools/perf/util/perf_api_probe.c index c28dd50bd571..e1e2d701599c 100644 --- a/tools/perf/util/perf_api_probe.c +++ b/tools/perf/util/perf_api_probe.c @@ -23,7 +23,7 @@ static int perf_do_probe_api(setup_probe_fn_t fn, struct perf_cpu cpu, const cha if (!evlist) return -ENOMEM; - if (parse_events(evlist, str, NULL)) + if (parse_event(evlist, str)) goto out_delete; evsel = evlist__first(evlist); diff --git a/tools/perf/util/record.c b/tools/perf/util/record.c index b529636ab3ea..7b58f6c7c69d 100644 --- a/tools/perf/util/record.c +++ b/tools/perf/util/record.c @@ -238,7 +238,7 @@ bool evlist__can_select_event(struct evlist *evlist, const char *str) if (!temp_evlist) return false; - err = parse_events(temp_evlist, str, NULL); + err = parse_event(temp_evlist, str); if (err) goto out_delete; -- cgit v1.2.3 From c08b4848f596fd95543197463b5162bd7bab2442 Mon Sep 17 00:00:00 2001 From: Chen Lifu Date: Wed, 15 Jun 2022 09:47:14 +0800 Subject: riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit Since commit 5d8544e2d007 ("RISC-V: Generic library routines and assembly") and commit ebcbd75e3962 ("riscv: Fix the bug in memory access fixup code"), if __clear_user and __copy_user return from an fixup branch, CSR_STATUS SR_SUM bit will be set, it is a vulnerability, so that S-mode memory accesses to pages that are accessible by U-mode will success. Disable S-mode access to U-mode memory should clear SR_SUM bit. Fixes: 5d8544e2d007 ("RISC-V: Generic library routines and assembly") Fixes: ebcbd75e3962 ("riscv: Fix the bug in memory access fixup code") Signed-off-by: Chen Lifu Reviewed-by: Ben Dooks Link: https://lore.kernel.org/r/20220615014714.1650349-1-chenlifu@huawei.com Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt --- arch/riscv/lib/uaccess.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S index 8c475f4da308..ec486e5369d9 100644 --- a/arch/riscv/lib/uaccess.S +++ b/arch/riscv/lib/uaccess.S @@ -175,7 +175,7 @@ ENTRY(__asm_copy_from_user) /* Exception fixup code */ 10: /* Disable access to user memory */ - csrs CSR_STATUS, t6 + csrc CSR_STATUS, t6 mv a0, t5 ret ENDPROC(__asm_copy_to_user) @@ -227,7 +227,7 @@ ENTRY(__clear_user) /* Exception fixup code */ 11: /* Disable access to user memory */ - csrs CSR_STATUS, t6 + csrc CSR_STATUS, t6 mv a0, a1 ret ENDPROC(__clear_user) -- cgit v1.2.3 From 487ceef03895285f44ab26f6cf0c19b21b73d40d Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 9 Aug 2022 15:45:56 -0600 Subject: dt-bindings: pinctrl: qcom,ipq6018: Fix example 'gpio-ranges' size 'gpio-ranges' entries have a fixed size of 1 phandle plus arg 3 cells. The qcom,ipq6018-pinctrl example is a cell short: Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.example.dtb: pinctrl@1000000: gpio-ranges:0: [1, 0, 80] is too short From schema: /usr/local/lib/python3.10/dist-packages/dtschema/schemas/gpio/gpio.yaml Signed-off-by: Rob Herring Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220809214556.2489822-1-robh@kernel.org --- Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml index b83c7f476e19..931e5c190ead 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml @@ -144,7 +144,7 @@ examples: #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 80>; + gpio-ranges = <&tlmm 0 0 80>; serial3-pinmux { pins = "gpio44", "gpio45"; -- cgit v1.2.3 From 2ac2920cd8d9334e24bfd30d518010f99077a947 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 28 Jul 2022 13:08:10 -0600 Subject: dt-bindings: mailbox: arm,mhu: Make secure interrupt optional The secure interrupt is only useful to secure world, therefore for NS users it shouldn't be required. Make it optional. This fixes a warning on Arm Juno board: mhu@2b1f0000: interrupts: [[0, 36, 4], [0, 35, 4]] is too short Signed-off-by: Rob Herring Reviewed-by: Sudeep Holla Link: https://lore.kernel.org/r/20220728190810.1290857-1-robh@kernel.org --- Documentation/devicetree/bindings/mailbox/arm,mhu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml index bd49c201477d..d9a4f4a02d7c 100644 --- a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml +++ b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml @@ -57,6 +57,7 @@ properties: maxItems: 1 interrupts: + minItems: 2 items: - description: low-priority non-secure - description: high-priority non-secure -- cgit v1.2.3 From 773891ffd4d628d05c4e22f34541e4779ee7a076 Mon Sep 17 00:00:00 2001 From: Paulo Alcantara Date: Mon, 8 Aug 2022 13:41:18 -0300 Subject: cifs: fix lock length calculation The lock length was wrongly set to 0 when fl_end == OFFSET_MAX, thus failing to lock the whole file when l_start=0 and l_len=0. This fixes test 2 from cthon04. Before patch: $ ./cthon04/lock/tlocklfs -t 2 /mnt Creating parent/child synchronization pipes. Test #1 - Test regions of an unlocked file. Parent: 1.1 - F_TEST [ 0, 1] PASSED. Parent: 1.2 - F_TEST [ 0, ENDING] PASSED. Parent: 1.3 - F_TEST [ 0,7fffffffffffffff] PASSED. Parent: 1.4 - F_TEST [ 1, 1] PASSED. Parent: 1.5 - F_TEST [ 1, ENDING] PASSED. Parent: 1.6 - F_TEST [ 1,7fffffffffffffff] PASSED. Parent: 1.7 - F_TEST [7fffffffffffffff, 1] PASSED. Parent: 1.8 - F_TEST [7fffffffffffffff, ENDING] PASSED. Parent: 1.9 - F_TEST [7fffffffffffffff,7fffffffffffffff] PASSED. Test #2 - Try to lock the whole file. Parent: 2.0 - F_TLOCK [ 0, ENDING] PASSED. Child: 2.1 - F_TEST [ 0, 1] FAILED! Child: **** Expected EACCES, returned success... Child: **** Probably implementation error. ** CHILD pass 1 results: 0/0 pass, 0/0 warn, 1/1 fail (pass/total). Parent: Child died ** PARENT pass 1 results: 10/10 pass, 0/0 warn, 0/0 fail (pass/total). After patch: $ ./cthon04/lock/tlocklfs -t 2 /mnt Creating parent/child synchronization pipes. Test #2 - Try to lock the whole file. Parent: 2.0 - F_TLOCK [ 0, ENDING] PASSED. Child: 2.1 - F_TEST [ 0, 1] PASSED. Child: 2.2 - F_TEST [ 0, ENDING] PASSED. Child: 2.3 - F_TEST [ 0,7fffffffffffffff] PASSED. Child: 2.4 - F_TEST [ 1, 1] PASSED. Child: 2.5 - F_TEST [ 1, ENDING] PASSED. Child: 2.6 - F_TEST [ 1,7fffffffffffffff] PASSED. Child: 2.7 - F_TEST [7fffffffffffffff, 1] PASSED. Child: 2.8 - F_TEST [7fffffffffffffff, ENDING] PASSED. Child: 2.9 - F_TEST [7fffffffffffffff,7fffffffffffffff] PASSED. Parent: 2.10 - F_ULOCK [ 0, ENDING] PASSED. ** PARENT pass 1 results: 2/2 pass, 0/0 warn, 0/0 fail (pass/total). ** CHILD pass 1 results: 9/9 pass, 0/0 warn, 0/0 fail (pass/total). Fixes: d80c69846ddf ("cifs: fix signed integer overflow when fl_end is OFFSET_MAX") Reported-by: Xiaoli Feng Cc: Signed-off-by: Paulo Alcantara (SUSE) Reviewed-by: Ronnie Sahlberg Signed-off-by: Steve French --- fs/cifs/cifsglob.h | 4 ++-- fs/cifs/file.c | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/fs/cifs/cifsglob.h b/fs/cifs/cifsglob.h index 3070407cafa7..a93024eaf251 100644 --- a/fs/cifs/cifsglob.h +++ b/fs/cifs/cifsglob.h @@ -2132,9 +2132,9 @@ static inline bool cifs_is_referral_server(struct cifs_tcon *tcon, return is_tcon_dfs(tcon) || (ref && (ref->flags & DFSREF_REFERRAL_SERVER)); } -static inline u64 cifs_flock_len(struct file_lock *fl) +static inline u64 cifs_flock_len(const struct file_lock *fl) { - return fl->fl_end == OFFSET_MAX ? 0 : fl->fl_end - fl->fl_start + 1; + return (u64)fl->fl_end - fl->fl_start + 1; } static inline size_t ntlmssp_workstation_name_size(const struct cifs_ses *ses) diff --git a/fs/cifs/file.c b/fs/cifs/file.c index 85f2abcb2795..09975bd7d860 100644 --- a/fs/cifs/file.c +++ b/fs/cifs/file.c @@ -1936,9 +1936,9 @@ int cifs_lock(struct file *file, int cmd, struct file_lock *flock) rc = -EACCES; xid = get_xid(); - cifs_dbg(FYI, "Lock parm: 0x%x flockflags: 0x%x flocktype: 0x%x start: %lld end: %lld\n", - cmd, flock->fl_flags, flock->fl_type, - flock->fl_start, flock->fl_end); + cifs_dbg(FYI, "%s: %pD2 cmd=0x%x type=0x%x flags=0x%x r=%lld:%lld\n", __func__, file, cmd, + flock->fl_flags, flock->fl_type, (long long)flock->fl_start, + (long long)flock->fl_end); cfile = (struct cifsFileInfo *)file->private_data; tcon = tlink_tcon(cfile->tlink); -- cgit v1.2.3 From 031d166f968efba6e4f091ff75d0bb5206bb3918 Mon Sep 17 00:00:00 2001 From: hexiaole Date: Tue, 9 Aug 2022 13:23:46 -0700 Subject: xfs: fix inode reservation space for removing transaction In 'fs/xfs/libxfs/xfs_trans_resv.c', the comment for transaction of removing a directory entry writes: /* fs/xfs/libxfs/xfs_trans_resv.c begin */ /* * For removing a directory entry we can modify: * the parent directory inode: inode size * the removed inode: inode size ... xfs_calc_remove_reservation( struct xfs_mount *mp) { return XFS_DQUOT_LOGRES(mp) + xfs_calc_iunlink_add_reservation(mp) + max((xfs_calc_inode_res(mp, 1) + ... /* fs/xfs/libxfs/xfs_trans_resv.c end */ There has 2 inode size of space to be reserverd, but the actual code for inode reservation space writes. There only count for 1 inode size to be reserved in 'xfs_calc_inode_res(mp, 1)', rather than 2. Signed-off-by: hexiaole Reviewed-by: Darrick J. Wong [djwong: remove redundant code citations] Signed-off-by: Darrick J. Wong --- fs/xfs/libxfs/xfs_trans_resv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/xfs/libxfs/xfs_trans_resv.c b/fs/xfs/libxfs/xfs_trans_resv.c index e9913c2c5a24..2c4ad6e4bb14 100644 --- a/fs/xfs/libxfs/xfs_trans_resv.c +++ b/fs/xfs/libxfs/xfs_trans_resv.c @@ -515,7 +515,7 @@ xfs_calc_remove_reservation( { return XFS_DQUOT_LOGRES(mp) + xfs_calc_iunlink_add_reservation(mp) + - max((xfs_calc_inode_res(mp, 1) + + max((xfs_calc_inode_res(mp, 2) + xfs_calc_buf_res(XFS_DIROP_LOG_COUNT(mp), XFS_FSB_TO_B(mp, 1))), (xfs_calc_buf_res(4, mp->m_sb.sb_sectsize) + -- cgit v1.2.3 From cd04345598b7c191d41574bc9da3fe435dc65605 Mon Sep 17 00:00:00 2001 From: David Howells Date: Mon, 8 Aug 2022 15:33:51 +0100 Subject: cifs: Remove {cifs,nfs}_fscache_release_page() Remove {cifs,nfs}_fscache_release_page() from fs/cifs/fscache.h. This functionality got built directly into cifs_release_folio() and will hopefully be replaced with netfs_release_folio() at some point. The "nfs_" version is a copy and paste error and should've been altered to read "cifs_". That can also be removed. Reported-by: Matthew Wilcox Signed-off-by: David Howells Reviewed-by: Jeff Layton cc: Steve French cc: linux-cifs@vger.kernel.org cc: samba-technical@lists.samba.org cc: linux-fsdevel@vger.kernel.org Signed-off-by: Steve French --- fs/cifs/fscache.h | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/fs/cifs/fscache.h b/fs/cifs/fscache.h index aa3b941a5555..67b601041f0a 100644 --- a/fs/cifs/fscache.h +++ b/fs/cifs/fscache.h @@ -108,17 +108,6 @@ static inline void cifs_readpage_to_fscache(struct inode *inode, __cifs_readpage_to_fscache(inode, page); } -static inline int cifs_fscache_release_page(struct page *page, gfp_t gfp) -{ - if (PageFsCache(page)) { - if (current_is_kswapd() || !(gfp & __GFP_FS)) - return false; - wait_on_page_fscache(page); - fscache_note_page_release(cifs_inode_cookie(page->mapping->host)); - } - return true; -} - #else /* CONFIG_CIFS_FSCACHE */ static inline void cifs_fscache_fill_coherency(struct inode *inode, @@ -154,11 +143,6 @@ cifs_readpage_from_fscache(struct inode *inode, struct page *page) static inline void cifs_readpage_to_fscache(struct inode *inode, struct page *page) {} -static inline int nfs_fscache_release_page(struct page *page, gfp_t gfp) -{ - return true; /* May release page */ -} - #endif /* CONFIG_CIFS_FSCACHE */ #endif /* _CIFS_FSCACHE_H */ -- cgit v1.2.3 From 74bba640d69914cf832b87f6bbb700e5ba430672 Mon Sep 17 00:00:00 2001 From: Allen Ballway Date: Wed, 10 Aug 2022 15:27:22 +0000 Subject: ALSA: hda/cirrus - support for iMac 12,1 model The 12,1 model requires the same configuration as the 12,2 model to enable headphones but has a different codec SSID. Adds 12,1 SSID for matching quirk. [ re-sorted in SSID order by tiwai ] Signed-off-by: Allen Ballway Cc: Link: https://lore.kernel.org/r/20220810152701.1.I902c2e591bbf8de9acb649d1322fa1f291849266@changeid Signed-off-by: Takashi Iwai --- sound/pci/hda/patch_cirrus.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/pci/hda/patch_cirrus.c b/sound/pci/hda/patch_cirrus.c index 678fbcaf2a3b..6807b4708a17 100644 --- a/sound/pci/hda/patch_cirrus.c +++ b/sound/pci/hda/patch_cirrus.c @@ -395,6 +395,7 @@ static const struct snd_pci_quirk cs420x_fixup_tbl[] = { /* codec SSID */ SND_PCI_QUIRK(0x106b, 0x0600, "iMac 14,1", CS420X_IMAC27_122), + SND_PCI_QUIRK(0x106b, 0x0900, "iMac 12,1", CS420X_IMAC27_122), SND_PCI_QUIRK(0x106b, 0x1c00, "MacBookPro 8,1", CS420X_MBP81), SND_PCI_QUIRK(0x106b, 0x2000, "iMac 12,2", CS420X_IMAC27_122), SND_PCI_QUIRK(0x106b, 0x2800, "MacBookPro 10,1", CS420X_MBP101), -- cgit v1.2.3 From 636aa8807b5780b76609b40cd3d3e1b5a225471c Mon Sep 17 00:00:00 2001 From: Mohan Kumar Date: Thu, 11 Aug 2022 10:57:04 +0530 Subject: ALSA: hda: Fix crash due to jack poll in suspend With jackpoll_in_suspend flag set, there is a possibility that jack poll worker thread will run even after system suspend was completed. Any register access after system pm callback flow will result in kernel crash as still jack poll worker thread tries to access registers. To fix the crash issue during system flow, cancel the jack poll worker thread during system pm prepare callback and cancel the worker thread at start of runtime suspend callback and re-schedule at last to avoid any unwarranted access of register by worker thread during suspend flow. Signed-off-by: Mohan Kumar Fixes: b33115bd05af ("ALSA: hda: Jack detection poll in suspend state") Link: https://lore.kernel.org/r/20220811052704.2944-1-mkumard@nvidia.com Signed-off-by: Takashi Iwai --- sound/pci/hda/hda_codec.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/sound/pci/hda/hda_codec.c b/sound/pci/hda/hda_codec.c index 7b2e62fa82d5..384426d7e9dd 100644 --- a/sound/pci/hda/hda_codec.c +++ b/sound/pci/hda/hda_codec.c @@ -2940,8 +2940,7 @@ static int hda_codec_runtime_suspend(struct device *dev) if (!codec->card) return 0; - if (!codec->bus->jackpoll_in_suspend) - cancel_delayed_work_sync(&codec->jackpoll_work); + cancel_delayed_work_sync(&codec->jackpoll_work); state = hda_call_codec_suspend(codec); if (codec->link_down_at_suspend || @@ -2949,6 +2948,11 @@ static int hda_codec_runtime_suspend(struct device *dev) (state & AC_PWRST_CLK_STOP_OK))) snd_hdac_codec_link_down(&codec->core); snd_hda_codec_display_power(codec, false); + + if (codec->bus->jackpoll_in_suspend && + (dev->power.power_state.event != PM_EVENT_SUSPEND)) + schedule_delayed_work(&codec->jackpoll_work, + codec->jackpoll_interval); return 0; } @@ -2972,6 +2976,9 @@ static int hda_codec_runtime_resume(struct device *dev) #ifdef CONFIG_PM_SLEEP static int hda_codec_pm_prepare(struct device *dev) { + struct hda_codec *codec = dev_to_hda_codec(dev); + + cancel_delayed_work_sync(&codec->jackpoll_work); dev->power.power_state = PMSG_SUSPEND; return pm_runtime_suspended(dev); } @@ -2991,9 +2998,6 @@ static void hda_codec_pm_complete(struct device *dev) static int hda_codec_pm_suspend(struct device *dev) { - struct hda_codec *codec = dev_to_hda_codec(dev); - - cancel_delayed_work_sync(&codec->jackpoll_work); dev->power.power_state = PMSG_SUSPEND; return pm_runtime_force_suspend(dev); } -- cgit v1.2.3 From c2a052a4a949df53f50a5024843432d2234cb824 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Fri, 24 Jun 2022 10:55:41 +0800 Subject: remoteproc: rename len of rpoc_vring to num Rename the member len in the structure rpoc_vring to num. And remove 'in bytes' from the comment of it. This is misleading. Because this actually refers to the size of the virtio vring to be created. The unit is not bytes. Signed-off-by: Xuan Zhuo Message-Id: <20220624025621.128843-2-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/remoteproc/remoteproc_core.c | 4 ++-- drivers/remoteproc/remoteproc_virtio.c | 10 +++++----- include/linux/remoteproc.h | 4 ++-- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c index 02a04ab34a23..2d2f3bab5888 100644 --- a/drivers/remoteproc/remoteproc_core.c +++ b/drivers/remoteproc/remoteproc_core.c @@ -334,7 +334,7 @@ int rproc_alloc_vring(struct rproc_vdev *rvdev, int i) size_t size; /* actual size of vring (in bytes) */ - size = PAGE_ALIGN(vring_size(rvring->len, rvring->align)); + size = PAGE_ALIGN(vring_size(rvring->num, rvring->align)); rsc = (void *)rproc->table_ptr + rvdev->rsc_offset; @@ -401,7 +401,7 @@ rproc_parse_vring(struct rproc_vdev *rvdev, struct fw_rsc_vdev *rsc, int i) return -EINVAL; } - rvring->len = vring->num; + rvring->num = vring->num; rvring->align = vring->align; rvring->rvdev = rvdev; diff --git a/drivers/remoteproc/remoteproc_virtio.c b/drivers/remoteproc/remoteproc_virtio.c index 70ab496d0431..d43d74733f0a 100644 --- a/drivers/remoteproc/remoteproc_virtio.c +++ b/drivers/remoteproc/remoteproc_virtio.c @@ -87,7 +87,7 @@ static struct virtqueue *rp_find_vq(struct virtio_device *vdev, struct fw_rsc_vdev *rsc; struct virtqueue *vq; void *addr; - int len, size; + int num, size; /* we're temporarily limited to two virtqueues per rvdev */ if (id >= ARRAY_SIZE(rvdev->vring)) @@ -104,20 +104,20 @@ static struct virtqueue *rp_find_vq(struct virtio_device *vdev, rvring = &rvdev->vring[id]; addr = mem->va; - len = rvring->len; + num = rvring->num; /* zero vring */ - size = vring_size(len, rvring->align); + size = vring_size(num, rvring->align); memset(addr, 0, size); dev_dbg(dev, "vring%d: va %pK qsz %d notifyid %d\n", - id, addr, len, rvring->notifyid); + id, addr, num, rvring->notifyid); /* * Create the new vq, and tell virtio we're not interested in * the 'weak' smp barriers, since we're talking with a real device. */ - vq = vring_new_virtqueue(id, len, rvring->align, vdev, false, ctx, + vq = vring_new_virtqueue(id, num, rvring->align, vdev, false, ctx, addr, rproc_virtio_notify, callback, name); if (!vq) { dev_err(dev, "vring_new_virtqueue %s failed\n", name); diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h index 7c943f0a2fc4..aea79c77db0f 100644 --- a/include/linux/remoteproc.h +++ b/include/linux/remoteproc.h @@ -597,7 +597,7 @@ struct rproc_subdev { /** * struct rproc_vring - remoteproc vring state * @va: virtual address - * @len: length, in bytes + * @num: vring size * @da: device address * @align: vring alignment * @notifyid: rproc-specific unique vring index @@ -606,7 +606,7 @@ struct rproc_subdev { */ struct rproc_vring { void *va; - int len; + int num; u32 da; u32 align; int notifyid; -- cgit v1.2.3 From 96ef18a24b87bef7c3d2dad72cf4c3013a9f7f35 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Fri, 24 Jun 2022 10:55:45 +0800 Subject: virtio_ring: remove the arg vq of vring_alloc_desc_extra() The parameter vq of vring_alloc_desc_extra() is useless. This patch removes this parameter. Subsequent patches will call this function to avoid passing useless arguments. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220624025621.128843-6-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index 643ca779fcc6..a5ec724c01d8 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -1637,8 +1637,7 @@ static void *virtqueue_detach_unused_buf_packed(struct virtqueue *_vq) return NULL; } -static struct vring_desc_extra *vring_alloc_desc_extra(struct vring_virtqueue *vq, - unsigned int num) +static struct vring_desc_extra *vring_alloc_desc_extra(unsigned int num) { struct vring_desc_extra *desc_extra; unsigned int i; @@ -1759,7 +1758,7 @@ static struct virtqueue *vring_create_virtqueue_packed( /* Put everything in free lists. */ vq->free_head = 0; - vq->packed.desc_extra = vring_alloc_desc_extra(vq, num); + vq->packed.desc_extra = vring_alloc_desc_extra(num); if (!vq->packed.desc_extra) goto err_desc_extra; @@ -2248,7 +2247,7 @@ struct virtqueue *__vring_new_virtqueue(unsigned int index, if (!vq->split.desc_state) goto err_state; - vq->split.desc_extra = vring_alloc_desc_extra(vq, vring.num); + vq->split.desc_extra = vring_alloc_desc_extra(vring.num); if (!vq->split.desc_extra) goto err_extra; -- cgit v1.2.3 From 309bba39c945ac8ab8083ac05cd6cfe5822968e0 Mon Sep 17 00:00:00 2001 From: Stefano Garzarella Date: Fri, 24 Jun 2022 09:56:56 +0200 Subject: vringh: iterate on iotlb_translate to handle large translations iotlb_translate() can return -ENOBUFS if the bio_vec is not big enough to contain all the ranges for translation. This can happen for example if the VMM maps a large bounce buffer, without using hugepages, that requires more than 16 ranges to translate the addresses. To handle this case, let's extend iotlb_translate() to also return the number of bytes successfully translated. In copy_from_iotlb()/copy_to_iotlb() loops by calling iotlb_translate() several times until we complete the translation. Signed-off-by: Stefano Garzarella Message-Id: <20220624075656.13997-1-sgarzare@redhat.com> Signed-off-by: Michael S. Tsirkin --- drivers/vhost/vringh.c | 78 ++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 56 insertions(+), 22 deletions(-) diff --git a/drivers/vhost/vringh.c b/drivers/vhost/vringh.c index eab55accf381..11f59dd06a74 100644 --- a/drivers/vhost/vringh.c +++ b/drivers/vhost/vringh.c @@ -1095,7 +1095,8 @@ EXPORT_SYMBOL(vringh_need_notify_kern); #if IS_REACHABLE(CONFIG_VHOST_IOTLB) static int iotlb_translate(const struct vringh *vrh, - u64 addr, u64 len, struct bio_vec iov[], + u64 addr, u64 len, u64 *translated, + struct bio_vec iov[], int iov_size, u32 perm) { struct vhost_iotlb_map *map; @@ -1136,43 +1137,76 @@ static int iotlb_translate(const struct vringh *vrh, spin_unlock(vrh->iotlb_lock); + if (translated) + *translated = min(len, s); + return ret; } static inline int copy_from_iotlb(const struct vringh *vrh, void *dst, void *src, size_t len) { - struct iov_iter iter; - struct bio_vec iov[16]; - int ret; + u64 total_translated = 0; - ret = iotlb_translate(vrh, (u64)(uintptr_t)src, - len, iov, 16, VHOST_MAP_RO); - if (ret < 0) - return ret; + while (total_translated < len) { + struct bio_vec iov[16]; + struct iov_iter iter; + u64 translated; + int ret; - iov_iter_bvec(&iter, READ, iov, ret, len); + ret = iotlb_translate(vrh, (u64)(uintptr_t)src, + len - total_translated, &translated, + iov, ARRAY_SIZE(iov), VHOST_MAP_RO); + if (ret == -ENOBUFS) + ret = ARRAY_SIZE(iov); + else if (ret < 0) + return ret; - ret = copy_from_iter(dst, len, &iter); + iov_iter_bvec(&iter, READ, iov, ret, translated); - return ret; + ret = copy_from_iter(dst, translated, &iter); + if (ret < 0) + return ret; + + src += translated; + dst += translated; + total_translated += translated; + } + + return total_translated; } static inline int copy_to_iotlb(const struct vringh *vrh, void *dst, void *src, size_t len) { - struct iov_iter iter; - struct bio_vec iov[16]; - int ret; + u64 total_translated = 0; - ret = iotlb_translate(vrh, (u64)(uintptr_t)dst, - len, iov, 16, VHOST_MAP_WO); - if (ret < 0) - return ret; + while (total_translated < len) { + struct bio_vec iov[16]; + struct iov_iter iter; + u64 translated; + int ret; + + ret = iotlb_translate(vrh, (u64)(uintptr_t)dst, + len - total_translated, &translated, + iov, ARRAY_SIZE(iov), VHOST_MAP_WO); + if (ret == -ENOBUFS) + ret = ARRAY_SIZE(iov); + else if (ret < 0) + return ret; - iov_iter_bvec(&iter, WRITE, iov, ret, len); + iov_iter_bvec(&iter, WRITE, iov, ret, translated); + + ret = copy_to_iter(src, translated, &iter); + if (ret < 0) + return ret; + + src += translated; + dst += translated; + total_translated += translated; + } - return copy_to_iter(src, len, &iter); + return total_translated; } static inline int getu16_iotlb(const struct vringh *vrh, @@ -1183,7 +1217,7 @@ static inline int getu16_iotlb(const struct vringh *vrh, int ret; /* Atomic read is needed for getu16 */ - ret = iotlb_translate(vrh, (u64)(uintptr_t)p, sizeof(*p), + ret = iotlb_translate(vrh, (u64)(uintptr_t)p, sizeof(*p), NULL, &iov, 1, VHOST_MAP_RO); if (ret < 0) return ret; @@ -1204,7 +1238,7 @@ static inline int putu16_iotlb(const struct vringh *vrh, int ret; /* Atomic write is needed for putu16 */ - ret = iotlb_translate(vrh, (u64)(uintptr_t)p, sizeof(*p), + ret = iotlb_translate(vrh, (u64)(uintptr_t)p, sizeof(*p), NULL, &iov, 1, VHOST_MAP_WO); if (ret < 0) return ret; -- cgit v1.2.3 From 020e1aede7ee31d8b0e24a46ee364c7bb0939f02 Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Tue, 28 Jun 2022 16:34:29 +0800 Subject: virtio_pmem: initialize provider_data through nd_region_desc We used to initialize the provider_data manually after nvdimm_pemm_region_create(). This seems to be racy if the flush is issued before the initialization of provider_data[1]. Fixing this by initializing the provider_data through nd_region_desc to make sure the provider_data is ready after the pmem is created. [1]: [ 80.152281] nd_pmem namespace0.0: unable to guarantee persistence of writes [ 92.393956] BUG: kernel NULL pointer dereference, address: 0000000000000318 [ 92.394551] #PF: supervisor read access in kernel mode [ 92.394955] #PF: error_code(0x0000) - not-present page [ 92.395365] PGD 0 P4D 0 [ 92.395566] Oops: 0000 [#1] PREEMPT SMP PTI [ 92.395867] CPU: 2 PID: 506 Comm: mkfs.ext4 Not tainted 5.19.0-rc1+ #453 [ 92.396365] Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS rel-1.16.0-0-gd239552ce722-prebuilt.qemu.org 04/01/2014 [ 92.397178] RIP: 0010:virtio_pmem_flush+0x2f/0x1f0 [ 92.397521] Code: 55 41 54 55 53 48 81 ec a0 00 00 00 65 48 8b 04 25 28 00 00 00 48 89 84 24 98 00 00 00 31 c0 48 8b 87 78 03 00 00 48 89 04 24 <48> 8b 98 18 03 00 00 e8 85 bf 6b 00 ba 58 00 00 00 be c0 0c 00 00 [ 92.398982] RSP: 0018:ffff9a7380aefc88 EFLAGS: 00010246 [ 92.399349] RAX: 0000000000000000 RBX: ffff8e77c3f86f00 RCX: 0000000000000000 [ 92.399833] RDX: ffffffffad4ea720 RSI: ffff8e77c41e39c0 RDI: ffff8e77c41c5c00 [ 92.400388] RBP: ffff8e77c41e39c0 R08: ffff8e77c19f0600 R09: 0000000000000000 [ 92.400874] R10: 0000000000000000 R11: 0000000000000000 R12: ffff8e77c0814e28 [ 92.401364] R13: 0000000000000000 R14: 0000000000000000 R15: ffff8e77c41e39c0 [ 92.401849] FS: 00007f3cd75b2780(0000) GS:ffff8e7937d00000(0000) knlGS:0000000000000000 [ 92.402423] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 92.402821] CR2: 0000000000000318 CR3: 0000000103c80002 CR4: 0000000000370ee0 [ 92.403307] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 92.403793] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 92.404278] Call Trace: [ 92.404481] [ 92.404654] ? mempool_alloc+0x5d/0x160 [ 92.404939] ? terminate_walk+0x5f/0xf0 [ 92.405226] ? bio_alloc_bioset+0xbb/0x3f0 [ 92.405525] async_pmem_flush+0x17/0x80 [ 92.405806] nvdimm_flush+0x11/0x30 [ 92.406067] pmem_submit_bio+0x1e9/0x200 [ 92.406354] __submit_bio+0x80/0x120 [ 92.406621] submit_bio_noacct_nocheck+0xdc/0x2a0 [ 92.406958] submit_bio_wait+0x4e/0x80 [ 92.407234] blkdev_issue_flush+0x31/0x50 [ 92.407526] ? punt_bios_to_rescuer+0x230/0x230 [ 92.407852] blkdev_fsync+0x1e/0x30 [ 92.408112] do_fsync+0x33/0x70 [ 92.408354] __x64_sys_fsync+0xb/0x10 [ 92.408625] do_syscall_64+0x43/0x90 [ 92.408895] entry_SYSCALL_64_after_hwframe+0x46/0xb0 [ 92.409257] RIP: 0033:0x7f3cd76c6c44 Fixes 6e84200c0a29 ("virtio-pmem: Add virtio pmem driver") Acked-by: Pankaj Gupta Reviewed-by: Dan Williams Signed-off-by: Jason Wang Message-Id: <20220628083430.61856-1-jasowang@redhat.com> Signed-off-by: Michael S. Tsirkin --- drivers/nvdimm/virtio_pmem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/nvdimm/virtio_pmem.c b/drivers/nvdimm/virtio_pmem.c index 995b6cdc67ed..48f8327d0431 100644 --- a/drivers/nvdimm/virtio_pmem.c +++ b/drivers/nvdimm/virtio_pmem.c @@ -81,6 +81,7 @@ static int virtio_pmem_probe(struct virtio_device *vdev) ndr_desc.res = &res; ndr_desc.numa_node = nid; ndr_desc.flush = async_pmem_flush; + ndr_desc.provider_data = vdev; set_bit(ND_REGION_PAGEMAP, &ndr_desc.flags); set_bit(ND_REGION_ASYNC, &ndr_desc.flags); nd_region = nvdimm_pmem_region_create(vpmem->nvdimm_bus, &ndr_desc); @@ -89,7 +90,6 @@ static int virtio_pmem_probe(struct virtio_device *vdev) err = -ENXIO; goto out_nd; } - nd_region->provider_data = dev_to_virtio(nd_region->dev.parent->parent); return 0; out_nd: nvdimm_bus_unregister(vpmem->nvdimm_bus); -- cgit v1.2.3 From 5d66322b2b23507e9907a68e9c504181ffccd62f Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Tue, 28 Jun 2022 16:34:30 +0800 Subject: virtio_pmem: set device ready in probe() The NVDIMM region could be available before the virtio_device_ready() that is called by virtio_dev_probe(). This means the driver tries to use device before DRIVER_OK which violates the spec, fixing this by set device ready before the nvdimm_pmem_region_create(). Note that this means the virtio_pmem_host_ack() could be triggered before the creation of the nd region, this is safe since the pmem_lock has been initialized and whether or not any available buffer is added before is validated by virtio_pmem_host_ack(). Fixes 6e84200c0a29 ("virtio-pmem: Add virtio pmem driver") Acked-by: Pankaj Gupta Signed-off-by: Jason Wang Message-Id: <20220628083430.61856-2-jasowang@redhat.com> Signed-off-by: Michael S. Tsirkin --- drivers/nvdimm/virtio_pmem.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/nvdimm/virtio_pmem.c b/drivers/nvdimm/virtio_pmem.c index 48f8327d0431..20da455d2ef6 100644 --- a/drivers/nvdimm/virtio_pmem.c +++ b/drivers/nvdimm/virtio_pmem.c @@ -84,6 +84,12 @@ static int virtio_pmem_probe(struct virtio_device *vdev) ndr_desc.provider_data = vdev; set_bit(ND_REGION_PAGEMAP, &ndr_desc.flags); set_bit(ND_REGION_ASYNC, &ndr_desc.flags); + /* + * The NVDIMM region could be available before the + * virtio_device_ready() that is called by + * virtio_dev_probe(), so we set device ready here. + */ + virtio_device_ready(vdev); nd_region = nvdimm_pmem_region_create(vpmem->nvdimm_bus, &ndr_desc); if (!nd_region) { dev_err(&vdev->dev, "failed to create nvdimm region\n"); @@ -92,6 +98,7 @@ static int virtio_pmem_probe(struct virtio_device *vdev) } return 0; out_nd: + virtio_reset_device(vdev); nvdimm_bus_unregister(vpmem->nvdimm_bus); out_vq: vdev->config->del_vqs(vdev); -- cgit v1.2.3 From ebe797f25f68f28581f46a9cb9c1997ac15c39a0 Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Thu, 30 Jun 2022 15:10:57 -0400 Subject: virtio: VIRTIO_HARDEN_NOTIFICATION is broken This option doesn't really work and breaks too many drivers. Not yet sure what's the right thing to do, for now let's make sure randconfig isn't broken by this. Fixes: c346dae4f3fb ("virtio: disable notification hardening by default") Cc: "Jason Wang" Signed-off-by: Michael S. Tsirkin Acked-by: Jason Wang --- drivers/virtio/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/virtio/Kconfig b/drivers/virtio/Kconfig index e1556d2a355a..afb9051e0125 100644 --- a/drivers/virtio/Kconfig +++ b/drivers/virtio/Kconfig @@ -31,11 +31,12 @@ if VIRTIO_MENU config VIRTIO_HARDEN_NOTIFICATION bool "Harden virtio notification" + depends on BROKEN help Enable this to harden the device notifications and suppress those that happen at a time where notifications are illegal. - Experimental: Note that several drivers still have bugs that + Experimental: Note that several drivers still have issues that may cause crashes or hangs when correct handling of notifications is enforced; depending on the subset of drivers and devices you use, this may or may not work. -- cgit v1.2.3 From 366958a7fd7b541cba478e2866ef08f34e20471b Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Wed, 8 Jun 2022 12:48:26 +0100 Subject: vdpa: Use device_iommu_capable() Use the new interface to check the capability for our device specifically. Signed-off-by: Robin Murphy Message-Id: <548e316fa282ce513fabb991a4c4d92258062eb5.1654688822.git.robin.murphy@arm.com> Signed-off-by: Michael S. Tsirkin Acked-by: Jason Wang --- drivers/vhost/vdpa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/vhost/vdpa.c b/drivers/vhost/vdpa.c index 23dcbfdfa13b..250ad4160ccb 100644 --- a/drivers/vhost/vdpa.c +++ b/drivers/vhost/vdpa.c @@ -1076,7 +1076,7 @@ static int vhost_vdpa_alloc_domain(struct vhost_vdpa *v) if (!bus) return -EFAULT; - if (!iommu_capable(bus, IOMMU_CAP_CACHE_COHERENCY)) + if (!device_iommu_capable(dma_dev, IOMMU_CAP_CACHE_COHERENCY)) return -ENOTSUPP; v->domain = iommu_domain_alloc(bus); -- cgit v1.2.3 From 51ded7cdf26deea7dd875047c2f005b81e80bdf4 Mon Sep 17 00:00:00 2001 From: Minghao Xue Date: Fri, 10 Jun 2022 16:58:26 +0800 Subject: dt-bindings: virtio: mmio: add optional wakeup-source property Some systems want to set the interrupt of virtio_mmio device as a wakeup source. On such systems, we'll use the existence of the "wakeup-source" property as a signal of requirement. Signed-off-by: Minghao Xue Reviewed-by: Krzysztof Kozlowski Message-Id: <1654851507-13891-2-git-send-email-quic_mingxue@quicinc.com> Signed-off-by: Michael S. Tsirkin --- Documentation/devicetree/bindings/virtio/mmio.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/virtio/mmio.yaml b/Documentation/devicetree/bindings/virtio/mmio.yaml index 10c22b5bd16a..0aa8433f0a5e 100644 --- a/Documentation/devicetree/bindings/virtio/mmio.yaml +++ b/Documentation/devicetree/bindings/virtio/mmio.yaml @@ -33,6 +33,10 @@ properties: description: Required for devices making accesses thru an IOMMU. maxItems: 1 + wakeup-source: + type: boolean + description: Required for setting irq of a virtio_mmio device as wakeup source. + required: - compatible - reg -- cgit v1.2.3 From 02213273f72a43bad3a8e9c18595a2c74ee487e8 Mon Sep 17 00:00:00 2001 From: Minghao Xue Date: Fri, 10 Jun 2022 16:58:27 +0800 Subject: virtio_mmio: add support to set IRQ of a virtio device as wakeup source According to virtio_mmio wakeup flag in device trees, set its IRQ as wakeup source in virtqueue initialization. Signed-off-by: Minghao Xue Message-Id: <1654851507-13891-3-git-send-email-quic_mingxue@quicinc.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_mmio.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index 083ff1eb743d..945cb8fb60b6 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -487,6 +487,9 @@ static int vm_find_vqs(struct virtio_device *vdev, unsigned int nvqs, if (err) return err; + if (of_property_read_bool(vm_dev->pdev->dev.of_node, "wakeup-source")) + enable_irq_wake(irq); + for (i = 0; i < nvqs; ++i) { if (!names[i]) { vqs[i] = NULL; -- cgit v1.2.3 From 0b6fd46ec5f5720b76cbb01300ed9f7b7c6365c4 Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Fri, 10 Jun 2022 11:47:37 +0200 Subject: drivers/virtio: Clarify CONFIG_VIRTIO_MEM for unsupported architectures Let's make it clearer that simply unlocking CONFIG_VIRTIO_MEM on an architecture is most probably not sufficient to have it working as expected. Cc: "Michael S. Tsirkin" Cc: Jason Wang Cc: Gavin Shan Signed-off-by: David Hildenbrand Message-Id: <20220610094737.65254-1-david@redhat.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/Kconfig | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/virtio/Kconfig b/drivers/virtio/Kconfig index afb9051e0125..02bbccd602c0 100644 --- a/drivers/virtio/Kconfig +++ b/drivers/virtio/Kconfig @@ -123,9 +123,11 @@ config VIRTIO_MEM This driver provides access to virtio-mem paravirtualized memory devices, allowing to hotplug and hotunplug memory. - This driver was only tested under x86-64 and arm64, but should - theoretically work on all architectures that support memory hotplug - and hotremove. + This driver currently only supports x86-64 and arm64. Although it + should compile on other architectures that implement memory + hot(un)plug, architecture-specific and/or common + code changes may be required for virtio-mem, kdump and kexec to work as + expected. If unsure, say M. -- cgit v1.2.3 From da802961832f9852886304290135457519815497 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:21 +0800 Subject: virtio: record the maximum queue num supported by the device. virtio-net can display the maximum (supported by hardware) ring size in ethtool -g eth0. When the subsequent patch implements vring reset, it can judge whether the ring size passed by the driver is legal based on this. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-2-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- arch/um/drivers/virtio_uml.c | 1 + drivers/platform/mellanox/mlxbf-tmfifo.c | 2 ++ drivers/remoteproc/remoteproc_virtio.c | 2 ++ drivers/s390/virtio/virtio_ccw.c | 3 +++ drivers/virtio/virtio_mmio.c | 2 ++ drivers/virtio/virtio_pci_legacy.c | 2 ++ drivers/virtio/virtio_pci_modern.c | 2 ++ drivers/virtio/virtio_vdpa.c | 2 ++ include/linux/virtio.h | 2 ++ 9 files changed, 18 insertions(+) diff --git a/arch/um/drivers/virtio_uml.c b/arch/um/drivers/virtio_uml.c index 82ff3785bf69..e719af8bdf56 100644 --- a/arch/um/drivers/virtio_uml.c +++ b/arch/um/drivers/virtio_uml.c @@ -958,6 +958,7 @@ static struct virtqueue *vu_setup_vq(struct virtio_device *vdev, goto error_create; } vq->priv = info; + vq->num_max = num; num = virtqueue_get_vring_size(vq); if (vu_dev->protocol_features & diff --git a/drivers/platform/mellanox/mlxbf-tmfifo.c b/drivers/platform/mellanox/mlxbf-tmfifo.c index 38800e86ed8a..1ae3c56b66b0 100644 --- a/drivers/platform/mellanox/mlxbf-tmfifo.c +++ b/drivers/platform/mellanox/mlxbf-tmfifo.c @@ -959,6 +959,8 @@ static int mlxbf_tmfifo_virtio_find_vqs(struct virtio_device *vdev, goto error; } + vq->num_max = vring->num; + vqs[i] = vq; vring->vq = vq; vq->priv = vring; diff --git a/drivers/remoteproc/remoteproc_virtio.c b/drivers/remoteproc/remoteproc_virtio.c index d43d74733f0a..0f7706e23eb9 100644 --- a/drivers/remoteproc/remoteproc_virtio.c +++ b/drivers/remoteproc/remoteproc_virtio.c @@ -125,6 +125,8 @@ static struct virtqueue *rp_find_vq(struct virtio_device *vdev, return ERR_PTR(-ENOMEM); } + vq->num_max = num; + rvring->vq = vq; vq->priv = rvring; diff --git a/drivers/s390/virtio/virtio_ccw.c b/drivers/s390/virtio/virtio_ccw.c index 161d3b141f0d..6b86d0280d6b 100644 --- a/drivers/s390/virtio/virtio_ccw.c +++ b/drivers/s390/virtio/virtio_ccw.c @@ -530,6 +530,9 @@ static struct virtqueue *virtio_ccw_setup_vq(struct virtio_device *vdev, err = -ENOMEM; goto out_err; } + + vq->num_max = info->num; + /* it may have been reduced */ info->num = virtqueue_get_vring_size(vq); diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index 945cb8fb60b6..3ff746e3f24a 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -403,6 +403,8 @@ static struct virtqueue *vm_setup_vq(struct virtio_device *vdev, unsigned int in goto error_new_virtqueue; } + vq->num_max = num; + /* Activate the queue */ writel(virtqueue_get_vring_size(vq), vm_dev->base + VIRTIO_MMIO_QUEUE_NUM); if (vm_dev->version == 1) { diff --git a/drivers/virtio/virtio_pci_legacy.c b/drivers/virtio/virtio_pci_legacy.c index a5e5721145c7..2257f1b3d8ae 100644 --- a/drivers/virtio/virtio_pci_legacy.c +++ b/drivers/virtio/virtio_pci_legacy.c @@ -135,6 +135,8 @@ static struct virtqueue *setup_vq(struct virtio_pci_device *vp_dev, if (!vq) return ERR_PTR(-ENOMEM); + vq->num_max = num; + q_pfn = virtqueue_get_desc_addr(vq) >> VIRTIO_PCI_QUEUE_ADDR_SHIFT; if (q_pfn >> 32) { dev_err(&vp_dev->pci_dev->dev, diff --git a/drivers/virtio/virtio_pci_modern.c b/drivers/virtio/virtio_pci_modern.c index 623906b4996c..e7e0b8c850f6 100644 --- a/drivers/virtio/virtio_pci_modern.c +++ b/drivers/virtio/virtio_pci_modern.c @@ -218,6 +218,8 @@ static struct virtqueue *setup_vq(struct virtio_pci_device *vp_dev, if (!vq) return ERR_PTR(-ENOMEM); + vq->num_max = num; + /* activate the queue */ vp_modern_set_queue_size(mdev, index, virtqueue_get_vring_size(vq)); vp_modern_queue_address(mdev, index, virtqueue_get_desc_addr(vq), diff --git a/drivers/virtio/virtio_vdpa.c b/drivers/virtio/virtio_vdpa.c index c40f7deb6b5a..9670cc79371d 100644 --- a/drivers/virtio/virtio_vdpa.c +++ b/drivers/virtio/virtio_vdpa.c @@ -183,6 +183,8 @@ virtio_vdpa_setup_vq(struct virtio_device *vdev, unsigned int index, goto error_new_virtqueue; } + vq->num_max = max_num; + /* Setup virtqueue callback */ cb.callback = callback ? virtio_vdpa_virtqueue_cb : NULL; cb.private = info; diff --git a/include/linux/virtio.h b/include/linux/virtio.h index d8fdf170637c..129bde7521e3 100644 --- a/include/linux/virtio.h +++ b/include/linux/virtio.h @@ -19,6 +19,7 @@ * @priv: a pointer for the virtqueue implementation to use. * @index: the zero-based ordinal number for this queue. * @num_free: number of elements we expect to be able to fit. + * @num_max: the maximum number of elements supported by the device. * * A note on @num_free: with indirect buffers, each buffer needs one * element in the queue, otherwise a buffer will need one element per @@ -31,6 +32,7 @@ struct virtqueue { struct virtio_device *vdev; unsigned int index; unsigned int num_free; + unsigned int num_max; void *priv; }; -- cgit v1.2.3 From 3086e9fc9173166774652a488467e4176ee1c81b Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:22 +0800 Subject: virtio: struct virtio_config_ops add callbacks for queue_reset reset can be divided into the following four steps (example): 1. transport: notify the device to reset the queue 2. vring: recycle the buffer submitted 3. vring: reset/resize the vring (may re-alloc) 4. transport: mmap vring to device, and enable the queue In order to support queue reset, add two callbacks in struct virtio_config_ops to implement steps 1 and 4. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-3-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- include/linux/virtio_config.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/linux/virtio_config.h b/include/linux/virtio_config.h index b47c2e7ed0ee..36ec7be1f480 100644 --- a/include/linux/virtio_config.h +++ b/include/linux/virtio_config.h @@ -78,6 +78,18 @@ struct virtio_shm_region { * @set_vq_affinity: set the affinity for a virtqueue (optional). * @get_vq_affinity: get the affinity for a virtqueue (optional). * @get_shm_region: get a shared memory region based on the index. + * @disable_vq_and_reset: reset a queue individually (optional). + * vq: the virtqueue + * Returns 0 on success or error status + * disable_vq_and_reset will guarantee that the callbacks are disabled and + * synchronized. + * Except for the callback, the caller should guarantee that the vring is + * not accessed by any functions of virtqueue. + * @enable_vq_after_reset: enable a reset queue + * vq: the virtqueue + * Returns 0 on success or error status + * If disable_vq_and_reset is set, then enable_vq_after_reset must also be + * set. */ typedef void vq_callback_t(struct virtqueue *); struct virtio_config_ops { @@ -104,6 +116,8 @@ struct virtio_config_ops { int index); bool (*get_shm_region)(struct virtio_device *vdev, struct virtio_shm_region *region, u8 id); + int (*disable_vq_and_reset)(struct virtqueue *vq); + int (*enable_vq_after_reset)(struct virtqueue *vq); }; /* If driver didn't advertise the feature, it will never appear. */ -- cgit v1.2.3 From a62eecb3a9c086fa7b47c5cc74ab8ca4e655a682 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:23 +0800 Subject: virtio_ring: update the document of the virtqueue_detach_unused_buf for queue reset Added documentation for virtqueue_detach_unused_buf, allowing it to be called on queue reset. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-4-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index a5ec724c01d8..17024389b62c 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -2130,8 +2130,8 @@ EXPORT_SYMBOL_GPL(virtqueue_enable_cb_delayed); * @_vq: the struct virtqueue we're talking about. * * Returns NULL or the "data" token handed to virtqueue_add_*(). - * This is not valid on an active queue; it is useful only for device - * shutdown. + * This is not valid on an active queue; it is useful for device + * shutdown or the reset queue. */ void *virtqueue_detach_unused_buf(struct virtqueue *_vq) { -- cgit v1.2.3 From 3ea19e3265d8d140bdd2905e7c40216368cac589 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:24 +0800 Subject: virtio_ring: extract the logic of freeing vring Introduce vring_free() to free the vring of vq. Subsequent patches will use vring_free() alone. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-5-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index 17024389b62c..a3d76fd87983 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -2316,14 +2316,10 @@ struct virtqueue *vring_new_virtqueue(unsigned int index, } EXPORT_SYMBOL_GPL(vring_new_virtqueue); -void vring_del_virtqueue(struct virtqueue *_vq) +static void vring_free(struct virtqueue *_vq) { struct vring_virtqueue *vq = to_vvq(_vq); - spin_lock(&vq->vq.vdev->vqs_list_lock); - list_del(&_vq->list); - spin_unlock(&vq->vq.vdev->vqs_list_lock); - if (vq->we_own_ring) { if (vq->packed_ring) { vring_free_queue(vq->vq.vdev, @@ -2354,6 +2350,18 @@ void vring_del_virtqueue(struct virtqueue *_vq) kfree(vq->split.desc_state); kfree(vq->split.desc_extra); } +} + +void vring_del_virtqueue(struct virtqueue *_vq) +{ + struct vring_virtqueue *vq = to_vvq(_vq); + + spin_lock(&vq->vq.vdev->vqs_list_lock); + list_del(&_vq->list); + spin_unlock(&vq->vq.vdev->vqs_list_lock); + + vring_free(_vq); + kfree(vq); } EXPORT_SYMBOL_GPL(vring_del_virtqueue); -- cgit v1.2.3 From d76136e434973691d8928cec1b3f93d38e30fe6e Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:25 +0800 Subject: virtio_ring: split vring_virtqueue Separate the two inline structures(split and packed) from the structure vring_virtqueue. In this way, we can use these two structures later to pass parameters and retain temporary variables. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-6-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 116 ++++++++++++++++++++++--------------------- 1 file changed, 60 insertions(+), 56 deletions(-) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index a3d76fd87983..1bc5794e9739 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -85,6 +85,64 @@ struct vring_desc_extra { u16 next; /* The next desc state in a list. */ }; +struct vring_virtqueue_split { + /* Actual memory layout for this queue. */ + struct vring vring; + + /* Last written value to avail->flags */ + u16 avail_flags_shadow; + + /* + * Last written value to avail->idx in + * guest byte order. + */ + u16 avail_idx_shadow; + + /* Per-descriptor state. */ + struct vring_desc_state_split *desc_state; + struct vring_desc_extra *desc_extra; + + /* DMA address and size information */ + dma_addr_t queue_dma_addr; + size_t queue_size_in_bytes; +}; + +struct vring_virtqueue_packed { + /* Actual memory layout for this queue. */ + struct { + unsigned int num; + struct vring_packed_desc *desc; + struct vring_packed_desc_event *driver; + struct vring_packed_desc_event *device; + } vring; + + /* Driver ring wrap counter. */ + bool avail_wrap_counter; + + /* Avail used flags. */ + u16 avail_used_flags; + + /* Index of the next avail descriptor. */ + u16 next_avail_idx; + + /* + * Last written value to driver->flags in + * guest byte order. + */ + u16 event_flags_shadow; + + /* Per-descriptor state. */ + struct vring_desc_state_packed *desc_state; + struct vring_desc_extra *desc_extra; + + /* DMA address and size information */ + dma_addr_t ring_dma_addr; + dma_addr_t driver_event_dma_addr; + dma_addr_t device_event_dma_addr; + size_t ring_size_in_bytes; + size_t event_size_in_bytes; +}; + struct vring_virtqueue { struct virtqueue vq; @@ -124,64 +182,10 @@ struct vring_virtqueue { union { /* Available for split ring */ - struct { - /* Actual memory layout for this queue. */ - struct vring vring; - - /* Last written value to avail->flags */ - u16 avail_flags_shadow; - - /* - * Last written value to avail->idx in - * guest byte order. - */ - u16 avail_idx_shadow; - - /* Per-descriptor state. */ - struct vring_desc_state_split *desc_state; - struct vring_desc_extra *desc_extra; - - /* DMA address and size information */ - dma_addr_t queue_dma_addr; - size_t queue_size_in_bytes; - } split; + struct vring_virtqueue_split split; /* Available for packed ring */ - struct { - /* Actual memory layout for this queue. */ - struct { - unsigned int num; - struct vring_packed_desc *desc; - struct vring_packed_desc_event *driver; - struct vring_packed_desc_event *device; - } vring; - - /* Driver ring wrap counter. */ - bool avail_wrap_counter; - - /* Avail used flags. */ - u16 avail_used_flags; - - /* Index of the next avail descriptor. */ - u16 next_avail_idx; - - /* - * Last written value to driver->flags in - * guest byte order. - */ - u16 event_flags_shadow; - - /* Per-descriptor state. */ - struct vring_desc_state_packed *desc_state; - struct vring_desc_extra *desc_extra; - - /* DMA address and size information */ - dma_addr_t ring_dma_addr; - dma_addr_t driver_event_dma_addr; - dma_addr_t device_event_dma_addr; - size_t ring_size_in_bytes; - size_t event_size_in_bytes; - } packed; + struct vring_virtqueue_packed packed; }; /* How to notify other side. FIXME: commonalize hcalls! */ -- cgit v1.2.3 From 3a897128d3193459a87551e54a7f0a71edb65153 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:26 +0800 Subject: virtio_ring: introduce virtqueue_init() Separate the logic of virtqueue initialization. These variables should be reset during reset. This logic can be called independently when implementing resize/reset later. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-7-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index 1bc5794e9739..a63ef2d99955 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -368,6 +368,24 @@ static int vring_mapping_error(const struct vring_virtqueue *vq, return dma_mapping_error(vring_dma_dev(vq), addr); } +static void virtqueue_init(struct vring_virtqueue *vq, u32 num) +{ + vq->vq.num_free = num; + + if (vq->packed_ring) + vq->last_used_idx = 0 | (1 << VRING_PACKED_EVENT_F_WRAP_CTR); + else + vq->last_used_idx = 0; + + vq->event_triggered = false; + vq->num_added = 0; + +#ifdef DEBUG + vq->in_use = false; + vq->last_add_time_valid = false; +#endif +} + /* * Split ring specific functions - *_split(). @@ -1706,7 +1724,6 @@ static struct virtqueue *vring_create_virtqueue_packed( vq->vq.callback = callback; vq->vq.vdev = vdev; vq->vq.name = name; - vq->vq.num_free = num; vq->vq.index = index; vq->we_own_ring = true; vq->notify = notify; @@ -1716,15 +1733,8 @@ static struct virtqueue *vring_create_virtqueue_packed( #else vq->broken = false; #endif - vq->last_used_idx = 0 | (1 << VRING_PACKED_EVENT_F_WRAP_CTR); - vq->event_triggered = false; - vq->num_added = 0; vq->packed_ring = true; vq->use_dma_api = vring_use_dma_api(vdev); -#ifdef DEBUG - vq->in_use = false; - vq->last_add_time_valid = false; -#endif vq->indirect = virtio_has_feature(vdev, VIRTIO_RING_F_INDIRECT_DESC) && !context; @@ -1773,6 +1783,8 @@ static struct virtqueue *vring_create_virtqueue_packed( cpu_to_le16(vq->packed.event_flags_shadow); } + virtqueue_init(vq, num); + spin_lock(&vdev->vqs_list_lock); list_add_tail(&vq->vq.list, &vdev->vqs); spin_unlock(&vdev->vqs_list_lock); @@ -2205,7 +2217,6 @@ struct virtqueue *__vring_new_virtqueue(unsigned int index, vq->vq.callback = callback; vq->vq.vdev = vdev; vq->vq.name = name; - vq->vq.num_free = vring.num; vq->vq.index = index; vq->we_own_ring = false; vq->notify = notify; @@ -2215,14 +2226,7 @@ struct virtqueue *__vring_new_virtqueue(unsigned int index, #else vq->broken = false; #endif - vq->last_used_idx = 0; - vq->event_triggered = false; - vq->num_added = 0; vq->use_dma_api = vring_use_dma_api(vdev); -#ifdef DEBUG - vq->in_use = false; - vq->last_add_time_valid = false; -#endif vq->indirect = virtio_has_feature(vdev, VIRTIO_RING_F_INDIRECT_DESC) && !context; @@ -2260,6 +2264,8 @@ struct virtqueue *__vring_new_virtqueue(unsigned int index, memset(vq->split.desc_state, 0, vring.num * sizeof(struct vring_desc_state_split)); + virtqueue_init(vq, vring.num); + spin_lock(&vdev->vqs_list_lock); list_add_tail(&vq->vq.list, &vdev->vqs); spin_unlock(&vdev->vqs_list_lock); -- cgit v1.2.3 From 07d9629d49584b6f79faa6158cd7aef7e6919703 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:27 +0800 Subject: virtio_ring: split: stop __vring_new_virtqueue as export symbol There is currently only one place to reference __vring_new_virtqueue() directly from the outside of virtio core. And here vring_new_virtqueue() can be used instead. Subsequent patches will modify __vring_new_virtqueue, so stop it as an export symbol for now. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-8-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 25 ++++++++++++++++--------- include/linux/virtio_ring.h | 10 ---------- tools/virtio/virtio_test.c | 4 ++-- 3 files changed, 18 insertions(+), 21 deletions(-) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index a63ef2d99955..8ce6cc73d814 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -204,6 +204,14 @@ struct vring_virtqueue { #endif }; +static struct virtqueue *__vring_new_virtqueue(unsigned int index, + struct vring vring, + struct virtio_device *vdev, + bool weak_barriers, + bool context, + bool (*notify)(struct virtqueue *), + void (*callback)(struct virtqueue *), + const char *name); /* * Helpers. @@ -2195,14 +2203,14 @@ irqreturn_t vring_interrupt(int irq, void *_vq) EXPORT_SYMBOL_GPL(vring_interrupt); /* Only available for split ring */ -struct virtqueue *__vring_new_virtqueue(unsigned int index, - struct vring vring, - struct virtio_device *vdev, - bool weak_barriers, - bool context, - bool (*notify)(struct virtqueue *), - void (*callback)(struct virtqueue *), - const char *name) +static struct virtqueue *__vring_new_virtqueue(unsigned int index, + struct vring vring, + struct virtio_device *vdev, + bool weak_barriers, + bool context, + bool (*notify)(struct virtqueue *), + void (*callback)(struct virtqueue *), + const char *name) { struct vring_virtqueue *vq; @@ -2277,7 +2285,6 @@ err_state: kfree(vq); return NULL; } -EXPORT_SYMBOL_GPL(__vring_new_virtqueue); struct virtqueue *vring_create_virtqueue( unsigned int index, diff --git a/include/linux/virtio_ring.h b/include/linux/virtio_ring.h index b485b13fa50b..8b8af1a38991 100644 --- a/include/linux/virtio_ring.h +++ b/include/linux/virtio_ring.h @@ -76,16 +76,6 @@ struct virtqueue *vring_create_virtqueue(unsigned int index, void (*callback)(struct virtqueue *vq), const char *name); -/* Creates a virtqueue with a custom layout. */ -struct virtqueue *__vring_new_virtqueue(unsigned int index, - struct vring vring, - struct virtio_device *vdev, - bool weak_barriers, - bool ctx, - bool (*notify)(struct virtqueue *), - void (*callback)(struct virtqueue *), - const char *name); - /* * Creates a virtqueue with a standard layout but a caller-allocated * ring. diff --git a/tools/virtio/virtio_test.c b/tools/virtio/virtio_test.c index 23f142af544a..86a410ddcedd 100644 --- a/tools/virtio/virtio_test.c +++ b/tools/virtio/virtio_test.c @@ -102,8 +102,8 @@ static void vq_reset(struct vq_info *info, int num, struct virtio_device *vdev) memset(info->ring, 0, vring_size(num, 4096)); vring_init(&info->vring, num, info->ring, 4096); - info->vq = __vring_new_virtqueue(info->idx, info->vring, vdev, true, - false, vq_notify, vq_callback, "test"); + info->vq = vring_new_virtqueue(info->idx, num, 4096, vdev, true, false, + info->ring, vq_notify, vq_callback, "test"); assert(info->vq); info->vq->priv = info; } -- cgit v1.2.3 From cd4c812acb8390a3cfa0a178b777979f9cdd3eeb Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:28 +0800 Subject: virtio_ring: split: __vring_new_virtqueue() accept struct vring_virtqueue_split __vring_new_virtqueue() instead accepts struct vring_virtqueue_split. The purpose of this is to pass more information into __vring_new_virtqueue() to make the code simpler and the structure cleaner. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-9-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index 8ce6cc73d814..1d51ed46b295 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -205,7 +205,7 @@ struct vring_virtqueue { }; static struct virtqueue *__vring_new_virtqueue(unsigned int index, - struct vring vring, + struct vring_virtqueue_split *vring_split, struct virtio_device *vdev, bool weak_barriers, bool context, @@ -949,6 +949,7 @@ static struct virtqueue *vring_create_virtqueue_split( void (*callback)(struct virtqueue *), const char *name) { + struct vring_virtqueue_split vring_split = {}; struct virtqueue *vq; void *queue = NULL; dma_addr_t dma_addr; @@ -984,10 +985,10 @@ static struct virtqueue *vring_create_virtqueue_split( return NULL; queue_size_in_bytes = vring_size(num, vring_align); - vring_init(&vring, num, queue, vring_align); + vring_init(&vring_split.vring, num, queue, vring_align); - vq = __vring_new_virtqueue(index, vring, vdev, weak_barriers, context, - notify, callback, name); + vq = __vring_new_virtqueue(index, &vring_split, vdev, weak_barriers, + context, notify, callback, name); if (!vq) { vring_free_queue(vdev, queue_size_in_bytes, queue, dma_addr); @@ -2204,7 +2205,7 @@ EXPORT_SYMBOL_GPL(vring_interrupt); /* Only available for split ring */ static struct virtqueue *__vring_new_virtqueue(unsigned int index, - struct vring vring, + struct vring_virtqueue_split *vring_split, struct virtio_device *vdev, bool weak_barriers, bool context, @@ -2246,7 +2247,7 @@ static struct virtqueue *__vring_new_virtqueue(unsigned int index, vq->split.queue_dma_addr = 0; vq->split.queue_size_in_bytes = 0; - vq->split.vring = vring; + vq->split.vring = vring_split->vring; vq->split.avail_flags_shadow = 0; vq->split.avail_idx_shadow = 0; @@ -2258,21 +2259,21 @@ static struct virtqueue *__vring_new_virtqueue(unsigned int index, vq->split.avail_flags_shadow); } - vq->split.desc_state = kmalloc_array(vring.num, + vq->split.desc_state = kmalloc_array(vring_split->vring.num, sizeof(struct vring_desc_state_split), GFP_KERNEL); if (!vq->split.desc_state) goto err_state; - vq->split.desc_extra = vring_alloc_desc_extra(vring.num); + vq->split.desc_extra = vring_alloc_desc_extra(vring_split->vring.num); if (!vq->split.desc_extra) goto err_extra; /* Put everything in free lists. */ vq->free_head = 0; - memset(vq->split.desc_state, 0, vring.num * + memset(vq->split.desc_state, 0, vring_split->vring.num * sizeof(struct vring_desc_state_split)); - virtqueue_init(vq, vring.num); + virtqueue_init(vq, vring_split->vring.num); spin_lock(&vdev->vqs_list_lock); list_add_tail(&vq->vq.list, &vdev->vqs); @@ -2322,14 +2323,14 @@ struct virtqueue *vring_new_virtqueue(unsigned int index, void (*callback)(struct virtqueue *vq), const char *name) { - struct vring vring; + struct vring_virtqueue_split vring_split = {}; if (virtio_has_feature(vdev, VIRTIO_F_RING_PACKED)) return NULL; - vring_init(&vring, num, pages, vring_align); - return __vring_new_virtqueue(index, vring, vdev, weak_barriers, context, - notify, callback, name); + vring_init(&vring_split.vring, num, pages, vring_align); + return __vring_new_virtqueue(index, &vring_split, vdev, weak_barriers, + context, notify, callback, name); } EXPORT_SYMBOL_GPL(vring_new_virtqueue); -- cgit v1.2.3 From 89f05d94a33abec2d38f644065ca5cff5f50c4d7 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:29 +0800 Subject: virtio_ring: split: introduce vring_free_split() Free the structure struct vring_vritqueue_split. Subsequent patches require it. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-10-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index 1d51ed46b295..71cc7762ec51 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -937,6 +937,17 @@ static void *virtqueue_detach_unused_buf_split(struct virtqueue *_vq) return NULL; } +static void vring_free_split(struct vring_virtqueue_split *vring_split, + struct virtio_device *vdev) +{ + vring_free_queue(vdev, vring_split->queue_size_in_bytes, + vring_split->vring.desc, + vring_split->queue_dma_addr); + + kfree(vring_split->desc_state); + kfree(vring_split->desc_extra); +} + static struct virtqueue *vring_create_virtqueue_split( unsigned int index, unsigned int num, -- cgit v1.2.3 From c2d87fe68d13f45f42861e25dcda21b132dbf554 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:30 +0800 Subject: virtio_ring: split: extract the logic of alloc queue Separate the logic of split to create vring queue. This feature is required for subsequent virtuqueue reset vring. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-11-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 65 +++++++++++++++++++++++++++----------------- 1 file changed, 40 insertions(+), 25 deletions(-) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index 71cc7762ec51..5597a9b9e518 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -948,29 +948,19 @@ static void vring_free_split(struct vring_virtqueue_split *vring_split, kfree(vring_split->desc_extra); } -static struct virtqueue *vring_create_virtqueue_split( - unsigned int index, - unsigned int num, - unsigned int vring_align, - struct virtio_device *vdev, - bool weak_barriers, - bool may_reduce_num, - bool context, - bool (*notify)(struct virtqueue *), - void (*callback)(struct virtqueue *), - const char *name) +static int vring_alloc_queue_split(struct vring_virtqueue_split *vring_split, + struct virtio_device *vdev, + u32 num, + unsigned int vring_align, + bool may_reduce_num) { - struct vring_virtqueue_split vring_split = {}; - struct virtqueue *vq; void *queue = NULL; dma_addr_t dma_addr; - size_t queue_size_in_bytes; - struct vring vring; /* We assume num is a power of 2. */ if (num & (num - 1)) { dev_warn(&vdev->dev, "Bad virtqueue length %u\n", num); - return NULL; + return -EINVAL; } /* TODO: allocate each queue chunk individually */ @@ -981,11 +971,11 @@ static struct virtqueue *vring_create_virtqueue_split( if (queue) break; if (!may_reduce_num) - return NULL; + return -ENOMEM; } if (!num) - return NULL; + return -ENOMEM; if (!queue) { /* Try to get a single page. You are my only hope! */ @@ -993,21 +983,46 @@ static struct virtqueue *vring_create_virtqueue_split( &dma_addr, GFP_KERNEL|__GFP_ZERO); } if (!queue) - return NULL; + return -ENOMEM; + + vring_init(&vring_split->vring, num, queue, vring_align); - queue_size_in_bytes = vring_size(num, vring_align); - vring_init(&vring_split.vring, num, queue, vring_align); + vring_split->queue_dma_addr = dma_addr; + vring_split->queue_size_in_bytes = vring_size(num, vring_align); + + return 0; +} + +static struct virtqueue *vring_create_virtqueue_split( + unsigned int index, + unsigned int num, + unsigned int vring_align, + struct virtio_device *vdev, + bool weak_barriers, + bool may_reduce_num, + bool context, + bool (*notify)(struct virtqueue *), + void (*callback)(struct virtqueue *), + const char *name) +{ + struct vring_virtqueue_split vring_split = {}; + struct virtqueue *vq; + int err; + + err = vring_alloc_queue_split(&vring_split, vdev, num, vring_align, + may_reduce_num); + if (err) + return NULL; vq = __vring_new_virtqueue(index, &vring_split, vdev, weak_barriers, context, notify, callback, name); if (!vq) { - vring_free_queue(vdev, queue_size_in_bytes, queue, - dma_addr); + vring_free_split(&vring_split, vdev); return NULL; } - to_vvq(vq)->split.queue_dma_addr = dma_addr; - to_vvq(vq)->split.queue_size_in_bytes = queue_size_in_bytes; + to_vvq(vq)->split.queue_dma_addr = vring_split.queue_dma_addr; + to_vvq(vq)->split.queue_size_in_bytes = vring_split.queue_size_in_bytes; to_vvq(vq)->we_own_ring = true; return vq; -- cgit v1.2.3 From a2b36c8d7ddbaff801bcaa4592522cd3b7b08112 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:31 +0800 Subject: virtio_ring: split: extract the logic of alloc state and extra Separate the logic of creating desc_state, desc_extra, and subsequent patches will call it independently. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-12-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 52 ++++++++++++++++++++++++++++++-------------- 1 file changed, 36 insertions(+), 16 deletions(-) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index 5597a9b9e518..03fc656b1f40 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -212,6 +212,7 @@ static struct virtqueue *__vring_new_virtqueue(unsigned int index, bool (*notify)(struct virtqueue *), void (*callback)(struct virtqueue *), const char *name); +static struct vring_desc_extra *vring_alloc_desc_extra(unsigned int num); /* * Helpers. @@ -937,6 +938,32 @@ static void *virtqueue_detach_unused_buf_split(struct virtqueue *_vq) return NULL; } +static int vring_alloc_state_extra_split(struct vring_virtqueue_split *vring_split) +{ + struct vring_desc_state_split *state; + struct vring_desc_extra *extra; + u32 num = vring_split->vring.num; + + state = kmalloc_array(num, sizeof(struct vring_desc_state_split), GFP_KERNEL); + if (!state) + goto err_state; + + extra = vring_alloc_desc_extra(num); + if (!extra) + goto err_extra; + + memset(state, 0, num * sizeof(struct vring_desc_state_split)); + + vring_split->desc_state = state; + vring_split->desc_extra = extra; + return 0; + +err_extra: + kfree(state); +err_state: + return -ENOMEM; +} + static void vring_free_split(struct vring_virtqueue_split *vring_split, struct virtio_device *vdev) { @@ -2240,6 +2267,7 @@ static struct virtqueue *__vring_new_virtqueue(unsigned int index, const char *name) { struct vring_virtqueue *vq; + int err; if (virtio_has_feature(vdev, VIRTIO_F_RING_PACKED)) return NULL; @@ -2285,19 +2313,17 @@ static struct virtqueue *__vring_new_virtqueue(unsigned int index, vq->split.avail_flags_shadow); } - vq->split.desc_state = kmalloc_array(vring_split->vring.num, - sizeof(struct vring_desc_state_split), GFP_KERNEL); - if (!vq->split.desc_state) - goto err_state; - - vq->split.desc_extra = vring_alloc_desc_extra(vring_split->vring.num); - if (!vq->split.desc_extra) - goto err_extra; + err = vring_alloc_state_extra_split(vring_split); + if (err) { + kfree(vq); + return NULL; + } /* Put everything in free lists. */ vq->free_head = 0; - memset(vq->split.desc_state, 0, vring_split->vring.num * - sizeof(struct vring_desc_state_split)); + + vq->split.desc_state = vring_split->desc_state; + vq->split.desc_extra = vring_split->desc_extra; virtqueue_init(vq, vring_split->vring.num); @@ -2305,12 +2331,6 @@ static struct virtqueue *__vring_new_virtqueue(unsigned int index, list_add_tail(&vq->vq.list, &vdev->vqs); spin_unlock(&vdev->vqs_list_lock); return &vq->vq; - -err_extra: - kfree(vq->split.desc_state); -err_state: - kfree(vq); - return NULL; } struct virtqueue *vring_create_virtqueue( -- cgit v1.2.3 From 198fa7be96e52bc89c9e8a7e1c3b9e059ff203a0 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:32 +0800 Subject: virtio_ring: split: extract the logic of vring init Separate the logic of initializing vring, and subsequent patches will call it separately. This function completes the variable initialization of split vring. It together with the logic of atatch constitutes the initialization of vring. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-13-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index 03fc656b1f40..e456cc16ea2a 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -938,6 +938,25 @@ static void *virtqueue_detach_unused_buf_split(struct virtqueue *_vq) return NULL; } +static void virtqueue_vring_init_split(struct vring_virtqueue_split *vring_split, + struct vring_virtqueue *vq) +{ + struct virtio_device *vdev; + + vdev = vq->vq.vdev; + + vring_split->avail_flags_shadow = 0; + vring_split->avail_idx_shadow = 0; + + /* No callback? Tell other side not to bother us. */ + if (!vq->vq.callback) { + vring_split->avail_flags_shadow |= VRING_AVAIL_F_NO_INTERRUPT; + if (!vq->event) + vring_split->vring.avail->flags = cpu_to_virtio16(vdev, + vring_split->avail_flags_shadow); + } +} + static int vring_alloc_state_extra_split(struct vring_virtqueue_split *vring_split) { struct vring_desc_state_split *state; @@ -2302,16 +2321,6 @@ static struct virtqueue *__vring_new_virtqueue(unsigned int index, vq->split.queue_size_in_bytes = 0; vq->split.vring = vring_split->vring; - vq->split.avail_flags_shadow = 0; - vq->split.avail_idx_shadow = 0; - - /* No callback? Tell other side not to bother us. */ - if (!callback) { - vq->split.avail_flags_shadow |= VRING_AVAIL_F_NO_INTERRUPT; - if (!vq->event) - vq->split.vring.avail->flags = cpu_to_virtio16(vdev, - vq->split.avail_flags_shadow); - } err = vring_alloc_state_extra_split(vring_split); if (err) { @@ -2325,6 +2334,8 @@ static struct virtqueue *__vring_new_virtqueue(unsigned int index, vq->split.desc_state = vring_split->desc_state; vq->split.desc_extra = vring_split->desc_extra; + virtqueue_vring_init_split(vring_split, vq); + virtqueue_init(vq, vring_split->vring.num); spin_lock(&vdev->vqs_list_lock); -- cgit v1.2.3 From e1d6a423ea1867a3a84f12a99981f036acb8f354 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:33 +0800 Subject: virtio_ring: split: extract the logic of attach vring Separate the logic of attach vring, subsequent patches will call it separately. virtqueue_vring_init_split() completes the initialization of other variables of vring split. We can directly use vq->split = *vring_split to complete attach. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-14-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index e456cc16ea2a..d0df887c3ada 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -957,6 +957,15 @@ static void virtqueue_vring_init_split(struct vring_virtqueue_split *vring_split } } +static void virtqueue_vring_attach_split(struct vring_virtqueue *vq, + struct vring_virtqueue_split *vring_split) +{ + vq->split = *vring_split; + + /* Put everything in free lists. */ + vq->free_head = 0; +} + static int vring_alloc_state_extra_split(struct vring_virtqueue_split *vring_split) { struct vring_desc_state_split *state; @@ -1067,8 +1076,6 @@ static struct virtqueue *vring_create_virtqueue_split( return NULL; } - to_vvq(vq)->split.queue_dma_addr = vring_split.queue_dma_addr; - to_vvq(vq)->split.queue_size_in_bytes = vring_split.queue_size_in_bytes; to_vvq(vq)->we_own_ring = true; return vq; @@ -2317,26 +2324,16 @@ static struct virtqueue *__vring_new_virtqueue(unsigned int index, if (virtio_has_feature(vdev, VIRTIO_F_ORDER_PLATFORM)) vq->weak_barriers = false; - vq->split.queue_dma_addr = 0; - vq->split.queue_size_in_bytes = 0; - - vq->split.vring = vring_split->vring; - err = vring_alloc_state_extra_split(vring_split); if (err) { kfree(vq); return NULL; } - /* Put everything in free lists. */ - vq->free_head = 0; - - vq->split.desc_state = vring_split->desc_state; - vq->split.desc_extra = vring_split->desc_extra; - virtqueue_vring_init_split(vring_split, vq); virtqueue_init(vq, vring_split->vring.num); + virtqueue_vring_attach_split(vq, vring_split); spin_lock(&vdev->vqs_list_lock); list_add_tail(&vq->vq.list, &vdev->vqs); -- cgit v1.2.3 From e5175b419a1394e77ff418dd9bfaf15555dfe594 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:34 +0800 Subject: virtio_ring: split: introduce virtqueue_reinit_split() Introduce a function to initialize vq without allocating new ring, desc_state, desc_extra. Subsequent patches will call this function after reset vq to reinitialize vq. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-15-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index d0df887c3ada..948f8da7b780 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -957,6 +957,29 @@ static void virtqueue_vring_init_split(struct vring_virtqueue_split *vring_split } } +static void virtqueue_reinit_split(struct vring_virtqueue *vq) +{ + int num; + + num = vq->split.vring.num; + + vq->split.vring.avail->flags = 0; + vq->split.vring.avail->idx = 0; + + /* reset avail event */ + vq->split.vring.avail->ring[num] = 0; + + vq->split.vring.used->flags = 0; + vq->split.vring.used->idx = 0; + + /* reset used event */ + *(__virtio16 *)&(vq->split.vring.used->ring[num]) = 0; + + virtqueue_init(vq, num); + + virtqueue_vring_init_split(&vq->split, vq); +} + static void virtqueue_vring_attach_split(struct vring_virtqueue *vq, struct vring_virtqueue_split *vring_split) { -- cgit v1.2.3 From af36b16f6c1e51975a3815eb21c21c47f3114393 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:35 +0800 Subject: virtio_ring: split: reserve vring_align, may_reduce_num In vring_alloc_queue_split() save vring_align, may_reduce_num to structure vring_virtqueue_split. Used to create a new vring when implementing resize. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-16-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index 948f8da7b780..8cbb19cdb1ce 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -105,6 +105,13 @@ struct vring_virtqueue_split { /* DMA address and size information */ dma_addr_t queue_dma_addr; size_t queue_size_in_bytes; + + /* + * The parameters for creating vrings are reserved for creating new + * vring. + */ + u32 vring_align; + bool may_reduce_num; }; struct vring_virtqueue_packed { @@ -1068,6 +1075,9 @@ static int vring_alloc_queue_split(struct vring_virtqueue_split *vring_split, vring_split->queue_dma_addr = dma_addr; vring_split->queue_size_in_bytes = vring_size(num, vring_align); + vring_split->vring_align = vring_align; + vring_split->may_reduce_num = may_reduce_num; + return 0; } -- cgit v1.2.3 From 6fea20e5611fc5c8264f04a878a98c06b6209eed Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:36 +0800 Subject: virtio_ring: split: introduce virtqueue_resize_split() virtio ring split supports resize. Only after the new vring is successfully allocated based on the new num, we will release the old vring. In any case, an error is returned, indicating that the vring still points to the old vring. In the case of an error, re-initialize(virtqueue_reinit_split()) the virtqueue to ensure that the vring can be used. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-17-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index 8cbb19cdb1ce..1852912d711e 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -220,6 +220,7 @@ static struct virtqueue *__vring_new_virtqueue(unsigned int index, void (*callback)(struct virtqueue *), const char *name); static struct vring_desc_extra *vring_alloc_desc_extra(unsigned int num); +static void vring_free(struct virtqueue *_vq); /* * Helpers. @@ -1114,6 +1115,39 @@ static struct virtqueue *vring_create_virtqueue_split( return vq; } +static int virtqueue_resize_split(struct virtqueue *_vq, u32 num) +{ + struct vring_virtqueue_split vring_split = {}; + struct vring_virtqueue *vq = to_vvq(_vq); + struct virtio_device *vdev = _vq->vdev; + int err; + + err = vring_alloc_queue_split(&vring_split, vdev, num, + vq->split.vring_align, + vq->split.may_reduce_num); + if (err) + goto err; + + err = vring_alloc_state_extra_split(&vring_split); + if (err) + goto err_state_extra; + + vring_free(&vq->vq); + + virtqueue_vring_init_split(&vring_split, vq); + + virtqueue_init(vq, vring_split.vring.num); + virtqueue_vring_attach_split(vq, &vring_split); + + return 0; + +err_state_extra: + vring_free_split(&vring_split, vdev); +err: + virtqueue_reinit_split(vq); + return -ENOMEM; +} + /* * Packed ring specific functions - *_packed(). -- cgit v1.2.3 From 6356f8bb01ddf4a6d9f2da16f7c0e3c093c7f548 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:37 +0800 Subject: virtio_ring: packed: introduce vring_free_packed Free the structure struct vring_vritqueue_packed. Subsequent patches require it. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-18-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index 1852912d711e..2993d817871a 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -1832,6 +1832,28 @@ static struct vring_desc_extra *vring_alloc_desc_extra(unsigned int num) return desc_extra; } +static void vring_free_packed(struct vring_virtqueue_packed *vring_packed, + struct virtio_device *vdev) +{ + if (vring_packed->vring.desc) + vring_free_queue(vdev, vring_packed->ring_size_in_bytes, + vring_packed->vring.desc, + vring_packed->ring_dma_addr); + + if (vring_packed->vring.driver) + vring_free_queue(vdev, vring_packed->event_size_in_bytes, + vring_packed->vring.driver, + vring_packed->driver_event_dma_addr); + + if (vring_packed->vring.device) + vring_free_queue(vdev, vring_packed->event_size_in_bytes, + vring_packed->vring.device, + vring_packed->device_event_dma_addr); + + kfree(vring_packed->desc_state); + kfree(vring_packed->desc_extra); +} + static struct virtqueue *vring_create_virtqueue_packed( unsigned int index, unsigned int num, -- cgit v1.2.3 From 6b60b9c008e56e43cdda6ae618f7f58679a8901a Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:38 +0800 Subject: virtio_ring: packed: extract the logic of alloc queue Separate the logic of packed to create vring queue. This feature is required for subsequent virtuqueue reset vring. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-19-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 80 ++++++++++++++++++++++++++++---------------- 1 file changed, 51 insertions(+), 29 deletions(-) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index 2993d817871a..8209923ea7d7 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -1854,19 +1854,10 @@ static void vring_free_packed(struct vring_virtqueue_packed *vring_packed, kfree(vring_packed->desc_extra); } -static struct virtqueue *vring_create_virtqueue_packed( - unsigned int index, - unsigned int num, - unsigned int vring_align, - struct virtio_device *vdev, - bool weak_barriers, - bool may_reduce_num, - bool context, - bool (*notify)(struct virtqueue *), - void (*callback)(struct virtqueue *), - const char *name) +static int vring_alloc_queue_packed(struct vring_virtqueue_packed *vring_packed, + struct virtio_device *vdev, + u32 num) { - struct vring_virtqueue *vq; struct vring_packed_desc *ring; struct vring_packed_desc_event *driver, *device; dma_addr_t ring_dma_addr, driver_event_dma_addr, device_event_dma_addr; @@ -1878,7 +1869,11 @@ static struct virtqueue *vring_create_virtqueue_packed( &ring_dma_addr, GFP_KERNEL|__GFP_NOWARN|__GFP_ZERO); if (!ring) - goto err_ring; + goto err; + + vring_packed->vring.desc = ring; + vring_packed->ring_dma_addr = ring_dma_addr; + vring_packed->ring_size_in_bytes = ring_size_in_bytes; event_size_in_bytes = sizeof(struct vring_packed_desc_event); @@ -1886,13 +1881,47 @@ static struct virtqueue *vring_create_virtqueue_packed( &driver_event_dma_addr, GFP_KERNEL|__GFP_NOWARN|__GFP_ZERO); if (!driver) - goto err_driver; + goto err; + + vring_packed->vring.driver = driver; + vring_packed->event_size_in_bytes = event_size_in_bytes; + vring_packed->driver_event_dma_addr = driver_event_dma_addr; device = vring_alloc_queue(vdev, event_size_in_bytes, &device_event_dma_addr, GFP_KERNEL|__GFP_NOWARN|__GFP_ZERO); if (!device) - goto err_device; + goto err; + + vring_packed->vring.device = device; + vring_packed->device_event_dma_addr = device_event_dma_addr; + + vring_packed->vring.num = num; + + return 0; + +err: + vring_free_packed(vring_packed, vdev); + return -ENOMEM; +} + +static struct virtqueue *vring_create_virtqueue_packed( + unsigned int index, + unsigned int num, + unsigned int vring_align, + struct virtio_device *vdev, + bool weak_barriers, + bool may_reduce_num, + bool context, + bool (*notify)(struct virtqueue *), + void (*callback)(struct virtqueue *), + const char *name) +{ + struct vring_virtqueue_packed vring_packed = {}; + struct vring_virtqueue *vq; + + if (vring_alloc_queue_packed(&vring_packed, vdev, num)) + goto err_ring; vq = kmalloc(sizeof(*vq), GFP_KERNEL); if (!vq) @@ -1920,17 +1949,14 @@ static struct virtqueue *vring_create_virtqueue_packed( if (virtio_has_feature(vdev, VIRTIO_F_ORDER_PLATFORM)) vq->weak_barriers = false; - vq->packed.ring_dma_addr = ring_dma_addr; - vq->packed.driver_event_dma_addr = driver_event_dma_addr; - vq->packed.device_event_dma_addr = device_event_dma_addr; + vq->packed.ring_dma_addr = vring_packed.ring_dma_addr; + vq->packed.driver_event_dma_addr = vring_packed.driver_event_dma_addr; + vq->packed.device_event_dma_addr = vring_packed.device_event_dma_addr; - vq->packed.ring_size_in_bytes = ring_size_in_bytes; - vq->packed.event_size_in_bytes = event_size_in_bytes; + vq->packed.ring_size_in_bytes = vring_packed.ring_size_in_bytes; + vq->packed.event_size_in_bytes = vring_packed.event_size_in_bytes; - vq->packed.vring.num = num; - vq->packed.vring.desc = ring; - vq->packed.vring.driver = driver; - vq->packed.vring.device = device; + vq->packed.vring = vring_packed.vring; vq->packed.next_avail_idx = 0; vq->packed.avail_wrap_counter = 1; @@ -1972,11 +1998,7 @@ err_desc_extra: err_desc_state: kfree(vq); err_vq: - vring_free_queue(vdev, event_size_in_bytes, device, device_event_dma_addr); -err_device: - vring_free_queue(vdev, event_size_in_bytes, driver, driver_event_dma_addr); -err_driver: - vring_free_queue(vdev, ring_size_in_bytes, ring, ring_dma_addr); + vring_free_packed(&vring_packed, vdev); err_ring: return NULL; } -- cgit v1.2.3 From ef3167cfd5f28bc86d68e82fc52d07ed03dff2f7 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:39 +0800 Subject: virtio_ring: packed: extract the logic of alloc state and extra Separate the logic for alloc desc_state and desc_extra, which will be called separately by subsequent patches. Use struct vring_packed to pass desc_state, desc_extra. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-20-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 48 +++++++++++++++++++++++++++++++------------- 1 file changed, 34 insertions(+), 14 deletions(-) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index 8209923ea7d7..533af061d009 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -1905,6 +1905,33 @@ err: return -ENOMEM; } +static int vring_alloc_state_extra_packed(struct vring_virtqueue_packed *vring_packed) +{ + struct vring_desc_state_packed *state; + struct vring_desc_extra *extra; + u32 num = vring_packed->vring.num; + + state = kmalloc_array(num, sizeof(struct vring_desc_state_packed), GFP_KERNEL); + if (!state) + goto err_desc_state; + + memset(state, 0, num * sizeof(struct vring_desc_state_packed)); + + extra = vring_alloc_desc_extra(num); + if (!extra) + goto err_desc_extra; + + vring_packed->desc_state = state; + vring_packed->desc_extra = extra; + + return 0; + +err_desc_extra: + kfree(state); +err_desc_state: + return -ENOMEM; +} + static struct virtqueue *vring_create_virtqueue_packed( unsigned int index, unsigned int num, @@ -1919,6 +1946,7 @@ static struct virtqueue *vring_create_virtqueue_packed( { struct vring_virtqueue_packed vring_packed = {}; struct vring_virtqueue *vq; + int err; if (vring_alloc_queue_packed(&vring_packed, vdev, num)) goto err_ring; @@ -1963,21 +1991,15 @@ static struct virtqueue *vring_create_virtqueue_packed( vq->packed.event_flags_shadow = 0; vq->packed.avail_used_flags = 1 << VRING_PACKED_DESC_F_AVAIL; - vq->packed.desc_state = kmalloc_array(num, - sizeof(struct vring_desc_state_packed), - GFP_KERNEL); - if (!vq->packed.desc_state) - goto err_desc_state; - - memset(vq->packed.desc_state, 0, - num * sizeof(struct vring_desc_state_packed)); + err = vring_alloc_state_extra_packed(&vring_packed); + if (err) + goto err_state_extra; /* Put everything in free lists. */ vq->free_head = 0; - vq->packed.desc_extra = vring_alloc_desc_extra(num); - if (!vq->packed.desc_extra) - goto err_desc_extra; + vq->packed.desc_state = vring_packed.desc_state; + vq->packed.desc_extra = vring_packed.desc_extra; /* No callback? Tell other side not to bother us. */ if (!callback) { @@ -1993,9 +2015,7 @@ static struct virtqueue *vring_create_virtqueue_packed( spin_unlock(&vdev->vqs_list_lock); return &vq->vq; -err_desc_extra: - kfree(vq->packed.desc_state); -err_desc_state: +err_state_extra: kfree(vq); err_vq: vring_free_packed(&vring_packed, vdev); -- cgit v1.2.3 From 1a107c87ebcf04ede1b86e5de192df34b6e50bd7 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:40 +0800 Subject: virtio_ring: packed: extract the logic of vring init Separate the logic of initializing vring, and subsequent patches will call it separately. This function completes the variable initialization of packed vring. It together with the logic of atatch constitutes the initialization of vring. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-21-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index 533af061d009..a6f90e6e621b 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -1932,6 +1932,22 @@ err_desc_state: return -ENOMEM; } +static void virtqueue_vring_init_packed(struct vring_virtqueue_packed *vring_packed, + bool callback) +{ + vring_packed->next_avail_idx = 0; + vring_packed->avail_wrap_counter = 1; + vring_packed->event_flags_shadow = 0; + vring_packed->avail_used_flags = 1 << VRING_PACKED_DESC_F_AVAIL; + + /* No callback? Tell other side not to bother us. */ + if (!callback) { + vring_packed->event_flags_shadow = VRING_PACKED_EVENT_FLAG_DISABLE; + vring_packed->vring.driver->flags = + cpu_to_le16(vring_packed->event_flags_shadow); + } +} + static struct virtqueue *vring_create_virtqueue_packed( unsigned int index, unsigned int num, @@ -1986,11 +2002,6 @@ static struct virtqueue *vring_create_virtqueue_packed( vq->packed.vring = vring_packed.vring; - vq->packed.next_avail_idx = 0; - vq->packed.avail_wrap_counter = 1; - vq->packed.event_flags_shadow = 0; - vq->packed.avail_used_flags = 1 << VRING_PACKED_DESC_F_AVAIL; - err = vring_alloc_state_extra_packed(&vring_packed); if (err) goto err_state_extra; @@ -2001,12 +2012,7 @@ static struct virtqueue *vring_create_virtqueue_packed( vq->packed.desc_state = vring_packed.desc_state; vq->packed.desc_extra = vring_packed.desc_extra; - /* No callback? Tell other side not to bother us. */ - if (!callback) { - vq->packed.event_flags_shadow = VRING_PACKED_EVENT_FLAG_DISABLE; - vq->packed.vring.driver->flags = - cpu_to_le16(vq->packed.event_flags_shadow); - } + virtqueue_vring_init_packed(&vring_packed, !!callback); virtqueue_init(vq, num); -- cgit v1.2.3 From 51d649f14aae0986c62cf798b262f99b49836e88 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:41 +0800 Subject: virtio_ring: packed: extract the logic of attach vring Separate the logic of attach vring, the subsequent patch will call it separately. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-22-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index a6f90e6e621b..93d2a950f536 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -1948,6 +1948,15 @@ static void virtqueue_vring_init_packed(struct vring_virtqueue_packed *vring_pac } } +static void virtqueue_vring_attach_packed(struct vring_virtqueue *vq, + struct vring_virtqueue_packed *vring_packed) +{ + vq->packed = *vring_packed; + + /* Put everything in free lists. */ + vq->free_head = 0; +} + static struct virtqueue *vring_create_virtqueue_packed( unsigned int index, unsigned int num, @@ -1993,28 +2002,14 @@ static struct virtqueue *vring_create_virtqueue_packed( if (virtio_has_feature(vdev, VIRTIO_F_ORDER_PLATFORM)) vq->weak_barriers = false; - vq->packed.ring_dma_addr = vring_packed.ring_dma_addr; - vq->packed.driver_event_dma_addr = vring_packed.driver_event_dma_addr; - vq->packed.device_event_dma_addr = vring_packed.device_event_dma_addr; - - vq->packed.ring_size_in_bytes = vring_packed.ring_size_in_bytes; - vq->packed.event_size_in_bytes = vring_packed.event_size_in_bytes; - - vq->packed.vring = vring_packed.vring; - err = vring_alloc_state_extra_packed(&vring_packed); if (err) goto err_state_extra; - /* Put everything in free lists. */ - vq->free_head = 0; - - vq->packed.desc_state = vring_packed.desc_state; - vq->packed.desc_extra = vring_packed.desc_extra; - virtqueue_vring_init_packed(&vring_packed, !!callback); virtqueue_init(vq, num); + virtqueue_vring_attach_packed(vq, &vring_packed); spin_lock(&vdev->vqs_list_lock); list_add_tail(&vq->vq.list, &vdev->vqs); -- cgit v1.2.3 From 56775e141b18790f70e05537f3a1417565e766ac Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:42 +0800 Subject: virtio_ring: packed: introduce virtqueue_reinit_packed() Introduce a function to initialize vq without allocating new ring, desc_state, desc_extra. Subsequent patches will call this function after reset vq to reinitialize vq. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-23-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index 93d2a950f536..db06fb0ddfd6 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -1957,6 +1957,18 @@ static void virtqueue_vring_attach_packed(struct vring_virtqueue *vq, vq->free_head = 0; } +static void virtqueue_reinit_packed(struct vring_virtqueue *vq) +{ + memset(vq->packed.vring.device, 0, vq->packed.event_size_in_bytes); + memset(vq->packed.vring.driver, 0, vq->packed.event_size_in_bytes); + + /* we need to reset the desc.flags. For more, see is_used_desc_packed() */ + memset(vq->packed.vring.desc, 0, vq->packed.ring_size_in_bytes); + + virtqueue_init(vq, vq->packed.vring.num); + virtqueue_vring_init_packed(&vq->packed, !!vq->vq.callback); +} + static struct virtqueue *vring_create_virtqueue_packed( unsigned int index, unsigned int num, -- cgit v1.2.3 From 947f9fcf674f8f3f09e01dfb5d8e564650875878 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:43 +0800 Subject: virtio_ring: packed: introduce virtqueue_resize_packed() virtio ring packed supports resize. Only after the new vring is successfully allocated based on the new num, we will release the old vring. In any case, an error is returned, indicating that the vring still points to the old vring. In the case of an error, re-initialize(by virtqueue_reinit_packed()) the virtqueue to ensure that the vring can be used. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-24-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index db06fb0ddfd6..bea5a3448217 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -2036,6 +2036,36 @@ err_ring: return NULL; } +static int virtqueue_resize_packed(struct virtqueue *_vq, u32 num) +{ + struct vring_virtqueue_packed vring_packed = {}; + struct vring_virtqueue *vq = to_vvq(_vq); + struct virtio_device *vdev = _vq->vdev; + int err; + + if (vring_alloc_queue_packed(&vring_packed, vdev, num)) + goto err_ring; + + err = vring_alloc_state_extra_packed(&vring_packed); + if (err) + goto err_state_extra; + + vring_free(&vq->vq); + + virtqueue_vring_init_packed(&vring_packed, !!vq->vq.callback); + + virtqueue_init(vq, vring_packed.vring.num); + virtqueue_vring_attach_packed(vq, &vring_packed); + + return 0; + +err_state_extra: + vring_free_packed(&vring_packed, vdev); +err_ring: + virtqueue_reinit_packed(vq); + return -ENOMEM; +} + /* * Generic functions and exported symbols. -- cgit v1.2.3 From c790e8e1817f1a17c05e64f1c4f16f231b8529d5 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:44 +0800 Subject: virtio_ring: introduce virtqueue_resize() Introduce virtqueue_resize() to implement the resize of vring. Based on these, the driver can dynamically adjust the size of the vring. For example: ethtool -G. virtqueue_resize() implements resize based on the vq reset function. In case of failure to allocate a new vring, it will give up resize and use the original vring. During this process, if the re-enable reset vq fails, the vq can no longer be used. Although the probability of this situation is not high. The parameter recycle is used to recycle the buffer that is no longer used. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-25-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 69 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/virtio.h | 3 ++ 2 files changed, 72 insertions(+) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index bea5a3448217..6447a09e2e38 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -2539,6 +2539,75 @@ struct virtqueue *vring_create_virtqueue( } EXPORT_SYMBOL_GPL(vring_create_virtqueue); +/** + * virtqueue_resize - resize the vring of vq + * @_vq: the struct virtqueue we're talking about. + * @num: new ring num + * @recycle: callback for recycle the useless buffer + * + * When it is really necessary to create a new vring, it will set the current vq + * into the reset state. Then call the passed callback to recycle the buffer + * that is no longer used. Only after the new vring is successfully created, the + * old vring will be released. + * + * Caller must ensure we don't call this with other virtqueue operations + * at the same time (except where noted). + * + * Returns zero or a negative error. + * 0: success. + * -ENOMEM: Failed to allocate a new ring, fall back to the original ring size. + * vq can still work normally + * -EBUSY: Failed to sync with device, vq may not work properly + * -ENOENT: Transport or device not supported + * -E2BIG/-EINVAL: num error + * -EPERM: Operation not permitted + * + */ +int virtqueue_resize(struct virtqueue *_vq, u32 num, + void (*recycle)(struct virtqueue *vq, void *buf)) +{ + struct vring_virtqueue *vq = to_vvq(_vq); + struct virtio_device *vdev = vq->vq.vdev; + void *buf; + int err; + + if (!vq->we_own_ring) + return -EPERM; + + if (num > vq->vq.num_max) + return -E2BIG; + + if (!num) + return -EINVAL; + + if ((vq->packed_ring ? vq->packed.vring.num : vq->split.vring.num) == num) + return 0; + + if (!vdev->config->disable_vq_and_reset) + return -ENOENT; + + if (!vdev->config->enable_vq_after_reset) + return -ENOENT; + + err = vdev->config->disable_vq_and_reset(_vq); + if (err) + return err; + + while ((buf = virtqueue_detach_unused_buf(_vq)) != NULL) + recycle(_vq, buf); + + if (vq->packed_ring) + err = virtqueue_resize_packed(_vq, num); + else + err = virtqueue_resize_split(_vq, num); + + if (vdev->config->enable_vq_after_reset(_vq)) + return -EBUSY; + + return err; +} +EXPORT_SYMBOL_GPL(virtqueue_resize); + /* Only available for split ring */ struct virtqueue *vring_new_virtqueue(unsigned int index, unsigned int num, diff --git a/include/linux/virtio.h b/include/linux/virtio.h index 129bde7521e3..62e31bca5602 100644 --- a/include/linux/virtio.h +++ b/include/linux/virtio.h @@ -91,6 +91,9 @@ dma_addr_t virtqueue_get_desc_addr(struct virtqueue *vq); dma_addr_t virtqueue_get_avail_addr(struct virtqueue *vq); dma_addr_t virtqueue_get_used_addr(struct virtqueue *vq); +int virtqueue_resize(struct virtqueue *vq, u32 num, + void (*recycle)(struct virtqueue *vq, void *buf)); + /** * virtio_device - representation of a device using virtio * @index: unique position on the virtio bus -- cgit v1.2.3 From ea024594b1dc5b6719c1400ae154690f5c203996 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:45 +0800 Subject: virtio_pci: struct virtio_pci_common_cfg add queue_notify_data Add queue_notify_data in struct virtio_pci_common_cfg, which comes from here https://github.com/oasis-tcs/virtio-spec/issues/89 In order not to affect the API, add a dedicated structure struct virtio_pci_modern_common_cfg to virtio_pci_modern.h. Since I want to add queue_reset after queue_notify_data, I submitted this patch first. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-26-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- include/linux/virtio_pci_modern.h | 7 +++++++ include/uapi/linux/virtio_pci.h | 1 + 2 files changed, 8 insertions(+) diff --git a/include/linux/virtio_pci_modern.h b/include/linux/virtio_pci_modern.h index eb2bd9b4077d..41f5a018bd94 100644 --- a/include/linux/virtio_pci_modern.h +++ b/include/linux/virtio_pci_modern.h @@ -5,6 +5,13 @@ #include #include +struct virtio_pci_modern_common_cfg { + struct virtio_pci_common_cfg cfg; + + __le16 queue_notify_data; /* read-write */ + __le16 padding; +}; + struct virtio_pci_modern_device { struct pci_dev *pci_dev; diff --git a/include/uapi/linux/virtio_pci.h b/include/uapi/linux/virtio_pci.h index 3a86f36d7e3d..f5981a874481 100644 --- a/include/uapi/linux/virtio_pci.h +++ b/include/uapi/linux/virtio_pci.h @@ -202,6 +202,7 @@ struct virtio_pci_cfg_cap { #define VIRTIO_PCI_COMMON_Q_AVAILHI 44 #define VIRTIO_PCI_COMMON_Q_USEDLO 48 #define VIRTIO_PCI_COMMON_Q_USEDHI 52 +#define VIRTIO_PCI_COMMON_Q_NDATA 56 #endif /* VIRTIO_PCI_NO_MODERN */ -- cgit v1.2.3 From 3251063155032729b8793ac3957136ae25c0bafa Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:46 +0800 Subject: virtio: allow to unbreak/break virtqueue individually This patch allows the new introduced __virtqueue_break()/__virtqueue_unbreak() to break/unbreak the virtqueue. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-27-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 24 ++++++++++++++++++++++++ include/linux/virtio.h | 3 +++ 2 files changed, 27 insertions(+) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index 6447a09e2e38..accb3ae6cc95 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -2724,6 +2724,30 @@ unsigned int virtqueue_get_vring_size(struct virtqueue *_vq) } EXPORT_SYMBOL_GPL(virtqueue_get_vring_size); +/* + * This function should only be called by the core, not directly by the driver. + */ +void __virtqueue_break(struct virtqueue *_vq) +{ + struct vring_virtqueue *vq = to_vvq(_vq); + + /* Pairs with READ_ONCE() in virtqueue_is_broken(). */ + WRITE_ONCE(vq->broken, true); +} +EXPORT_SYMBOL_GPL(__virtqueue_break); + +/* + * This function should only be called by the core, not directly by the driver. + */ +void __virtqueue_unbreak(struct virtqueue *_vq) +{ + struct vring_virtqueue *vq = to_vvq(_vq); + + /* Pairs with READ_ONCE() in virtqueue_is_broken(). */ + WRITE_ONCE(vq->broken, false); +} +EXPORT_SYMBOL_GPL(__virtqueue_unbreak); + bool virtqueue_is_broken(struct virtqueue *_vq) { struct vring_virtqueue *vq = to_vvq(_vq); diff --git a/include/linux/virtio.h b/include/linux/virtio.h index 62e31bca5602..d45ee82a4470 100644 --- a/include/linux/virtio.h +++ b/include/linux/virtio.h @@ -138,6 +138,9 @@ bool is_virtio_device(struct device *dev); void virtio_break_device(struct virtio_device *dev); void __virtio_unbreak_device(struct virtio_device *dev); +void __virtqueue_break(struct virtqueue *_vq); +void __virtqueue_unbreak(struct virtqueue *_vq); + void virtio_config_changed(struct virtio_device *dev); #ifdef CONFIG_PM_SLEEP int virtio_device_freeze(struct virtio_device *dev); -- cgit v1.2.3 From d94587b5bb5c4bba32fbc2bd92c86cc6de25167f Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:47 +0800 Subject: virtio: queue_reset: add VIRTIO_F_RING_RESET Added VIRTIO_F_RING_RESET, it came from here https://github.com/oasis-tcs/virtio-spec/issues/124 https://github.com/oasis-tcs/virtio-spec/issues/139 This feature indicates that the driver can reset a queue individually. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-28-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- include/uapi/linux/virtio_config.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/virtio_config.h b/include/uapi/linux/virtio_config.h index f0fb0ae021c0..3c05162bc988 100644 --- a/include/uapi/linux/virtio_config.h +++ b/include/uapi/linux/virtio_config.h @@ -52,7 +52,7 @@ * rest are per-device feature bits. */ #define VIRTIO_TRANSPORT_F_START 28 -#define VIRTIO_TRANSPORT_F_END 38 +#define VIRTIO_TRANSPORT_F_END 41 #ifndef VIRTIO_CONFIG_NO_LEGACY /* Do we get callbacks when the ring is completely used, even if we've @@ -98,4 +98,9 @@ * Does the device support Single Root I/O Virtualization? */ #define VIRTIO_F_SR_IOV 37 + +/* + * This feature indicates that the driver can reset a queue individually. + */ +#define VIRTIO_F_RING_RESET 40 #endif /* _UAPI_LINUX_VIRTIO_CONFIG_H */ -- cgit v1.2.3 From 4913e85441b40386c4bb093f188b955d8165f1b7 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:48 +0800 Subject: virtio_ring: struct virtqueue introduce reset Introduce a new member reset to the structure virtqueue to determine whether the current vq is in the reset state. Subsequent patches will use it. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-29-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_ring.c | 2 ++ include/linux/virtio.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index accb3ae6cc95..d66c8e6d0ef3 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -1996,6 +1996,7 @@ static struct virtqueue *vring_create_virtqueue_packed( vq->vq.vdev = vdev; vq->vq.name = name; vq->vq.index = index; + vq->vq.reset = false; vq->we_own_ring = true; vq->notify = notify; vq->weak_barriers = weak_barriers; @@ -2481,6 +2482,7 @@ static struct virtqueue *__vring_new_virtqueue(unsigned int index, vq->vq.vdev = vdev; vq->vq.name = name; vq->vq.index = index; + vq->vq.reset = false; vq->we_own_ring = false; vq->notify = notify; vq->weak_barriers = weak_barriers; diff --git a/include/linux/virtio.h b/include/linux/virtio.h index d45ee82a4470..a3f73bb6733e 100644 --- a/include/linux/virtio.h +++ b/include/linux/virtio.h @@ -20,6 +20,7 @@ * @index: the zero-based ordinal number for this queue. * @num_free: number of elements we expect to be able to fit. * @num_max: the maximum number of elements supported by the device. + * @reset: vq is in reset state or not. * * A note on @num_free: with indirect buffers, each buffer needs one * element in the queue, otherwise a buffer will need one element per @@ -34,6 +35,7 @@ struct virtqueue { unsigned int num_free; unsigned int num_max; void *priv; + bool reset; }; int virtqueue_add_outbuf(struct virtqueue *vq, -- cgit v1.2.3 From 0cdd450e70510c9e13af8099e9f6c1467e6a0b91 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:49 +0800 Subject: virtio_pci: struct virtio_pci_common_cfg add queue_reset Add queue_reset in virtio_pci_modern_common_cfg. https://github.com/oasis-tcs/virtio-spec/issues/124 https://github.com/oasis-tcs/virtio-spec/issues/139 Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-30-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- include/linux/virtio_pci_modern.h | 2 +- include/uapi/linux/virtio_pci.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/linux/virtio_pci_modern.h b/include/linux/virtio_pci_modern.h index 41f5a018bd94..05123b9a606f 100644 --- a/include/linux/virtio_pci_modern.h +++ b/include/linux/virtio_pci_modern.h @@ -9,7 +9,7 @@ struct virtio_pci_modern_common_cfg { struct virtio_pci_common_cfg cfg; __le16 queue_notify_data; /* read-write */ - __le16 padding; + __le16 queue_reset; /* read-write */ }; struct virtio_pci_modern_device { diff --git a/include/uapi/linux/virtio_pci.h b/include/uapi/linux/virtio_pci.h index f5981a874481..f703afc7ad31 100644 --- a/include/uapi/linux/virtio_pci.h +++ b/include/uapi/linux/virtio_pci.h @@ -203,6 +203,7 @@ struct virtio_pci_cfg_cap { #define VIRTIO_PCI_COMMON_Q_USEDLO 48 #define VIRTIO_PCI_COMMON_Q_USEDHI 52 #define VIRTIO_PCI_COMMON_Q_NDATA 56 +#define VIRTIO_PCI_COMMON_Q_RESET 58 #endif /* VIRTIO_PCI_NO_MODERN */ -- cgit v1.2.3 From 0b50cece0b7857732d2055f2c77f8730c10f9196 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:50 +0800 Subject: virtio_pci: introduce helper to get/set queue reset Introduce new helpers to implement queue reset and get queue reset status. https://github.com/oasis-tcs/virtio-spec/issues/124 https://github.com/oasis-tcs/virtio-spec/issues/139 Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-31-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_pci_modern_dev.c | 39 ++++++++++++++++++++++++++++++++++ include/linux/virtio_pci_modern.h | 2 ++ 2 files changed, 41 insertions(+) diff --git a/drivers/virtio/virtio_pci_modern_dev.c b/drivers/virtio/virtio_pci_modern_dev.c index fa2a9445bb18..869cb46bef96 100644 --- a/drivers/virtio/virtio_pci_modern_dev.c +++ b/drivers/virtio/virtio_pci_modern_dev.c @@ -3,6 +3,7 @@ #include #include #include +#include /* * vp_modern_map_capability - map a part of virtio pci capability @@ -474,6 +475,44 @@ void vp_modern_set_status(struct virtio_pci_modern_device *mdev, } EXPORT_SYMBOL_GPL(vp_modern_set_status); +/* + * vp_modern_get_queue_reset - get the queue reset status + * @mdev: the modern virtio-pci device + * @index: queue index + */ +int vp_modern_get_queue_reset(struct virtio_pci_modern_device *mdev, u16 index) +{ + struct virtio_pci_modern_common_cfg __iomem *cfg; + + cfg = (struct virtio_pci_modern_common_cfg __iomem *)mdev->common; + + vp_iowrite16(index, &cfg->cfg.queue_select); + return vp_ioread16(&cfg->queue_reset); +} +EXPORT_SYMBOL_GPL(vp_modern_get_queue_reset); + +/* + * vp_modern_set_queue_reset - reset the queue + * @mdev: the modern virtio-pci device + * @index: queue index + */ +void vp_modern_set_queue_reset(struct virtio_pci_modern_device *mdev, u16 index) +{ + struct virtio_pci_modern_common_cfg __iomem *cfg; + + cfg = (struct virtio_pci_modern_common_cfg __iomem *)mdev->common; + + vp_iowrite16(index, &cfg->cfg.queue_select); + vp_iowrite16(1, &cfg->queue_reset); + + while (vp_ioread16(&cfg->queue_reset)) + msleep(1); + + while (vp_ioread16(&cfg->cfg.queue_enable)) + msleep(1); +} +EXPORT_SYMBOL_GPL(vp_modern_set_queue_reset); + /* * vp_modern_queue_vector - set the MSIX vector for a specific virtqueue * @mdev: the modern virtio-pci device diff --git a/include/linux/virtio_pci_modern.h b/include/linux/virtio_pci_modern.h index 05123b9a606f..c4eeb79b0139 100644 --- a/include/linux/virtio_pci_modern.h +++ b/include/linux/virtio_pci_modern.h @@ -113,4 +113,6 @@ void __iomem * vp_modern_map_vq_notify(struct virtio_pci_modern_device *mdev, u16 index, resource_size_t *pa); int vp_modern_probe(struct virtio_pci_modern_device *mdev); void vp_modern_remove(struct virtio_pci_modern_device *mdev); +int vp_modern_get_queue_reset(struct virtio_pci_modern_device *mdev, u16 index); +void vp_modern_set_queue_reset(struct virtio_pci_modern_device *mdev, u16 index); #endif -- cgit v1.2.3 From 56bdc06139404b3b06ed75ec99b93445d7e0b8c3 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:51 +0800 Subject: virtio_pci: extract the logic of active vq for modern pci Introduce vp_active_vq() to configure vring to backend after vq attach vring. And configure vq vector if necessary. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-32-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_pci_modern.c | 46 +++++++++++++++++++++++--------------- 1 file changed, 28 insertions(+), 18 deletions(-) diff --git a/drivers/virtio/virtio_pci_modern.c b/drivers/virtio/virtio_pci_modern.c index e7e0b8c850f6..9041d9a41b7d 100644 --- a/drivers/virtio/virtio_pci_modern.c +++ b/drivers/virtio/virtio_pci_modern.c @@ -176,6 +176,29 @@ static void vp_reset(struct virtio_device *vdev) vp_synchronize_vectors(vdev); } +static int vp_active_vq(struct virtqueue *vq, u16 msix_vec) +{ + struct virtio_pci_device *vp_dev = to_vp_device(vq->vdev); + struct virtio_pci_modern_device *mdev = &vp_dev->mdev; + unsigned long index; + + index = vq->index; + + /* activate the queue */ + vp_modern_set_queue_size(mdev, index, virtqueue_get_vring_size(vq)); + vp_modern_queue_address(mdev, index, virtqueue_get_desc_addr(vq), + virtqueue_get_avail_addr(vq), + virtqueue_get_used_addr(vq)); + + if (msix_vec != VIRTIO_MSI_NO_VECTOR) { + msix_vec = vp_modern_queue_vector(mdev, index, msix_vec); + if (msix_vec == VIRTIO_MSI_NO_VECTOR) + return -EBUSY; + } + + return 0; +} + static u16 vp_config_vector(struct virtio_pci_device *vp_dev, u16 vector) { return vp_modern_config_vector(&vp_dev->mdev, vector); @@ -220,32 +243,19 @@ static struct virtqueue *setup_vq(struct virtio_pci_device *vp_dev, vq->num_max = num; - /* activate the queue */ - vp_modern_set_queue_size(mdev, index, virtqueue_get_vring_size(vq)); - vp_modern_queue_address(mdev, index, virtqueue_get_desc_addr(vq), - virtqueue_get_avail_addr(vq), - virtqueue_get_used_addr(vq)); + err = vp_active_vq(vq, msix_vec); + if (err) + goto err; vq->priv = (void __force *)vp_modern_map_vq_notify(mdev, index, NULL); if (!vq->priv) { err = -ENOMEM; - goto err_map_notify; - } - - if (msix_vec != VIRTIO_MSI_NO_VECTOR) { - msix_vec = vp_modern_queue_vector(mdev, index, msix_vec); - if (msix_vec == VIRTIO_MSI_NO_VECTOR) { - err = -EBUSY; - goto err_assign_vector; - } + goto err; } return vq; -err_assign_vector: - if (!mdev->notify_base) - pci_iounmap(mdev->pci_dev, (void __iomem __force *)vq->priv); -err_map_notify: +err: vring_del_virtqueue(vq); return ERR_PTR(err); } -- cgit v1.2.3 From 04ca0b0b16f11faf74fa92468dab51b8372586cd Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:52 +0800 Subject: virtio_pci: support VIRTIO_F_RING_RESET This patch implements virtio pci support for QUEUE RESET. Performing reset on a queue is divided into these steps: 1. notify the device to reset the queue 2. recycle the buffer submitted 3. reset the vring (may re-alloc) 4. mmap vring to device, and enable the queue This patch implements virtio_reset_vq(), virtio_enable_resetq() in the pci scenario. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-33-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_pci_common.c | 12 ++++-- drivers/virtio/virtio_pci_modern.c | 88 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 97 insertions(+), 3 deletions(-) diff --git a/drivers/virtio/virtio_pci_common.c b/drivers/virtio/virtio_pci_common.c index ca51fcc9daab..ad258a9d3b9f 100644 --- a/drivers/virtio/virtio_pci_common.c +++ b/drivers/virtio/virtio_pci_common.c @@ -214,9 +214,15 @@ static void vp_del_vq(struct virtqueue *vq) struct virtio_pci_vq_info *info = vp_dev->vqs[vq->index]; unsigned long flags; - spin_lock_irqsave(&vp_dev->lock, flags); - list_del(&info->node); - spin_unlock_irqrestore(&vp_dev->lock, flags); + /* + * If it fails during re-enable reset vq. This way we won't rejoin + * info->node to the queue. Prevent unexpected irqs. + */ + if (!vq->reset) { + spin_lock_irqsave(&vp_dev->lock, flags); + list_del(&info->node); + spin_unlock_irqrestore(&vp_dev->lock, flags); + } vp_dev->del_vq(info); kfree(info); diff --git a/drivers/virtio/virtio_pci_modern.c b/drivers/virtio/virtio_pci_modern.c index 9041d9a41b7d..c3b9f2761849 100644 --- a/drivers/virtio/virtio_pci_modern.c +++ b/drivers/virtio/virtio_pci_modern.c @@ -34,6 +34,9 @@ static void vp_transport_features(struct virtio_device *vdev, u64 features) if ((features & BIT_ULL(VIRTIO_F_SR_IOV)) && pci_find_ext_capability(pci_dev, PCI_EXT_CAP_ID_SRIOV)) __virtio_set_bit(vdev, VIRTIO_F_SR_IOV); + + if (features & BIT_ULL(VIRTIO_F_RING_RESET)) + __virtio_set_bit(vdev, VIRTIO_F_RING_RESET); } /* virtio config->finalize_features() implementation */ @@ -199,6 +202,87 @@ static int vp_active_vq(struct virtqueue *vq, u16 msix_vec) return 0; } +static int vp_modern_disable_vq_and_reset(struct virtqueue *vq) +{ + struct virtio_pci_device *vp_dev = to_vp_device(vq->vdev); + struct virtio_pci_modern_device *mdev = &vp_dev->mdev; + struct virtio_pci_vq_info *info; + unsigned long flags; + + if (!virtio_has_feature(vq->vdev, VIRTIO_F_RING_RESET)) + return -ENOENT; + + vp_modern_set_queue_reset(mdev, vq->index); + + info = vp_dev->vqs[vq->index]; + + /* delete vq from irq handler */ + spin_lock_irqsave(&vp_dev->lock, flags); + list_del(&info->node); + spin_unlock_irqrestore(&vp_dev->lock, flags); + + INIT_LIST_HEAD(&info->node); + +#ifdef CONFIG_VIRTIO_HARDEN_NOTIFICATION + __virtqueue_break(vq); +#endif + + /* For the case where vq has an exclusive irq, call synchronize_irq() to + * wait for completion. + * + * note: We can't use disable_irq() since it conflicts with the affinity + * managed IRQ that is used by some drivers. + */ + if (vp_dev->per_vq_vectors && info->msix_vector != VIRTIO_MSI_NO_VECTOR) + synchronize_irq(pci_irq_vector(vp_dev->pci_dev, info->msix_vector)); + + vq->reset = true; + + return 0; +} + +static int vp_modern_enable_vq_after_reset(struct virtqueue *vq) +{ + struct virtio_pci_device *vp_dev = to_vp_device(vq->vdev); + struct virtio_pci_modern_device *mdev = &vp_dev->mdev; + struct virtio_pci_vq_info *info; + unsigned long flags, index; + int err; + + if (!vq->reset) + return -EBUSY; + + index = vq->index; + info = vp_dev->vqs[index]; + + if (vp_modern_get_queue_reset(mdev, index)) + return -EBUSY; + + if (vp_modern_get_queue_enable(mdev, index)) + return -EBUSY; + + err = vp_active_vq(vq, info->msix_vector); + if (err) + return err; + + if (vq->callback) { + spin_lock_irqsave(&vp_dev->lock, flags); + list_add(&info->node, &vp_dev->virtqueues); + spin_unlock_irqrestore(&vp_dev->lock, flags); + } else { + INIT_LIST_HEAD(&info->node); + } + +#ifdef CONFIG_VIRTIO_HARDEN_NOTIFICATION + __virtqueue_unbreak(vq); +#endif + + vp_modern_set_queue_enable(&vp_dev->mdev, index, true); + vq->reset = false; + + return 0; +} + static u16 vp_config_vector(struct virtio_pci_device *vp_dev, u16 vector) { return vp_modern_config_vector(&vp_dev->mdev, vector); @@ -413,6 +497,8 @@ static const struct virtio_config_ops virtio_pci_config_nodev_ops = { .set_vq_affinity = vp_set_vq_affinity, .get_vq_affinity = vp_get_vq_affinity, .get_shm_region = vp_get_shm_region, + .disable_vq_and_reset = vp_modern_disable_vq_and_reset, + .enable_vq_after_reset = vp_modern_enable_vq_after_reset, }; static const struct virtio_config_ops virtio_pci_config_ops = { @@ -431,6 +517,8 @@ static const struct virtio_config_ops virtio_pci_config_ops = { .set_vq_affinity = vp_set_vq_affinity, .get_vq_affinity = vp_get_vq_affinity, .get_shm_region = vp_get_shm_region, + .disable_vq_and_reset = vp_modern_disable_vq_and_reset, + .enable_vq_after_reset = vp_modern_enable_vq_after_reset, }; /* the PCI probing function */ -- cgit v1.2.3 From a10fba0377145fccefea4dc4dd5915b7ed87e546 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:53 +0800 Subject: virtio: find_vqs() add arg sizes find_vqs() adds a new parameter sizes to specify the size of each vq vring. NULL as sizes means that all queues in find_vqs() use the maximum size. A value in the array is 0, which means that the corresponding queue uses the maximum size. In the split scenario, the meaning of size is the largest size, because it may be limited by memory, the virtio core will try a smaller size. And the size is power of 2. Signed-off-by: Xuan Zhuo Acked-by: Hans de Goede Reviewed-by: Mathieu Poirier Acked-by: Jason Wang Message-Id: <20220801063902.129329-34-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- arch/um/drivers/virtio_uml.c | 2 +- drivers/platform/mellanox/mlxbf-tmfifo.c | 1 + drivers/remoteproc/remoteproc_virtio.c | 1 + drivers/s390/virtio/virtio_ccw.c | 1 + drivers/virtio/virtio_mmio.c | 1 + drivers/virtio/virtio_pci_common.c | 2 +- drivers/virtio/virtio_pci_common.h | 2 +- drivers/virtio/virtio_pci_modern.c | 7 +++++-- drivers/virtio/virtio_vdpa.c | 1 + include/linux/virtio_config.h | 14 +++++++++----- 10 files changed, 22 insertions(+), 10 deletions(-) diff --git a/arch/um/drivers/virtio_uml.c b/arch/um/drivers/virtio_uml.c index e719af8bdf56..79e38afd4b91 100644 --- a/arch/um/drivers/virtio_uml.c +++ b/arch/um/drivers/virtio_uml.c @@ -1011,7 +1011,7 @@ error_kzalloc: static int vu_find_vqs(struct virtio_device *vdev, unsigned nvqs, struct virtqueue *vqs[], vq_callback_t *callbacks[], - const char * const names[], const bool *ctx, + const char * const names[], u32 sizes[], const bool *ctx, struct irq_affinity *desc) { struct virtio_uml_device *vu_dev = to_virtio_uml_device(vdev); diff --git a/drivers/platform/mellanox/mlxbf-tmfifo.c b/drivers/platform/mellanox/mlxbf-tmfifo.c index 1ae3c56b66b0..8be13d416f48 100644 --- a/drivers/platform/mellanox/mlxbf-tmfifo.c +++ b/drivers/platform/mellanox/mlxbf-tmfifo.c @@ -928,6 +928,7 @@ static int mlxbf_tmfifo_virtio_find_vqs(struct virtio_device *vdev, struct virtqueue *vqs[], vq_callback_t *callbacks[], const char * const names[], + u32 sizes[], const bool *ctx, struct irq_affinity *desc) { diff --git a/drivers/remoteproc/remoteproc_virtio.c b/drivers/remoteproc/remoteproc_virtio.c index 0f7706e23eb9..81c4f5776109 100644 --- a/drivers/remoteproc/remoteproc_virtio.c +++ b/drivers/remoteproc/remoteproc_virtio.c @@ -158,6 +158,7 @@ static int rproc_virtio_find_vqs(struct virtio_device *vdev, unsigned int nvqs, struct virtqueue *vqs[], vq_callback_t *callbacks[], const char * const names[], + u32 sizes[], const bool * ctx, struct irq_affinity *desc) { diff --git a/drivers/s390/virtio/virtio_ccw.c b/drivers/s390/virtio/virtio_ccw.c index 6b86d0280d6b..72500cd2dbf5 100644 --- a/drivers/s390/virtio/virtio_ccw.c +++ b/drivers/s390/virtio/virtio_ccw.c @@ -635,6 +635,7 @@ static int virtio_ccw_find_vqs(struct virtio_device *vdev, unsigned nvqs, struct virtqueue *vqs[], vq_callback_t *callbacks[], const char * const names[], + u32 sizes[], const bool *ctx, struct irq_affinity *desc) { diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index 3ff746e3f24a..dfcecfd7aba1 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -474,6 +474,7 @@ static int vm_find_vqs(struct virtio_device *vdev, unsigned int nvqs, struct virtqueue *vqs[], vq_callback_t *callbacks[], const char * const names[], + u32 sizes[], const bool *ctx, struct irq_affinity *desc) { diff --git a/drivers/virtio/virtio_pci_common.c b/drivers/virtio/virtio_pci_common.c index ad258a9d3b9f..7ad734584823 100644 --- a/drivers/virtio/virtio_pci_common.c +++ b/drivers/virtio/virtio_pci_common.c @@ -396,7 +396,7 @@ out_del_vqs: /* the config->find_vqs() implementation */ int vp_find_vqs(struct virtio_device *vdev, unsigned int nvqs, struct virtqueue *vqs[], vq_callback_t *callbacks[], - const char * const names[], const bool *ctx, + const char * const names[], u32 sizes[], const bool *ctx, struct irq_affinity *desc) { int err; diff --git a/drivers/virtio/virtio_pci_common.h b/drivers/virtio/virtio_pci_common.h index 23112d84218f..a5ff838b85a5 100644 --- a/drivers/virtio/virtio_pci_common.h +++ b/drivers/virtio/virtio_pci_common.h @@ -110,7 +110,7 @@ void vp_del_vqs(struct virtio_device *vdev); /* the config->find_vqs() implementation */ int vp_find_vqs(struct virtio_device *vdev, unsigned int nvqs, struct virtqueue *vqs[], vq_callback_t *callbacks[], - const char * const names[], const bool *ctx, + const char * const names[], u32 sizes[], const bool *ctx, struct irq_affinity *desc); const char *vp_bus_name(struct virtio_device *vdev); diff --git a/drivers/virtio/virtio_pci_modern.c b/drivers/virtio/virtio_pci_modern.c index c3b9f2761849..be51ec849252 100644 --- a/drivers/virtio/virtio_pci_modern.c +++ b/drivers/virtio/virtio_pci_modern.c @@ -347,12 +347,15 @@ err: static int vp_modern_find_vqs(struct virtio_device *vdev, unsigned int nvqs, struct virtqueue *vqs[], vq_callback_t *callbacks[], - const char * const names[], const bool *ctx, + const char * const names[], + u32 sizes[], + const bool *ctx, struct irq_affinity *desc) { struct virtio_pci_device *vp_dev = to_vp_device(vdev); struct virtqueue *vq; - int rc = vp_find_vqs(vdev, nvqs, vqs, callbacks, names, ctx, desc); + int rc = vp_find_vqs(vdev, nvqs, vqs, callbacks, names, sizes, ctx, + desc); if (rc) return rc; diff --git a/drivers/virtio/virtio_vdpa.c b/drivers/virtio/virtio_vdpa.c index 9670cc79371d..832d2c5b1b19 100644 --- a/drivers/virtio/virtio_vdpa.c +++ b/drivers/virtio/virtio_vdpa.c @@ -269,6 +269,7 @@ static int virtio_vdpa_find_vqs(struct virtio_device *vdev, unsigned int nvqs, struct virtqueue *vqs[], vq_callback_t *callbacks[], const char * const names[], + u32 sizes[], const bool *ctx, struct irq_affinity *desc) { diff --git a/include/linux/virtio_config.h b/include/linux/virtio_config.h index 36ec7be1f480..888f7e96f0c7 100644 --- a/include/linux/virtio_config.h +++ b/include/linux/virtio_config.h @@ -55,6 +55,7 @@ struct virtio_shm_region { * include a NULL entry for vqs that do not need a callback * names: array of virtqueue names (mainly for debugging) * include a NULL entry for vqs unused by driver + * sizes: array of virtqueue sizes * Returns 0 on success or error status * @del_vqs: free virtqueues found by find_vqs(). * @synchronize_cbs: synchronize with the virtqueue callbacks (optional) @@ -103,7 +104,9 @@ struct virtio_config_ops { void (*reset)(struct virtio_device *vdev); int (*find_vqs)(struct virtio_device *, unsigned nvqs, struct virtqueue *vqs[], vq_callback_t *callbacks[], - const char * const names[], const bool *ctx, + const char * const names[], + u32 sizes[], + const bool *ctx, struct irq_affinity *desc); void (*del_vqs)(struct virtio_device *); void (*synchronize_cbs)(struct virtio_device *); @@ -212,7 +215,7 @@ struct virtqueue *virtio_find_single_vq(struct virtio_device *vdev, const char *names[] = { n }; struct virtqueue *vq; int err = vdev->config->find_vqs(vdev, 1, &vq, callbacks, names, NULL, - NULL); + NULL, NULL); if (err < 0) return ERR_PTR(err); return vq; @@ -224,7 +227,8 @@ int virtio_find_vqs(struct virtio_device *vdev, unsigned nvqs, const char * const names[], struct irq_affinity *desc) { - return vdev->config->find_vqs(vdev, nvqs, vqs, callbacks, names, NULL, desc); + return vdev->config->find_vqs(vdev, nvqs, vqs, callbacks, names, NULL, + NULL, desc); } static inline @@ -233,8 +237,8 @@ int virtio_find_vqs_ctx(struct virtio_device *vdev, unsigned nvqs, const char * const names[], const bool *ctx, struct irq_affinity *desc) { - return vdev->config->find_vqs(vdev, nvqs, vqs, callbacks, names, ctx, - desc); + return vdev->config->find_vqs(vdev, nvqs, vqs, callbacks, names, NULL, + ctx, desc); } /** -- cgit v1.2.3 From cdb44806fca2d0ad29ca644cbf1505433902ee0c Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:54 +0800 Subject: virtio_pci: support the arg sizes of find_vqs() Virtio PCI supports new parameter sizes of find_vqs(). Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-35-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_pci_common.c | 18 ++++++++++-------- drivers/virtio/virtio_pci_common.h | 1 + drivers/virtio/virtio_pci_legacy.c | 6 +++++- drivers/virtio/virtio_pci_modern.c | 10 +++++++--- 4 files changed, 23 insertions(+), 12 deletions(-) diff --git a/drivers/virtio/virtio_pci_common.c b/drivers/virtio/virtio_pci_common.c index 7ad734584823..00ad476a815d 100644 --- a/drivers/virtio/virtio_pci_common.c +++ b/drivers/virtio/virtio_pci_common.c @@ -174,6 +174,7 @@ error: static struct virtqueue *vp_setup_vq(struct virtio_device *vdev, unsigned int index, void (*callback)(struct virtqueue *vq), const char *name, + u32 size, bool ctx, u16 msix_vec) { @@ -186,7 +187,7 @@ static struct virtqueue *vp_setup_vq(struct virtio_device *vdev, unsigned int in if (!info) return ERR_PTR(-ENOMEM); - vq = vp_dev->setup_vq(vp_dev, info, index, callback, name, ctx, + vq = vp_dev->setup_vq(vp_dev, info, index, callback, name, size, ctx, msix_vec); if (IS_ERR(vq)) goto out_info; @@ -283,7 +284,7 @@ void vp_del_vqs(struct virtio_device *vdev) static int vp_find_vqs_msix(struct virtio_device *vdev, unsigned int nvqs, struct virtqueue *vqs[], vq_callback_t *callbacks[], - const char * const names[], bool per_vq_vectors, + const char * const names[], u32 sizes[], bool per_vq_vectors, const bool *ctx, struct irq_affinity *desc) { @@ -326,8 +327,8 @@ static int vp_find_vqs_msix(struct virtio_device *vdev, unsigned int nvqs, else msix_vec = VP_MSIX_VQ_VECTOR; vqs[i] = vp_setup_vq(vdev, queue_idx++, callbacks[i], names[i], - ctx ? ctx[i] : false, - msix_vec); + sizes ? sizes[i] : 0, + ctx ? ctx[i] : false, msix_vec); if (IS_ERR(vqs[i])) { err = PTR_ERR(vqs[i]); goto error_find; @@ -357,7 +358,7 @@ error_find: static int vp_find_vqs_intx(struct virtio_device *vdev, unsigned int nvqs, struct virtqueue *vqs[], vq_callback_t *callbacks[], - const char * const names[], const bool *ctx) + const char * const names[], u32 sizes[], const bool *ctx) { struct virtio_pci_device *vp_dev = to_vp_device(vdev); int i, err, queue_idx = 0; @@ -379,6 +380,7 @@ static int vp_find_vqs_intx(struct virtio_device *vdev, unsigned int nvqs, continue; } vqs[i] = vp_setup_vq(vdev, queue_idx++, callbacks[i], names[i], + sizes ? sizes[i] : 0, ctx ? ctx[i] : false, VIRTIO_MSI_NO_VECTOR); if (IS_ERR(vqs[i])) { @@ -402,15 +404,15 @@ int vp_find_vqs(struct virtio_device *vdev, unsigned int nvqs, int err; /* Try MSI-X with one vector per queue. */ - err = vp_find_vqs_msix(vdev, nvqs, vqs, callbacks, names, true, ctx, desc); + err = vp_find_vqs_msix(vdev, nvqs, vqs, callbacks, names, sizes, true, ctx, desc); if (!err) return 0; /* Fallback: MSI-X with one vector for config, one shared for queues. */ - err = vp_find_vqs_msix(vdev, nvqs, vqs, callbacks, names, false, ctx, desc); + err = vp_find_vqs_msix(vdev, nvqs, vqs, callbacks, names, sizes, false, ctx, desc); if (!err) return 0; /* Finally fall back to regular interrupts. */ - return vp_find_vqs_intx(vdev, nvqs, vqs, callbacks, names, ctx); + return vp_find_vqs_intx(vdev, nvqs, vqs, callbacks, names, sizes, ctx); } const char *vp_bus_name(struct virtio_device *vdev) diff --git a/drivers/virtio/virtio_pci_common.h b/drivers/virtio/virtio_pci_common.h index a5ff838b85a5..c0448378b698 100644 --- a/drivers/virtio/virtio_pci_common.h +++ b/drivers/virtio/virtio_pci_common.h @@ -80,6 +80,7 @@ struct virtio_pci_device { unsigned int idx, void (*callback)(struct virtqueue *vq), const char *name, + u32 size, bool ctx, u16 msix_vec); void (*del_vq)(struct virtio_pci_vq_info *info); diff --git a/drivers/virtio/virtio_pci_legacy.c b/drivers/virtio/virtio_pci_legacy.c index 2257f1b3d8ae..d75e5c4e637f 100644 --- a/drivers/virtio/virtio_pci_legacy.c +++ b/drivers/virtio/virtio_pci_legacy.c @@ -112,6 +112,7 @@ static struct virtqueue *setup_vq(struct virtio_pci_device *vp_dev, unsigned int index, void (*callback)(struct virtqueue *vq), const char *name, + u32 size, bool ctx, u16 msix_vec) { @@ -125,10 +126,13 @@ static struct virtqueue *setup_vq(struct virtio_pci_device *vp_dev, if (!num || vp_legacy_get_queue_enable(&vp_dev->ldev, index)) return ERR_PTR(-ENOENT); + if (!size || size > num) + size = num; + info->msix_vector = msix_vec; /* create the vring */ - vq = vring_create_virtqueue(index, num, + vq = vring_create_virtqueue(index, size, VIRTIO_PCI_VRING_ALIGN, &vp_dev->vdev, true, false, ctx, vp_notify, callback, name); diff --git a/drivers/virtio/virtio_pci_modern.c b/drivers/virtio/virtio_pci_modern.c index be51ec849252..f7965c5dd36b 100644 --- a/drivers/virtio/virtio_pci_modern.c +++ b/drivers/virtio/virtio_pci_modern.c @@ -293,6 +293,7 @@ static struct virtqueue *setup_vq(struct virtio_pci_device *vp_dev, unsigned int index, void (*callback)(struct virtqueue *vq), const char *name, + u32 size, bool ctx, u16 msix_vec) { @@ -310,15 +311,18 @@ static struct virtqueue *setup_vq(struct virtio_pci_device *vp_dev, if (!num || vp_modern_get_queue_enable(mdev, index)) return ERR_PTR(-ENOENT); - if (num & (num - 1)) { - dev_warn(&vp_dev->pci_dev->dev, "bad queue size %u", num); + if (!size || size > num) + size = num; + + if (size & (size - 1)) { + dev_warn(&vp_dev->pci_dev->dev, "bad queue size %u", size); return ERR_PTR(-EINVAL); } info->msix_vector = msix_vec; /* create the vring */ - vq = vring_create_virtqueue(index, num, + vq = vring_create_virtqueue(index, size, SMP_CACHE_BYTES, &vp_dev->vdev, true, true, ctx, vp_notify, callback, name); -- cgit v1.2.3 From fbed86abba6e0472d98079790e58060e4332608a Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:55 +0800 Subject: virtio_mmio: support the arg sizes of find_vqs() Virtio MMIO support the new parameter sizes of find_vqs(). Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-36-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_mmio.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index dfcecfd7aba1..c492a57531c6 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -360,7 +360,7 @@ static void vm_synchronize_cbs(struct virtio_device *vdev) static struct virtqueue *vm_setup_vq(struct virtio_device *vdev, unsigned int index, void (*callback)(struct virtqueue *vq), - const char *name, bool ctx) + const char *name, u32 size, bool ctx) { struct virtio_mmio_device *vm_dev = to_virtio_mmio_device(vdev); struct virtio_mmio_vq_info *info; @@ -395,8 +395,11 @@ static struct virtqueue *vm_setup_vq(struct virtio_device *vdev, unsigned int in goto error_new_virtqueue; } + if (!size || size > num) + size = num; + /* Create the vring */ - vq = vring_create_virtqueue(index, num, VIRTIO_MMIO_VRING_ALIGN, vdev, + vq = vring_create_virtqueue(index, size, VIRTIO_MMIO_VRING_ALIGN, vdev, true, true, ctx, vm_notify, callback, name); if (!vq) { err = -ENOMEM; @@ -500,6 +503,7 @@ static int vm_find_vqs(struct virtio_device *vdev, unsigned int nvqs, } vqs[i] = vm_setup_vq(vdev, queue_idx++, callbacks[i], names[i], + sizes ? sizes[i] : 0, ctx ? ctx[i] : false); if (IS_ERR(vqs[i])) { vm_del_vqs(vdev); -- cgit v1.2.3 From fe3dc04e31aa51f91dc7f741a5f76cc4817eb5b4 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:56 +0800 Subject: virtio: add helper virtio_find_vqs_ctx_size() Introduce helper virtio_find_vqs_ctx_size() to call find_vqs and specify the maximum size of each vq ring. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-37-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- include/linux/virtio_config.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/linux/virtio_config.h b/include/linux/virtio_config.h index 888f7e96f0c7..6adff09f7170 100644 --- a/include/linux/virtio_config.h +++ b/include/linux/virtio_config.h @@ -241,6 +241,18 @@ int virtio_find_vqs_ctx(struct virtio_device *vdev, unsigned nvqs, ctx, desc); } +static inline +int virtio_find_vqs_ctx_size(struct virtio_device *vdev, u32 nvqs, + struct virtqueue *vqs[], + vq_callback_t *callbacks[], + const char * const names[], + u32 sizes[], + const bool *ctx, struct irq_affinity *desc) +{ + return vdev->config->find_vqs(vdev, nvqs, vqs, callbacks, names, sizes, + ctx, desc); +} + /** * virtio_synchronize_cbs - synchronize with virtqueue callbacks * @vdev: the device -- cgit v1.2.3 From 762faee5a2678559d3dc09d95f8f2c54cd0466a7 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:57 +0800 Subject: virtio_net: set the default max ring size by find_vqs() Use virtio_find_vqs_ctx_size() to specify the maximum ring size of tx, rx at the same time. | rx/tx ring size ------------------------------------------- speed == UNKNOWN or < 10G| 1024 speed < 40G | 4096 speed >= 40G | 8192 Call virtnet_update_settings() once before calling init_vqs() to update speed. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-38-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/net/virtio_net.c | 42 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 38 insertions(+), 4 deletions(-) diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index ec8e1b3108c3..00948b0fb589 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c @@ -3225,6 +3225,29 @@ static unsigned int mergeable_min_buf_len(struct virtnet_info *vi, struct virtqu (unsigned int)GOOD_PACKET_LEN); } +static void virtnet_config_sizes(struct virtnet_info *vi, u32 *sizes) +{ + u32 i, rx_size, tx_size; + + if (vi->speed == SPEED_UNKNOWN || vi->speed < SPEED_10000) { + rx_size = 1024; + tx_size = 1024; + + } else if (vi->speed < SPEED_40000) { + rx_size = 1024 * 4; + tx_size = 1024 * 4; + + } else { + rx_size = 1024 * 8; + tx_size = 1024 * 8; + } + + for (i = 0; i < vi->max_queue_pairs; i++) { + sizes[rxq2vq(i)] = rx_size; + sizes[txq2vq(i)] = tx_size; + } +} + static int virtnet_find_vqs(struct virtnet_info *vi) { vq_callback_t **callbacks; @@ -3232,6 +3255,7 @@ static int virtnet_find_vqs(struct virtnet_info *vi) int ret = -ENOMEM; int i, total_vqs; const char **names; + u32 *sizes; bool *ctx; /* We expect 1 RX virtqueue followed by 1 TX virtqueue, followed by @@ -3259,10 +3283,15 @@ static int virtnet_find_vqs(struct virtnet_info *vi) ctx = NULL; } + sizes = kmalloc_array(total_vqs, sizeof(*sizes), GFP_KERNEL); + if (!sizes) + goto err_sizes; + /* Parameters for control virtqueue, if any */ if (vi->has_cvq) { callbacks[total_vqs - 1] = NULL; names[total_vqs - 1] = "control"; + sizes[total_vqs - 1] = 64; } /* Allocate/initialize parameters for send/receive virtqueues */ @@ -3277,8 +3306,10 @@ static int virtnet_find_vqs(struct virtnet_info *vi) ctx[rxq2vq(i)] = true; } - ret = virtio_find_vqs_ctx(vi->vdev, total_vqs, vqs, callbacks, - names, ctx, NULL); + virtnet_config_sizes(vi, sizes); + + ret = virtio_find_vqs_ctx_size(vi->vdev, total_vqs, vqs, callbacks, + names, sizes, ctx, NULL); if (ret) goto err_find; @@ -3298,6 +3329,8 @@ static int virtnet_find_vqs(struct virtnet_info *vi) err_find: + kfree(sizes); +err_sizes: kfree(ctx); err_ctx: kfree(names); @@ -3648,6 +3681,9 @@ static int virtnet_probe(struct virtio_device *vdev) vi->curr_queue_pairs = num_online_cpus(); vi->max_queue_pairs = max_queue_pairs; + virtnet_init_settings(dev); + virtnet_update_settings(vi); + /* Allocate/initialize the rx/tx queues, and invoke find_vqs */ err = init_vqs(vi); if (err) @@ -3660,8 +3696,6 @@ static int virtnet_probe(struct virtio_device *vdev) netif_set_real_num_tx_queues(dev, vi->curr_queue_pairs); netif_set_real_num_rx_queues(dev, vi->curr_queue_pairs); - virtnet_init_settings(dev); - if (virtio_has_feature(vdev, VIRTIO_NET_F_STANDBY)) { vi->failover = net_failover_create(vi->dev); if (IS_ERR(vi->failover)) { -- cgit v1.2.3 From 8597b5ddcbba840ab852e1083f1a8dd1c6d41d1b Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:58 +0800 Subject: virtio_net: get ringparam by virtqueue_get_vring_max_size() Use virtqueue_get_vring_max_size() in virtnet_get_ringparam() to set tx,rx_max_pending. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-39-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/net/virtio_net.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index 00948b0fb589..204bfe49d6b4 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c @@ -2282,10 +2282,10 @@ static void virtnet_get_ringparam(struct net_device *dev, { struct virtnet_info *vi = netdev_priv(dev); - ring->rx_max_pending = virtqueue_get_vring_size(vi->rq[0].vq); - ring->tx_max_pending = virtqueue_get_vring_size(vi->sq[0].vq); - ring->rx_pending = ring->rx_max_pending; - ring->tx_pending = ring->tx_max_pending; + ring->rx_max_pending = vi->rq[0].vq->num_max; + ring->tx_max_pending = vi->sq[0].vq->num_max; + ring->rx_pending = virtqueue_get_vring_size(vi->rq[0].vq); + ring->tx_pending = virtqueue_get_vring_size(vi->sq[0].vq); } static bool virtnet_commit_rss_command(struct virtnet_info *vi) -- cgit v1.2.3 From 6e345f8c7cd029ad3aaece15ad4425ac26e4eb63 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:59 +0800 Subject: virtio_net: split free_unused_bufs() This patch separates two functions for freeing sq buf and rq buf from free_unused_bufs(). When supporting the enable/disable tx/rq queue in the future, it is necessary to support separate recovery of a sq buf or a rq buf. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-40-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/net/virtio_net.c | 41 +++++++++++++++++++++++++---------------- 1 file changed, 25 insertions(+), 16 deletions(-) diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index 204bfe49d6b4..8cad913926e5 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c @@ -3168,6 +3168,27 @@ static void free_receive_page_frags(struct virtnet_info *vi) put_page(vi->rq[i].alloc_frag.page); } +static void virtnet_sq_free_unused_buf(struct virtqueue *vq, void *buf) +{ + if (!is_xdp_frame(buf)) + dev_kfree_skb(buf); + else + xdp_return_frame(ptr_to_xdp(buf)); +} + +static void virtnet_rq_free_unused_buf(struct virtqueue *vq, void *buf) +{ + struct virtnet_info *vi = vq->vdev->priv; + int i = vq2rxq(vq); + + if (vi->mergeable_rx_bufs) + put_page(virt_to_head_page(buf)); + else if (vi->big_packets) + give_pages(&vi->rq[i], buf); + else + put_page(virt_to_head_page(buf)); +} + static void free_unused_bufs(struct virtnet_info *vi) { void *buf; @@ -3175,26 +3196,14 @@ static void free_unused_bufs(struct virtnet_info *vi) for (i = 0; i < vi->max_queue_pairs; i++) { struct virtqueue *vq = vi->sq[i].vq; - while ((buf = virtqueue_detach_unused_buf(vq)) != NULL) { - if (!is_xdp_frame(buf)) - dev_kfree_skb(buf); - else - xdp_return_frame(ptr_to_xdp(buf)); - } + while ((buf = virtqueue_detach_unused_buf(vq)) != NULL) + virtnet_sq_free_unused_buf(vq, buf); } for (i = 0; i < vi->max_queue_pairs; i++) { struct virtqueue *vq = vi->rq[i].vq; - - while ((buf = virtqueue_detach_unused_buf(vq)) != NULL) { - if (vi->mergeable_rx_bufs) { - put_page(virt_to_head_page(buf)); - } else if (vi->big_packets) { - give_pages(&vi->rq[i], buf); - } else { - put_page(virt_to_head_page(buf)); - } - } + while ((buf = virtqueue_detach_unused_buf(vq)) != NULL) + virtnet_rq_free_unused_buf(vq, buf); } } -- cgit v1.2.3 From 6a4763e268030362340bc3286560d44be15a7421 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:39:00 +0800 Subject: virtio_net: support rx queue resize This patch implements the resize function of the rx queues. Based on this function, it is possible to modify the ring num of the queue. Includes fixup: virtio_net: fix for stuck when change rx ring size with dev down When dev is set to DOWN state, napi has been disabled, if we modify the ring size at this time, we should not call napi_disable() again, which will cause stuck. And all operations are under the protection of rtnl_lock, so there is no need to consider concurrency issues. Message-Id: <20220801063902.129329-41-xuanzhuo@linux.alibaba.com> Acked-by: Jason Wang Message-Id: <20220811080258.79398-2-xuanzhuo@linux.alibaba.com> Reported-by: Kangjie Xu Signed-off-by: Xuan Zhuo Signed-off-by: Michael S. Tsirkin --- drivers/net/virtio_net.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index 8cad913926e5..4cf278dd9004 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c @@ -284,6 +284,8 @@ struct padded_vnet_hdr { char padding[12]; }; +static void virtnet_rq_free_unused_buf(struct virtqueue *vq, void *buf); + static bool is_xdp_frame(void *ptr) { return (unsigned long)ptr & VIRTIO_XDP_FLAG; @@ -1872,6 +1874,29 @@ static netdev_tx_t start_xmit(struct sk_buff *skb, struct net_device *dev) return NETDEV_TX_OK; } +static int virtnet_rx_resize(struct virtnet_info *vi, + struct receive_queue *rq, u32 ring_num) +{ + bool running = netif_running(vi->dev); + int err, qindex; + + qindex = rq - vi->rq; + + if (running) + napi_disable(&rq->napi); + + err = virtqueue_resize(rq->vq, ring_num, virtnet_rq_free_unused_buf); + if (err) + netdev_err(vi->dev, "resize rx fail: rx queue index: %d err: %d\n", qindex, err); + + if (!try_fill_recv(vi, rq, GFP_KERNEL)) + schedule_delayed_work(&vi->refill, 0); + + if (running) + virtnet_napi_enable(rq->vq, &rq->napi); + return err; +} + /* * Send command via the control virtqueue and check status. Commands * supported by the hypervisor, as indicated by feature bits, should -- cgit v1.2.3 From ebcce492636506443e4361db6587e6acd1a624f9 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:39:01 +0800 Subject: virtio_net: support tx queue resize This patch implements the resize function of the tx queues. Based on this function, it is possible to modify the ring num of the queue. Inludes fixup: virtio_net: fix for stuck when change tx ring size with dev down When dev is set to DOWN state, napi has been disabled, if we modify the ring size at this time, we should not call napi_disable() again, which will cause stuck. And all operations are under the protection of rtnl_lock, so there is no need to consider concurrency issues. Message-Id: <20220801063902.129329-42-xuanzhuo@linux.alibaba.com> Acked-by: Jason Wang Message-Id: <20220811080258.79398-3-xuanzhuo@linux.alibaba.com> Reported-by: Kangjie Xu Signed-off-by: Xuan Zhuo Signed-off-by: Michael S. Tsirkin --- drivers/net/virtio_net.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index 4cf278dd9004..6aa0871b438c 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c @@ -135,6 +135,9 @@ struct send_queue { struct virtnet_sq_stats stats; struct napi_struct napi; + + /* Record whether sq is in reset state. */ + bool reset; }; /* Internal representation of a receive virtqueue */ @@ -285,6 +288,7 @@ struct padded_vnet_hdr { }; static void virtnet_rq_free_unused_buf(struct virtqueue *vq, void *buf); +static void virtnet_sq_free_unused_buf(struct virtqueue *vq, void *buf); static bool is_xdp_frame(void *ptr) { @@ -1627,6 +1631,11 @@ static void virtnet_poll_cleantx(struct receive_queue *rq) return; if (__netif_tx_trylock(txq)) { + if (sq->reset) { + __netif_tx_unlock(txq); + return; + } + do { virtqueue_disable_cb(sq->vq); free_old_xmit_skbs(sq, true); @@ -1897,6 +1906,47 @@ static int virtnet_rx_resize(struct virtnet_info *vi, return err; } +static int virtnet_tx_resize(struct virtnet_info *vi, + struct send_queue *sq, u32 ring_num) +{ + bool running = netif_running(vi->dev); + struct netdev_queue *txq; + int err, qindex; + + qindex = sq - vi->sq; + + if (running) + virtnet_napi_tx_disable(&sq->napi); + + txq = netdev_get_tx_queue(vi->dev, qindex); + + /* 1. wait all ximt complete + * 2. fix the race of netif_stop_subqueue() vs netif_start_subqueue() + */ + __netif_tx_lock_bh(txq); + + /* Prevent rx poll from accessing sq. */ + sq->reset = true; + + /* Prevent the upper layer from trying to send packets. */ + netif_stop_subqueue(vi->dev, qindex); + + __netif_tx_unlock_bh(txq); + + err = virtqueue_resize(sq->vq, ring_num, virtnet_sq_free_unused_buf); + if (err) + netdev_err(vi->dev, "resize tx fail: tx queue index: %d err: %d\n", qindex, err); + + __netif_tx_lock_bh(txq); + sq->reset = false; + netif_tx_wake_queue(txq); + __netif_tx_unlock_bh(txq); + + if (running) + virtnet_napi_tx_enable(vi, sq->vq, &sq->napi); + return err; +} + /* * Send command via the control virtqueue and check status. Commands * supported by the hypervisor, as indicated by feature bits, should -- cgit v1.2.3 From a335b33f4f354c5b77a79d505708f6d2f486ceab Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:39:02 +0800 Subject: virtio_net: support set_ringparam Support set_ringparam based on virtio queue reset. Users can use ethtool -G eth0 to modify the ring size of virtio-net. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-43-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin --- drivers/net/virtio_net.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index 6aa0871b438c..16783ed782c5 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c @@ -2363,6 +2363,53 @@ static void virtnet_get_ringparam(struct net_device *dev, ring->tx_pending = virtqueue_get_vring_size(vi->sq[0].vq); } +static int virtnet_set_ringparam(struct net_device *dev, + struct ethtool_ringparam *ring, + struct kernel_ethtool_ringparam *kernel_ring, + struct netlink_ext_ack *extack) +{ + struct virtnet_info *vi = netdev_priv(dev); + u32 rx_pending, tx_pending; + struct receive_queue *rq; + struct send_queue *sq; + int i, err; + + if (ring->rx_mini_pending || ring->rx_jumbo_pending) + return -EINVAL; + + rx_pending = virtqueue_get_vring_size(vi->rq[0].vq); + tx_pending = virtqueue_get_vring_size(vi->sq[0].vq); + + if (ring->rx_pending == rx_pending && + ring->tx_pending == tx_pending) + return 0; + + if (ring->rx_pending > vi->rq[0].vq->num_max) + return -EINVAL; + + if (ring->tx_pending > vi->sq[0].vq->num_max) + return -EINVAL; + + for (i = 0; i < vi->max_queue_pairs; i++) { + rq = vi->rq + i; + sq = vi->sq + i; + + if (ring->tx_pending != tx_pending) { + err = virtnet_tx_resize(vi, sq, ring->tx_pending); + if (err) + return err; + } + + if (ring->rx_pending != rx_pending) { + err = virtnet_rx_resize(vi, rq, ring->rx_pending); + if (err) + return err; + } + } + + return 0; +} + static bool virtnet_commit_rss_command(struct virtnet_info *vi) { struct net_device *dev = vi->dev; @@ -2850,6 +2897,7 @@ static const struct ethtool_ops virtnet_ethtool_ops = { .get_drvinfo = virtnet_get_drvinfo, .get_link = ethtool_op_get_link, .get_ringparam = virtnet_get_ringparam, + .set_ringparam = virtnet_set_ringparam, .get_strings = virtnet_get_strings, .get_sset_count = virtnet_get_sset_count, .get_ethtool_stats = virtnet_get_ethtool_stats, -- cgit v1.2.3 From 42a84c09eff355d895723866b1a5ff48f093112a Mon Sep 17 00:00:00 2001 From: Stefano Garzarella Date: Thu, 30 Jun 2022 17:32:19 +0200 Subject: vdpa_sim_blk: use dev_dbg() to print errors Use dev_dbg() instead of dev_err()/dev_warn() to avoid flooding the host with prints, when the guest driver is misbehaving. In this way, prints can be dynamically enabled when the vDPA block simulator is used to validate a driver. Suggested-by: Jason Wang Acked-by: Jason Wang Signed-off-by: Stefano Garzarella Message-Id: <20220630153221.83371-2-sgarzare@redhat.com> Signed-off-by: Michael S. Tsirkin --- drivers/vdpa/vdpa_sim/vdpa_sim_blk.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c b/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c index 42d401d43911..a83a5c76f620 100644 --- a/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c +++ b/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c @@ -76,13 +76,13 @@ static bool vdpasim_blk_handle_req(struct vdpasim *vdpasim, return false; if (vq->out_iov.used < 1 || vq->in_iov.used < 1) { - dev_err(&vdpasim->vdpa.dev, "missing headers - out_iov: %u in_iov %u\n", + dev_dbg(&vdpasim->vdpa.dev, "missing headers - out_iov: %u in_iov %u\n", vq->out_iov.used, vq->in_iov.used); return false; } if (vq->in_iov.iov[vq->in_iov.used - 1].iov_len < 1) { - dev_err(&vdpasim->vdpa.dev, "request in header too short\n"); + dev_dbg(&vdpasim->vdpa.dev, "request in header too short\n"); return false; } @@ -96,7 +96,7 @@ static bool vdpasim_blk_handle_req(struct vdpasim *vdpasim, bytes = vringh_iov_pull_iotlb(&vq->vring, &vq->out_iov, &hdr, sizeof(hdr)); if (bytes != sizeof(hdr)) { - dev_err(&vdpasim->vdpa.dev, "request out header too short\n"); + dev_dbg(&vdpasim->vdpa.dev, "request out header too short\n"); return false; } @@ -110,7 +110,7 @@ static bool vdpasim_blk_handle_req(struct vdpasim *vdpasim, switch (type) { case VIRTIO_BLK_T_IN: if (!vdpasim_blk_check_range(sector, to_push)) { - dev_err(&vdpasim->vdpa.dev, + dev_dbg(&vdpasim->vdpa.dev, "reading over the capacity - offset: 0x%llx len: 0x%zx\n", offset, to_push); status = VIRTIO_BLK_S_IOERR; @@ -121,7 +121,7 @@ static bool vdpasim_blk_handle_req(struct vdpasim *vdpasim, vdpasim->buffer + offset, to_push); if (bytes < 0) { - dev_err(&vdpasim->vdpa.dev, + dev_dbg(&vdpasim->vdpa.dev, "vringh_iov_push_iotlb() error: %zd offset: 0x%llx len: 0x%zx\n", bytes, offset, to_push); status = VIRTIO_BLK_S_IOERR; @@ -133,7 +133,7 @@ static bool vdpasim_blk_handle_req(struct vdpasim *vdpasim, case VIRTIO_BLK_T_OUT: if (!vdpasim_blk_check_range(sector, to_pull)) { - dev_err(&vdpasim->vdpa.dev, + dev_dbg(&vdpasim->vdpa.dev, "writing over the capacity - offset: 0x%llx len: 0x%zx\n", offset, to_pull); status = VIRTIO_BLK_S_IOERR; @@ -144,7 +144,7 @@ static bool vdpasim_blk_handle_req(struct vdpasim *vdpasim, vdpasim->buffer + offset, to_pull); if (bytes < 0) { - dev_err(&vdpasim->vdpa.dev, + dev_dbg(&vdpasim->vdpa.dev, "vringh_iov_pull_iotlb() error: %zd offset: 0x%llx len: 0x%zx\n", bytes, offset, to_pull); status = VIRTIO_BLK_S_IOERR; @@ -157,7 +157,7 @@ static bool vdpasim_blk_handle_req(struct vdpasim *vdpasim, vdpasim_blk_id, VIRTIO_BLK_ID_BYTES); if (bytes < 0) { - dev_err(&vdpasim->vdpa.dev, + dev_dbg(&vdpasim->vdpa.dev, "vringh_iov_push_iotlb() error: %zd\n", bytes); status = VIRTIO_BLK_S_IOERR; break; @@ -167,8 +167,8 @@ static bool vdpasim_blk_handle_req(struct vdpasim *vdpasim, break; default: - dev_warn(&vdpasim->vdpa.dev, - "Unsupported request type %d\n", type); + dev_dbg(&vdpasim->vdpa.dev, + "Unsupported request type %d\n", type); status = VIRTIO_BLK_S_IOERR; break; } -- cgit v1.2.3 From 9c4df0900f376f28e8e5cca640a10a0085f16b66 Mon Sep 17 00:00:00 2001 From: Stefano Garzarella Date: Thu, 30 Jun 2022 17:32:20 +0200 Subject: vdpa_sim_blk: limit the number of request handled per batch MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Limit the number of requests (4 per queue as for vdpa_sim_net) handled in a batch to prevent the worker from using the CPU for too long. Suggested-by: Eugenio Pérez Signed-off-by: Stefano Garzarella Message-Id: <20220630153221.83371-3-sgarzare@redhat.com> Signed-off-by: Michael S. Tsirkin Acked-by: Jason Wang --- drivers/vdpa/vdpa_sim/vdpa_sim_blk.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c b/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c index a83a5c76f620..b2d75efec63a 100644 --- a/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c +++ b/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c @@ -197,6 +197,7 @@ static bool vdpasim_blk_handle_req(struct vdpasim *vdpasim, static void vdpasim_blk_work(struct work_struct *work) { struct vdpasim *vdpasim = container_of(work, struct vdpasim, work); + bool reschedule = false; int i; spin_lock(&vdpasim->lock); @@ -206,6 +207,7 @@ static void vdpasim_blk_work(struct work_struct *work) for (i = 0; i < VDPASIM_BLK_VQ_NUM; i++) { struct vdpasim_virtqueue *vq = &vdpasim->vqs[i]; + int reqs = 0; if (!vq->ready) continue; @@ -218,10 +220,18 @@ static void vdpasim_blk_work(struct work_struct *work) if (vringh_need_notify_iotlb(&vq->vring) > 0) vringh_notify(&vq->vring); local_bh_enable(); + + if (++reqs > 4) { + reschedule = true; + break; + } } } out: spin_unlock(&vdpasim->lock); + + if (reschedule) + schedule_work(&vdpasim->work); } static void vdpasim_blk_get_config(struct vdpasim *vdpasim, void *config) -- cgit v1.2.3 From 8472019eec2ccff60144d8585367b2856a59416e Mon Sep 17 00:00:00 2001 From: Stefano Garzarella Date: Thu, 30 Jun 2022 17:32:21 +0200 Subject: vdpa_sim_blk: call vringh_complete_iotlb() also in the error path Call vringh_complete_iotlb() even when we encounter a serious error that prevents us from writing the status in the "in" header (e.g. the header length is incorrect, etc.). The guest is misbehaving, so maybe the ring is in a bad state, but let's avoid making things worse. Acked-by: Jason Wang Signed-off-by: Stefano Garzarella Message-Id: <20220630153221.83371-4-sgarzare@redhat.com> Signed-off-by: Michael S. Tsirkin --- drivers/vdpa/vdpa_sim/vdpa_sim_blk.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c b/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c index b2d75efec63a..43422b3854d2 100644 --- a/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c +++ b/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c @@ -63,6 +63,7 @@ static bool vdpasim_blk_handle_req(struct vdpasim *vdpasim, { size_t pushed = 0, to_pull, to_push; struct virtio_blk_outhdr hdr; + bool handled = false; ssize_t bytes; loff_t offset; u64 sector; @@ -78,12 +79,12 @@ static bool vdpasim_blk_handle_req(struct vdpasim *vdpasim, if (vq->out_iov.used < 1 || vq->in_iov.used < 1) { dev_dbg(&vdpasim->vdpa.dev, "missing headers - out_iov: %u in_iov %u\n", vq->out_iov.used, vq->in_iov.used); - return false; + goto err; } if (vq->in_iov.iov[vq->in_iov.used - 1].iov_len < 1) { dev_dbg(&vdpasim->vdpa.dev, "request in header too short\n"); - return false; + goto err; } /* The last byte is the status and we checked if the last iov has @@ -97,7 +98,7 @@ static bool vdpasim_blk_handle_req(struct vdpasim *vdpasim, sizeof(hdr)); if (bytes != sizeof(hdr)) { dev_dbg(&vdpasim->vdpa.dev, "request out header too short\n"); - return false; + goto err; } to_pull -= bytes; @@ -182,16 +183,19 @@ static bool vdpasim_blk_handle_req(struct vdpasim *vdpasim, /* Last byte is the status */ bytes = vringh_iov_push_iotlb(&vq->vring, &vq->in_iov, &status, 1); if (bytes != 1) - return false; + goto err; pushed += bytes; /* Make sure data is wrote before advancing index */ smp_wmb(); + handled = true; + +err: vringh_complete_iotlb(&vq->vring, vq->head, pushed); - return true; + return handled; } static void vdpasim_blk_work(struct work_struct *work) -- cgit v1.2.3 From 19cd4a5471b8eaa4bd161b0fdb4567f2fc88d809 Mon Sep 17 00:00:00 2001 From: Stefano Garzarella Date: Tue, 21 Jun 2022 17:13:23 +0200 Subject: vdpa_sim_blk: set number of address spaces and virtqueue groups MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit bda324fd037a ("vdpasim: control virtqueue support") added two new fields (nas, ngroups) to vdpasim_dev_attr, but we forgot to initialize them for vdpa_sim_blk. When creating a new vdpa_sim_blk device this causes the kernel to panic in this way:    $ vdpa dev add mgmtdev vdpasim_blk name blk0    BUG: kernel NULL pointer dereference, address: 0000000000000030    ...    RIP: 0010:vhost_iotlb_add_range_ctx+0x41/0x220 [vhost_iotlb]    ...    Call Trace:         vhost_iotlb_add_range+0x11/0x800 [vhost_iotlb]     vdpasim_map_range+0x91/0xd0 [vdpa_sim]     vdpasim_alloc_coherent+0x56/0x90 [vdpa_sim]     ... This happens because vdpasim->iommu[0] is not initialized when dev_attr.nas is 0. Let's fix this issue by initializing both (nas, ngroups) to 1 for vdpa_sim_blk. Fixes: bda324fd037a ("vdpasim: control virtqueue support") Cc: gautam.dawar@xilinx.com Signed-off-by: Stefano Garzarella Message-Id: <20220621151323.190431-1-sgarzare@redhat.com> Signed-off-by: Michael S. Tsirkin Acked-by: Eugenio Pérez --- drivers/vdpa/vdpa_sim/vdpa_sim_blk.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c b/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c index 43422b3854d2..dde965a826bb 100644 --- a/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c +++ b/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c @@ -34,7 +34,11 @@ #define VDPASIM_BLK_CAPACITY 0x40000 #define VDPASIM_BLK_SIZE_MAX 0x1000 #define VDPASIM_BLK_SEG_MAX 32 + +/* 1 virtqueue, 1 address space, 1 virtqueue group */ #define VDPASIM_BLK_VQ_NUM 1 +#define VDPASIM_BLK_AS_NUM 1 +#define VDPASIM_BLK_GROUP_NUM 1 static char vdpasim_blk_id[VIRTIO_BLK_ID_BYTES] = "vdpa_blk_sim"; @@ -274,6 +278,8 @@ static int vdpasim_blk_dev_add(struct vdpa_mgmt_dev *mdev, const char *name, dev_attr.id = VIRTIO_ID_BLOCK; dev_attr.supported_features = VDPASIM_BLK_FEATURES; dev_attr.nvqs = VDPASIM_BLK_VQ_NUM; + dev_attr.ngroups = VDPASIM_BLK_GROUP_NUM; + dev_attr.nas = VDPASIM_BLK_AS_NUM; dev_attr.config_size = sizeof(struct virtio_blk_config); dev_attr.get_config = vdpasim_blk_get_config; dev_attr.work_fn = vdpasim_blk_work; -- cgit v1.2.3 From 67f8f10c0bd78c4a0f0e983e050ab90da015323b Mon Sep 17 00:00:00 2001 From: Stefano Garzarella Date: Tue, 21 Jun 2022 17:12:08 +0200 Subject: vdpa_sim: use max_iotlb_entries as a limit in vhost_iotlb_init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit bda324fd037a ("vdpasim: control virtqueue support") changed the allocation of iotlbs calling vhost_iotlb_init() for each address space, instead of vhost_iotlb_alloc(). With this change we forgot to use the limit we had introduced with the `max_iotlb_entries` module parameter. Fixes: bda324fd037a ("vdpasim: control virtqueue support") Cc: gautam.dawar@xilinx.com Signed-off-by: Stefano Garzarella Message-Id: <20220621151208.189959-1-sgarzare@redhat.com> Signed-off-by: Michael S. Tsirkin Acked-by: Eugenio Pérez --- drivers/vdpa/vdpa_sim/vdpa_sim.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/vdpa/vdpa_sim/vdpa_sim.c b/drivers/vdpa/vdpa_sim/vdpa_sim.c index 0f2865899647..3e81532c01cb 100644 --- a/drivers/vdpa/vdpa_sim/vdpa_sim.c +++ b/drivers/vdpa/vdpa_sim/vdpa_sim.c @@ -33,7 +33,7 @@ MODULE_PARM_DESC(batch_mapping, "Batched mapping 1 -Enable; 0 - Disable"); static int max_iotlb_entries = 2048; module_param(max_iotlb_entries, int, 0444); MODULE_PARM_DESC(max_iotlb_entries, - "Maximum number of iotlb entries. 0 means unlimited. (default: 2048)"); + "Maximum number of iotlb entries for each address space. 0 means unlimited. (default: 2048)"); #define VDPASIM_QUEUE_ALIGN PAGE_SIZE #define VDPASIM_QUEUE_MAX 256 @@ -291,7 +291,7 @@ struct vdpasim *vdpasim_create(struct vdpasim_dev_attr *dev_attr) goto err_iommu; for (i = 0; i < vdpasim->dev_attr.nas; i++) - vhost_iotlb_init(&vdpasim->iommu[i], 0, 0); + vhost_iotlb_init(&vdpasim->iommu[i], max_iotlb_entries, 0); vdpasim->buffer = kvmalloc(dev_attr->buffer_size, GFP_KERNEL); if (!vdpasim->buffer) -- cgit v1.2.3 From 71aa95a69c765bd0ec1c6d9d6263e6fefa1f5072 Mon Sep 17 00:00:00 2001 From: Xu Qiang Date: Mon, 4 Jul 2022 02:14:05 +0000 Subject: vdpa/mlx5: Use eth_broadcast_addr() to assign broadcast address Using eth_broadcast_addr() to assign broadcast address instead of memset(). Reported-by: Hulk Robot Signed-off-by: Xu Qiang Message-Id: <20220704021405.64545-1-xuqiang36@huawei.com> Signed-off-by: Michael S. Tsirkin Acked-by: Jason Wang --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index e85c1d71f4ed..99bbbf38c8b1 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -1440,7 +1440,7 @@ static int mlx5_vdpa_add_mac_vlan_rules(struct mlx5_vdpa_net *ndev, u8 *mac, headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers); dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c, outer_headers.dmac_47_16); dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v, outer_headers.dmac_47_16); - memset(dmac_c, 0xff, ETH_ALEN); + eth_broadcast_addr(dmac_c); ether_addr_copy(dmac_v, mac); MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1); if (tagged) { -- cgit v1.2.3 From 6e33fa094f1f5a96140cc2439b17f4f3ef9e4a9d Mon Sep 17 00:00:00 2001 From: Zhang Jiaming Date: Mon, 4 Jul 2022 10:41:04 +0800 Subject: vdpa: ifcvf: Fix spelling mistake in comments There is a typo(does't) in comments. It maybe 'doesn't' instead of 'does't'. Signed-off-by: Zhang Jiaming Message-Id: <20220704024104.15535-1-jiaming@nfschina.com> Signed-off-by: Michael S. Tsirkin Acked-by: Jason Wang --- drivers/vdpa/ifcvf/ifcvf_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/vdpa/ifcvf/ifcvf_main.c b/drivers/vdpa/ifcvf/ifcvf_main.c index 0a5670729412..e2e201885713 100644 --- a/drivers/vdpa/ifcvf/ifcvf_main.c +++ b/drivers/vdpa/ifcvf/ifcvf_main.c @@ -685,7 +685,7 @@ static struct vdpa_notification_area ifcvf_get_vq_notification(struct vdpa_devic } /* - * IFCVF currently does't have on-chip IOMMU, so not + * IFCVF currently doesn't have on-chip IOMMU, so not * implemented set_map()/dma_map()/dma_unmap() */ static const struct vdpa_config_ops ifc_vdpa_ops = { -- cgit v1.2.3 From 994cea53183c211f218d5dbe14ab634f5762f068 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Mon, 4 Jul 2022 20:04:56 +0100 Subject: vDPA/ifcvf: remove duplicated assignment to pointer cfg The assignment to pointer cfg is duplicated, the second assignment is redundant and can be removed. Signed-off-by: Colin Ian King Message-Id: <20220704190456.593464-1-colin.i.king@gmail.com> Signed-off-by: Michael S. Tsirkin Acked-by: Jason Wang --- drivers/vdpa/ifcvf/ifcvf_base.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/vdpa/ifcvf/ifcvf_base.c b/drivers/vdpa/ifcvf/ifcvf_base.c index 48c4dadb0c7c..47b94091733c 100644 --- a/drivers/vdpa/ifcvf/ifcvf_base.c +++ b/drivers/vdpa/ifcvf/ifcvf_base.c @@ -29,7 +29,6 @@ u16 ifcvf_set_config_vector(struct ifcvf_hw *hw, int vector) { struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg; - cfg = hw->common_cfg; vp_iowrite16(vector, &cfg->msix_config); return vp_ioread16(&cfg->msix_config); -- cgit v1.2.3 From d650f830f38b19039958f3f4504ceeb2b5922da7 Mon Sep 17 00:00:00 2001 From: Stefano Garzarella Date: Tue, 5 Jul 2022 09:22:49 +0200 Subject: tools/virtio: fix build MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix the build caused by the following changes: - phys_addr_t is now defined in tools/include/linux/types.h - dev_warn_once() is used in drivers/virtio/virtio_ring.c - linux/uio.h included by vringh.h use INT_MAX defined in limits.h Signed-off-by: Stefano Garzarella Message-Id: <20220705072249.7867-1-sgarzare@redhat.com> Signed-off-by: Michael S. Tsirkin Acked-by: Eugenio Pérez Signed-off-by: Peng Fan Acked-by: Jason Wang --- tools/virtio/linux/kernel.h | 2 +- tools/virtio/linux/vringh.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/virtio/linux/kernel.h b/tools/virtio/linux/kernel.h index 0b493542e61a..21593bf97755 100644 --- a/tools/virtio/linux/kernel.h +++ b/tools/virtio/linux/kernel.h @@ -29,7 +29,6 @@ #define READ 0 #define WRITE 1 -typedef unsigned long long phys_addr_t; typedef unsigned long long dma_addr_t; typedef size_t __kernel_size_t; typedef unsigned int __wsum; @@ -136,6 +135,7 @@ static inline void *krealloc_array(void *p, size_t new_n, size_t new_size, gfp_t #endif #define dev_err(dev, format, ...) fprintf (stderr, format, ## __VA_ARGS__) #define dev_warn(dev, format, ...) fprintf (stderr, format, ## __VA_ARGS__) +#define dev_warn_once(dev, format, ...) fprintf (stderr, format, ## __VA_ARGS__) #define min(x, y) ({ \ typeof(x) _min1 = (x); \ diff --git a/tools/virtio/linux/vringh.h b/tools/virtio/linux/vringh.h index 9348957be56e..e11c6aece734 100644 --- a/tools/virtio/linux/vringh.h +++ b/tools/virtio/linux/vringh.h @@ -1 +1,2 @@ +#include #include "../../../include/linux/vringh.h" -- cgit v1.2.3 From 95bf9798779af166b1d6d184d794834214a1a261 Mon Sep 17 00:00:00 2001 From: Bo Liu Date: Wed, 6 Jul 2022 23:17:51 -0400 Subject: virtio: Check dev_set_name() return value It's possible that dev_set_name() returns -ENOMEM, catch and handle this. Signed-off-by: Bo Liu Message-Id: <20220707031751.4802-1-liubo03@inspur.com> Signed-off-by: Michael S. Tsirkin Acked-by: Jason Wang --- drivers/virtio/virtio.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/virtio/virtio.c b/drivers/virtio/virtio.c index 7deeed30d1f3..ddd4466da83b 100644 --- a/drivers/virtio/virtio.c +++ b/drivers/virtio/virtio.c @@ -428,7 +428,9 @@ int register_virtio_device(struct virtio_device *dev) goto out; dev->index = err; - dev_set_name(&dev->dev, "virtio%u", dev->index); + err = dev_set_name(&dev->dev, "virtio%u", dev->index); + if (err) + goto out_ida_remove; err = virtio_device_of_init(dev); if (err) -- cgit v1.2.3 From 699b045a8e43bd1063db4795be685bfd659649dc Mon Sep 17 00:00:00 2001 From: Alvaro Karsz Date: Mon, 18 Jul 2022 12:11:02 +0300 Subject: net: virtio_net: notifications coalescing support New VirtIO network feature: VIRTIO_NET_F_NOTF_COAL. Control a Virtio network device notifications coalescing parameters using the control virtqueue. A device that supports this fetature can receive VIRTIO_NET_CTRL_NOTF_COAL control commands. - VIRTIO_NET_CTRL_NOTF_COAL_TX_SET: Ask the network device to change the following parameters: - tx_usecs: Maximum number of usecs to delay a TX notification. - tx_max_packets: Maximum number of packets to send before a TX notification. - VIRTIO_NET_CTRL_NOTF_COAL_RX_SET: Ask the network device to change the following parameters: - rx_usecs: Maximum number of usecs to delay a RX notification. - rx_max_packets: Maximum number of packets to receive before a RX notification. VirtIO spec. patch: https://lists.oasis-open.org/archives/virtio-comment/202206/msg00100.html Signed-off-by: Alvaro Karsz Message-Id: <20220718091102.498774-1-alvaro.karsz@solid-run.com> Signed-off-by: Michael S. Tsirkin Reviewed-by: Jakub Kicinski Acked-by: Jason Wang --- drivers/net/virtio_net.c | 111 ++++++++++++++++++++++++++++++++++------ include/uapi/linux/virtio_net.h | 34 +++++++++++- 2 files changed, 129 insertions(+), 16 deletions(-) diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index 16783ed782c5..d9c434b00e9b 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c @@ -270,6 +270,12 @@ struct virtnet_info { u8 duplex; u32 speed; + /* Interrupt coalescing settings */ + u32 tx_usecs; + u32 rx_usecs; + u32 tx_max_packets; + u32 rx_max_packets; + unsigned long guest_offloads; unsigned long guest_offloads_capable; @@ -2737,27 +2743,89 @@ static int virtnet_get_link_ksettings(struct net_device *dev, return 0; } +static int virtnet_send_notf_coal_cmds(struct virtnet_info *vi, + struct ethtool_coalesce *ec) +{ + struct scatterlist sgs_tx, sgs_rx; + struct virtio_net_ctrl_coal_tx coal_tx; + struct virtio_net_ctrl_coal_rx coal_rx; + + coal_tx.tx_usecs = cpu_to_le32(ec->tx_coalesce_usecs); + coal_tx.tx_max_packets = cpu_to_le32(ec->tx_max_coalesced_frames); + sg_init_one(&sgs_tx, &coal_tx, sizeof(coal_tx)); + + if (!virtnet_send_command(vi, VIRTIO_NET_CTRL_NOTF_COAL, + VIRTIO_NET_CTRL_NOTF_COAL_TX_SET, + &sgs_tx)) + return -EINVAL; + + /* Save parameters */ + vi->tx_usecs = ec->tx_coalesce_usecs; + vi->tx_max_packets = ec->tx_max_coalesced_frames; + + coal_rx.rx_usecs = cpu_to_le32(ec->rx_coalesce_usecs); + coal_rx.rx_max_packets = cpu_to_le32(ec->rx_max_coalesced_frames); + sg_init_one(&sgs_rx, &coal_rx, sizeof(coal_rx)); + + if (!virtnet_send_command(vi, VIRTIO_NET_CTRL_NOTF_COAL, + VIRTIO_NET_CTRL_NOTF_COAL_RX_SET, + &sgs_rx)) + return -EINVAL; + + /* Save parameters */ + vi->rx_usecs = ec->rx_coalesce_usecs; + vi->rx_max_packets = ec->rx_max_coalesced_frames; + + return 0; +} + +static int virtnet_coal_params_supported(struct ethtool_coalesce *ec) +{ + /* usecs coalescing is supported only if VIRTIO_NET_F_NOTF_COAL + * feature is negotiated. + */ + if (ec->rx_coalesce_usecs || ec->tx_coalesce_usecs) + return -EOPNOTSUPP; + + if (ec->tx_max_coalesced_frames > 1 || + ec->rx_max_coalesced_frames != 1) + return -EINVAL; + + return 0; +} + static int virtnet_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec, struct kernel_ethtool_coalesce *kernel_coal, struct netlink_ext_ack *extack) { struct virtnet_info *vi = netdev_priv(dev); - int i, napi_weight; - - if (ec->tx_max_coalesced_frames > 1 || - ec->rx_max_coalesced_frames != 1) - return -EINVAL; + int ret, i, napi_weight; + bool update_napi = false; + /* Can't change NAPI weight if the link is up */ napi_weight = ec->tx_max_coalesced_frames ? NAPI_POLL_WEIGHT : 0; if (napi_weight ^ vi->sq[0].napi.weight) { if (dev->flags & IFF_UP) return -EBUSY; + else + update_napi = true; + } + + if (virtio_has_feature(vi->vdev, VIRTIO_NET_F_NOTF_COAL)) + ret = virtnet_send_notf_coal_cmds(vi, ec); + else + ret = virtnet_coal_params_supported(ec); + + if (ret) + return ret; + + if (update_napi) { for (i = 0; i < vi->max_queue_pairs; i++) vi->sq[i].napi.weight = napi_weight; } - return 0; + return ret; } static int virtnet_get_coalesce(struct net_device *dev, @@ -2765,16 +2833,19 @@ static int virtnet_get_coalesce(struct net_device *dev, struct kernel_ethtool_coalesce *kernel_coal, struct netlink_ext_ack *extack) { - struct ethtool_coalesce ec_default = { - .cmd = ETHTOOL_GCOALESCE, - .rx_max_coalesced_frames = 1, - }; struct virtnet_info *vi = netdev_priv(dev); - memcpy(ec, &ec_default, sizeof(ec_default)); + if (virtio_has_feature(vi->vdev, VIRTIO_NET_F_NOTF_COAL)) { + ec->rx_coalesce_usecs = vi->rx_usecs; + ec->tx_coalesce_usecs = vi->tx_usecs; + ec->tx_max_coalesced_frames = vi->tx_max_packets; + ec->rx_max_coalesced_frames = vi->rx_max_packets; + } else { + ec->rx_max_coalesced_frames = 1; - if (vi->sq[0].napi.weight) - ec->tx_max_coalesced_frames = 1; + if (vi->sq[0].napi.weight) + ec->tx_max_coalesced_frames = 1; + } return 0; } @@ -2893,7 +2964,8 @@ static int virtnet_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info) } static const struct ethtool_ops virtnet_ethtool_ops = { - .supported_coalesce_params = ETHTOOL_COALESCE_MAX_FRAMES, + .supported_coalesce_params = ETHTOOL_COALESCE_MAX_FRAMES | + ETHTOOL_COALESCE_USECS, .get_drvinfo = virtnet_get_drvinfo, .get_link = ethtool_op_get_link, .get_ringparam = virtnet_get_ringparam, @@ -3606,6 +3678,8 @@ static bool virtnet_validate_features(struct virtio_device *vdev) VIRTNET_FAIL_ON(vdev, VIRTIO_NET_F_RSS, "VIRTIO_NET_F_CTRL_VQ") || VIRTNET_FAIL_ON(vdev, VIRTIO_NET_F_HASH_REPORT, + "VIRTIO_NET_F_CTRL_VQ") || + VIRTNET_FAIL_ON(vdev, VIRTIO_NET_F_NOTF_COAL, "VIRTIO_NET_F_CTRL_VQ"))) { return false; } @@ -3742,6 +3816,13 @@ static int virtnet_probe(struct virtio_device *vdev) if (virtio_has_feature(vdev, VIRTIO_NET_F_MRG_RXBUF)) vi->mergeable_rx_bufs = true; + if (virtio_has_feature(vi->vdev, VIRTIO_NET_F_NOTF_COAL)) { + vi->rx_usecs = 0; + vi->tx_usecs = 0; + vi->tx_max_packets = 0; + vi->rx_max_packets = 0; + } + if (virtio_has_feature(vdev, VIRTIO_NET_F_HASH_REPORT)) vi->has_rss_hash_report = true; @@ -3977,7 +4058,7 @@ static struct virtio_device_id id_table[] = { VIRTIO_NET_F_CTRL_MAC_ADDR, \ VIRTIO_NET_F_MTU, VIRTIO_NET_F_CTRL_GUEST_OFFLOADS, \ VIRTIO_NET_F_SPEED_DUPLEX, VIRTIO_NET_F_STANDBY, \ - VIRTIO_NET_F_RSS, VIRTIO_NET_F_HASH_REPORT + VIRTIO_NET_F_RSS, VIRTIO_NET_F_HASH_REPORT, VIRTIO_NET_F_NOTF_COAL static unsigned int features[] = { VIRTNET_FEATURES, diff --git a/include/uapi/linux/virtio_net.h b/include/uapi/linux/virtio_net.h index 3f55a4215f11..29ced55514d4 100644 --- a/include/uapi/linux/virtio_net.h +++ b/include/uapi/linux/virtio_net.h @@ -56,7 +56,7 @@ #define VIRTIO_NET_F_MQ 22 /* Device supports Receive Flow * Steering */ #define VIRTIO_NET_F_CTRL_MAC_ADDR 23 /* Set MAC address */ - +#define VIRTIO_NET_F_NOTF_COAL 53 /* Guest can handle notifications coalescing */ #define VIRTIO_NET_F_HASH_REPORT 57 /* Supports hash report */ #define VIRTIO_NET_F_RSS 60 /* Supports RSS RX steering */ #define VIRTIO_NET_F_RSC_EXT 61 /* extended coalescing info */ @@ -355,4 +355,36 @@ struct virtio_net_hash_config { #define VIRTIO_NET_CTRL_GUEST_OFFLOADS 5 #define VIRTIO_NET_CTRL_GUEST_OFFLOADS_SET 0 +/* + * Control notifications coalescing. + * + * Request the device to change the notifications coalescing parameters. + * + * Available with the VIRTIO_NET_F_NOTF_COAL feature bit. + */ +#define VIRTIO_NET_CTRL_NOTF_COAL 6 +/* + * Set the tx-usecs/tx-max-packets patameters. + * tx-usecs - Maximum number of usecs to delay a TX notification. + * tx-max-packets - Maximum number of packets to send before a TX notification. + */ +struct virtio_net_ctrl_coal_tx { + __le32 tx_max_packets; + __le32 tx_usecs; +}; + +#define VIRTIO_NET_CTRL_NOTF_COAL_TX_SET 0 + +/* + * Set the rx-usecs/rx-max-packets patameters. + * rx-usecs - Maximum number of usecs to delay a RX notification. + * rx-max-frames - Maximum number of packets to receive before a RX notification. + */ +struct virtio_net_ctrl_coal_rx { + __le32 rx_max_packets; + __le32 rx_usecs; +}; + +#define VIRTIO_NET_CTRL_NOTF_COAL_RX_SET 1 + #endif /* _UAPI_LINUX_VIRTIO_NET_H */ -- cgit v1.2.3 From c32ee693125aa19a021dad32abbd49f5c6f70031 Mon Sep 17 00:00:00 2001 From: Xie Yongji Date: Wed, 3 Aug 2022 12:55:19 +0800 Subject: vduse: Remove unnecessary spin lock protection Now we use domain->iotlb_lock to protect two different variables: domain->bounce_maps->bounce_page and domain->iotlb. But for domain->bounce_maps->bounce_page, we actually don't need any synchronization between vduse_domain_get_bounce_page() and vduse_domain_free_bounce_pages() since vduse_domain_get_bounce_page() will only be called in page fault handler and vduse_domain_free_bounce_pages() will be called during file release. So let's remove the unnecessary spin lock protection in vduse_domain_get_bounce_page(). Then the usage of domain->iotlb_lock could be more clear: the lock will be only used to protect the domain->iotlb. Signed-off-by: Xie Yongji Acked-by: Jason Wang Message-Id: <20220803045523.23851-2-xieyongji@bytedance.com> Signed-off-by: Michael S. Tsirkin --- drivers/vdpa/vdpa_user/iova_domain.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/vdpa/vdpa_user/iova_domain.c b/drivers/vdpa/vdpa_user/iova_domain.c index 6daa3978d290..bca1f0b8850c 100644 --- a/drivers/vdpa/vdpa_user/iova_domain.c +++ b/drivers/vdpa/vdpa_user/iova_domain.c @@ -211,17 +211,14 @@ static struct page * vduse_domain_get_bounce_page(struct vduse_iova_domain *domain, u64 iova) { struct vduse_bounce_map *map; - struct page *page = NULL; + struct page *page; - spin_lock(&domain->iotlb_lock); map = &domain->bounce_maps[iova >> PAGE_SHIFT]; if (!map->bounce_page) - goto out; + return NULL; page = map->bounce_page; get_page(page); -out: - spin_unlock(&domain->iotlb_lock); return page; } -- cgit v1.2.3 From 82eb46f94ae5faa87ace248d950292c87384a097 Mon Sep 17 00:00:00 2001 From: Xie Yongji Date: Wed, 3 Aug 2022 12:55:20 +0800 Subject: vduse: Use memcpy_{to,from}_page() in do_bounce() kmap_atomic() is being deprecated in favor of kmap_local_page(). The use of kmap_atomic() in do_bounce() is all thread local therefore kmap_local_page() is a sufficient replacement. Convert to kmap_local_page() but, instead of open coding it, use the helpers memcpy_to_page() and memcpy_from_page(). Signed-off-by: Xie Yongji Acked-by: Jason Wang Reviewed-by: Muchun Song Message-Id: <20220803045523.23851-3-xieyongji@bytedance.com> Signed-off-by: Michael S. Tsirkin --- drivers/vdpa/vdpa_user/iova_domain.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/vdpa/vdpa_user/iova_domain.c b/drivers/vdpa/vdpa_user/iova_domain.c index bca1f0b8850c..50d7c08d5450 100644 --- a/drivers/vdpa/vdpa_user/iova_domain.c +++ b/drivers/vdpa/vdpa_user/iova_domain.c @@ -138,18 +138,17 @@ static void do_bounce(phys_addr_t orig, void *addr, size_t size, { unsigned long pfn = PFN_DOWN(orig); unsigned int offset = offset_in_page(orig); - char *buffer; + struct page *page; unsigned int sz = 0; while (size) { sz = min_t(size_t, PAGE_SIZE - offset, size); - buffer = kmap_atomic(pfn_to_page(pfn)); + page = pfn_to_page(pfn); if (dir == DMA_TO_DEVICE) - memcpy(addr, buffer + offset, sz); + memcpy_from_page(addr, page, offset, sz); else - memcpy(buffer + offset, addr, sz); - kunmap_atomic(buffer); + memcpy_to_page(page, offset, addr, sz); size -= sz; pfn++; -- cgit v1.2.3 From 6c77ed22880d3e8ae91b1d2cce26dbd6c69f38b7 Mon Sep 17 00:00:00 2001 From: Xie Yongji Date: Wed, 3 Aug 2022 12:55:21 +0800 Subject: vduse: Support using userspace pages as bounce buffer Introduce two APIs: vduse_domain_add_user_bounce_pages() and vduse_domain_remove_user_bounce_pages() to support adding and removing userspace pages for bounce buffers. During adding and removing, the DMA data would be copied from the kernel bounce pages to the userspace bounce pages and back. Signed-off-by: Xie Yongji Acked-by: Jason Wang Message-Id: <20220803045523.23851-4-xieyongji@bytedance.com> Signed-off-by: Michael S. Tsirkin --- drivers/vdpa/vdpa_user/iova_domain.c | 96 +++++++++++++++++++++++++++++++++--- drivers/vdpa/vdpa_user/iova_domain.h | 8 +++ 2 files changed, 96 insertions(+), 8 deletions(-) diff --git a/drivers/vdpa/vdpa_user/iova_domain.c b/drivers/vdpa/vdpa_user/iova_domain.c index 50d7c08d5450..e682bc7ee6c9 100644 --- a/drivers/vdpa/vdpa_user/iova_domain.c +++ b/drivers/vdpa/vdpa_user/iova_domain.c @@ -178,8 +178,9 @@ static void vduse_domain_bounce(struct vduse_iova_domain *domain, map->orig_phys == INVALID_PHYS_ADDR)) return; - addr = page_address(map->bounce_page) + offset; - do_bounce(map->orig_phys + offset, addr, sz, dir); + addr = kmap_local_page(map->bounce_page); + do_bounce(map->orig_phys + offset, addr + offset, sz, dir); + kunmap_local(addr); size -= sz; iova += sz; } @@ -210,20 +211,23 @@ static struct page * vduse_domain_get_bounce_page(struct vduse_iova_domain *domain, u64 iova) { struct vduse_bounce_map *map; - struct page *page; + struct page *page = NULL; + read_lock(&domain->bounce_lock); map = &domain->bounce_maps[iova >> PAGE_SHIFT]; - if (!map->bounce_page) - return NULL; + if (domain->user_bounce_pages || !map->bounce_page) + goto out; page = map->bounce_page; get_page(page); +out: + read_unlock(&domain->bounce_lock); return page; } static void -vduse_domain_free_bounce_pages(struct vduse_iova_domain *domain) +vduse_domain_free_kernel_bounce_pages(struct vduse_iova_domain *domain) { struct vduse_bounce_map *map; unsigned long pfn, bounce_pfns; @@ -243,6 +247,73 @@ vduse_domain_free_bounce_pages(struct vduse_iova_domain *domain) } } +int vduse_domain_add_user_bounce_pages(struct vduse_iova_domain *domain, + struct page **pages, int count) +{ + struct vduse_bounce_map *map; + int i, ret; + + /* Now we don't support partial mapping */ + if (count != (domain->bounce_size >> PAGE_SHIFT)) + return -EINVAL; + + write_lock(&domain->bounce_lock); + ret = -EEXIST; + if (domain->user_bounce_pages) + goto out; + + for (i = 0; i < count; i++) { + map = &domain->bounce_maps[i]; + if (map->bounce_page) { + /* Copy kernel page to user page if it's in use */ + if (map->orig_phys != INVALID_PHYS_ADDR) + memcpy_to_page(pages[i], 0, + page_address(map->bounce_page), + PAGE_SIZE); + __free_page(map->bounce_page); + } + map->bounce_page = pages[i]; + get_page(pages[i]); + } + domain->user_bounce_pages = true; + ret = 0; +out: + write_unlock(&domain->bounce_lock); + + return ret; +} + +void vduse_domain_remove_user_bounce_pages(struct vduse_iova_domain *domain) +{ + struct vduse_bounce_map *map; + unsigned long i, count; + + write_lock(&domain->bounce_lock); + if (!domain->user_bounce_pages) + goto out; + + count = domain->bounce_size >> PAGE_SHIFT; + for (i = 0; i < count; i++) { + struct page *page = NULL; + + map = &domain->bounce_maps[i]; + if (WARN_ON(!map->bounce_page)) + continue; + + /* Copy user page to kernel page if it's in use */ + if (map->orig_phys != INVALID_PHYS_ADDR) { + page = alloc_page(GFP_ATOMIC | __GFP_NOFAIL); + memcpy_from_page(page_address(page), + map->bounce_page, 0, PAGE_SIZE); + } + put_page(map->bounce_page); + map->bounce_page = page; + } + domain->user_bounce_pages = false; +out: + write_unlock(&domain->bounce_lock); +} + void vduse_domain_reset_bounce_map(struct vduse_iova_domain *domain) { if (!domain->bounce_map) @@ -318,13 +389,18 @@ dma_addr_t vduse_domain_map_page(struct vduse_iova_domain *domain, if (vduse_domain_init_bounce_map(domain)) goto err; + read_lock(&domain->bounce_lock); if (vduse_domain_map_bounce_page(domain, (u64)iova, (u64)size, pa)) - goto err; + goto err_unlock; if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL) vduse_domain_bounce(domain, iova, size, DMA_TO_DEVICE); + read_unlock(&domain->bounce_lock); + return iova; +err_unlock: + read_unlock(&domain->bounce_lock); err: vduse_domain_free_iova(iovad, iova, size); return DMA_MAPPING_ERROR; @@ -336,10 +412,12 @@ void vduse_domain_unmap_page(struct vduse_iova_domain *domain, { struct iova_domain *iovad = &domain->stream_iovad; + read_lock(&domain->bounce_lock); if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) vduse_domain_bounce(domain, dma_addr, size, DMA_FROM_DEVICE); vduse_domain_unmap_bounce_page(domain, (u64)dma_addr, (u64)size); + read_unlock(&domain->bounce_lock); vduse_domain_free_iova(iovad, dma_addr, size); } @@ -447,7 +525,8 @@ static int vduse_domain_release(struct inode *inode, struct file *file) spin_lock(&domain->iotlb_lock); vduse_iotlb_del_range(domain, 0, ULLONG_MAX); - vduse_domain_free_bounce_pages(domain); + vduse_domain_remove_user_bounce_pages(domain); + vduse_domain_free_kernel_bounce_pages(domain); spin_unlock(&domain->iotlb_lock); put_iova_domain(&domain->stream_iovad); put_iova_domain(&domain->consistent_iovad); @@ -507,6 +586,7 @@ vduse_domain_create(unsigned long iova_limit, size_t bounce_size) goto err_file; domain->file = file; + rwlock_init(&domain->bounce_lock); spin_lock_init(&domain->iotlb_lock); init_iova_domain(&domain->stream_iovad, PAGE_SIZE, IOVA_START_PFN); diff --git a/drivers/vdpa/vdpa_user/iova_domain.h b/drivers/vdpa/vdpa_user/iova_domain.h index 2722d9b8e21a..4e0e50e7ac15 100644 --- a/drivers/vdpa/vdpa_user/iova_domain.h +++ b/drivers/vdpa/vdpa_user/iova_domain.h @@ -14,6 +14,7 @@ #include #include #include +#include #define IOVA_START_PFN 1 @@ -34,6 +35,8 @@ struct vduse_iova_domain { struct vhost_iotlb *iotlb; spinlock_t iotlb_lock; struct file *file; + bool user_bounce_pages; + rwlock_t bounce_lock; }; int vduse_domain_set_map(struct vduse_iova_domain *domain, @@ -61,6 +64,11 @@ void vduse_domain_free_coherent(struct vduse_iova_domain *domain, size_t size, void vduse_domain_reset_bounce_map(struct vduse_iova_domain *domain); +int vduse_domain_add_user_bounce_pages(struct vduse_iova_domain *domain, + struct page **pages, int count); + +void vduse_domain_remove_user_bounce_pages(struct vduse_iova_domain *domain); + void vduse_domain_destroy(struct vduse_iova_domain *domain); struct vduse_iova_domain *vduse_domain_create(unsigned long iova_limit, -- cgit v1.2.3 From 79a463be9e0051997508d52cf411ed5e91d657f6 Mon Sep 17 00:00:00 2001 From: Xie Yongji Date: Wed, 3 Aug 2022 12:55:22 +0800 Subject: vduse: Support registering userspace memory for IOVA regions Introduce two ioctls: VDUSE_IOTLB_REG_UMEM and VDUSE_IOTLB_DEREG_UMEM to support registering and de-registering userspace memory for IOVA regions. Now it only supports registering userspace memory for bounce buffer region in virtio-vdpa case. Signed-off-by: Xie Yongji Acked-by: Jason Wang Message-Id: <20220803045523.23851-5-xieyongji@bytedance.com> Signed-off-by: Michael S. Tsirkin --- drivers/vdpa/vdpa_user/vduse_dev.c | 141 +++++++++++++++++++++++++++++++++++++ include/uapi/linux/vduse.h | 23 ++++++ 2 files changed, 164 insertions(+) diff --git a/drivers/vdpa/vdpa_user/vduse_dev.c b/drivers/vdpa/vdpa_user/vduse_dev.c index 3bc27de58f46..eedff0a3885a 100644 --- a/drivers/vdpa/vdpa_user/vduse_dev.c +++ b/drivers/vdpa/vdpa_user/vduse_dev.c @@ -21,6 +21,8 @@ #include #include #include +#include +#include #include #include #include @@ -64,6 +66,13 @@ struct vduse_vdpa { struct vduse_dev *dev; }; +struct vduse_umem { + unsigned long iova; + unsigned long npages; + struct page **pages; + struct mm_struct *mm; +}; + struct vduse_dev { struct vduse_vdpa *vdev; struct device *dev; @@ -95,6 +104,8 @@ struct vduse_dev { u8 status; u32 vq_num; u32 vq_align; + struct vduse_umem *umem; + struct mutex mem_lock; }; struct vduse_dev_msg { @@ -917,6 +928,102 @@ unlock: return ret; } +static int vduse_dev_dereg_umem(struct vduse_dev *dev, + u64 iova, u64 size) +{ + int ret; + + mutex_lock(&dev->mem_lock); + ret = -ENOENT; + if (!dev->umem) + goto unlock; + + ret = -EINVAL; + if (dev->umem->iova != iova || size != dev->domain->bounce_size) + goto unlock; + + vduse_domain_remove_user_bounce_pages(dev->domain); + unpin_user_pages_dirty_lock(dev->umem->pages, + dev->umem->npages, true); + atomic64_sub(dev->umem->npages, &dev->umem->mm->pinned_vm); + mmdrop(dev->umem->mm); + vfree(dev->umem->pages); + kfree(dev->umem); + dev->umem = NULL; + ret = 0; +unlock: + mutex_unlock(&dev->mem_lock); + return ret; +} + +static int vduse_dev_reg_umem(struct vduse_dev *dev, + u64 iova, u64 uaddr, u64 size) +{ + struct page **page_list = NULL; + struct vduse_umem *umem = NULL; + long pinned = 0; + unsigned long npages, lock_limit; + int ret; + + if (!dev->domain->bounce_map || + size != dev->domain->bounce_size || + iova != 0 || uaddr & ~PAGE_MASK) + return -EINVAL; + + mutex_lock(&dev->mem_lock); + ret = -EEXIST; + if (dev->umem) + goto unlock; + + ret = -ENOMEM; + npages = size >> PAGE_SHIFT; + page_list = __vmalloc(array_size(npages, sizeof(struct page *)), + GFP_KERNEL_ACCOUNT); + umem = kzalloc(sizeof(*umem), GFP_KERNEL); + if (!page_list || !umem) + goto unlock; + + mmap_read_lock(current->mm); + + lock_limit = PFN_DOWN(rlimit(RLIMIT_MEMLOCK)); + if (npages + atomic64_read(¤t->mm->pinned_vm) > lock_limit) + goto out; + + pinned = pin_user_pages(uaddr, npages, FOLL_LONGTERM | FOLL_WRITE, + page_list, NULL); + if (pinned != npages) { + ret = pinned < 0 ? pinned : -ENOMEM; + goto out; + } + + ret = vduse_domain_add_user_bounce_pages(dev->domain, + page_list, pinned); + if (ret) + goto out; + + atomic64_add(npages, ¤t->mm->pinned_vm); + + umem->pages = page_list; + umem->npages = pinned; + umem->iova = iova; + umem->mm = current->mm; + mmgrab(current->mm); + + dev->umem = umem; +out: + if (ret && pinned > 0) + unpin_user_pages(page_list, pinned); + + mmap_read_unlock(current->mm); +unlock: + if (ret) { + vfree(page_list); + kfree(umem); + } + mutex_unlock(&dev->mem_lock); + return ret; +} + static long vduse_dev_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { @@ -1089,6 +1196,38 @@ static long vduse_dev_ioctl(struct file *file, unsigned int cmd, ret = vduse_dev_queue_irq_work(dev, &dev->vqs[index].inject); break; } + case VDUSE_IOTLB_REG_UMEM: { + struct vduse_iova_umem umem; + + ret = -EFAULT; + if (copy_from_user(&umem, argp, sizeof(umem))) + break; + + ret = -EINVAL; + if (!is_mem_zero((const char *)umem.reserved, + sizeof(umem.reserved))) + break; + + ret = vduse_dev_reg_umem(dev, umem.iova, + umem.uaddr, umem.size); + break; + } + case VDUSE_IOTLB_DEREG_UMEM: { + struct vduse_iova_umem umem; + + ret = -EFAULT; + if (copy_from_user(&umem, argp, sizeof(umem))) + break; + + ret = -EINVAL; + if (!is_mem_zero((const char *)umem.reserved, + sizeof(umem.reserved))) + break; + + ret = vduse_dev_dereg_umem(dev, umem.iova, + umem.size); + break; + } default: ret = -ENOIOCTLCMD; break; @@ -1101,6 +1240,7 @@ static int vduse_dev_release(struct inode *inode, struct file *file) { struct vduse_dev *dev = file->private_data; + vduse_dev_dereg_umem(dev, 0, dev->domain->bounce_size); spin_lock(&dev->msg_lock); /* Make sure the inflight messages can processed after reconncection */ list_splice_init(&dev->recv_list, &dev->send_list); @@ -1163,6 +1303,7 @@ static struct vduse_dev *vduse_dev_create(void) return NULL; mutex_init(&dev->lock); + mutex_init(&dev->mem_lock); spin_lock_init(&dev->msg_lock); INIT_LIST_HEAD(&dev->send_list); INIT_LIST_HEAD(&dev->recv_list); diff --git a/include/uapi/linux/vduse.h b/include/uapi/linux/vduse.h index 7cfe1c1280c0..9885e0571f09 100644 --- a/include/uapi/linux/vduse.h +++ b/include/uapi/linux/vduse.h @@ -210,6 +210,29 @@ struct vduse_vq_eventfd { */ #define VDUSE_VQ_INJECT_IRQ _IOW(VDUSE_BASE, 0x17, __u32) +/** + * struct vduse_iova_umem - userspace memory configuration for one IOVA region + * @uaddr: start address of userspace memory, it must be aligned to page size + * @iova: start of the IOVA region + * @size: size of the IOVA region + * @reserved: for future use, needs to be initialized to zero + * + * Structure used by VDUSE_IOTLB_REG_UMEM and VDUSE_IOTLB_DEREG_UMEM + * ioctls to register/de-register userspace memory for IOVA regions + */ +struct vduse_iova_umem { + __u64 uaddr; + __u64 iova; + __u64 size; + __u64 reserved[3]; +}; + +/* Register userspace memory for IOVA regions */ +#define VDUSE_IOTLB_REG_UMEM _IOW(VDUSE_BASE, 0x18, struct vduse_iova_umem) + +/* De-register the userspace memory. Caller should set iova and size field. */ +#define VDUSE_IOTLB_DEREG_UMEM _IOW(VDUSE_BASE, 0x19, struct vduse_iova_umem) + /* The control messages definition for read(2)/write(2) on /dev/vduse/$NAME */ /** -- cgit v1.2.3 From ad146355bfad627bd0717ece73997c6c93b1b82e Mon Sep 17 00:00:00 2001 From: Xie Yongji Date: Wed, 3 Aug 2022 12:55:23 +0800 Subject: vduse: Support querying information of IOVA regions This introduces a new ioctl: VDUSE_IOTLB_GET_INFO to support querying some information of IOVA regions. Now it can be used to query whether the IOVA region supports userspace memory registration. Signed-off-by: Xie Yongji Message-Id: <20220803045523.23851-6-xieyongji@bytedance.com> Signed-off-by: Michael S. Tsirkin Acked-by: Jason Wang --- drivers/vdpa/vdpa_user/vduse_dev.c | 39 ++++++++++++++++++++++++++++++++++++++ include/uapi/linux/vduse.h | 24 +++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/drivers/vdpa/vdpa_user/vduse_dev.c b/drivers/vdpa/vdpa_user/vduse_dev.c index eedff0a3885a..41c0b29739f1 100644 --- a/drivers/vdpa/vdpa_user/vduse_dev.c +++ b/drivers/vdpa/vdpa_user/vduse_dev.c @@ -1228,6 +1228,45 @@ static long vduse_dev_ioctl(struct file *file, unsigned int cmd, umem.size); break; } + case VDUSE_IOTLB_GET_INFO: { + struct vduse_iova_info info; + struct vhost_iotlb_map *map; + struct vduse_iova_domain *domain = dev->domain; + + ret = -EFAULT; + if (copy_from_user(&info, argp, sizeof(info))) + break; + + ret = -EINVAL; + if (info.start > info.last) + break; + + if (!is_mem_zero((const char *)info.reserved, + sizeof(info.reserved))) + break; + + spin_lock(&domain->iotlb_lock); + map = vhost_iotlb_itree_first(domain->iotlb, + info.start, info.last); + if (map) { + info.start = map->start; + info.last = map->last; + info.capability = 0; + if (domain->bounce_map && map->start == 0 && + map->last == domain->bounce_size - 1) + info.capability |= VDUSE_IOVA_CAP_UMEM; + } + spin_unlock(&domain->iotlb_lock); + if (!map) + break; + + ret = -EFAULT; + if (copy_to_user(argp, &info, sizeof(info))) + break; + + ret = 0; + break; + } default: ret = -ENOIOCTLCMD; break; diff --git a/include/uapi/linux/vduse.h b/include/uapi/linux/vduse.h index 9885e0571f09..11bd48c72c6c 100644 --- a/include/uapi/linux/vduse.h +++ b/include/uapi/linux/vduse.h @@ -233,6 +233,30 @@ struct vduse_iova_umem { /* De-register the userspace memory. Caller should set iova and size field. */ #define VDUSE_IOTLB_DEREG_UMEM _IOW(VDUSE_BASE, 0x19, struct vduse_iova_umem) +/** + * struct vduse_iova_info - information of one IOVA region + * @start: start of the IOVA region + * @last: last of the IOVA region + * @capability: capability of the IOVA regsion + * @reserved: for future use, needs to be initialized to zero + * + * Structure used by VDUSE_IOTLB_GET_INFO ioctl to get information of + * one IOVA region. + */ +struct vduse_iova_info { + __u64 start; + __u64 last; +#define VDUSE_IOVA_CAP_UMEM (1 << 0) + __u64 capability; + __u64 reserved[3]; +}; + +/* + * Find the first IOVA region that overlaps with the range [start, last] + * and return some information on it. Caller should set start and last fields. + */ +#define VDUSE_IOTLB_GET_INFO _IOWR(VDUSE_BASE, 0x1a, struct vduse_iova_info) + /* The control messages definition for read(2)/write(2) on /dev/vduse/$NAME */ /** -- cgit v1.2.3 From cae15c2ed8e6e058bd5e32de292ab7982640161e Mon Sep 17 00:00:00 2001 From: Eli Cohen Date: Thu, 14 Jul 2022 14:39:26 +0300 Subject: vdpa/mlx5: Implement susupend virtqueue callback Implement the suspend callback allowing to suspend the virtqueues so they stop processing descriptors. This is required to allow to query a consistent state of the virtqueue while live migration is taking place. Signed-off-by: Eli Cohen Message-Id: <20220714113927.85729-2-elic@nvidia.com> Signed-off-by: Michael S. Tsirkin --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 83 ++++++++++++++++++++++++++++++++++++-- include/linux/mlx5/mlx5_ifc_vdpa.h | 8 ++++ 2 files changed, 88 insertions(+), 3 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index 99bbbf38c8b1..a476e06476f6 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -164,6 +164,7 @@ struct mlx5_vdpa_net { bool setup; u32 cur_num_vqs; u32 rqt_size; + bool nb_registered; struct notifier_block nb; struct vdpa_callback config_cb; struct mlx5_vdpa_wq_ent cvq_ent; @@ -895,6 +896,7 @@ static int create_virtqueue(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtque if (err) goto err_cmd; + mvq->fw_state = MLX5_VIRTIO_NET_Q_OBJECT_STATE_INIT; kfree(in); mvq->virtq_id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); @@ -922,6 +924,7 @@ static void destroy_virtqueue(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtq mlx5_vdpa_warn(&ndev->mvdev, "destroy virtqueue 0x%x\n", mvq->virtq_id); return; } + mvq->fw_state = MLX5_VIRTIO_NET_Q_OBJECT_NONE; umems_destroy(ndev, mvq); } @@ -1121,6 +1124,20 @@ err_cmd: return err; } +static bool is_valid_state_change(int oldstate, int newstate) +{ + switch (oldstate) { + case MLX5_VIRTIO_NET_Q_OBJECT_STATE_INIT: + return newstate == MLX5_VIRTIO_NET_Q_OBJECT_STATE_RDY; + case MLX5_VIRTIO_NET_Q_OBJECT_STATE_RDY: + return newstate == MLX5_VIRTIO_NET_Q_OBJECT_STATE_SUSPEND; + case MLX5_VIRTIO_NET_Q_OBJECT_STATE_SUSPEND: + case MLX5_VIRTIO_NET_Q_OBJECT_STATE_ERR: + default: + return false; + } +} + static int modify_virtqueue(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq, int state) { int inlen = MLX5_ST_SZ_BYTES(modify_virtio_net_q_in); @@ -1130,6 +1147,12 @@ static int modify_virtqueue(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtque void *in; int err; + if (mvq->fw_state == MLX5_VIRTIO_NET_Q_OBJECT_NONE) + return 0; + + if (!is_valid_state_change(mvq->fw_state, state)) + return -EINVAL; + in = kzalloc(inlen, GFP_KERNEL); if (!in) return -ENOMEM; @@ -1992,6 +2015,7 @@ static void mlx5_vdpa_set_vq_ready(struct vdpa_device *vdev, u16 idx, bool ready struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev); struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev); struct mlx5_vdpa_virtqueue *mvq; + int err; if (!mvdev->actual_features) return; @@ -2005,8 +2029,16 @@ static void mlx5_vdpa_set_vq_ready(struct vdpa_device *vdev, u16 idx, bool ready } mvq = &ndev->vqs[idx]; - if (!ready) + if (!ready) { suspend_vq(ndev, mvq); + } else { + err = modify_virtqueue(ndev, mvq, MLX5_VIRTIO_NET_Q_OBJECT_STATE_RDY); + if (err) { + mlx5_vdpa_warn(mvdev, "modify VQ %d to ready failed (%d)\n", idx, err); + ready = false; + } + } + mvq->ready = ready; } @@ -2733,6 +2765,37 @@ out_err: return err; } +static void mlx5_vdpa_cvq_suspend(struct mlx5_vdpa_dev *mvdev) +{ + struct mlx5_control_vq *cvq; + + if (!(mvdev->actual_features & BIT_ULL(VIRTIO_NET_F_CTRL_VQ))) + return; + + cvq = &mvdev->cvq; + cvq->ready = false; +} + +static int mlx5_vdpa_suspend(struct vdpa_device *vdev) +{ + struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev); + struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev); + struct mlx5_vdpa_virtqueue *mvq; + int i; + + down_write(&ndev->reslock); + mlx5_notifier_unregister(mvdev->mdev, &ndev->nb); + ndev->nb_registered = false; + flush_workqueue(ndev->mvdev.wq); + for (i = 0; i < ndev->cur_num_vqs; i++) { + mvq = &ndev->vqs[i]; + suspend_vq(ndev, mvq); + } + mlx5_vdpa_cvq_suspend(mvdev); + up_write(&ndev->reslock); + return 0; +} + static const struct vdpa_config_ops mlx5_vdpa_ops = { .set_vq_address = mlx5_vdpa_set_vq_address, .set_vq_num = mlx5_vdpa_set_vq_num, @@ -2763,6 +2826,7 @@ static const struct vdpa_config_ops mlx5_vdpa_ops = { .get_generation = mlx5_vdpa_get_generation, .set_map = mlx5_vdpa_set_map, .free = mlx5_vdpa_free, + .suspend = mlx5_vdpa_suspend, }; static int query_mtu(struct mlx5_core_dev *mdev, u16 *mtu) @@ -2828,6 +2892,7 @@ static void init_mvqs(struct mlx5_vdpa_net *ndev) mvq->index = i; mvq->ndev = ndev; mvq->fwqp.fw = true; + mvq->fw_state = MLX5_VIRTIO_NET_Q_OBJECT_NONE; } for (; i < ndev->mvdev.max_vqs; i++) { mvq = &ndev->vqs[i]; @@ -2902,13 +2967,21 @@ static int event_handler(struct notifier_block *nb, unsigned long event, void *p switch (eqe->sub_type) { case MLX5_PORT_CHANGE_SUBTYPE_DOWN: case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: + down_read(&ndev->reslock); + if (!ndev->nb_registered) { + up_read(&ndev->reslock); + return NOTIFY_DONE; + } wqent = kzalloc(sizeof(*wqent), GFP_ATOMIC); - if (!wqent) + if (!wqent) { + up_read(&ndev->reslock); return NOTIFY_DONE; + } wqent->mvdev = &ndev->mvdev; INIT_WORK(&wqent->work, update_carrier); queue_work(ndev->mvdev.wq, &wqent->work); + up_read(&ndev->reslock); ret = NOTIFY_OK; break; default: @@ -3062,6 +3135,7 @@ static int mlx5_vdpa_dev_add(struct vdpa_mgmt_dev *v_mdev, const char *name, ndev->nb.notifier_call = event_handler; mlx5_notifier_register(mdev, &ndev->nb); + ndev->nb_registered = true; mvdev->vdev.mdev = &mgtdev->mgtdev; err = _vdpa_register_device(&mvdev->vdev, max_vqs + 1); if (err) @@ -3093,7 +3167,10 @@ static void mlx5_vdpa_dev_del(struct vdpa_mgmt_dev *v_mdev, struct vdpa_device * struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev); struct workqueue_struct *wq; - mlx5_notifier_unregister(mvdev->mdev, &ndev->nb); + if (ndev->nb_registered) { + mlx5_notifier_unregister(mvdev->mdev, &ndev->nb); + ndev->nb_registered = false; + } wq = mvdev->wq; mvdev->wq = NULL; destroy_workqueue(wq); diff --git a/include/linux/mlx5/mlx5_ifc_vdpa.h b/include/linux/mlx5/mlx5_ifc_vdpa.h index 4414ed5b6ed2..9becdc3fa503 100644 --- a/include/linux/mlx5/mlx5_ifc_vdpa.h +++ b/include/linux/mlx5/mlx5_ifc_vdpa.h @@ -150,6 +150,14 @@ enum { MLX5_VIRTIO_NET_Q_OBJECT_STATE_ERR = 0x3, }; +/* This indicates that the object was not created or has already + * been desroyed. It is very safe to assume that this object will never + * have so many states + */ +enum { + MLX5_VIRTIO_NET_Q_OBJECT_NONE = 0xffffffff +}; + enum { MLX5_RQTC_LIST_Q_TYPE_RQ = 0x0, MLX5_RQTC_LIST_Q_TYPE_VIRTIO_NET_Q = 0x1, -- cgit v1.2.3 From 8fcd20c307042b0bb4fd3aee7fc23c94080306ad Mon Sep 17 00:00:00 2001 From: Eli Cohen Date: Thu, 14 Jul 2022 14:39:27 +0300 Subject: vdpa/mlx5: Support different address spaces for control and data Partition virtqueues to two different address spaces: one for control virtqueue which is implemented in software, and one for data virtqueues. Based-on: <20220526124338.36247-1-eperezma@redhat.com> Signed-off-by: Eli Cohen Message-Id: <20220714113927.85729-3-elic@nvidia.com> Signed-off-by: Michael S. Tsirkin --- drivers/vdpa/mlx5/core/mlx5_vdpa.h | 11 +++++ drivers/vdpa/mlx5/net/mlx5_vnet.c | 88 +++++++++++++++++++++++++++++++++----- 2 files changed, 88 insertions(+), 11 deletions(-) diff --git a/drivers/vdpa/mlx5/core/mlx5_vdpa.h b/drivers/vdpa/mlx5/core/mlx5_vdpa.h index 44104093163b..6af9fdbb86b7 100644 --- a/drivers/vdpa/mlx5/core/mlx5_vdpa.h +++ b/drivers/vdpa/mlx5/core/mlx5_vdpa.h @@ -70,6 +70,16 @@ struct mlx5_vdpa_wq_ent { struct mlx5_vdpa_dev *mvdev; }; +enum { + MLX5_VDPA_DATAVQ_GROUP, + MLX5_VDPA_CVQ_GROUP, + MLX5_VDPA_NUMVQ_GROUPS +}; + +enum { + MLX5_VDPA_NUM_AS = MLX5_VDPA_NUMVQ_GROUPS +}; + struct mlx5_vdpa_dev { struct vdpa_device vdev; struct mlx5_core_dev *mdev; @@ -85,6 +95,7 @@ struct mlx5_vdpa_dev { struct mlx5_vdpa_mr mr; struct mlx5_control_vq cvq; struct workqueue_struct *wq; + unsigned int group2asid[MLX5_VDPA_NUMVQ_GROUPS]; }; int mlx5_vdpa_alloc_pd(struct mlx5_vdpa_dev *dev, u32 *pdn, u16 uid); diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index a476e06476f6..289cf91b1ff5 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -2127,9 +2127,14 @@ static u32 mlx5_vdpa_get_vq_align(struct vdpa_device *vdev) return PAGE_SIZE; } -static u32 mlx5_vdpa_get_vq_group(struct vdpa_device *vdpa, u16 idx) +static u32 mlx5_vdpa_get_vq_group(struct vdpa_device *vdev, u16 idx) { - return 0; + struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev); + + if (is_ctrl_vq_idx(mvdev, idx)) + return MLX5_VDPA_CVQ_GROUP; + + return MLX5_VDPA_DATAVQ_GROUP; } enum { MLX5_VIRTIO_NET_F_GUEST_CSUM = 1 << 9, @@ -2543,6 +2548,15 @@ err_clear: up_write(&ndev->reslock); } +static void init_group_to_asid_map(struct mlx5_vdpa_dev *mvdev) +{ + int i; + + /* default mapping all groups are mapped to asid 0 */ + for (i = 0; i < MLX5_VDPA_NUMVQ_GROUPS; i++) + mvdev->group2asid[i] = 0; +} + static int mlx5_vdpa_reset(struct vdpa_device *vdev) { struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev); @@ -2561,7 +2575,9 @@ static int mlx5_vdpa_reset(struct vdpa_device *vdev) ndev->mvdev.cvq.completed_desc = 0; memset(ndev->event_cbs, 0, sizeof(*ndev->event_cbs) * (mvdev->max_vqs + 1)); ndev->mvdev.actual_features = 0; + init_group_to_asid_map(mvdev); ++mvdev->generation; + if (MLX5_CAP_GEN(mvdev->mdev, umem_uid_0)) { if (mlx5_vdpa_create_mr(mvdev, NULL)) mlx5_vdpa_warn(mvdev, "create MR failed\n"); @@ -2599,26 +2615,63 @@ static u32 mlx5_vdpa_get_generation(struct vdpa_device *vdev) return mvdev->generation; } -static int mlx5_vdpa_set_map(struct vdpa_device *vdev, unsigned int asid, - struct vhost_iotlb *iotlb) +static int set_map_control(struct mlx5_vdpa_dev *mvdev, struct vhost_iotlb *iotlb) +{ + u64 start = 0ULL, last = 0ULL - 1; + struct vhost_iotlb_map *map; + int err = 0; + + spin_lock(&mvdev->cvq.iommu_lock); + vhost_iotlb_reset(mvdev->cvq.iotlb); + + for (map = vhost_iotlb_itree_first(iotlb, start, last); map; + map = vhost_iotlb_itree_next(map, start, last)) { + err = vhost_iotlb_add_range(mvdev->cvq.iotlb, map->start, + map->last, map->addr, map->perm); + if (err) + goto out; + } + +out: + spin_unlock(&mvdev->cvq.iommu_lock); + return err; +} + +static int set_map_data(struct mlx5_vdpa_dev *mvdev, struct vhost_iotlb *iotlb) { - struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev); - struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev); bool change_map; int err; - down_write(&ndev->reslock); - err = mlx5_vdpa_handle_set_map(mvdev, iotlb, &change_map); if (err) { mlx5_vdpa_warn(mvdev, "set map failed(%d)\n", err); - goto err; + return err; } if (change_map) err = mlx5_vdpa_change_map(mvdev, iotlb); -err: + return err; +} + +static int mlx5_vdpa_set_map(struct vdpa_device *vdev, unsigned int asid, + struct vhost_iotlb *iotlb) +{ + struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev); + struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev); + int err; + + down_write(&ndev->reslock); + if (mvdev->group2asid[MLX5_VDPA_DATAVQ_GROUP] == asid) { + err = set_map_data(mvdev, iotlb); + if (err) + goto out; + } + + if (mvdev->group2asid[MLX5_VDPA_CVQ_GROUP] == asid) + err = set_map_control(mvdev, iotlb); + +out: up_write(&ndev->reslock); return err; } @@ -2796,6 +2849,18 @@ static int mlx5_vdpa_suspend(struct vdpa_device *vdev) return 0; } +static int mlx5_set_group_asid(struct vdpa_device *vdev, u32 group, + unsigned int asid) +{ + struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev); + + if (group >= MLX5_VDPA_NUMVQ_GROUPS) + return -EINVAL; + + mvdev->group2asid[group] = asid; + return 0; +} + static const struct vdpa_config_ops mlx5_vdpa_ops = { .set_vq_address = mlx5_vdpa_set_vq_address, .set_vq_num = mlx5_vdpa_set_vq_num, @@ -2825,6 +2890,7 @@ static const struct vdpa_config_ops mlx5_vdpa_ops = { .set_config = mlx5_vdpa_set_config, .get_generation = mlx5_vdpa_get_generation, .set_map = mlx5_vdpa_set_map, + .set_group_asid = mlx5_set_group_asid, .free = mlx5_vdpa_free, .suspend = mlx5_vdpa_suspend, }; @@ -3055,7 +3121,7 @@ static int mlx5_vdpa_dev_add(struct vdpa_mgmt_dev *v_mdev, const char *name, } ndev = vdpa_alloc_device(struct mlx5_vdpa_net, mvdev.vdev, mdev->device, &mlx5_vdpa_ops, - 1, 1, name, false); + MLX5_VDPA_NUMVQ_GROUPS, MLX5_VDPA_NUM_AS, name, false); if (IS_ERR(ndev)) return PTR_ERR(ndev); -- cgit v1.2.3 From 5a4b0420b28fed7e8df81ac7e3b53834142053dd Mon Sep 17 00:00:00 2001 From: Mike Christie Date: Thu, 7 Jul 2022 22:05:24 -0500 Subject: vhost-scsi: Fix max number of virtqueues Qemu takes it's num_queues limit then adds the fixed queues (control and event) to the total it will request from the kernel. So when a user requests 128 (or qemu does it's num_queues calculation based on vCPUS and other system limits), we hit errors due to userspace trying to setup 130 queues when vhost-scsi has a hard coded limit of 128. This has vhost-scsi adjust it's max so we can do a total of 130 virtqueues (128 IO and 2 fixed). For the case where the user has 128 vCPUs the guest OS can then nicely map each IO virtqueue to a vCPU and not have the odd case where 2 vCPUs share a virtqueue. Signed-off-by: Mike Christie Message-Id: <20220708030525.5065-2-michael.christie@oracle.com> Signed-off-by: Michael S. Tsirkin Acked-by: Jason Wang --- drivers/vhost/scsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/vhost/scsi.c b/drivers/vhost/scsi.c index ffd9e6c2ffc1..8d6b4eef554d 100644 --- a/drivers/vhost/scsi.c +++ b/drivers/vhost/scsi.c @@ -159,7 +159,7 @@ enum { }; #define VHOST_SCSI_MAX_TARGET 256 -#define VHOST_SCSI_MAX_VQ 128 +#define VHOST_SCSI_MAX_VQ 128 + VHOST_SCSI_VQ_IO #define VHOST_SCSI_MAX_EVENT 128 struct vhost_scsi_virtqueue { -- cgit v1.2.3 From f49c2226af8444563897e25bf293ea29e377995a Mon Sep 17 00:00:00 2001 From: Mike Christie Date: Thu, 7 Jul 2022 22:05:25 -0500 Subject: vhost scsi: Allow user to control num virtqueues We are currently hard coded to always create 128 IO virtqueues, so this adds a modparam to control it. For large systems where we are ok with using memory for virtqueues it allows us to add up to 1024. This limit was just selected becuase that's qemu's limit. Signed-off-by: Mike Christie Message-Id: <20220708030525.5065-3-michael.christie@oracle.com> Signed-off-by: Michael S. Tsirkin Acked-by: Jason Wang --- drivers/vhost/scsi.c | 85 +++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 61 insertions(+), 24 deletions(-) diff --git a/drivers/vhost/scsi.c b/drivers/vhost/scsi.c index 8d6b4eef554d..d9861ab2c300 100644 --- a/drivers/vhost/scsi.c +++ b/drivers/vhost/scsi.c @@ -159,9 +159,13 @@ enum { }; #define VHOST_SCSI_MAX_TARGET 256 -#define VHOST_SCSI_MAX_VQ 128 + VHOST_SCSI_VQ_IO +#define VHOST_SCSI_MAX_IO_VQ 1024 #define VHOST_SCSI_MAX_EVENT 128 +static unsigned vhost_scsi_max_io_vqs = 128; +module_param_named(max_io_vqs, vhost_scsi_max_io_vqs, uint, 0644); +MODULE_PARM_DESC(max_io_vqs, "Set the max number of IO virtqueues a vhost scsi device can support. The default is 128. The max is 1024."); + struct vhost_scsi_virtqueue { struct vhost_virtqueue vq; /* @@ -186,7 +190,9 @@ struct vhost_scsi { char vs_vhost_wwpn[TRANSPORT_IQN_LEN]; struct vhost_dev dev; - struct vhost_scsi_virtqueue vqs[VHOST_SCSI_MAX_VQ]; + struct vhost_scsi_virtqueue *vqs; + unsigned long *compl_bitmap; + struct vhost_scsi_inflight **old_inflight; struct vhost_work vs_completion_work; /* cmd completion work item */ struct llist_head vs_completion_list; /* cmd completion queue */ @@ -245,7 +251,7 @@ static void vhost_scsi_init_inflight(struct vhost_scsi *vs, struct vhost_virtqueue *vq; int idx, i; - for (i = 0; i < VHOST_SCSI_MAX_VQ; i++) { + for (i = 0; i < vs->dev.nvqs; i++) { vq = &vs->vqs[i].vq; mutex_lock(&vq->mutex); @@ -533,7 +539,6 @@ static void vhost_scsi_complete_cmd_work(struct vhost_work *work) { struct vhost_scsi *vs = container_of(work, struct vhost_scsi, vs_completion_work); - DECLARE_BITMAP(signal, VHOST_SCSI_MAX_VQ); struct virtio_scsi_cmd_resp v_rsp; struct vhost_scsi_cmd *cmd, *t; struct llist_node *llnode; @@ -541,7 +546,7 @@ static void vhost_scsi_complete_cmd_work(struct vhost_work *work) struct iov_iter iov_iter; int ret, vq; - bitmap_zero(signal, VHOST_SCSI_MAX_VQ); + bitmap_zero(vs->compl_bitmap, vs->dev.nvqs); llnode = llist_del_all(&vs->vs_completion_list); llist_for_each_entry_safe(cmd, t, llnode, tvc_completion_list) { se_cmd = &cmd->tvc_se_cmd; @@ -566,7 +571,7 @@ static void vhost_scsi_complete_cmd_work(struct vhost_work *work) vhost_add_used(cmd->tvc_vq, cmd->tvc_vq_desc, 0); q = container_of(cmd->tvc_vq, struct vhost_scsi_virtqueue, vq); vq = q - vs->vqs; - __set_bit(vq, signal); + __set_bit(vq, vs->compl_bitmap); } else pr_err("Faulted on virtio_scsi_cmd_resp\n"); @@ -574,8 +579,8 @@ static void vhost_scsi_complete_cmd_work(struct vhost_work *work) } vq = -1; - while ((vq = find_next_bit(signal, VHOST_SCSI_MAX_VQ, vq + 1)) - < VHOST_SCSI_MAX_VQ) + while ((vq = find_next_bit(vs->compl_bitmap, vs->dev.nvqs, vq + 1)) + < vs->dev.nvqs) vhost_signal(&vs->dev, &vs->vqs[vq].vq); } @@ -1421,26 +1426,25 @@ static void vhost_scsi_handle_kick(struct vhost_work *work) /* Callers must hold dev mutex */ static void vhost_scsi_flush(struct vhost_scsi *vs) { - struct vhost_scsi_inflight *old_inflight[VHOST_SCSI_MAX_VQ]; int i; /* Init new inflight and remember the old inflight */ - vhost_scsi_init_inflight(vs, old_inflight); + vhost_scsi_init_inflight(vs, vs->old_inflight); /* * The inflight->kref was initialized to 1. We decrement it here to * indicate the start of the flush operation so that it will reach 0 * when all the reqs are finished. */ - for (i = 0; i < VHOST_SCSI_MAX_VQ; i++) - kref_put(&old_inflight[i]->kref, vhost_scsi_done_inflight); + for (i = 0; i < vs->dev.nvqs; i++) + kref_put(&vs->old_inflight[i]->kref, vhost_scsi_done_inflight); /* Flush both the vhost poll and vhost work */ vhost_dev_flush(&vs->dev); /* Wait for all reqs issued before the flush to be finished */ - for (i = 0; i < VHOST_SCSI_MAX_VQ; i++) - wait_for_completion(&old_inflight[i]->comp); + for (i = 0; i < vs->dev.nvqs; i++) + wait_for_completion(&vs->old_inflight[i]->comp); } static void vhost_scsi_destroy_vq_cmds(struct vhost_virtqueue *vq) @@ -1603,7 +1607,7 @@ vhost_scsi_set_endpoint(struct vhost_scsi *vs, memcpy(vs->vs_vhost_wwpn, t->vhost_wwpn, sizeof(vs->vs_vhost_wwpn)); - for (i = VHOST_SCSI_VQ_IO; i < VHOST_SCSI_MAX_VQ; i++) { + for (i = VHOST_SCSI_VQ_IO; i < vs->dev.nvqs; i++) { vq = &vs->vqs[i].vq; if (!vhost_vq_is_setup(vq)) continue; @@ -1613,7 +1617,7 @@ vhost_scsi_set_endpoint(struct vhost_scsi *vs, goto destroy_vq_cmds; } - for (i = 0; i < VHOST_SCSI_MAX_VQ; i++) { + for (i = 0; i < vs->dev.nvqs; i++) { vq = &vs->vqs[i].vq; mutex_lock(&vq->mutex); vhost_vq_set_backend(vq, vs_tpg); @@ -1715,7 +1719,7 @@ vhost_scsi_clear_endpoint(struct vhost_scsi *vs, target_undepend_item(&se_tpg->tpg_group.cg_item); } if (match) { - for (i = 0; i < VHOST_SCSI_MAX_VQ; i++) { + for (i = 0; i < vs->dev.nvqs; i++) { vq = &vs->vqs[i].vq; mutex_lock(&vq->mutex); vhost_vq_set_backend(vq, NULL); @@ -1724,7 +1728,7 @@ vhost_scsi_clear_endpoint(struct vhost_scsi *vs, /* Make sure cmds are not running before tearing them down. */ vhost_scsi_flush(vs); - for (i = 0; i < VHOST_SCSI_MAX_VQ; i++) { + for (i = 0; i < vs->dev.nvqs; i++) { vq = &vs->vqs[i].vq; vhost_scsi_destroy_vq_cmds(vq); } @@ -1764,7 +1768,7 @@ static int vhost_scsi_set_features(struct vhost_scsi *vs, u64 features) return -EFAULT; } - for (i = 0; i < VHOST_SCSI_MAX_VQ; i++) { + for (i = 0; i < vs->dev.nvqs; i++) { vq = &vs->vqs[i].vq; mutex_lock(&vq->mutex); vq->acked_features = features; @@ -1778,16 +1782,40 @@ static int vhost_scsi_open(struct inode *inode, struct file *f) { struct vhost_scsi *vs; struct vhost_virtqueue **vqs; - int r = -ENOMEM, i; + int r = -ENOMEM, i, nvqs = vhost_scsi_max_io_vqs; vs = kvzalloc(sizeof(*vs), GFP_KERNEL); if (!vs) goto err_vs; - vqs = kmalloc_array(VHOST_SCSI_MAX_VQ, sizeof(*vqs), GFP_KERNEL); - if (!vqs) + if (nvqs > VHOST_SCSI_MAX_IO_VQ) { + pr_err("Invalid max_io_vqs of %d. Using %d.\n", nvqs, + VHOST_SCSI_MAX_IO_VQ); + nvqs = VHOST_SCSI_MAX_IO_VQ; + } else if (nvqs == 0) { + pr_err("Invalid max_io_vqs of %d. Using 1.\n", nvqs); + nvqs = 1; + } + nvqs += VHOST_SCSI_VQ_IO; + + vs->compl_bitmap = bitmap_alloc(nvqs, GFP_KERNEL); + if (!vs->compl_bitmap) + goto err_compl_bitmap; + + vs->old_inflight = kmalloc_array(nvqs, sizeof(*vs->old_inflight), + GFP_KERNEL | __GFP_ZERO); + if (!vs->old_inflight) + goto err_inflight; + + vs->vqs = kmalloc_array(nvqs, sizeof(*vs->vqs), + GFP_KERNEL | __GFP_ZERO); + if (!vs->vqs) goto err_vqs; + vqs = kmalloc_array(nvqs, sizeof(*vqs), GFP_KERNEL); + if (!vqs) + goto err_local_vqs; + vhost_work_init(&vs->vs_completion_work, vhost_scsi_complete_cmd_work); vhost_work_init(&vs->vs_event_work, vhost_scsi_evt_work); @@ -1798,11 +1826,11 @@ static int vhost_scsi_open(struct inode *inode, struct file *f) vqs[VHOST_SCSI_VQ_EVT] = &vs->vqs[VHOST_SCSI_VQ_EVT].vq; vs->vqs[VHOST_SCSI_VQ_CTL].vq.handle_kick = vhost_scsi_ctl_handle_kick; vs->vqs[VHOST_SCSI_VQ_EVT].vq.handle_kick = vhost_scsi_evt_handle_kick; - for (i = VHOST_SCSI_VQ_IO; i < VHOST_SCSI_MAX_VQ; i++) { + for (i = VHOST_SCSI_VQ_IO; i < nvqs; i++) { vqs[i] = &vs->vqs[i].vq; vs->vqs[i].vq.handle_kick = vhost_scsi_handle_kick; } - vhost_dev_init(&vs->dev, vqs, VHOST_SCSI_MAX_VQ, UIO_MAXIOV, + vhost_dev_init(&vs->dev, vqs, nvqs, UIO_MAXIOV, VHOST_SCSI_WEIGHT, 0, true, NULL); vhost_scsi_init_inflight(vs, NULL); @@ -1810,7 +1838,13 @@ static int vhost_scsi_open(struct inode *inode, struct file *f) f->private_data = vs; return 0; +err_local_vqs: + kfree(vs->vqs); err_vqs: + kfree(vs->old_inflight); +err_inflight: + bitmap_free(vs->compl_bitmap); +err_compl_bitmap: kvfree(vs); err_vs: return r; @@ -1828,6 +1862,9 @@ static int vhost_scsi_release(struct inode *inode, struct file *f) vhost_dev_stop(&vs->dev); vhost_dev_cleanup(&vs->dev); kfree(vs->dev.vqs); + kfree(vs->vqs); + kfree(vs->old_inflight); + bitmap_free(vs->compl_bitmap); kvfree(vs); return 0; } -- cgit v1.2.3 From 0d6e5e8d1686ce5d055c5ecaa76e5f51609ce9da Mon Sep 17 00:00:00 2001 From: Zhu Lingshan Date: Fri, 22 Jul 2022 19:53:04 +0800 Subject: vDPA/ifcvf: get_config_size should return a value no greater than dev implementation Drivers must not access a BAR outside the capability length, and for a virtio device, ifcvf driver should not report any non-standard capability contents to the upper layers. Function ifcvf_get_config_size() is introduced here to return a safe value of the device config capability size. Signed-off-by: Zhu Lingshan Message-Id: <20220722115309.82746-2-lingshan.zhu@intel.com> Signed-off-by: Michael S. Tsirkin --- drivers/vdpa/ifcvf/ifcvf_base.c | 13 +++++++++++-- drivers/vdpa/ifcvf/ifcvf_base.h | 2 ++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/vdpa/ifcvf/ifcvf_base.c b/drivers/vdpa/ifcvf/ifcvf_base.c index 47b94091733c..75a703b803a2 100644 --- a/drivers/vdpa/ifcvf/ifcvf_base.c +++ b/drivers/vdpa/ifcvf/ifcvf_base.c @@ -127,6 +127,7 @@ int ifcvf_init_hw(struct ifcvf_hw *hw, struct pci_dev *pdev) break; case VIRTIO_PCI_CAP_DEVICE_CFG: hw->dev_cfg = get_cap_addr(hw, &cap); + hw->cap_dev_config_size = le32_to_cpu(cap.length); IFCVF_DBG(pdev, "hw->dev_cfg = %p\n", hw->dev_cfg); break; } @@ -232,15 +233,23 @@ int ifcvf_verify_min_features(struct ifcvf_hw *hw, u64 features) u32 ifcvf_get_config_size(struct ifcvf_hw *hw) { struct ifcvf_adapter *adapter; + u32 net_config_size = sizeof(struct virtio_net_config); + u32 blk_config_size = sizeof(struct virtio_blk_config); + u32 cap_size = hw->cap_dev_config_size; u32 config_size; adapter = vf_to_adapter(hw); + /* If the onboard device config space size is greater than + * the size of struct virtio_net/blk_config, only the spec + * implementing contents size is returned, this is very + * unlikely, defensive programming. + */ switch (hw->dev_type) { case VIRTIO_ID_NET: - config_size = sizeof(struct virtio_net_config); + config_size = min(cap_size, net_config_size); break; case VIRTIO_ID_BLOCK: - config_size = sizeof(struct virtio_blk_config); + config_size = min(cap_size, blk_config_size); break; default: config_size = 0; diff --git a/drivers/vdpa/ifcvf/ifcvf_base.h b/drivers/vdpa/ifcvf/ifcvf_base.h index 115b61f4924b..f5563f665cc6 100644 --- a/drivers/vdpa/ifcvf/ifcvf_base.h +++ b/drivers/vdpa/ifcvf/ifcvf_base.h @@ -87,6 +87,8 @@ struct ifcvf_hw { int config_irq; int vqs_reused_irq; u16 nr_vring; + /* VIRTIO_PCI_CAP_DEVICE_CFG size */ + u32 cap_dev_config_size; }; struct ifcvf_adapter { -- cgit v1.2.3 From 378b2e956820ff5c082d05f42828badcfbabb614 Mon Sep 17 00:00:00 2001 From: Zhu Lingshan Date: Fri, 22 Jul 2022 19:53:05 +0800 Subject: vDPA/ifcvf: support userspace to query features and MQ of a management device Adapting to current netlink interfaces, this commit allows userspace to query feature bits and MQ capability of a management device. Currently both the vDPA device and the management device are the VF itself, thus this ifcvf should initialize the virtio capabilities in probe() before setting up the struct vdpa_mgmt_dev. Signed-off-by: Zhu Lingshan Message-Id: <20220722115309.82746-3-lingshan.zhu@intel.com> Signed-off-by: Michael S. Tsirkin --- drivers/vdpa/ifcvf/ifcvf_main.c | 142 +++++++++++++++++++++------------------- 1 file changed, 76 insertions(+), 66 deletions(-) diff --git a/drivers/vdpa/ifcvf/ifcvf_main.c b/drivers/vdpa/ifcvf/ifcvf_main.c index e2e201885713..f9c0044c6442 100644 --- a/drivers/vdpa/ifcvf/ifcvf_main.c +++ b/drivers/vdpa/ifcvf/ifcvf_main.c @@ -752,59 +752,36 @@ static int ifcvf_vdpa_dev_add(struct vdpa_mgmt_dev *mdev, const char *name, { struct ifcvf_vdpa_mgmt_dev *ifcvf_mgmt_dev; struct ifcvf_adapter *adapter; + struct vdpa_device *vdpa_dev; struct pci_dev *pdev; struct ifcvf_hw *vf; - struct device *dev; - int ret, i; + int ret; ifcvf_mgmt_dev = container_of(mdev, struct ifcvf_vdpa_mgmt_dev, mdev); - if (ifcvf_mgmt_dev->adapter) + if (!ifcvf_mgmt_dev->adapter) return -EOPNOTSUPP; - pdev = ifcvf_mgmt_dev->pdev; - dev = &pdev->dev; - adapter = vdpa_alloc_device(struct ifcvf_adapter, vdpa, - dev, &ifc_vdpa_ops, 1, 1, name, false); - if (IS_ERR(adapter)) { - IFCVF_ERR(pdev, "Failed to allocate vDPA structure"); - return PTR_ERR(adapter); - } - - ifcvf_mgmt_dev->adapter = adapter; - + adapter = ifcvf_mgmt_dev->adapter; vf = &adapter->vf; - vf->dev_type = get_dev_type(pdev); - vf->base = pcim_iomap_table(pdev); + pdev = adapter->pdev; + vdpa_dev = &adapter->vdpa; - adapter->pdev = pdev; - adapter->vdpa.dma_dev = &pdev->dev; - - ret = ifcvf_init_hw(vf, pdev); - if (ret) { - IFCVF_ERR(pdev, "Failed to init IFCVF hw\n"); - goto err; - } - - for (i = 0; i < vf->nr_vring; i++) - vf->vring[i].irq = -EINVAL; - - vf->hw_features = ifcvf_get_hw_features(vf); - vf->config_size = ifcvf_get_config_size(vf); + if (name) + ret = dev_set_name(&vdpa_dev->dev, "%s", name); + else + ret = dev_set_name(&vdpa_dev->dev, "vdpa%u", vdpa_dev->index); - adapter->vdpa.mdev = &ifcvf_mgmt_dev->mdev; ret = _vdpa_register_device(&adapter->vdpa, vf->nr_vring); if (ret) { + put_device(&adapter->vdpa.dev); IFCVF_ERR(pdev, "Failed to register to vDPA bus"); - goto err; + return ret; } return 0; - -err: - put_device(&adapter->vdpa.dev); - return ret; } + static void ifcvf_vdpa_dev_del(struct vdpa_mgmt_dev *mdev, struct vdpa_device *dev) { struct ifcvf_vdpa_mgmt_dev *ifcvf_mgmt_dev; @@ -823,61 +800,94 @@ static int ifcvf_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct ifcvf_vdpa_mgmt_dev *ifcvf_mgmt_dev; struct device *dev = &pdev->dev; + struct ifcvf_adapter *adapter; + struct ifcvf_hw *vf; u32 dev_type; - int ret; - - ifcvf_mgmt_dev = kzalloc(sizeof(struct ifcvf_vdpa_mgmt_dev), GFP_KERNEL); - if (!ifcvf_mgmt_dev) { - IFCVF_ERR(pdev, "Failed to alloc memory for the vDPA management device\n"); - return -ENOMEM; - } - - dev_type = get_dev_type(pdev); - switch (dev_type) { - case VIRTIO_ID_NET: - ifcvf_mgmt_dev->mdev.id_table = id_table_net; - break; - case VIRTIO_ID_BLOCK: - ifcvf_mgmt_dev->mdev.id_table = id_table_blk; - break; - default: - IFCVF_ERR(pdev, "VIRTIO ID %u not supported\n", dev_type); - ret = -EOPNOTSUPP; - goto err; - } - - ifcvf_mgmt_dev->mdev.ops = &ifcvf_vdpa_mgmt_dev_ops; - ifcvf_mgmt_dev->mdev.device = dev; - ifcvf_mgmt_dev->pdev = pdev; + int ret, i; ret = pcim_enable_device(pdev); if (ret) { IFCVF_ERR(pdev, "Failed to enable device\n"); - goto err; + return ret; } - ret = pcim_iomap_regions(pdev, BIT(0) | BIT(2) | BIT(4), IFCVF_DRIVER_NAME); if (ret) { IFCVF_ERR(pdev, "Failed to request MMIO region\n"); - goto err; + return ret; } ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); if (ret) { IFCVF_ERR(pdev, "No usable DMA configuration\n"); - goto err; + return ret; } ret = devm_add_action_or_reset(dev, ifcvf_free_irq_vectors, pdev); if (ret) { IFCVF_ERR(pdev, "Failed for adding devres for freeing irq vectors\n"); - goto err; + return ret; } pci_set_master(pdev); + adapter = vdpa_alloc_device(struct ifcvf_adapter, vdpa, + dev, &ifc_vdpa_ops, 1, 1, NULL, false); + if (IS_ERR(adapter)) { + IFCVF_ERR(pdev, "Failed to allocate vDPA structure"); + return PTR_ERR(adapter); + } + + vf = &adapter->vf; + vf->dev_type = get_dev_type(pdev); + vf->base = pcim_iomap_table(pdev); + + adapter->pdev = pdev; + adapter->vdpa.dma_dev = &pdev->dev; + + ret = ifcvf_init_hw(vf, pdev); + if (ret) { + IFCVF_ERR(pdev, "Failed to init IFCVF hw\n"); + return ret; + } + + for (i = 0; i < vf->nr_vring; i++) + vf->vring[i].irq = -EINVAL; + + vf->hw_features = ifcvf_get_hw_features(vf); + vf->config_size = ifcvf_get_config_size(vf); + + ifcvf_mgmt_dev = kzalloc(sizeof(struct ifcvf_vdpa_mgmt_dev), GFP_KERNEL); + if (!ifcvf_mgmt_dev) { + IFCVF_ERR(pdev, "Failed to alloc memory for the vDPA management device\n"); + return -ENOMEM; + } + + ifcvf_mgmt_dev->mdev.ops = &ifcvf_vdpa_mgmt_dev_ops; + ifcvf_mgmt_dev->mdev.device = dev; + ifcvf_mgmt_dev->adapter = adapter; + + dev_type = get_dev_type(pdev); + switch (dev_type) { + case VIRTIO_ID_NET: + ifcvf_mgmt_dev->mdev.id_table = id_table_net; + break; + case VIRTIO_ID_BLOCK: + ifcvf_mgmt_dev->mdev.id_table = id_table_blk; + break; + default: + IFCVF_ERR(pdev, "VIRTIO ID %u not supported\n", dev_type); + ret = -EOPNOTSUPP; + goto err; + } + + ifcvf_mgmt_dev->mdev.max_supported_vqs = vf->nr_vring; + ifcvf_mgmt_dev->mdev.supported_features = vf->hw_features; + + adapter->vdpa.mdev = &ifcvf_mgmt_dev->mdev; + + ret = vdpa_mgmtdev_register(&ifcvf_mgmt_dev->mdev); if (ret) { IFCVF_ERR(pdev, -- cgit v1.2.3 From a34bed37fc9d3da319bb75dfbf02a7d3e95e12de Mon Sep 17 00:00:00 2001 From: Zhu Lingshan Date: Fri, 22 Jul 2022 19:53:07 +0800 Subject: vDPA: !FEATURES_OK should not block querying device config space Users may want to query the config space of a vDPA device, to choose a appropriate one for a certain guest. This means the users need to read the config space before FEATURES_OK, and the existence of config space contents does not depend on FEATURES_OK. The spec says: The device MUST allow reading of any device-specific configuration field before FEATURES_OK is set by the driver. This includes fields which are conditional on feature bits, as long as those feature bits are offered by the device. Signed-off-by: Zhu Lingshan Message-Id: <20220722115309.82746-5-lingshan.zhu@intel.com> Signed-off-by: Michael S. Tsirkin --- drivers/vdpa/vdpa.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/vdpa/vdpa.c b/drivers/vdpa/vdpa.c index ebf2f363fbe7..0e99b20e942e 100644 --- a/drivers/vdpa/vdpa.c +++ b/drivers/vdpa/vdpa.c @@ -846,17 +846,9 @@ vdpa_dev_config_fill(struct vdpa_device *vdev, struct sk_buff *msg, u32 portid, { u32 device_id; void *hdr; - u8 status; int err; down_read(&vdev->cf_lock); - status = vdev->config->get_status(vdev); - if (!(status & VIRTIO_CONFIG_S_FEATURES_OK)) { - NL_SET_ERR_MSG_MOD(extack, "Features negotiation not completed"); - err = -EAGAIN; - goto out; - } - hdr = genlmsg_put(msg, portid, seq, &vdpa_nl_family, flags, VDPA_CMD_DEV_CONFIG_GET); if (!hdr) { -- cgit v1.2.3 From 79e0034cb3485e64622ec0aabf8a6f4f8143f47b Mon Sep 17 00:00:00 2001 From: Zhu Lingshan Date: Fri, 22 Jul 2022 19:53:09 +0800 Subject: vDPA: fix 'cast to restricted le16' warnings in vdpa.c This commit fixes spars warnings: cast to restricted __le16 in function vdpa_dev_net_config_fill() and vdpa_fill_stats_rec() Signed-off-by: Zhu Lingshan Reviewed-by: Parav Pandit Message-Id: <20220722115309.82746-7-lingshan.zhu@intel.com> Signed-off-by: Michael S. Tsirkin --- drivers/vdpa/vdpa.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/vdpa/vdpa.c b/drivers/vdpa/vdpa.c index 0e99b20e942e..c06c02704461 100644 --- a/drivers/vdpa/vdpa.c +++ b/drivers/vdpa/vdpa.c @@ -824,11 +824,11 @@ static int vdpa_dev_net_config_fill(struct vdpa_device *vdev, struct sk_buff *ms config.mac)) return -EMSGSIZE; - val_u16 = le16_to_cpu(config.status); + val_u16 = __virtio16_to_cpu(true, config.status); if (nla_put_u16(msg, VDPA_ATTR_DEV_NET_STATUS, val_u16)) return -EMSGSIZE; - val_u16 = le16_to_cpu(config.mtu); + val_u16 = __virtio16_to_cpu(true, config.mtu); if (nla_put_u16(msg, VDPA_ATTR_DEV_NET_CFG_MTU, val_u16)) return -EMSGSIZE; @@ -905,7 +905,7 @@ static int vdpa_fill_stats_rec(struct vdpa_device *vdev, struct sk_buff *msg, } vdpa_get_config_unlocked(vdev, 0, &config, sizeof(config)); - max_vqp = le16_to_cpu(config.max_virtqueue_pairs); + max_vqp = __virtio16_to_cpu(true, config.max_virtqueue_pairs); if (nla_put_u16(msg, VDPA_ATTR_DEV_NET_CFG_MAX_VQP, max_vqp)) return -EMSGSIZE; -- cgit v1.2.3 From ebe6a354fa7e0a7d5b581da31ad031b19d8693f9 Mon Sep 17 00:00:00 2001 From: Bo Liu Date: Fri, 5 Aug 2022 05:12:54 -0400 Subject: vhost-vdpa: Call ida_simple_remove() when failed In function vhost_vdpa_probe(), when code execution fails, we should call ida_simple_remove() to free ida. Signed-off-by: Bo Liu Message-Id: <20220805091254.20026-1-liubo03@inspur.com> Signed-off-by: Michael S. Tsirkin --- drivers/vhost/vdpa.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/vhost/vdpa.c b/drivers/vhost/vdpa.c index 250ad4160ccb..2c997d77d266 100644 --- a/drivers/vhost/vdpa.c +++ b/drivers/vhost/vdpa.c @@ -1363,6 +1363,7 @@ static int vhost_vdpa_probe(struct vdpa_device *vdpa) err: put_device(&v->dev); + ida_simple_remove(&vhost_vdpa_ida, v->minor); return r; } -- cgit v1.2.3 From 99e8927d8a4da8eb8a8a5904dc13a3156be8e7c0 Mon Sep 17 00:00:00 2001 From: Bo Liu Date: Wed, 10 Aug 2022 04:51:51 -0400 Subject: virtio_vdpa: support the arg sizes of find_vqs() Virtio vdpa support the new parameter sizes of find_vqs(). Signed-off-by: Bo Liu Message-Id: <20220810085151.7251-1-liubo03@inspur.com> Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_vdpa.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/virtio/virtio_vdpa.c b/drivers/virtio/virtio_vdpa.c index 832d2c5b1b19..9bc4d110b800 100644 --- a/drivers/virtio/virtio_vdpa.c +++ b/drivers/virtio/virtio_vdpa.c @@ -131,7 +131,7 @@ static irqreturn_t virtio_vdpa_virtqueue_cb(void *private) static struct virtqueue * virtio_vdpa_setup_vq(struct virtio_device *vdev, unsigned int index, void (*callback)(struct virtqueue *vq), - const char *name, bool ctx) + const char *name, u32 size, bool ctx) { struct virtio_vdpa_device *vd_dev = to_virtio_vdpa_device(vdev); struct vdpa_device *vdpa = vd_get_vdpa(vdev); @@ -168,14 +168,17 @@ virtio_vdpa_setup_vq(struct virtio_device *vdev, unsigned int index, goto error_new_virtqueue; } + if (!size || size > max_num) + size = max_num; + if (ops->get_vq_num_min) min_num = ops->get_vq_num_min(vdpa); - may_reduce_num = (max_num == min_num) ? false : true; + may_reduce_num = (size == min_num) ? false : true; /* Create the vring */ align = ops->get_vq_align(vdpa); - vq = vring_create_virtqueue(index, max_num, align, vdev, + vq = vring_create_virtqueue(index, size, align, vdev, true, may_reduce_num, ctx, virtio_vdpa_notify, callback, name); if (!vq) { @@ -285,9 +288,9 @@ static int virtio_vdpa_find_vqs(struct virtio_device *vdev, unsigned int nvqs, continue; } - vqs[i] = virtio_vdpa_setup_vq(vdev, queue_idx++, - callbacks[i], names[i], ctx ? - ctx[i] : false); + vqs[i] = virtio_vdpa_setup_vq(vdev, queue_idx++, callbacks[i], + names[i], sizes ? sizes[i] : 0, + ctx ? ctx[i] : false); if (IS_ERR(vqs[i])) { err = PTR_ERR(vqs[i]); goto err_setup_vq; -- cgit v1.2.3 From 8d12ec10292877751ee4463b11a63bd850bc09b5 Mon Sep 17 00:00:00 2001 From: Shigeru Yoshida Date: Thu, 11 Aug 2022 01:09:48 +0900 Subject: virtio-blk: Avoid use-after-free on suspend/resume hctx->user_data is set to vq in virtblk_init_hctx(). However, vq is freed on suspend and reallocated on resume. So, hctx->user_data is invalid after resume, and it will cause use-after-free accessing which will result in the kernel crash something like below: [ 22.428391] Call Trace: [ 22.428899] [ 22.429339] virtqueue_add_split+0x3eb/0x620 [ 22.430035] ? __blk_mq_alloc_requests+0x17f/0x2d0 [ 22.430789] ? kvm_clock_get_cycles+0x14/0x30 [ 22.431496] virtqueue_add_sgs+0xad/0xd0 [ 22.432108] virtblk_add_req+0xe8/0x150 [ 22.432692] virtio_queue_rqs+0xeb/0x210 [ 22.433330] blk_mq_flush_plug_list+0x1b8/0x280 [ 22.434059] __blk_flush_plug+0xe1/0x140 [ 22.434853] blk_finish_plug+0x20/0x40 [ 22.435512] read_pages+0x20a/0x2e0 [ 22.436063] ? folio_add_lru+0x62/0xa0 [ 22.436652] page_cache_ra_unbounded+0x112/0x160 [ 22.437365] filemap_get_pages+0xe1/0x5b0 [ 22.437964] ? context_to_sid+0x70/0x100 [ 22.438580] ? sidtab_context_to_sid+0x32/0x400 [ 22.439979] filemap_read+0xcd/0x3d0 [ 22.440917] xfs_file_buffered_read+0x4a/0xc0 [ 22.441984] xfs_file_read_iter+0x65/0xd0 [ 22.442970] __kernel_read+0x160/0x2e0 [ 22.443921] bprm_execve+0x21b/0x640 [ 22.444809] do_execveat_common.isra.0+0x1a8/0x220 [ 22.446008] __x64_sys_execve+0x2d/0x40 [ 22.446920] do_syscall_64+0x37/0x90 [ 22.447773] entry_SYSCALL_64_after_hwframe+0x63/0xcd This patch fixes this issue by getting vq from vblk, and removes virtblk_init_hctx(). Fixes: 4e0400525691 ("virtio-blk: support polling I/O") Cc: "Suwan Kim" Signed-off-by: Shigeru Yoshida Message-Id: <20220810160948.959781-1-syoshida@redhat.com> Signed-off-by: Michael S. Tsirkin --- drivers/block/virtio_blk.c | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/drivers/block/virtio_blk.c b/drivers/block/virtio_blk.c index 6fc7850c2b0a..d756423e0059 100644 --- a/drivers/block/virtio_blk.c +++ b/drivers/block/virtio_blk.c @@ -101,6 +101,14 @@ static inline blk_status_t virtblk_result(struct virtblk_req *vbr) } } +static inline struct virtio_blk_vq *get_virtio_blk_vq(struct blk_mq_hw_ctx *hctx) +{ + struct virtio_blk *vblk = hctx->queue->queuedata; + struct virtio_blk_vq *vq = &vblk->vqs[hctx->queue_num]; + + return vq; +} + static int virtblk_add_req(struct virtqueue *vq, struct virtblk_req *vbr) { struct scatterlist hdr, status, *sgs[3]; @@ -416,7 +424,7 @@ static void virtio_queue_rqs(struct request **rqlist) struct request *requeue_list = NULL; rq_list_for_each_safe(rqlist, req, next) { - struct virtio_blk_vq *vq = req->mq_hctx->driver_data; + struct virtio_blk_vq *vq = get_virtio_blk_vq(req->mq_hctx); bool kick; if (!virtblk_prep_rq_batch(req)) { @@ -837,7 +845,7 @@ static void virtblk_complete_batch(struct io_comp_batch *iob) static int virtblk_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob) { struct virtio_blk *vblk = hctx->queue->queuedata; - struct virtio_blk_vq *vq = hctx->driver_data; + struct virtio_blk_vq *vq = get_virtio_blk_vq(hctx); struct virtblk_req *vbr; unsigned long flags; unsigned int len; @@ -862,22 +870,10 @@ static int virtblk_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob) return found; } -static int virtblk_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, - unsigned int hctx_idx) -{ - struct virtio_blk *vblk = data; - struct virtio_blk_vq *vq = &vblk->vqs[hctx_idx]; - - WARN_ON(vblk->tag_set.tags[hctx_idx] != hctx->tags); - hctx->driver_data = vq; - return 0; -} - static const struct blk_mq_ops virtio_mq_ops = { .queue_rq = virtio_queue_rq, .queue_rqs = virtio_queue_rqs, .commit_rqs = virtio_commit_rqs, - .init_hctx = virtblk_init_hctx, .complete = virtblk_request_done, .map_queues = virtblk_map_queues, .poll = virtblk_poll, -- cgit v1.2.3 From 848ecea184e1253758423b37cbfc1ed732ccf5b4 Mon Sep 17 00:00:00 2001 From: Eugenio Pérez Date: Wed, 10 Aug 2022 19:15:09 +0200 Subject: vdpa: Add suspend operation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This operation is optional: It it's not implemented, backend feature bit will not be exposed. Signed-off-by: Eugenio Pérez Message-Id: <20220810171512.2343333-2-eperezma@redhat.com> Signed-off-by: Michael S. Tsirkin --- include/linux/vdpa.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/linux/vdpa.h b/include/linux/vdpa.h index 7b4a13d3bd91..d282f464d2f1 100644 --- a/include/linux/vdpa.h +++ b/include/linux/vdpa.h @@ -218,6 +218,9 @@ struct vdpa_map_file { * @reset: Reset device * @vdev: vdpa device * Returns integer: success (0) or error (< 0) + * @suspend: Suspend or resume the device (optional) + * @vdev: vdpa device + * Returns integer: success (0) or error (< 0) * @get_config_size: Get the size of the configuration space includes * fields that are conditional on feature bits. * @vdev: vdpa device @@ -319,6 +322,7 @@ struct vdpa_config_ops { u8 (*get_status)(struct vdpa_device *vdev); void (*set_status)(struct vdpa_device *vdev, u8 status); int (*reset)(struct vdpa_device *vdev); + int (*suspend)(struct vdpa_device *vdev); size_t (*get_config_size)(struct vdpa_device *vdev); void (*get_config)(struct vdpa_device *vdev, unsigned int offset, void *buf, unsigned int len); -- cgit v1.2.3 From 0723f1df5c3ec8a1112d150dab98e149361ef488 Mon Sep 17 00:00:00 2001 From: Eugenio Pérez Date: Wed, 10 Aug 2022 19:15:10 +0200 Subject: vhost-vdpa: introduce SUSPEND backend feature bit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Userland knows if it can suspend the device or not by checking this feature bit. It's only offered if the vdpa driver backend implements the suspend() operation callback, and to offer it or userland to ack it if the backend does not offer that callback is an error. Signed-off-by: Eugenio Pérez Message-Id: <20220810171512.2343333-3-eperezma@redhat.com> Signed-off-by: Michael S. Tsirkin --- drivers/vhost/vdpa.c | 16 +++++++++++++++- include/uapi/linux/vhost_types.h | 2 ++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/vhost/vdpa.c b/drivers/vhost/vdpa.c index 2c997d77d266..092752fea8e1 100644 --- a/drivers/vhost/vdpa.c +++ b/drivers/vhost/vdpa.c @@ -347,6 +347,14 @@ static long vhost_vdpa_set_config(struct vhost_vdpa *v, return 0; } +static bool vhost_vdpa_can_suspend(const struct vhost_vdpa *v) +{ + struct vdpa_device *vdpa = v->vdpa; + const struct vdpa_config_ops *ops = vdpa->config; + + return ops->suspend; +} + static long vhost_vdpa_get_features(struct vhost_vdpa *v, u64 __user *featurep) { struct vdpa_device *vdpa = v->vdpa; @@ -577,7 +585,11 @@ static long vhost_vdpa_unlocked_ioctl(struct file *filep, if (cmd == VHOST_SET_BACKEND_FEATURES) { if (copy_from_user(&features, featurep, sizeof(features))) return -EFAULT; - if (features & ~VHOST_VDPA_BACKEND_FEATURES) + if (features & ~(VHOST_VDPA_BACKEND_FEATURES | + BIT_ULL(VHOST_BACKEND_F_SUSPEND))) + return -EOPNOTSUPP; + if ((features & BIT_ULL(VHOST_BACKEND_F_SUSPEND)) && + !vhost_vdpa_can_suspend(v)) return -EOPNOTSUPP; vhost_set_backend_features(&v->vdev, features); return 0; @@ -628,6 +640,8 @@ static long vhost_vdpa_unlocked_ioctl(struct file *filep, break; case VHOST_GET_BACKEND_FEATURES: features = VHOST_VDPA_BACKEND_FEATURES; + if (vhost_vdpa_can_suspend(v)) + features |= BIT_ULL(VHOST_BACKEND_F_SUSPEND); if (copy_to_user(featurep, &features, sizeof(features))) r = -EFAULT; break; diff --git a/include/uapi/linux/vhost_types.h b/include/uapi/linux/vhost_types.h index 634cee485abb..1bdd6e363f4c 100644 --- a/include/uapi/linux/vhost_types.h +++ b/include/uapi/linux/vhost_types.h @@ -161,5 +161,7 @@ struct vhost_vdpa_iova_range { * message */ #define VHOST_BACKEND_F_IOTLB_ASID 0x3 +/* Device can be suspended */ +#define VHOST_BACKEND_F_SUSPEND 0x4 #endif -- cgit v1.2.3 From f345a0143b4dd1cfc850009c6979a3801b86a06f Mon Sep 17 00:00:00 2001 From: Eugenio Pérez Date: Wed, 10 Aug 2022 19:15:11 +0200 Subject: vhost-vdpa: uAPI to suspend the device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ioctl adds support for suspending the device from userspace. This is a must before getting virtqueue indexes (base) for live migration, since the device could modify them after userland gets them. There are individual ways to perform that action for some devices (VHOST_NET_SET_BACKEND, VHOST_VSOCK_SET_RUNNING, ...) but there was no way to perform it for any vhost device (and, in particular, vhost-vdpa). After a successful return of the ioctl call the device must not process more virtqueue descriptors. The device can answer to read or writes of config fields as if it were not suspended. In particular, writing to "queue_enable" with a value of 1 will not make the device start processing buffers of the virtqueue. Signed-off-by: Eugenio Pérez Message-Id: <20220810171512.2343333-4-eperezma@redhat.com> Signed-off-by: Michael S. Tsirkin --- drivers/vhost/vdpa.c | 19 +++++++++++++++++++ include/uapi/linux/vhost.h | 9 +++++++++ 2 files changed, 28 insertions(+) diff --git a/drivers/vhost/vdpa.c b/drivers/vhost/vdpa.c index 092752fea8e1..166044642fd5 100644 --- a/drivers/vhost/vdpa.c +++ b/drivers/vhost/vdpa.c @@ -478,6 +478,22 @@ static long vhost_vdpa_get_vqs_count(struct vhost_vdpa *v, u32 __user *argp) return 0; } +/* After a successful return of ioctl the device must not process more + * virtqueue descriptors. The device can answer to read or writes of config + * fields as if it were not suspended. In particular, writing to "queue_enable" + * with a value of 1 will not make the device start processing buffers. + */ +static long vhost_vdpa_suspend(struct vhost_vdpa *v) +{ + struct vdpa_device *vdpa = v->vdpa; + const struct vdpa_config_ops *ops = vdpa->config; + + if (!ops->suspend) + return -EOPNOTSUPP; + + return ops->suspend(vdpa); +} + static long vhost_vdpa_vring_ioctl(struct vhost_vdpa *v, unsigned int cmd, void __user *argp) { @@ -654,6 +670,9 @@ static long vhost_vdpa_unlocked_ioctl(struct file *filep, case VHOST_VDPA_GET_VQS_COUNT: r = vhost_vdpa_get_vqs_count(v, argp); break; + case VHOST_VDPA_SUSPEND: + r = vhost_vdpa_suspend(v); + break; default: r = vhost_dev_ioctl(&v->vdev, cmd, argp); if (r == -ENOIOCTLCMD) diff --git a/include/uapi/linux/vhost.h b/include/uapi/linux/vhost.h index cab645d4a645..f9f115a7c75b 100644 --- a/include/uapi/linux/vhost.h +++ b/include/uapi/linux/vhost.h @@ -171,4 +171,13 @@ #define VHOST_VDPA_SET_GROUP_ASID _IOW(VHOST_VIRTIO, 0x7C, \ struct vhost_vring_state) +/* Suspend a device so it does not process virtqueue requests anymore + * + * After the return of ioctl the device must preserve all the necessary state + * (the virtqueue vring base plus the possible device specific states) that is + * required for restoring in the future. The device must not change its + * configuration after that point. + */ +#define VHOST_VDPA_SUSPEND _IO(VHOST_VIRTIO, 0x7D) + #endif -- cgit v1.2.3 From 0c89e2a3a9d0815b6eb769ed22157bd9996cbb58 Mon Sep 17 00:00:00 2001 From: Eugenio Pérez Date: Wed, 10 Aug 2022 19:15:12 +0200 Subject: vdpa_sim: Implement suspend vdpa op MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement suspend operation for vdpa_sim devices, so vhost-vdpa will offer that backend feature and userspace can effectively suspend the device. This is a must before get virtqueue indexes (base) for live migration, since the device could modify them after userland gets them. There are individual ways to perform that action for some devices (VHOST_NET_SET_BACKEND, VHOST_VSOCK_SET_RUNNING, ...) but there was no way to perform it for any vhost device (and, in particular, vhost-vdpa). Reviewed-by: Stefano Garzarella Signed-off-by: Eugenio Pérez Message-Id: <20220810171512.2343333-5-eperezma@redhat.com> Signed-off-by: Michael S. Tsirkin --- drivers/vdpa/vdpa_sim/vdpa_sim.c | 14 ++++++++++++++ drivers/vdpa/vdpa_sim/vdpa_sim.h | 1 + drivers/vdpa/vdpa_sim/vdpa_sim_blk.c | 3 +++ drivers/vdpa/vdpa_sim/vdpa_sim_net.c | 3 +++ 4 files changed, 21 insertions(+) diff --git a/drivers/vdpa/vdpa_sim/vdpa_sim.c b/drivers/vdpa/vdpa_sim/vdpa_sim.c index 3e81532c01cb..225b7f5d8be3 100644 --- a/drivers/vdpa/vdpa_sim/vdpa_sim.c +++ b/drivers/vdpa/vdpa_sim/vdpa_sim.c @@ -107,6 +107,7 @@ static void vdpasim_do_reset(struct vdpasim *vdpasim) for (i = 0; i < vdpasim->dev_attr.nas; i++) vhost_iotlb_reset(&vdpasim->iommu[i]); + vdpasim->running = true; spin_unlock(&vdpasim->iommu_lock); vdpasim->features = 0; @@ -505,6 +506,17 @@ static int vdpasim_reset(struct vdpa_device *vdpa) return 0; } +static int vdpasim_suspend(struct vdpa_device *vdpa) +{ + struct vdpasim *vdpasim = vdpa_to_sim(vdpa); + + spin_lock(&vdpasim->lock); + vdpasim->running = false; + spin_unlock(&vdpasim->lock); + + return 0; +} + static size_t vdpasim_get_config_size(struct vdpa_device *vdpa) { struct vdpasim *vdpasim = vdpa_to_sim(vdpa); @@ -694,6 +706,7 @@ static const struct vdpa_config_ops vdpasim_config_ops = { .get_status = vdpasim_get_status, .set_status = vdpasim_set_status, .reset = vdpasim_reset, + .suspend = vdpasim_suspend, .get_config_size = vdpasim_get_config_size, .get_config = vdpasim_get_config, .set_config = vdpasim_set_config, @@ -726,6 +739,7 @@ static const struct vdpa_config_ops vdpasim_batch_config_ops = { .get_status = vdpasim_get_status, .set_status = vdpasim_set_status, .reset = vdpasim_reset, + .suspend = vdpasim_suspend, .get_config_size = vdpasim_get_config_size, .get_config = vdpasim_get_config, .set_config = vdpasim_set_config, diff --git a/drivers/vdpa/vdpa_sim/vdpa_sim.h b/drivers/vdpa/vdpa_sim/vdpa_sim.h index 622782e92239..061986f30911 100644 --- a/drivers/vdpa/vdpa_sim/vdpa_sim.h +++ b/drivers/vdpa/vdpa_sim/vdpa_sim.h @@ -66,6 +66,7 @@ struct vdpasim { u32 generation; u64 features; u32 groups; + bool running; /* spinlock to synchronize iommu table */ spinlock_t iommu_lock; }; diff --git a/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c b/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c index dde965a826bb..ba253f8bce32 100644 --- a/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c +++ b/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c @@ -213,6 +213,9 @@ static void vdpasim_blk_work(struct work_struct *work) if (!(vdpasim->status & VIRTIO_CONFIG_S_DRIVER_OK)) goto out; + if (!vdpasim->running) + goto out; + for (i = 0; i < VDPASIM_BLK_VQ_NUM; i++) { struct vdpasim_virtqueue *vq = &vdpasim->vqs[i]; int reqs = 0; diff --git a/drivers/vdpa/vdpa_sim/vdpa_sim_net.c b/drivers/vdpa/vdpa_sim/vdpa_sim_net.c index 5125976a4df8..886449e88502 100644 --- a/drivers/vdpa/vdpa_sim/vdpa_sim_net.c +++ b/drivers/vdpa/vdpa_sim/vdpa_sim_net.c @@ -154,6 +154,9 @@ static void vdpasim_net_work(struct work_struct *work) spin_lock(&vdpasim->lock); + if (!vdpasim->running) + goto out; + if (!(vdpasim->status & VIRTIO_CONFIG_S_DRIVER_OK)) goto out; -- cgit v1.2.3 From b91cf6e95b4f987d0d26def0c9cca3168d7752cb Mon Sep 17 00:00:00 2001 From: Stefano Garzarella Date: Thu, 11 Aug 2022 10:36:29 +0200 Subject: vdpa_sim_blk: check if sector is 0 for commands other than read or write VIRTIO spec states: "The sector number indicates the offset (multiplied by 512) where the read or write is to occur. This field is unused and set to 0 for commands other than read or write." Signed-off-by: Stefano Garzarella Message-Id: <20220811083632.77525-2-sgarzare@redhat.com> Signed-off-by: Michael S. Tsirkin --- drivers/vdpa/vdpa_sim/vdpa_sim_blk.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c b/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c index ba253f8bce32..69c9f4f36f9a 100644 --- a/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c +++ b/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c @@ -112,6 +112,15 @@ static bool vdpasim_blk_handle_req(struct vdpasim *vdpasim, offset = sector << SECTOR_SHIFT; status = VIRTIO_BLK_S_OK; + if (type != VIRTIO_BLK_T_IN && type != VIRTIO_BLK_T_OUT && + sector != 0) { + dev_dbg(&vdpasim->vdpa.dev, + "sector must be 0 for %u request - sector: 0x%llx\n", + type, sector); + status = VIRTIO_BLK_S_IOERR; + goto err_status; + } + switch (type) { case VIRTIO_BLK_T_IN: if (!vdpasim_blk_check_range(sector, to_push)) { @@ -178,6 +187,7 @@ static bool vdpasim_blk_handle_req(struct vdpasim *vdpasim, break; } +err_status: /* If some operations fail, we need to skip the remaining bytes * to put the status in the last byte */ -- cgit v1.2.3 From ac926e1b468e03818e31568f6e520390b945b038 Mon Sep 17 00:00:00 2001 From: Stefano Garzarella Date: Thu, 11 Aug 2022 10:36:30 +0200 Subject: vdpa_sim_blk: make vdpasim_blk_check_range usable by other requests Next patches will add handling of other requests, where will be useful to reuse vdpasim_blk_check_range(). So let's make it more generic by adding the `max_sectors` parameter, since different requests allow different numbers of maximum sectors. Let's also print the messages directly in vdpasim_blk_check_range() to avoid duplicate prints. Signed-off-by: Stefano Garzarella Message-Id: <20220811083632.77525-3-sgarzare@redhat.com> Signed-off-by: Michael S. Tsirkin --- drivers/vdpa/vdpa_sim/vdpa_sim_blk.c | 38 ++++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c b/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c index 69c9f4f36f9a..24dd9cae6450 100644 --- a/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c +++ b/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c @@ -42,18 +42,28 @@ static char vdpasim_blk_id[VIRTIO_BLK_ID_BYTES] = "vdpa_blk_sim"; -static bool vdpasim_blk_check_range(u64 start_sector, size_t range_size) +static bool vdpasim_blk_check_range(struct vdpasim *vdpasim, u64 start_sector, + u64 num_sectors, u64 max_sectors) { - u64 range_sectors = range_size >> SECTOR_SHIFT; - - if (range_size > VDPASIM_BLK_SIZE_MAX * VDPASIM_BLK_SEG_MAX) - return false; + if (start_sector > VDPASIM_BLK_CAPACITY) { + dev_dbg(&vdpasim->vdpa.dev, + "starting sector exceeds the capacity - start: 0x%llx capacity: 0x%x\n", + start_sector, VDPASIM_BLK_CAPACITY); + } - if (start_sector > VDPASIM_BLK_CAPACITY) + if (num_sectors > max_sectors) { + dev_dbg(&vdpasim->vdpa.dev, + "number of sectors exceeds the max allowed in a request - num: 0x%llx max: 0x%llx\n", + num_sectors, max_sectors); return false; + } - if (range_sectors > VDPASIM_BLK_CAPACITY - start_sector) + if (num_sectors > VDPASIM_BLK_CAPACITY - start_sector) { + dev_dbg(&vdpasim->vdpa.dev, + "request exceeds the capacity - start: 0x%llx num: 0x%llx capacity: 0x%x\n", + start_sector, num_sectors, VDPASIM_BLK_CAPACITY); return false; + } return true; } @@ -123,10 +133,9 @@ static bool vdpasim_blk_handle_req(struct vdpasim *vdpasim, switch (type) { case VIRTIO_BLK_T_IN: - if (!vdpasim_blk_check_range(sector, to_push)) { - dev_dbg(&vdpasim->vdpa.dev, - "reading over the capacity - offset: 0x%llx len: 0x%zx\n", - offset, to_push); + if (!vdpasim_blk_check_range(vdpasim, sector, + to_push >> SECTOR_SHIFT, + VDPASIM_BLK_SIZE_MAX * VDPASIM_BLK_SEG_MAX)) { status = VIRTIO_BLK_S_IOERR; break; } @@ -146,10 +155,9 @@ static bool vdpasim_blk_handle_req(struct vdpasim *vdpasim, break; case VIRTIO_BLK_T_OUT: - if (!vdpasim_blk_check_range(sector, to_pull)) { - dev_dbg(&vdpasim->vdpa.dev, - "writing over the capacity - offset: 0x%llx len: 0x%zx\n", - offset, to_pull); + if (!vdpasim_blk_check_range(vdpasim, sector, + to_pull >> SECTOR_SHIFT, + VDPASIM_BLK_SIZE_MAX * VDPASIM_BLK_SEG_MAX)) { status = VIRTIO_BLK_S_IOERR; break; } -- cgit v1.2.3 From 518083d2f5b2e7c91549ac1723923e8ae3d679ca Mon Sep 17 00:00:00 2001 From: Stefano Garzarella Date: Thu, 11 Aug 2022 10:36:31 +0200 Subject: vdpa_sim_blk: add support for VIRTIO_BLK_T_FLUSH The simulator behaves like a ramdisk, so we don't have to do anything when a VIRTIO_BLK_T_FLUSH request is received, but it could be useful to test driver behavior. Let's expose the VIRTIO_BLK_F_FLUSH feature to inform the driver that we support the flush command. Signed-off-by: Stefano Garzarella Message-Id: <20220811083632.77525-4-sgarzare@redhat.com> Signed-off-by: Michael S. Tsirkin --- drivers/vdpa/vdpa_sim/vdpa_sim_blk.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c b/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c index 24dd9cae6450..1f18f336cf0c 100644 --- a/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c +++ b/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c @@ -25,6 +25,7 @@ #define DRV_LICENSE "GPL v2" #define VDPASIM_BLK_FEATURES (VDPASIM_FEATURES | \ + (1ULL << VIRTIO_BLK_F_FLUSH) | \ (1ULL << VIRTIO_BLK_F_SIZE_MAX) | \ (1ULL << VIRTIO_BLK_F_SEG_MAX) | \ (1ULL << VIRTIO_BLK_F_BLK_SIZE) | \ @@ -188,6 +189,10 @@ static bool vdpasim_blk_handle_req(struct vdpasim *vdpasim, pushed += bytes; break; + case VIRTIO_BLK_T_FLUSH: + /* nothing to do */ + break; + default: dev_dbg(&vdpasim->vdpa.dev, "Unsupported request type %d\n", type); -- cgit v1.2.3 From 4a44a5eda245453ed7bd14239c596262cb53b665 Mon Sep 17 00:00:00 2001 From: Stefano Garzarella Date: Thu, 11 Aug 2022 10:36:32 +0200 Subject: vdpa_sim_blk: add support for discard and write-zeroes Expose VIRTIO_BLK_F_DISCARD and VIRTIO_BLK_F_WRITE_ZEROES features to the drivers and handle VIRTIO_BLK_T_DISCARD and VIRTIO_BLK_T_WRITE_ZEROES requests checking ranges and flags. The simulator behaves like a ramdisk, so for VIRTIO_BLK_F_DISCARD does nothing, while for VIRTIO_BLK_T_WRITE_ZEROES sets to 0 the specified region. Signed-off-by: Stefano Garzarella Message-Id: <20220811083632.77525-5-sgarzare@redhat.com> Signed-off-by: Michael S. Tsirkin --- drivers/vdpa/vdpa_sim/vdpa_sim_blk.c | 74 +++++++++++++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 1 deletion(-) diff --git a/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c b/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c index 1f18f336cf0c..c8bfea3b7db2 100644 --- a/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c +++ b/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c @@ -30,11 +30,14 @@ (1ULL << VIRTIO_BLK_F_SEG_MAX) | \ (1ULL << VIRTIO_BLK_F_BLK_SIZE) | \ (1ULL << VIRTIO_BLK_F_TOPOLOGY) | \ - (1ULL << VIRTIO_BLK_F_MQ)) + (1ULL << VIRTIO_BLK_F_MQ) | \ + (1ULL << VIRTIO_BLK_F_DISCARD) | \ + (1ULL << VIRTIO_BLK_F_WRITE_ZEROES)) #define VDPASIM_BLK_CAPACITY 0x40000 #define VDPASIM_BLK_SIZE_MAX 0x1000 #define VDPASIM_BLK_SEG_MAX 32 +#define VDPASIM_BLK_DWZ_MAX_SECTORS UINT_MAX /* 1 virtqueue, 1 address space, 1 virtqueue group */ #define VDPASIM_BLK_VQ_NUM 1 @@ -193,6 +196,64 @@ static bool vdpasim_blk_handle_req(struct vdpasim *vdpasim, /* nothing to do */ break; + case VIRTIO_BLK_T_DISCARD: + case VIRTIO_BLK_T_WRITE_ZEROES: { + struct virtio_blk_discard_write_zeroes range; + u32 num_sectors, flags; + + if (to_pull != sizeof(range)) { + dev_dbg(&vdpasim->vdpa.dev, + "discard/write_zeroes header len: 0x%zx [expected: 0x%zx]\n", + to_pull, sizeof(range)); + status = VIRTIO_BLK_S_IOERR; + break; + } + + bytes = vringh_iov_pull_iotlb(&vq->vring, &vq->out_iov, &range, + to_pull); + if (bytes < 0) { + dev_dbg(&vdpasim->vdpa.dev, + "vringh_iov_pull_iotlb() error: %zd offset: 0x%llx len: 0x%zx\n", + bytes, offset, to_pull); + status = VIRTIO_BLK_S_IOERR; + break; + } + + sector = le64_to_cpu(range.sector); + offset = sector << SECTOR_SHIFT; + num_sectors = le32_to_cpu(range.num_sectors); + flags = le32_to_cpu(range.flags); + + if (type == VIRTIO_BLK_T_DISCARD && flags != 0) { + dev_dbg(&vdpasim->vdpa.dev, + "discard unexpected flags set - flags: 0x%x\n", + flags); + status = VIRTIO_BLK_S_UNSUPP; + break; + } + + if (type == VIRTIO_BLK_T_WRITE_ZEROES && + flags & ~VIRTIO_BLK_WRITE_ZEROES_FLAG_UNMAP) { + dev_dbg(&vdpasim->vdpa.dev, + "write_zeroes unexpected flags set - flags: 0x%x\n", + flags); + status = VIRTIO_BLK_S_UNSUPP; + break; + } + + if (!vdpasim_blk_check_range(vdpasim, sector, num_sectors, + VDPASIM_BLK_DWZ_MAX_SECTORS)) { + status = VIRTIO_BLK_S_IOERR; + break; + } + + if (type == VIRTIO_BLK_T_WRITE_ZEROES) { + memset(vdpasim->buffer + offset, 0, + num_sectors << SECTOR_SHIFT); + } + + break; + } default: dev_dbg(&vdpasim->vdpa.dev, "Unsupported request type %d\n", type); @@ -281,6 +342,17 @@ static void vdpasim_blk_get_config(struct vdpasim *vdpasim, void *config) blk_config->min_io_size = cpu_to_vdpasim16(vdpasim, 1); blk_config->opt_io_size = cpu_to_vdpasim32(vdpasim, 1); blk_config->blk_size = cpu_to_vdpasim32(vdpasim, SECTOR_SIZE); + /* VIRTIO_BLK_F_DISCARD */ + blk_config->discard_sector_alignment = + cpu_to_vdpasim32(vdpasim, SECTOR_SIZE); + blk_config->max_discard_sectors = + cpu_to_vdpasim32(vdpasim, VDPASIM_BLK_DWZ_MAX_SECTORS); + blk_config->max_discard_seg = cpu_to_vdpasim32(vdpasim, 1); + /* VIRTIO_BLK_F_WRITE_ZEROES */ + blk_config->max_write_zeroes_sectors = + cpu_to_vdpasim32(vdpasim, VDPASIM_BLK_DWZ_MAX_SECTORS); + blk_config->max_write_zeroes_seg = cpu_to_vdpasim32(vdpasim, 1); + } static void vdpasim_blk_mgmtdev_release(struct device *dev) -- cgit v1.2.3 From f37527a09dac324c74bb341c841096395a2f2566 Mon Sep 17 00:00:00 2001 From: "Dennis P. Kliem" Date: Thu, 11 Aug 2022 12:56:57 +0200 Subject: nvme-pci: add NVME_QUIRK_BOGUS_NID for ADATA XPG GAMMIX S70 ADATA XPG GAMMIX S70 reports bogus eui64 values that appear to be the same across all drives. Quirk them out so they are not marked as "non globally unique" duplicates. Signed-off-by: Dennis P. Kliem Signed-off-by: Christoph Hellwig --- drivers/nvme/host/pci.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c index 71a4f26ba476..a222caa1ab00 100644 --- a/drivers/nvme/host/pci.c +++ b/drivers/nvme/host/pci.c @@ -3516,6 +3516,8 @@ static const struct pci_device_id nvme_id_table[] = { .driver_data = NVME_QUIRK_BOGUS_NID, }, { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */ .driver_data = NVME_QUIRK_BOGUS_NID, }, + { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */ + .driver_data = NVME_QUIRK_BOGUS_NID, }, { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */ .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */ -- cgit v1.2.3 From 8689b80b22dbf1f5e993233370fe57f08731b14d Mon Sep 17 00:00:00 2001 From: Robin Reckmann Date: Sun, 7 Aug 2022 23:04:54 +0900 Subject: i2c: qcom-geni: Fix GPI DMA buffer sync-back Fix i2c transfers using GPI DMA mode for all message types that do not set the I2C_M_DMA_SAFE flag (e.g. SMBus "read byte"). In this case a bounce buffer is returned by i2c_get_dma_safe_msg_buf(), and it has to synced back to the message after the transfer is done. Add missing assignment of dma buffer in geni_i2c_gpi(). Set xferred in i2c_put_dma_safe_msg_buf() to true in case of no error to ensure the sync-back of this dma buffer to the message. Fixes: d8703554f4de ("i2c: qcom-geni: Add support for GPI DMA") Signed-off-by: Robin Reckmann Tested-by: Luca Weiss Tested-by: Caleb Connolly Reviewed-by: Konrad Dybcio Signed-off-by: Wolfram Sang --- drivers/i2c/busses/i2c-qcom-geni.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c index 6ac179a373ff..1bef67fe4b25 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -494,12 +494,12 @@ static void geni_i2c_gpi_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, { if (tx_buf) { dma_unmap_single(gi2c->se.dev->parent, tx_addr, msg->len, DMA_TO_DEVICE); - i2c_put_dma_safe_msg_buf(tx_buf, msg, false); + i2c_put_dma_safe_msg_buf(tx_buf, msg, !gi2c->err); } if (rx_buf) { dma_unmap_single(gi2c->se.dev->parent, rx_addr, msg->len, DMA_FROM_DEVICE); - i2c_put_dma_safe_msg_buf(rx_buf, msg, false); + i2c_put_dma_safe_msg_buf(rx_buf, msg, !gi2c->err); } } @@ -563,6 +563,7 @@ static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, desc->callback_param = gi2c; dmaengine_submit(desc); + *buf = dma_buf; *dma_addr_p = addr; return 0; -- cgit v1.2.3 From 0a0b80a44c7d111a0404d91847db57be8b667a15 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Aug 2022 17:39:47 +0200 Subject: dt-bindings: i2c: qcom,i2c-cci: convert to dtschema Convert the Qualcomm Camera Control Interface (CCI) I2C controller to DT schema. The original bindings were not complete, so this includes changes: 1. Add address/size-cells. 2. Describe the clocks per variant. 3. Use more descriptive example based on sdm845. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Wolfram Sang --- .../devicetree/bindings/i2c/i2c-qcom-cci.txt | 96 -------- .../devicetree/bindings/i2c/qcom,i2c-cci.yaml | 242 +++++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 243 insertions(+), 97 deletions(-) delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt create mode 100644 Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml diff --git a/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt b/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt deleted file mode 100644 index 166865e48849..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt +++ /dev/null @@ -1,96 +0,0 @@ -Qualcomm Camera Control Interface (CCI) I2C controller - -PROPERTIES: - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,msm8916-cci" - "qcom,msm8974-cci" - "qcom,msm8996-cci" - "qcom,sdm845-cci" - "qcom,sm8250-cci" - "qcom,sm8450-cci" - -- reg - Usage: required - Value type: - Definition: base address CCI I2C controller and length of memory - mapped region. - -- interrupts: - Usage: required - Value type: - Definition: specifies the CCI I2C interrupt. The format of the - specifier is defined by the binding document describing - the node's interrupt parent. - -- clocks: - Usage: required - Value type: - Definition: a list of phandle, should contain an entry for each - entries in clock-names. - -- clock-names - Usage: required - Value type: - Definition: a list of clock names, must include "cci" clock. - -- power-domains - Usage: required for "qcom,msm8996-cci" - Value type: - Definition: - -SUBNODES: - -The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8974, -msm8996, sdm845, sm8250 and sm8450), described as subdevices named "i2c-bus@0" -and "i2c-bus@1". - -PROPERTIES: - -- reg: - Usage: required - Value type: - Definition: Index of the CCI bus/master - -- clock-frequency: - Usage: optional - Value type: - Definition: Desired I2C bus clock frequency in Hz, defaults to 100 - kHz if omitted. - -Example: - - cci@a0c000 { - compatible = "qcom,msm8996-cci"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xa0c000 0x1000>; - interrupts = ; - clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>, - <&mmcc CAMSS_TOP_AHB_CLK>, - <&mmcc CAMSS_CCI_AHB_CLK>, - <&mmcc CAMSS_CCI_CLK>, - <&mmcc CAMSS_AHB_CLK>; - clock-names = "mmss_mmagic_ahb", - "camss_top_ahb", - "cci_ahb", - "cci", - "camss_ahb"; - - i2c-bus@0 { - reg = <0>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c-bus@1 { - reg = <1>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml new file mode 100644 index 000000000000..90c9e401229e --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -0,0 +1,242 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/qcom,i2c-cci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Control Interface (CCI) I2C controller + +maintainers: + - Loic Poulain + - Robert Foss + +properties: + compatible: + enum: + - qcom,msm8916-cci + - qcom,msm8974-cci + - qcom,msm8996-cci + - qcom,sdm845-cci + - qcom,sm8250-cci + - qcom,sm8450-cci + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + clocks: + minItems: 4 + maxItems: 6 + + clock-names: + minItems: 4 + maxItems: 6 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + reg: + maxItems: 1 + +patternProperties: + "^i2c-bus@[01]$": + $ref: /schemas/i2c/i2c-controller.yaml# + unevaluatedProperties: false + + properties: + reg: + maxItems: 1 + + clock-frequency: + default: 100000 + +required: + - compatible + - clock-names + - clocks + - interrupts + - reg + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8996-cci + then: + required: + - power-domains + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8916-cci + then: + properties: + i2c-bus@1: false + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8916-cci + - qcom,msm8996-cci + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: camss_top_ahb + - const: cci_ahb + - const: cci + - const: camss_ahb + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-cci + then: + properties: + clocks: + minItems: 6 + clock-names: + items: + - const: camnoc_axi + - const: soc_ahb + - const: slow_ahb_src + - const: cpas_ahb + - const: cci + - const: cci_src + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8250-cci + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + clock-names: + items: + - const: camnoc_axi + - const: slow_ahb_src + - const: cpas_ahb + - const: cci + - const: cci_src + +additionalProperties: false + +examples: + - | + #include + #include + #include + + cci@ac4a000 { + reg = <0x0ac4a000 0x4000>; + compatible = "qcom,sdm845-cci"; + #address-cells = <1>; + #size-cells = <0>; + + interrupts = ; + power-domains = <&clock_camcc TITAN_TOP_GDSC>; + + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CCI_CLK>, + <&clock_camcc CAM_CC_CCI_CLK_SRC>; + clock-names = "camnoc_axi", + "soc_ahb", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_CCI_CLK>; + assigned-clock-rates = <80000000>, + <37500000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-1 = <&cci0_sleep &cci1_sleep>; + + i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + + camera@10 { + compatible = "ovti,ov8856"; + reg = <0x10>; + + reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_default>; + + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "xvclk"; + clock-frequency = <19200000>; + + dovdd-supply = <&vreg_lvs1a_1p8>; + avdd-supply = <&cam0_avdd_2v8>; + dvdd-supply = <&cam0_dvdd_1v2>; + + port { + ov8856_ep: endpoint { + link-frequencies = /bits/ 64 <360000000 180000000>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csiphy0_ep>; + }; + }; + }; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + + camera@60 { + compatible = "ovti,ov7251"; + reg = <0x60>; + + enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam3_default>; + + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "xclk"; + clock-frequency = <24000000>; + + vdddo-supply = <&vreg_lvs1a_1p8>; + vdda-supply = <&cam3_avdd_2v8>; + + port { + ov7251_ep: endpoint { + data-lanes = <0 1>; + remote-endpoint = <&csiphy3_ep>; + }; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 9b6c0f0bda14..67a6c6d06aa9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16879,7 +16879,7 @@ M: Robert Foss L: linux-i2c@vger.kernel.org L: linux-arm-msm@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt +F: Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml F: drivers/i2c/busses/i2c-qcom-cci.c QUALCOMM INTERCONNECT BWMON DRIVER -- cgit v1.2.3 From dde61c48303afae6d5db50fc2c9f7199413945e5 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Fri, 5 Aug 2022 08:43:46 +0100 Subject: i2c: microchip-corei2c: fix erroneous late ack send A late ack is currently being sent at the end of a transfer due to incorrect logic in mchp_corei2c_empty_rx(). Currently the Assert Ack bit is being written to the controller's control reg after the last byte has been received, causing it to sent another byte with the ack. Instead, the AA flag should be written to the control register when the penultimate byte is read so it is sent out for the last byte. Reported-by: Andreas Buerkler Fixes: 64a6f1c4987e ("i2c: add support for microchip fpga i2c controllers") Tested-by: Lewis Hanly Signed-off-by: Conor Dooley [wsa: fixed typos in commit message] Signed-off-by: Wolfram Sang --- drivers/i2c/busses/i2c-microchip-corei2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-microchip-corei2c.c b/drivers/i2c/busses/i2c-microchip-corei2c.c index 6df0f1c33278..4d7e9b25f018 100644 --- a/drivers/i2c/busses/i2c-microchip-corei2c.c +++ b/drivers/i2c/busses/i2c-microchip-corei2c.c @@ -206,7 +206,7 @@ static void mchp_corei2c_empty_rx(struct mchp_corei2c_dev *idev) idev->msg_len--; } - if (idev->msg_len == 0) { + if (idev->msg_len <= 1) { ctrl = readb(idev->base + CORE_I2C_CTRL); ctrl &= ~CTRL_AA; writeb(ctrl, idev->base + CORE_I2C_CTRL); -- cgit v1.2.3 From 93e530d2a1c4c0fcce45e01ae6c5c6287a08d3e3 Mon Sep 17 00:00:00 2001 From: Eli Cohen Date: Thu, 11 Aug 2022 16:40:10 +0300 Subject: vdpa/mlx5: Fix possible uninitialized return value Initialize err local variable to return -EAGAIN if the asid cannot be found thus avoiding returning uninitialized value. Fixes: 8fcd20c30704 ("vdpa/mlx5: Support different address spaces for control and data") Reported-by: Dan Carpenter Signed-off-by: Eli Cohen Message-Id: <20220811134010.952291-1-elic@nvidia.com> Signed-off-by: Michael S. Tsirkin --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index 289cf91b1ff5..ed100a35e596 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -2659,7 +2659,7 @@ static int mlx5_vdpa_set_map(struct vdpa_device *vdev, unsigned int asid, { struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev); struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev); - int err; + int err = -EINVAL; down_write(&ndev->reslock); if (mvdev->group2asid[MLX5_VDPA_DATAVQ_GROUP] == asid) { -- cgit v1.2.3 From a664375da76c6da8f83dc7997e43c568e1eb9a6a Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Tue, 9 Aug 2022 15:16:32 +0200 Subject: netfilter: nf_ct_sane: remove pseudo skb linearization For historical reason this code performs pseudo linearization of skbs via skb_header_pointer and a global 64k buffer. With arrival of BIG TCP, packets generated by TCP stack can exceed 64kb. Rewrite this to only extract the needed header data. This also allows to get rid of the locking. Fixes: 7c4e983c4f3c ("net: allow gso_max_size to exceed 65536") Fixes: 0fe79f28bfaf ("net: allow gro_max_size to exceed 65536") Signed-off-by: Florian Westphal Signed-off-by: Pablo Neira Ayuso --- net/netfilter/nf_conntrack_sane.c | 68 +++++++++++++++++---------------------- 1 file changed, 30 insertions(+), 38 deletions(-) diff --git a/net/netfilter/nf_conntrack_sane.c b/net/netfilter/nf_conntrack_sane.c index fcb33b1d5456..13dc421fc4f5 100644 --- a/net/netfilter/nf_conntrack_sane.c +++ b/net/netfilter/nf_conntrack_sane.c @@ -34,10 +34,6 @@ MODULE_AUTHOR("Michal Schmidt "); MODULE_DESCRIPTION("SANE connection tracking helper"); MODULE_ALIAS_NFCT_HELPER(HELPER_NAME); -static char *sane_buffer; - -static DEFINE_SPINLOCK(nf_sane_lock); - #define MAX_PORTS 8 static u_int16_t ports[MAX_PORTS]; static unsigned int ports_c; @@ -67,14 +63,16 @@ static int help(struct sk_buff *skb, unsigned int dataoff, datalen; const struct tcphdr *th; struct tcphdr _tcph; - void *sb_ptr; int ret = NF_ACCEPT; int dir = CTINFO2DIR(ctinfo); struct nf_ct_sane_master *ct_sane_info = nfct_help_data(ct); struct nf_conntrack_expect *exp; struct nf_conntrack_tuple *tuple; - struct sane_request *req; struct sane_reply_net_start *reply; + union { + struct sane_request req; + struct sane_reply_net_start repl; + } buf; /* Until there's been traffic both ways, don't look in packets. */ if (ctinfo != IP_CT_ESTABLISHED && @@ -92,59 +90,62 @@ static int help(struct sk_buff *skb, return NF_ACCEPT; datalen = skb->len - dataoff; - - spin_lock_bh(&nf_sane_lock); - sb_ptr = skb_header_pointer(skb, dataoff, datalen, sane_buffer); - if (!sb_ptr) { - spin_unlock_bh(&nf_sane_lock); - return NF_ACCEPT; - } - if (dir == IP_CT_DIR_ORIGINAL) { + const struct sane_request *req; + if (datalen != sizeof(struct sane_request)) - goto out; + return NF_ACCEPT; + + req = skb_header_pointer(skb, dataoff, datalen, &buf.req); + if (!req) + return NF_ACCEPT; - req = sb_ptr; if (req->RPC_code != htonl(SANE_NET_START)) { /* Not an interesting command */ - ct_sane_info->state = SANE_STATE_NORMAL; - goto out; + WRITE_ONCE(ct_sane_info->state, SANE_STATE_NORMAL); + return NF_ACCEPT; } /* We're interested in the next reply */ - ct_sane_info->state = SANE_STATE_START_REQUESTED; - goto out; + WRITE_ONCE(ct_sane_info->state, SANE_STATE_START_REQUESTED); + return NF_ACCEPT; } + /* IP_CT_DIR_REPLY */ + /* Is it a reply to an uninteresting command? */ - if (ct_sane_info->state != SANE_STATE_START_REQUESTED) - goto out; + if (READ_ONCE(ct_sane_info->state) != SANE_STATE_START_REQUESTED) + return NF_ACCEPT; /* It's a reply to SANE_NET_START. */ - ct_sane_info->state = SANE_STATE_NORMAL; + WRITE_ONCE(ct_sane_info->state, SANE_STATE_NORMAL); if (datalen < sizeof(struct sane_reply_net_start)) { pr_debug("NET_START reply too short\n"); - goto out; + return NF_ACCEPT; } - reply = sb_ptr; + datalen = sizeof(struct sane_reply_net_start); + + reply = skb_header_pointer(skb, dataoff, datalen, &buf.repl); + if (!reply) + return NF_ACCEPT; + if (reply->status != htonl(SANE_STATUS_SUCCESS)) { /* saned refused the command */ pr_debug("unsuccessful SANE_STATUS = %u\n", ntohl(reply->status)); - goto out; + return NF_ACCEPT; } /* Invalid saned reply? Ignore it. */ if (reply->zero != 0) - goto out; + return NF_ACCEPT; exp = nf_ct_expect_alloc(ct); if (exp == NULL) { nf_ct_helper_log(skb, ct, "cannot alloc expectation"); - ret = NF_DROP; - goto out; + return NF_DROP; } tuple = &ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple; @@ -162,9 +163,6 @@ static int help(struct sk_buff *skb, } nf_ct_expect_put(exp); - -out: - spin_unlock_bh(&nf_sane_lock); return ret; } @@ -178,7 +176,6 @@ static const struct nf_conntrack_expect_policy sane_exp_policy = { static void __exit nf_conntrack_sane_fini(void) { nf_conntrack_helpers_unregister(sane, ports_c * 2); - kfree(sane_buffer); } static int __init nf_conntrack_sane_init(void) @@ -187,10 +184,6 @@ static int __init nf_conntrack_sane_init(void) NF_CT_HELPER_BUILD_BUG_ON(sizeof(struct nf_ct_sane_master)); - sane_buffer = kmalloc(65536, GFP_KERNEL); - if (!sane_buffer) - return -ENOMEM; - if (ports_c == 0) ports[ports_c++] = SANE_PORT; @@ -210,7 +203,6 @@ static int __init nf_conntrack_sane_init(void) ret = nf_conntrack_helpers_register(sane, ports_c * 2); if (ret < 0) { pr_err("failed to register helpers\n"); - kfree(sane_buffer); return ret; } -- cgit v1.2.3 From f3e124c36f70d5ffcdd4e8bdbe7bb28a98a715c0 Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Tue, 9 Aug 2022 15:16:33 +0200 Subject: netfilter: nf_ct_h323: cap packet size at 64k With BIG TCP, packets generated by tcp stack may exceed 64kb. Cap datalen at 64kb. The internal message format uses 16bit fields, so no embedded message can exceed 64k size. Multiple h323 messages in a single superpacket may now result in a message to get treated as incomplete/truncated, but thats better than scribbling past h323_buffer. Another alternative suitable for net tree would be a switch to skb_linearize(). Fixes: 7c4e983c4f3c ("net: allow gso_max_size to exceed 65536") Fixes: 0fe79f28bfaf ("net: allow gro_max_size to exceed 65536") Signed-off-by: Florian Westphal Signed-off-by: Pablo Neira Ayuso --- net/netfilter/nf_conntrack_h323_main.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/net/netfilter/nf_conntrack_h323_main.c b/net/netfilter/nf_conntrack_h323_main.c index bb76305bb7ff..5a9bce24f3c3 100644 --- a/net/netfilter/nf_conntrack_h323_main.c +++ b/net/netfilter/nf_conntrack_h323_main.c @@ -34,6 +34,8 @@ #include #include +#define H323_MAX_SIZE 65535 + /* Parameters */ static unsigned int default_rrq_ttl __read_mostly = 300; module_param(default_rrq_ttl, uint, 0600); @@ -86,6 +88,9 @@ static int get_tpkt_data(struct sk_buff *skb, unsigned int protoff, if (tcpdatalen <= 0) /* No TCP data */ goto clear_out; + if (tcpdatalen > H323_MAX_SIZE) + tcpdatalen = H323_MAX_SIZE; + if (*data == NULL) { /* first TPKT */ /* Get first TPKT pointer */ tpkt = skb_header_pointer(skb, tcpdataoff, tcpdatalen, @@ -1169,6 +1174,9 @@ static unsigned char *get_udp_data(struct sk_buff *skb, unsigned int protoff, if (dataoff >= skb->len) return NULL; *datalen = skb->len - dataoff; + if (*datalen > H323_MAX_SIZE) + *datalen = H323_MAX_SIZE; + return skb_header_pointer(skb, dataoff, *datalen, h323_buffer); } @@ -1770,7 +1778,7 @@ static int __init nf_conntrack_h323_init(void) NF_CT_HELPER_BUILD_BUG_ON(sizeof(struct nf_ct_h323_master)); - h323_buffer = kmalloc(65536, GFP_KERNEL); + h323_buffer = kmalloc(H323_MAX_SIZE + 1, GFP_KERNEL); if (!h323_buffer) return -ENOMEM; ret = h323_helper_init(); -- cgit v1.2.3 From c783a29c7e5934eabac2b760571489ad83bf4fd1 Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Tue, 9 Aug 2022 15:16:34 +0200 Subject: netfilter: nf_ct_ftp: prefer skb_linearize This uses a pseudo-linearization scheme with a 64k global buffer, but BIG TCP arrival means IPv6 TCP stack can generate skbs that exceed this size. Use skb_linearize. It should be possible to rewrite this to properly deal with segmented skbs (i.e., only do small chunk-wise accesses), but this is going to be a lot more intrusive than this because every helper function needs to get the sk_buff instead of a pointer to a raw data buffer. In practice, provided we're really looking at FTP control channel packets, there should never be a case where we deal with huge packets. Fixes: 7c4e983c4f3c ("net: allow gso_max_size to exceed 65536") Fixes: 0fe79f28bfaf ("net: allow gro_max_size to exceed 65536") Signed-off-by: Florian Westphal Signed-off-by: Pablo Neira Ayuso --- net/netfilter/nf_conntrack_ftp.c | 24 ++++++------------------ 1 file changed, 6 insertions(+), 18 deletions(-) diff --git a/net/netfilter/nf_conntrack_ftp.c b/net/netfilter/nf_conntrack_ftp.c index a414274338cf..0d9332e9cf71 100644 --- a/net/netfilter/nf_conntrack_ftp.c +++ b/net/netfilter/nf_conntrack_ftp.c @@ -34,11 +34,6 @@ MODULE_DESCRIPTION("ftp connection tracking helper"); MODULE_ALIAS("ip_conntrack_ftp"); MODULE_ALIAS_NFCT_HELPER(HELPER_NAME); -/* This is slow, but it's simple. --RR */ -static char *ftp_buffer; - -static DEFINE_SPINLOCK(nf_ftp_lock); - #define MAX_PORTS 8 static u_int16_t ports[MAX_PORTS]; static unsigned int ports_c; @@ -398,6 +393,9 @@ static int help(struct sk_buff *skb, return NF_ACCEPT; } + if (unlikely(skb_linearize(skb))) + return NF_DROP; + th = skb_header_pointer(skb, protoff, sizeof(_tcph), &_tcph); if (th == NULL) return NF_ACCEPT; @@ -411,12 +409,8 @@ static int help(struct sk_buff *skb, } datalen = skb->len - dataoff; - spin_lock_bh(&nf_ftp_lock); - fb_ptr = skb_header_pointer(skb, dataoff, datalen, ftp_buffer); - if (!fb_ptr) { - spin_unlock_bh(&nf_ftp_lock); - return NF_ACCEPT; - } + spin_lock_bh(&ct->lock); + fb_ptr = skb->data + dataoff; ends_in_nl = (fb_ptr[datalen - 1] == '\n'); seq = ntohl(th->seq) + datalen; @@ -544,7 +538,7 @@ out_update_nl: if (ends_in_nl) update_nl_seq(ct, seq, ct_ftp_info, dir, skb); out: - spin_unlock_bh(&nf_ftp_lock); + spin_unlock_bh(&ct->lock); return ret; } @@ -571,7 +565,6 @@ static const struct nf_conntrack_expect_policy ftp_exp_policy = { static void __exit nf_conntrack_ftp_fini(void) { nf_conntrack_helpers_unregister(ftp, ports_c * 2); - kfree(ftp_buffer); } static int __init nf_conntrack_ftp_init(void) @@ -580,10 +573,6 @@ static int __init nf_conntrack_ftp_init(void) NF_CT_HELPER_BUILD_BUG_ON(sizeof(struct nf_ct_ftp_master)); - ftp_buffer = kmalloc(65536, GFP_KERNEL); - if (!ftp_buffer) - return -ENOMEM; - if (ports_c == 0) ports[ports_c++] = FTP_PORT; @@ -603,7 +592,6 @@ static int __init nf_conntrack_ftp_init(void) ret = nf_conntrack_helpers_register(ftp, ports_c * 2); if (ret < 0) { pr_err("failed to register helpers\n"); - kfree(ftp_buffer); return ret; } -- cgit v1.2.3 From 976bf59c69cd2e2c17f0ab20a14c0e700cba0f15 Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Tue, 9 Aug 2022 15:16:35 +0200 Subject: netfilter: nf_ct_irc: cap packet search space to 4k This uses a pseudo-linearization scheme with a 64k global buffer, but BIG TCP arrival means IPv6 TCP stack can generate skbs that exceed this size. In practice, IRC commands are not expected to exceed 512 bytes, plus this is interactive protocol, so we should not see large packets in practice. Given most IRC connections nowadays use TLS so this helper could also be removed in the near future. Fixes: 7c4e983c4f3c ("net: allow gso_max_size to exceed 65536") Fixes: 0fe79f28bfaf ("net: allow gro_max_size to exceed 65536") Signed-off-by: Florian Westphal Signed-off-by: Pablo Neira Ayuso --- net/netfilter/nf_conntrack_irc.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/net/netfilter/nf_conntrack_irc.c b/net/netfilter/nf_conntrack_irc.c index 08ee4e760a3d..1796c456ac98 100644 --- a/net/netfilter/nf_conntrack_irc.c +++ b/net/netfilter/nf_conntrack_irc.c @@ -39,6 +39,7 @@ unsigned int (*nf_nat_irc_hook)(struct sk_buff *skb, EXPORT_SYMBOL_GPL(nf_nat_irc_hook); #define HELPER_NAME "irc" +#define MAX_SEARCH_SIZE 4095 MODULE_AUTHOR("Harald Welte "); MODULE_DESCRIPTION("IRC (DCC) connection tracking helper"); @@ -121,6 +122,7 @@ static int help(struct sk_buff *skb, unsigned int protoff, int i, ret = NF_ACCEPT; char *addr_beg_p, *addr_end_p; typeof(nf_nat_irc_hook) nf_nat_irc; + unsigned int datalen; /* If packet is coming from IRC server */ if (dir == IP_CT_DIR_REPLY) @@ -140,8 +142,12 @@ static int help(struct sk_buff *skb, unsigned int protoff, if (dataoff >= skb->len) return NF_ACCEPT; + datalen = skb->len - dataoff; + if (datalen > MAX_SEARCH_SIZE) + datalen = MAX_SEARCH_SIZE; + spin_lock_bh(&irc_buffer_lock); - ib_ptr = skb_header_pointer(skb, dataoff, skb->len - dataoff, + ib_ptr = skb_header_pointer(skb, dataoff, datalen, irc_buffer); if (!ib_ptr) { spin_unlock_bh(&irc_buffer_lock); @@ -149,7 +155,7 @@ static int help(struct sk_buff *skb, unsigned int protoff, } data = ib_ptr; - data_limit = ib_ptr + skb->len - dataoff; + data_limit = ib_ptr + datalen; /* strlen("\1DCC SENT t AAAAAAAA P\1\n")=24 * 5+MINMATCHLEN+strlen("t AAAAAAAA P\1\n")=14 */ @@ -251,7 +257,7 @@ static int __init nf_conntrack_irc_init(void) irc_exp_policy.max_expected = max_dcc_channels; irc_exp_policy.timeout = dcc_timeout; - irc_buffer = kmalloc(65536, GFP_KERNEL); + irc_buffer = kmalloc(MAX_SEARCH_SIZE + 1, GFP_KERNEL); if (!irc_buffer) return -ENOMEM; -- cgit v1.2.3 From 8eb060e10185cfc97ef0200d197ec246ba0f9f8c Mon Sep 17 00:00:00 2001 From: Dao Lu Date: Mon, 20 Jun 2022 13:15:25 -0700 Subject: arch/riscv: add Zihintpause support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement support for the ZiHintPause extension. The PAUSE instruction is a HINT that indicates the current hart’s rate of instruction retirement should be temporarily reduced or paused. Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Signed-off-by: Dao Lu [Palmer: Some minor merge conflicts.] Link: https://lore.kernel.org/all/20220620201530.3929352-1-daolu@rivosinc.com/ Link: https://lore.kernel.org/all/20220811053356.17375-1-palmer@rivosinc.com/ Signed-off-by: Palmer Dabbelt --- arch/riscv/Makefile | 4 ++++ arch/riscv/include/asm/hwcap.h | 5 +++++ arch/riscv/include/asm/vdso/processor.h | 21 ++++++++++++++++++--- arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 1 + 5 files changed, 29 insertions(+), 3 deletions(-) diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 42d7ff8730aa..3fa8ef336822 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -60,6 +60,10 @@ riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei toolchain-supports-zicbom := $(call cc-option-yn, -march=$(riscv-march-y)_zicbom) riscv-march-$(toolchain-supports-zicbom) := $(riscv-march-y)_zicbom +# Check if the toolchain supports Zihintpause extension +toolchain-supports-zihintpause := $(call cc-option-yn, -march=$(riscv-march-y)_zihintpause) +riscv-march-$(toolchain-supports-zihintpause) := $(riscv-march-y)_zihintpause + KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) KBUILD_AFLAGS += -march=$(riscv-march-y) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index ed4045e70f7a..3c8a5ca95c72 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -8,6 +8,7 @@ #ifndef _ASM_RISCV_HWCAP_H #define _ASM_RISCV_HWCAP_H +#include #include #include @@ -55,6 +56,7 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, RISCV_ISA_EXT_SVPBMT, RISCV_ISA_EXT_ZICBOM, + RISCV_ISA_EXT_ZIHINTPAUSE, RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; @@ -65,6 +67,7 @@ enum riscv_isa_ext_id { */ enum riscv_isa_ext_key { RISCV_ISA_EXT_KEY_FPU, /* For 'F' and 'D' */ + RISCV_ISA_EXT_KEY_ZIHINTPAUSE, RISCV_ISA_EXT_KEY_MAX, }; @@ -84,6 +87,8 @@ static __always_inline int riscv_isa_ext2key(int num) return RISCV_ISA_EXT_KEY_FPU; case RISCV_ISA_EXT_d: return RISCV_ISA_EXT_KEY_FPU; + case RISCV_ISA_EXT_ZIHINTPAUSE: + return RISCV_ISA_EXT_KEY_ZIHINTPAUSE; default: return -EINVAL; } diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h index 134388cbaaa1..1e4f8b4aef79 100644 --- a/arch/riscv/include/asm/vdso/processor.h +++ b/arch/riscv/include/asm/vdso/processor.h @@ -4,15 +4,30 @@ #ifndef __ASSEMBLY__ +#include #include +#include static inline void cpu_relax(void) { + if (!static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_ZIHINTPAUSE])) { #ifdef __riscv_muldiv - int dummy; - /* In lieu of a halt instruction, induce a long-latency stall. */ - __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); + int dummy; + /* In lieu of a halt instruction, induce a long-latency stall. */ + __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); #endif + } else { + /* + * Reduce instruction retirement. + * This assumes the PC changes. + */ +#ifdef __riscv_zihintpause + __asm__ __volatile__ ("pause"); +#else + /* Encoding of the pause instruction */ + __asm__ __volatile__ (".4byte 0x100000F"); +#endif + } barrier(); } diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 76a2a225e3d9..a77c380703c5 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -94,6 +94,7 @@ static struct riscv_isa_ext_data isa_ext_arr[] = { __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), + __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), }; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index f914e8da157a..c233fbc5b873 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -202,6 +202,7 @@ void __init riscv_fill_hwcap(void) SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); + SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); } #undef SET_ISA_EXT_MAP } -- cgit v1.2.3 From e3a7c2947b9e01b9cedd3f67849c0ae95f0fadfa Mon Sep 17 00:00:00 2001 From: Mikulas Patocka Date: Wed, 10 Aug 2022 16:16:34 -0400 Subject: dm bufio: fix some cases where the code sleeps with spinlock held Commit b32d45824aa7 ("dm bufio: Add DM_BUFIO_CLIENT_NO_SLEEP flag") added a "NO_SLEEP" mode, it replaces a mutex with a spinlock, and it is only usable when the device is in read-only mode (because the write path may be sleeping while holding the dm_bufio_client lock). However, there are still two points where the code could sleep even in read-only mode. One is in __get_unclaimed_buffer -> __make_buffer_clean. The other is in __try_evict_buffer -> __make_buffer_clean. These functions will call __make_buffer_clean which sleeps if the buffer is being read. Fix these cases so that if c->no_sleep is set __make_buffer_clean will not be called and the buffer will be skipped instead. Fixes: b32d45824aa7 ("dm bufio: Add DM_BUFIO_CLIENT_NO_SLEEP flag") Signed-off-by: Mikulas Patocka Signed-off-by: Mike Snitzer --- drivers/md/dm-bufio.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/md/dm-bufio.c b/drivers/md/dm-bufio.c index bef8c6eb5bdb..799915220e6c 100644 --- a/drivers/md/dm-bufio.c +++ b/drivers/md/dm-bufio.c @@ -815,6 +815,10 @@ static struct dm_buffer *__get_unclaimed_buffer(struct dm_bufio_client *c) BUG_ON(test_bit(B_WRITING, &b->state)); BUG_ON(test_bit(B_DIRTY, &b->state)); + if (static_branch_unlikely(&no_sleep_enabled) && c->no_sleep && + unlikely(test_bit(B_READING, &b->state))) + continue; + if (!b->hold_count) { __make_buffer_clean(b); __unlink_buffer(b); @@ -823,6 +827,9 @@ static struct dm_buffer *__get_unclaimed_buffer(struct dm_bufio_client *c) cond_resched(); } + if (static_branch_unlikely(&no_sleep_enabled) && c->no_sleep) + return NULL; + list_for_each_entry_reverse(b, &c->lru[LIST_DIRTY], lru_list) { BUG_ON(test_bit(B_READING, &b->state)); @@ -1632,7 +1639,8 @@ static void drop_buffers(struct dm_bufio_client *c) */ static bool __try_evict_buffer(struct dm_buffer *b, gfp_t gfp) { - if (!(gfp & __GFP_FS)) { + if (!(gfp & __GFP_FS) || + (static_branch_unlikely(&no_sleep_enabled) && b->c->no_sleep)) { if (test_bit(B_READING, &b->state) || test_bit(B_WRITING, &b->state) || test_bit(B_DIRTY, &b->state)) -- cgit v1.2.3 From 7fe05e125d5f730bd2d0fc53985bee77b6c762f0 Mon Sep 17 00:00:00 2001 From: Benjamin Mikailenko Date: Fri, 15 Jul 2022 18:27:07 -0400 Subject: ice: Fix VSI rebuild WARN_ON check for VF In commit b03d519d3460 ("ice: store VF pointer instead of VF ID") WARN_ON checks were added to validate the vsi->vf pointer and catch programming errors. However, one check to vsi->vf was missed. This caused a call trace when resetting VFs. Fix ice_vsi_rebuild by encompassing VF pointer in WARN_ON check. Fixes: b03d519d3460 ("ice: store VF pointer instead of VF ID") Signed-off-by: Benjamin Mikailenko Tested-by: Marek Szlosek Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/ice/ice_lib.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/ice/ice_lib.c b/drivers/net/ethernet/intel/ice/ice_lib.c index a830f7f9aed0..0d4dbca88964 100644 --- a/drivers/net/ethernet/intel/ice/ice_lib.c +++ b/drivers/net/ethernet/intel/ice/ice_lib.c @@ -3181,7 +3181,7 @@ int ice_vsi_rebuild(struct ice_vsi *vsi, bool init_vsi) pf = vsi->back; vtype = vsi->type; - if (WARN_ON(vtype == ICE_VSI_VF) && !vsi->vf) + if (WARN_ON(vtype == ICE_VSI_VF && !vsi->vf)) return -EINVAL; ice_vsi_init_vlan_ops(vsi); -- cgit v1.2.3 From 05b98fd2da6bdf241d3b9ba40582d60a84a89d70 Mon Sep 17 00:00:00 2001 From: Ronnie Sahlberg Date: Wed, 10 Aug 2022 22:00:08 -0500 Subject: cifs: Move cached-dir functions into a separate file Also rename crfid to cfid to have consistent naming for this variable. This commit does not change any logic. Signed-off-by: Ronnie Sahlberg Reviewed-by: Paulo Alcantara (SUSE) Signed-off-by: Steve French --- fs/cifs/Makefile | 2 +- fs/cifs/cached_dir.c | 362 +++++++++++++++++++++++++++++++++++++++++++++++++++ fs/cifs/cached_dir.h | 26 ++++ fs/cifs/cifsfs.c | 20 +-- fs/cifs/cifsglob.h | 2 +- fs/cifs/cifsproto.h | 1 - fs/cifs/file.c | 9 +- fs/cifs/inode.c | 1 + fs/cifs/misc.c | 12 +- fs/cifs/readdir.c | 1 + fs/cifs/smb2inode.c | 5 +- fs/cifs/smb2misc.c | 11 +- fs/cifs/smb2ops.c | 297 +----------------------------------------- fs/cifs/smb2pdu.c | 3 +- fs/cifs/smb2proto.h | 10 -- 15 files changed, 411 insertions(+), 351 deletions(-) create mode 100644 fs/cifs/cached_dir.c create mode 100644 fs/cifs/cached_dir.h diff --git a/fs/cifs/Makefile b/fs/cifs/Makefile index e882e912a517..7c9785973f49 100644 --- a/fs/cifs/Makefile +++ b/fs/cifs/Makefile @@ -7,7 +7,7 @@ obj-$(CONFIG_CIFS) += cifs.o cifs-y := trace.o cifsfs.o cifs_debug.o connect.o dir.o file.o \ inode.o link.o misc.o netmisc.o smbencrypt.o transport.o \ - cifs_unicode.o nterr.o cifsencrypt.o \ + cached_dir.o cifs_unicode.o nterr.o cifsencrypt.o \ readdir.o ioctl.o sess.o export.o unc.o winucase.o \ smb2ops.o smb2maperror.o smb2transport.o \ smb2misc.o smb2pdu.o smb2inode.o smb2file.o cifsacl.o fs_context.o \ diff --git a/fs/cifs/cached_dir.c b/fs/cifs/cached_dir.c new file mode 100644 index 000000000000..753b850b6f87 --- /dev/null +++ b/fs/cifs/cached_dir.c @@ -0,0 +1,362 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Functions to handle the cached directory entries + * + * Copyright (c) 2022, Ronnie Sahlberg + */ + +#include "cifsglob.h" +#include "cifsproto.h" +#include "cifs_debug.h" +#include "smb2proto.h" +#include "cached_dir.h" + +/* + * Open the and cache a directory handle. + * If error then *cfid is not initialized. + */ +int open_cached_dir(unsigned int xid, struct cifs_tcon *tcon, + const char *path, + struct cifs_sb_info *cifs_sb, + struct cached_fid **cfid) +{ + struct cifs_ses *ses; + struct TCP_Server_Info *server; + struct cifs_open_parms oparms; + struct smb2_create_rsp *o_rsp = NULL; + struct smb2_query_info_rsp *qi_rsp = NULL; + int resp_buftype[2]; + struct smb_rqst rqst[2]; + struct kvec rsp_iov[2]; + struct kvec open_iov[SMB2_CREATE_IOV_SIZE]; + struct kvec qi_iov[1]; + int rc, flags = 0; + __le16 utf16_path = 0; /* Null - since an open of top of share */ + u8 oplock = SMB2_OPLOCK_LEVEL_II; + struct cifs_fid *pfid; + struct dentry *dentry; + + if (tcon == NULL || tcon->nohandlecache || + is_smb1_server(tcon->ses->server)) + return -EOPNOTSUPP; + + ses = tcon->ses; + server = ses->server; + + if (cifs_sb->root == NULL) + return -ENOENT; + + if (strlen(path)) + return -ENOENT; + + dentry = cifs_sb->root; + + mutex_lock(&tcon->cfid.fid_mutex); + if (tcon->cfid.is_valid) { + cifs_dbg(FYI, "found a cached root file handle\n"); + *cfid = &tcon->cfid; + kref_get(&tcon->cfid.refcount); + mutex_unlock(&tcon->cfid.fid_mutex); + return 0; + } + + /* + * We do not hold the lock for the open because in case + * SMB2_open needs to reconnect, it will end up calling + * cifs_mark_open_files_invalid() which takes the lock again + * thus causing a deadlock + */ + + mutex_unlock(&tcon->cfid.fid_mutex); + + if (smb3_encryption_required(tcon)) + flags |= CIFS_TRANSFORM_REQ; + + if (!server->ops->new_lease_key) + return -EIO; + + pfid = tcon->cfid.fid; + server->ops->new_lease_key(pfid); + + memset(rqst, 0, sizeof(rqst)); + resp_buftype[0] = resp_buftype[1] = CIFS_NO_BUFFER; + memset(rsp_iov, 0, sizeof(rsp_iov)); + + /* Open */ + memset(&open_iov, 0, sizeof(open_iov)); + rqst[0].rq_iov = open_iov; + rqst[0].rq_nvec = SMB2_CREATE_IOV_SIZE; + + oparms.tcon = tcon; + oparms.create_options = cifs_create_options(cifs_sb, CREATE_NOT_FILE); + oparms.desired_access = FILE_READ_ATTRIBUTES; + oparms.disposition = FILE_OPEN; + oparms.fid = pfid; + oparms.reconnect = false; + + rc = SMB2_open_init(tcon, server, + &rqst[0], &oplock, &oparms, &utf16_path); + if (rc) + goto oshr_free; + smb2_set_next_command(tcon, &rqst[0]); + + memset(&qi_iov, 0, sizeof(qi_iov)); + rqst[1].rq_iov = qi_iov; + rqst[1].rq_nvec = 1; + + rc = SMB2_query_info_init(tcon, server, + &rqst[1], COMPOUND_FID, + COMPOUND_FID, FILE_ALL_INFORMATION, + SMB2_O_INFO_FILE, 0, + sizeof(struct smb2_file_all_info) + + PATH_MAX * 2, 0, NULL); + if (rc) + goto oshr_free; + + smb2_set_related(&rqst[1]); + + rc = compound_send_recv(xid, ses, server, + flags, 2, rqst, + resp_buftype, rsp_iov); + mutex_lock(&tcon->cfid.fid_mutex); + + /* + * Now we need to check again as the cached root might have + * been successfully re-opened from a concurrent process + */ + + if (tcon->cfid.is_valid) { + /* work was already done */ + + /* stash fids for close() later */ + struct cifs_fid fid = { + .persistent_fid = pfid->persistent_fid, + .volatile_fid = pfid->volatile_fid, + }; + + /* + * caller expects this func to set the fid in cfid to valid + * cached root, so increment the refcount. + */ + kref_get(&tcon->cfid.refcount); + + mutex_unlock(&tcon->cfid.fid_mutex); + + if (rc == 0) { + /* close extra handle outside of crit sec */ + SMB2_close(xid, tcon, fid.persistent_fid, fid.volatile_fid); + } + rc = 0; + goto oshr_free; + } + + /* Cached root is still invalid, continue normaly */ + + if (rc) { + if (rc == -EREMCHG) { + tcon->need_reconnect = true; + pr_warn_once("server share %s deleted\n", + tcon->treeName); + } + goto oshr_exit; + } + + atomic_inc(&tcon->num_remote_opens); + + o_rsp = (struct smb2_create_rsp *)rsp_iov[0].iov_base; + oparms.fid->persistent_fid = o_rsp->PersistentFileId; + oparms.fid->volatile_fid = o_rsp->VolatileFileId; +#ifdef CONFIG_CIFS_DEBUG2 + oparms.fid->mid = le64_to_cpu(o_rsp->hdr.MessageId); +#endif /* CIFS_DEBUG2 */ + + tcon->cfid.tcon = tcon; + tcon->cfid.is_valid = true; + tcon->cfid.dentry = dentry; + dget(dentry); + kref_init(&tcon->cfid.refcount); + + /* BB TBD check to see if oplock level check can be removed below */ + if (o_rsp->OplockLevel == SMB2_OPLOCK_LEVEL_LEASE) { + /* + * See commit 2f94a3125b87. Increment the refcount when we + * get a lease for root, release it if lease break occurs + */ + kref_get(&tcon->cfid.refcount); + tcon->cfid.has_lease = true; + smb2_parse_contexts(server, o_rsp, + &oparms.fid->epoch, + oparms.fid->lease_key, &oplock, + NULL, NULL); + } else + goto oshr_exit; + + qi_rsp = (struct smb2_query_info_rsp *)rsp_iov[1].iov_base; + if (le32_to_cpu(qi_rsp->OutputBufferLength) < sizeof(struct smb2_file_all_info)) + goto oshr_exit; + if (!smb2_validate_and_copy_iov( + le16_to_cpu(qi_rsp->OutputBufferOffset), + sizeof(struct smb2_file_all_info), + &rsp_iov[1], sizeof(struct smb2_file_all_info), + (char *)&tcon->cfid.file_all_info)) + tcon->cfid.file_all_info_is_valid = true; + tcon->cfid.time = jiffies; + + +oshr_exit: + mutex_unlock(&tcon->cfid.fid_mutex); +oshr_free: + SMB2_open_free(&rqst[0]); + SMB2_query_info_free(&rqst[1]); + free_rsp_buf(resp_buftype[0], rsp_iov[0].iov_base); + free_rsp_buf(resp_buftype[1], rsp_iov[1].iov_base); + if (rc == 0) + *cfid = &tcon->cfid; + + return rc; +} + +int open_cached_dir_by_dentry(struct cifs_tcon *tcon, + struct dentry *dentry, + struct cached_fid **cfid) +{ + mutex_lock(&tcon->cfid.fid_mutex); + if (tcon->cfid.dentry == dentry) { + cifs_dbg(FYI, "found a cached root file handle by dentry\n"); + *cfid = &tcon->cfid; + kref_get(&tcon->cfid.refcount); + mutex_unlock(&tcon->cfid.fid_mutex); + return 0; + } + mutex_unlock(&tcon->cfid.fid_mutex); + return -ENOENT; +} + +static void +smb2_close_cached_fid(struct kref *ref) +{ + struct cached_fid *cfid = container_of(ref, struct cached_fid, + refcount); + struct cached_dirent *dirent, *q; + + if (cfid->is_valid) { + cifs_dbg(FYI, "clear cached root file handle\n"); + SMB2_close(0, cfid->tcon, cfid->fid->persistent_fid, + cfid->fid->volatile_fid); + } + + /* + * We only check validity above to send SMB2_close, + * but we still need to invalidate these entries + * when this function is called + */ + cfid->is_valid = false; + cfid->file_all_info_is_valid = false; + cfid->has_lease = false; + if (cfid->dentry) { + dput(cfid->dentry); + cfid->dentry = NULL; + } + /* + * Delete all cached dirent names + */ + mutex_lock(&cfid->dirents.de_mutex); + list_for_each_entry_safe(dirent, q, &cfid->dirents.entries, entry) { + list_del(&dirent->entry); + kfree(dirent->name); + kfree(dirent); + } + cfid->dirents.is_valid = 0; + cfid->dirents.is_failed = 0; + cfid->dirents.ctx = NULL; + cfid->dirents.pos = 0; + mutex_unlock(&cfid->dirents.de_mutex); + +} + +void close_cached_dir(struct cached_fid *cfid) +{ + mutex_lock(&cfid->fid_mutex); + kref_put(&cfid->refcount, smb2_close_cached_fid); + mutex_unlock(&cfid->fid_mutex); +} + +void close_cached_dir_lease_locked(struct cached_fid *cfid) +{ + if (cfid->has_lease) { + cfid->has_lease = false; + kref_put(&cfid->refcount, smb2_close_cached_fid); + } +} + +void close_cached_dir_lease(struct cached_fid *cfid) +{ + mutex_lock(&cfid->fid_mutex); + close_cached_dir_lease_locked(cfid); + mutex_unlock(&cfid->fid_mutex); +} + +/* + * Called from cifs_kill_sb when we unmount a share + */ +void close_all_cached_dirs(struct cifs_sb_info *cifs_sb) +{ + struct rb_root *root = &cifs_sb->tlink_tree; + struct rb_node *node; + struct cached_fid *cfid; + struct cifs_tcon *tcon; + struct tcon_link *tlink; + + for (node = rb_first(root); node; node = rb_next(node)) { + tlink = rb_entry(node, struct tcon_link, tl_rbnode); + tcon = tlink_tcon(tlink); + if (IS_ERR(tcon)) + continue; + cfid = &tcon->cfid; + mutex_lock(&cfid->fid_mutex); + if (cfid->dentry) { + dput(cfid->dentry); + cfid->dentry = NULL; + } + mutex_unlock(&cfid->fid_mutex); + } +} + +/* + * Invalidate and close all cached dirs when a TCON has been reset + * due to a session loss. + */ +void invalidate_all_cached_dirs(struct cifs_tcon *tcon) +{ + mutex_lock(&tcon->cfid.fid_mutex); + tcon->cfid.is_valid = false; + /* cached handle is not valid, so SMB2_CLOSE won't be sent below */ + close_cached_dir_lease_locked(&tcon->cfid); + memset(tcon->cfid.fid, 0, sizeof(struct cifs_fid)); + mutex_unlock(&tcon->cfid.fid_mutex); +} + +static void +smb2_cached_lease_break(struct work_struct *work) +{ + struct cached_fid *cfid = container_of(work, + struct cached_fid, lease_break); + + close_cached_dir_lease(cfid); +} + +int cached_dir_lease_break(struct cifs_tcon *tcon, __u8 lease_key[16]) +{ + if (tcon->cfid.is_valid && + !memcmp(lease_key, + tcon->cfid.fid->lease_key, + SMB2_LEASE_KEY_SIZE)) { + tcon->cfid.time = 0; + INIT_WORK(&tcon->cfid.lease_break, + smb2_cached_lease_break); + queue_work(cifsiod_wq, + &tcon->cfid.lease_break); + return true; + } + return false; +} diff --git a/fs/cifs/cached_dir.h b/fs/cifs/cached_dir.h new file mode 100644 index 000000000000..51c6b968f8b6 --- /dev/null +++ b/fs/cifs/cached_dir.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Functions to handle the cached directory entries + * + * Copyright (c) 2022, Ronnie Sahlberg + */ + +#ifndef _CACHED_DIR_H +#define _CACHED_DIR_H + + +extern int open_cached_dir(unsigned int xid, struct cifs_tcon *tcon, + const char *path, + struct cifs_sb_info *cifs_sb, + struct cached_fid **cfid); +extern int open_cached_dir_by_dentry(struct cifs_tcon *tcon, + struct dentry *dentry, + struct cached_fid **cfid); +extern void close_cached_dir(struct cached_fid *cfid); +extern void close_cached_dir_lease(struct cached_fid *cfid); +extern void close_cached_dir_lease_locked(struct cached_fid *cfid); +extern void close_all_cached_dirs(struct cifs_sb_info *cifs_sb); +extern void invalidate_all_cached_dirs(struct cifs_tcon *tcon); +extern int cached_dir_lease_break(struct cifs_tcon *tcon, __u8 lease_key[16]); + +#endif /* _CACHED_DIR_H */ diff --git a/fs/cifs/cifsfs.c b/fs/cifs/cifsfs.c index 8849f0852110..945fb083cea7 100644 --- a/fs/cifs/cifsfs.c +++ b/fs/cifs/cifsfs.c @@ -46,6 +46,7 @@ #include "netlink.h" #endif #include "fs_context.h" +#include "cached_dir.h" /* * DOS dates from 1980/1/1 through 2107/12/31 @@ -283,30 +284,13 @@ out_no_root: static void cifs_kill_sb(struct super_block *sb) { struct cifs_sb_info *cifs_sb = CIFS_SB(sb); - struct cifs_tcon *tcon; - struct cached_fid *cfid; - struct rb_root *root = &cifs_sb->tlink_tree; - struct rb_node *node; - struct tcon_link *tlink; /* * We ned to release all dentries for the cached directories * before we kill the sb. */ if (cifs_sb->root) { - for (node = rb_first(root); node; node = rb_next(node)) { - tlink = rb_entry(node, struct tcon_link, tl_rbnode); - tcon = tlink_tcon(tlink); - if (IS_ERR(tcon)) - continue; - cfid = &tcon->crfid; - mutex_lock(&cfid->fid_mutex); - if (cfid->dentry) { - dput(cfid->dentry); - cfid->dentry = NULL; - } - mutex_unlock(&cfid->fid_mutex); - } + close_all_cached_dirs(cifs_sb); /* finally release root dentry */ dput(cifs_sb->root); diff --git a/fs/cifs/cifsglob.h b/fs/cifs/cifsglob.h index a93024eaf251..8b82f13d11e0 100644 --- a/fs/cifs/cifsglob.h +++ b/fs/cifs/cifsglob.h @@ -1257,7 +1257,7 @@ struct cifs_tcon { struct fscache_volume *fscache; /* cookie for share */ #endif struct list_head pending_opens; /* list of incomplete opens */ - struct cached_fid crfid; /* Cached root fid */ + struct cached_fid cfid; /* Cached root fid */ /* BB add field for back pointer to sb struct(s)? */ #ifdef CONFIG_CIFS_DFS_UPCALL struct list_head ulist; /* cache update list */ diff --git a/fs/cifs/cifsproto.h b/fs/cifs/cifsproto.h index daaadffa2b88..87a77a684339 100644 --- a/fs/cifs/cifsproto.h +++ b/fs/cifs/cifsproto.h @@ -597,7 +597,6 @@ enum securityEnum cifs_select_sectype(struct TCP_Server_Info *, struct cifs_aio_ctx *cifs_aio_ctx_alloc(void); void cifs_aio_ctx_release(struct kref *refcount); int setup_aio_ctx_iter(struct cifs_aio_ctx *ctx, struct iov_iter *iter, int rw); -void smb2_cached_lease_break(struct work_struct *work); int cifs_alloc_hash(const char *name, struct crypto_shash **shash, struct sdesc **sdesc); diff --git a/fs/cifs/file.c b/fs/cifs/file.c index 09975bd7d860..42f2639a1a66 100644 --- a/fs/cifs/file.c +++ b/fs/cifs/file.c @@ -34,6 +34,7 @@ #include "smbdirect.h" #include "fs_context.h" #include "cifs_ioctl.h" +#include "cached_dir.h" /* * Mark as invalid, all open files on tree connections since they @@ -64,13 +65,7 @@ cifs_mark_open_files_invalid(struct cifs_tcon *tcon) } spin_unlock(&tcon->open_file_lock); - mutex_lock(&tcon->crfid.fid_mutex); - tcon->crfid.is_valid = false; - /* cached handle is not valid, so SMB2_CLOSE won't be sent below */ - close_cached_dir_lease_locked(&tcon->crfid); - memset(tcon->crfid.fid, 0, sizeof(struct cifs_fid)); - mutex_unlock(&tcon->crfid.fid_mutex); - + invalidate_all_cached_dirs(tcon); spin_lock(&tcon->tc_lock); if (tcon->status == TID_IN_FILES_INVALIDATE) tcon->status = TID_NEED_TCON; diff --git a/fs/cifs/inode.c b/fs/cifs/inode.c index eeeaba3dec05..bac08c20f559 100644 --- a/fs/cifs/inode.c +++ b/fs/cifs/inode.c @@ -25,6 +25,7 @@ #include "fscache.h" #include "fs_context.h" #include "cifs_ioctl.h" +#include "cached_dir.h" static void cifs_set_ops(struct inode *inode) { diff --git a/fs/cifs/misc.c b/fs/cifs/misc.c index 7a906067db04..ea0405cfaee3 100644 --- a/fs/cifs/misc.c +++ b/fs/cifs/misc.c @@ -116,13 +116,13 @@ tconInfoAlloc(void) ret_buf = kzalloc(sizeof(*ret_buf), GFP_KERNEL); if (!ret_buf) return NULL; - ret_buf->crfid.fid = kzalloc(sizeof(*ret_buf->crfid.fid), GFP_KERNEL); - if (!ret_buf->crfid.fid) { + ret_buf->cfid.fid = kzalloc(sizeof(*ret_buf->cfid.fid), GFP_KERNEL); + if (!ret_buf->cfid.fid) { kfree(ret_buf); return NULL; } - INIT_LIST_HEAD(&ret_buf->crfid.dirents.entries); - mutex_init(&ret_buf->crfid.dirents.de_mutex); + INIT_LIST_HEAD(&ret_buf->cfid.dirents.entries); + mutex_init(&ret_buf->cfid.dirents.de_mutex); atomic_inc(&tconInfoAllocCount); ret_buf->status = TID_NEW; @@ -131,7 +131,7 @@ tconInfoAlloc(void) INIT_LIST_HEAD(&ret_buf->openFileList); INIT_LIST_HEAD(&ret_buf->tcon_list); spin_lock_init(&ret_buf->open_file_lock); - mutex_init(&ret_buf->crfid.fid_mutex); + mutex_init(&ret_buf->cfid.fid_mutex); spin_lock_init(&ret_buf->stat_lock); atomic_set(&ret_buf->num_local_opens, 0); atomic_set(&ret_buf->num_remote_opens, 0); @@ -149,7 +149,7 @@ tconInfoFree(struct cifs_tcon *buf_to_free) atomic_dec(&tconInfoAllocCount); kfree(buf_to_free->nativeFileSystem); kfree_sensitive(buf_to_free->password); - kfree(buf_to_free->crfid.fid); + kfree(buf_to_free->cfid.fid); kfree(buf_to_free); } diff --git a/fs/cifs/readdir.c b/fs/cifs/readdir.c index 384cabdf47ca..a06072ae6c7e 100644 --- a/fs/cifs/readdir.c +++ b/fs/cifs/readdir.c @@ -21,6 +21,7 @@ #include "cifsfs.h" #include "smb2proto.h" #include "fs_context.h" +#include "cached_dir.h" /* * To be safe - for UCS to UTF-8 with strings loaded with the rare long diff --git a/fs/cifs/smb2inode.c b/fs/cifs/smb2inode.c index 8571a459c710..f6f9fc3f2e2d 100644 --- a/fs/cifs/smb2inode.c +++ b/fs/cifs/smb2inode.c @@ -23,6 +23,7 @@ #include "smb2glob.h" #include "smb2pdu.h" #include "smb2proto.h" +#include "cached_dir.h" static void free_set_inf_compound(struct smb_rqst *rqst) @@ -518,9 +519,9 @@ smb2_query_path_info(const unsigned int xid, struct cifs_tcon *tcon, rc = open_cached_dir(xid, tcon, full_path, cifs_sb, &cfid); /* If it is a root and its handle is cached then use it */ if (!rc) { - if (tcon->crfid.file_all_info_is_valid) { + if (tcon->cfid.file_all_info_is_valid) { move_smb2_info_to_cifs(data, - &tcon->crfid.file_all_info); + &tcon->cfid.file_all_info); } else { rc = SMB2_query_info(xid, tcon, cfid->fid->persistent_fid, diff --git a/fs/cifs/smb2misc.c b/fs/cifs/smb2misc.c index 818cc4dee0e2..6a6ec6efb45a 100644 --- a/fs/cifs/smb2misc.c +++ b/fs/cifs/smb2misc.c @@ -16,6 +16,7 @@ #include "smb2status.h" #include "smb2glob.h" #include "nterr.h" +#include "cached_dir.h" static int check_smb2_hdr(struct smb2_hdr *shdr, __u64 mid) @@ -648,15 +649,7 @@ smb2_is_valid_lease_break(char *buffer) } spin_unlock(&tcon->open_file_lock); - if (tcon->crfid.is_valid && - !memcmp(rsp->LeaseKey, - tcon->crfid.fid->lease_key, - SMB2_LEASE_KEY_SIZE)) { - tcon->crfid.time = 0; - INIT_WORK(&tcon->crfid.lease_break, - smb2_cached_lease_break); - queue_work(cifsiod_wq, - &tcon->crfid.lease_break); + if (cached_dir_lease_break(tcon, rsp->LeaseKey)) { spin_unlock(&cifs_tcp_ses_lock); return true; } diff --git a/fs/cifs/smb2ops.c b/fs/cifs/smb2ops.c index c0039dc0715a..8cb1eed1dd63 100644 --- a/fs/cifs/smb2ops.c +++ b/fs/cifs/smb2ops.c @@ -27,6 +27,7 @@ #include "smbdirect.h" #include "fscache.h" #include "fs_context.h" +#include "cached_dir.h" /* Change credits for different ops and return the total number of credits */ static int @@ -701,300 +702,6 @@ out: return rc; } -static void -smb2_close_cached_fid(struct kref *ref) -{ - struct cached_fid *cfid = container_of(ref, struct cached_fid, - refcount); - struct cached_dirent *dirent, *q; - - if (cfid->is_valid) { - cifs_dbg(FYI, "clear cached root file handle\n"); - SMB2_close(0, cfid->tcon, cfid->fid->persistent_fid, - cfid->fid->volatile_fid); - } - - /* - * We only check validity above to send SMB2_close, - * but we still need to invalidate these entries - * when this function is called - */ - cfid->is_valid = false; - cfid->file_all_info_is_valid = false; - cfid->has_lease = false; - if (cfid->dentry) { - dput(cfid->dentry); - cfid->dentry = NULL; - } - /* - * Delete all cached dirent names - */ - mutex_lock(&cfid->dirents.de_mutex); - list_for_each_entry_safe(dirent, q, &cfid->dirents.entries, entry) { - list_del(&dirent->entry); - kfree(dirent->name); - kfree(dirent); - } - cfid->dirents.is_valid = 0; - cfid->dirents.is_failed = 0; - cfid->dirents.ctx = NULL; - cfid->dirents.pos = 0; - mutex_unlock(&cfid->dirents.de_mutex); - -} - -void close_cached_dir(struct cached_fid *cfid) -{ - mutex_lock(&cfid->fid_mutex); - kref_put(&cfid->refcount, smb2_close_cached_fid); - mutex_unlock(&cfid->fid_mutex); -} - -void close_cached_dir_lease_locked(struct cached_fid *cfid) -{ - if (cfid->has_lease) { - cfid->has_lease = false; - kref_put(&cfid->refcount, smb2_close_cached_fid); - } -} - -void close_cached_dir_lease(struct cached_fid *cfid) -{ - mutex_lock(&cfid->fid_mutex); - close_cached_dir_lease_locked(cfid); - mutex_unlock(&cfid->fid_mutex); -} - -void -smb2_cached_lease_break(struct work_struct *work) -{ - struct cached_fid *cfid = container_of(work, - struct cached_fid, lease_break); - - close_cached_dir_lease(cfid); -} - -/* - * Open the and cache a directory handle. - * Only supported for the root handle. - * If error then *cfid is not initialized. - */ -int open_cached_dir(unsigned int xid, struct cifs_tcon *tcon, - const char *path, - struct cifs_sb_info *cifs_sb, - struct cached_fid **cfid) -{ - struct cifs_ses *ses; - struct TCP_Server_Info *server; - struct cifs_open_parms oparms; - struct smb2_create_rsp *o_rsp = NULL; - struct smb2_query_info_rsp *qi_rsp = NULL; - int resp_buftype[2]; - struct smb_rqst rqst[2]; - struct kvec rsp_iov[2]; - struct kvec open_iov[SMB2_CREATE_IOV_SIZE]; - struct kvec qi_iov[1]; - int rc, flags = 0; - __le16 utf16_path = 0; /* Null - since an open of top of share */ - u8 oplock = SMB2_OPLOCK_LEVEL_II; - struct cifs_fid *pfid; - struct dentry *dentry; - - if (tcon == NULL || tcon->nohandlecache || - is_smb1_server(tcon->ses->server)) - return -ENOTSUPP; - - ses = tcon->ses; - server = ses->server; - - if (cifs_sb->root == NULL) - return -ENOENT; - - if (strlen(path)) - return -ENOENT; - - dentry = cifs_sb->root; - - mutex_lock(&tcon->crfid.fid_mutex); - if (tcon->crfid.is_valid) { - cifs_dbg(FYI, "found a cached root file handle\n"); - *cfid = &tcon->crfid; - kref_get(&tcon->crfid.refcount); - mutex_unlock(&tcon->crfid.fid_mutex); - return 0; - } - - /* - * We do not hold the lock for the open because in case - * SMB2_open needs to reconnect, it will end up calling - * cifs_mark_open_files_invalid() which takes the lock again - * thus causing a deadlock - */ - - mutex_unlock(&tcon->crfid.fid_mutex); - - if (smb3_encryption_required(tcon)) - flags |= CIFS_TRANSFORM_REQ; - - if (!server->ops->new_lease_key) - return -EIO; - - pfid = tcon->crfid.fid; - server->ops->new_lease_key(pfid); - - memset(rqst, 0, sizeof(rqst)); - resp_buftype[0] = resp_buftype[1] = CIFS_NO_BUFFER; - memset(rsp_iov, 0, sizeof(rsp_iov)); - - /* Open */ - memset(&open_iov, 0, sizeof(open_iov)); - rqst[0].rq_iov = open_iov; - rqst[0].rq_nvec = SMB2_CREATE_IOV_SIZE; - - oparms.tcon = tcon; - oparms.create_options = cifs_create_options(cifs_sb, CREATE_NOT_FILE); - oparms.desired_access = FILE_READ_ATTRIBUTES; - oparms.disposition = FILE_OPEN; - oparms.fid = pfid; - oparms.reconnect = false; - - rc = SMB2_open_init(tcon, server, - &rqst[0], &oplock, &oparms, &utf16_path); - if (rc) - goto oshr_free; - smb2_set_next_command(tcon, &rqst[0]); - - memset(&qi_iov, 0, sizeof(qi_iov)); - rqst[1].rq_iov = qi_iov; - rqst[1].rq_nvec = 1; - - rc = SMB2_query_info_init(tcon, server, - &rqst[1], COMPOUND_FID, - COMPOUND_FID, FILE_ALL_INFORMATION, - SMB2_O_INFO_FILE, 0, - sizeof(struct smb2_file_all_info) + - PATH_MAX * 2, 0, NULL); - if (rc) - goto oshr_free; - - smb2_set_related(&rqst[1]); - - rc = compound_send_recv(xid, ses, server, - flags, 2, rqst, - resp_buftype, rsp_iov); - mutex_lock(&tcon->crfid.fid_mutex); - - /* - * Now we need to check again as the cached root might have - * been successfully re-opened from a concurrent process - */ - - if (tcon->crfid.is_valid) { - /* work was already done */ - - /* stash fids for close() later */ - struct cifs_fid fid = { - .persistent_fid = pfid->persistent_fid, - .volatile_fid = pfid->volatile_fid, - }; - - /* - * caller expects this func to set the fid in crfid to valid - * cached root, so increment the refcount. - */ - kref_get(&tcon->crfid.refcount); - - mutex_unlock(&tcon->crfid.fid_mutex); - - if (rc == 0) { - /* close extra handle outside of crit sec */ - SMB2_close(xid, tcon, fid.persistent_fid, fid.volatile_fid); - } - rc = 0; - goto oshr_free; - } - - /* Cached root is still invalid, continue normaly */ - - if (rc) { - if (rc == -EREMCHG) { - tcon->need_reconnect = true; - pr_warn_once("server share %s deleted\n", - tcon->treeName); - } - goto oshr_exit; - } - - atomic_inc(&tcon->num_remote_opens); - - o_rsp = (struct smb2_create_rsp *)rsp_iov[0].iov_base; - oparms.fid->persistent_fid = o_rsp->PersistentFileId; - oparms.fid->volatile_fid = o_rsp->VolatileFileId; -#ifdef CONFIG_CIFS_DEBUG2 - oparms.fid->mid = le64_to_cpu(o_rsp->hdr.MessageId); -#endif /* CIFS_DEBUG2 */ - - tcon->crfid.tcon = tcon; - tcon->crfid.is_valid = true; - tcon->crfid.dentry = dentry; - dget(dentry); - kref_init(&tcon->crfid.refcount); - - /* BB TBD check to see if oplock level check can be removed below */ - if (o_rsp->OplockLevel == SMB2_OPLOCK_LEVEL_LEASE) { - /* - * See commit 2f94a3125b87. Increment the refcount when we - * get a lease for root, release it if lease break occurs - */ - kref_get(&tcon->crfid.refcount); - tcon->crfid.has_lease = true; - smb2_parse_contexts(server, o_rsp, - &oparms.fid->epoch, - oparms.fid->lease_key, &oplock, - NULL, NULL); - } else - goto oshr_exit; - - qi_rsp = (struct smb2_query_info_rsp *)rsp_iov[1].iov_base; - if (le32_to_cpu(qi_rsp->OutputBufferLength) < sizeof(struct smb2_file_all_info)) - goto oshr_exit; - if (!smb2_validate_and_copy_iov( - le16_to_cpu(qi_rsp->OutputBufferOffset), - sizeof(struct smb2_file_all_info), - &rsp_iov[1], sizeof(struct smb2_file_all_info), - (char *)&tcon->crfid.file_all_info)) - tcon->crfid.file_all_info_is_valid = true; - tcon->crfid.time = jiffies; - - -oshr_exit: - mutex_unlock(&tcon->crfid.fid_mutex); -oshr_free: - SMB2_open_free(&rqst[0]); - SMB2_query_info_free(&rqst[1]); - free_rsp_buf(resp_buftype[0], rsp_iov[0].iov_base); - free_rsp_buf(resp_buftype[1], rsp_iov[1].iov_base); - if (rc == 0) - *cfid = &tcon->crfid; - return rc; -} - -int open_cached_dir_by_dentry(struct cifs_tcon *tcon, - struct dentry *dentry, - struct cached_fid **cfid) -{ - mutex_lock(&tcon->crfid.fid_mutex); - if (tcon->crfid.dentry == dentry) { - cifs_dbg(FYI, "found a cached root file handle by dentry\n"); - *cfid = &tcon->crfid; - kref_get(&tcon->crfid.refcount); - mutex_unlock(&tcon->crfid.fid_mutex); - return 0; - } - mutex_unlock(&tcon->crfid.fid_mutex); - return -ENOENT; -} - static void smb3_qfs_tcon(const unsigned int xid, struct cifs_tcon *tcon, struct cifs_sb_info *cifs_sb) @@ -1077,7 +784,7 @@ smb2_is_path_accessible(const unsigned int xid, struct cifs_tcon *tcon, struct cifs_open_parms oparms; struct cifs_fid fid; - if ((*full_path == 0) && tcon->crfid.is_valid) + if ((*full_path == 0) && tcon->cfid.is_valid) return 0; utf16_path = cifs_convert_path_to_utf16(full_path, cifs_sb); diff --git a/fs/cifs/smb2pdu.c b/fs/cifs/smb2pdu.c index 590a1d4ac140..7c200b938267 100644 --- a/fs/cifs/smb2pdu.c +++ b/fs/cifs/smb2pdu.c @@ -39,6 +39,7 @@ #ifdef CONFIG_CIFS_DFS_UPCALL #include "dfs_cache.h" #endif +#include "cached_dir.h" /* * The following table defines the expected "StructureSize" of SMB2 requests @@ -1978,7 +1979,7 @@ SMB2_tdis(const unsigned int xid, struct cifs_tcon *tcon) } spin_unlock(&ses->chan_lock); - close_cached_dir_lease(&tcon->crfid); + close_cached_dir_lease(&tcon->cfid); rc = smb2_plain_req_init(SMB2_TREE_DISCONNECT, tcon, ses->server, (void **) &req, diff --git a/fs/cifs/smb2proto.h b/fs/cifs/smb2proto.h index a69f1eed1cfe..51c5bf4a338a 100644 --- a/fs/cifs/smb2proto.h +++ b/fs/cifs/smb2proto.h @@ -54,16 +54,6 @@ extern bool smb2_is_valid_oplock_break(char *buffer, extern int smb3_handle_read_data(struct TCP_Server_Info *server, struct mid_q_entry *mid); -extern int open_cached_dir(unsigned int xid, struct cifs_tcon *tcon, - const char *path, - struct cifs_sb_info *cifs_sb, - struct cached_fid **cfid); -extern int open_cached_dir_by_dentry(struct cifs_tcon *tcon, - struct dentry *dentry, - struct cached_fid **cfid); -extern void close_cached_dir(struct cached_fid *cfid); -extern void close_cached_dir_lease(struct cached_fid *cfid); -extern void close_cached_dir_lease_locked(struct cached_fid *cfid); extern void move_smb2_info_to_cifs(FILE_ALL_INFO *dst, struct smb2_file_all_info *src); extern int smb2_query_reparse_tag(const unsigned int xid, struct cifs_tcon *tcon, -- cgit v1.2.3 From cf90b74341eecc32ceef0c136954a1668e43b1e7 Mon Sep 17 00:00:00 2001 From: Michal Jaron Date: Mon, 25 Jul 2022 10:32:43 +0200 Subject: ice: Fix call trace with null VSI during VF reset During stress test with attaching and detaching VF from KVM and simultaneously changing VFs spoofcheck and trust there was a call trace in ice_reset_vf that VF's VSI is null. [145237.352797] WARNING: CPU: 46 PID: 840629 at drivers/net/ethernet/intel/ice/ice_vf_lib.c:508 ice_reset_vf+0x3d6/0x410 [ice] [145237.352851] Modules linked in: ice(E) vfio_pci vfio_pci_core vfio_virqfd vfio_iommu_type1 vfio iavf dm_mod xt_CHECKSUM xt_MASQUERADE xt_conntrack ipt_REJECT nf_reject_ipv4 nft_compat nft_chain_nat nf_nat nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 nf_tables nfnetlink tun bridge stp llc sunrpc intel_rapl_msr intel_rapl_common sb_edac x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel kvm iTCO_wdt iTC O_vendor_support irqbypass crct10dif_pclmul crc32_pclmul ghash_clmulni_intel rapl ipmi_si intel_cstate ipmi_devintf joydev intel_uncore m ei_me ipmi_msghandler i2c_i801 pcspkr mei lpc_ich ioatdma i2c_smbus acpi_pad acpi_power_meter ip_tables xfs libcrc32c i2c_algo_bit drm_sh mem_helper drm_kms_helper sd_mod t10_pi crc64_rocksoft syscopyarea crc64 sysfillrect sg sysimgblt fb_sys_fops drm i40e ixgbe ahci libahci libata crc32c_intel mdio dca wmi fuse [last unloaded: ice] [145237.352917] CPU: 46 PID: 840629 Comm: kworker/46:2 Tainted: G S W I E 5.19.0-rc6+ #24 [145237.352921] Hardware name: Intel Corporation S2600WTT/S2600WTT, BIOS SE5C610.86B.01.01.0008.021120151325 02/11/2015 [145237.352923] Workqueue: ice ice_service_task [ice] [145237.352948] RIP: 0010:ice_reset_vf+0x3d6/0x410 [ice] [145237.352984] Code: 30 ec f3 cc e9 28 fd ff ff 0f b7 4b 50 48 c7 c2 48 19 9c c0 4c 89 ee 48 c7 c7 30 fe 9e c0 e8 d1 21 9d cc 31 c0 e9 a 9 fe ff ff <0f> 0b b8 ea ff ff ff e9 c1 fc ff ff 0f 0b b8 fb ff ff ff e9 91 fe [145237.352987] RSP: 0018:ffffb453e257fdb8 EFLAGS: 00010246 [145237.352990] RAX: ffff8bd0040181c0 RBX: ffff8be68db8f800 RCX: 0000000000000000 [145237.352991] RDX: 000000000000ffff RSI: 0000000000000000 RDI: ffff8be68db8f800 [145237.352993] RBP: ffff8bd0040181c0 R08: 0000000000001000 R09: ffff8bcfd520e000 [145237.352995] R10: 0000000000000000 R11: 00008417b5ab0bc0 R12: 0000000000000005 [145237.352996] R13: ffff8bcee061c0d0 R14: ffff8bd004019640 R15: 0000000000000000 [145237.352998] FS: 0000000000000000(0000) GS:ffff8be5dfb00000(0000) knlGS:0000000000000000 [145237.353000] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [145237.353002] CR2: 00007fd81f651d68 CR3: 0000001a0fe10001 CR4: 00000000001726e0 [145237.353003] Call Trace: [145237.353008] [145237.353011] ice_process_vflr_event+0x8d/0xb0 [ice] [145237.353049] ice_service_task+0x79f/0xef0 [ice] [145237.353074] process_one_work+0x1c8/0x390 [145237.353081] ? process_one_work+0x390/0x390 [145237.353084] worker_thread+0x30/0x360 [145237.353087] ? process_one_work+0x390/0x390 [145237.353090] kthread+0xe8/0x110 [145237.353094] ? kthread_complete_and_exit+0x20/0x20 [145237.353097] ret_from_fork+0x22/0x30 [145237.353103] Remove WARN_ON() from check if VSI is null in ice_reset_vf. Add "VF is already removed\n" in dev_dbg(). This WARN_ON() is unnecessary and causes call trace, despite that call trace, driver still works. There is no need for this warn because this piece of code is responsible for disabling VF's Tx/Rx queues when VF is disabled, but when VF is already removed there is no need to do reset or disable queues. Fixes: efe41860008e ("ice: Fix memory corruption in VF driver") Signed-off-by: Michal Jaron Signed-off-by: Jedrzej Jagielski Tested-by: Marek Szlosek Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/ice/ice_vf_lib.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/ice/ice_vf_lib.c b/drivers/net/ethernet/intel/ice/ice_vf_lib.c index 8fd7c3e37f5e..76f70fe1d998 100644 --- a/drivers/net/ethernet/intel/ice/ice_vf_lib.c +++ b/drivers/net/ethernet/intel/ice/ice_vf_lib.c @@ -571,8 +571,10 @@ int ice_reset_vf(struct ice_vf *vf, u32 flags) if (ice_is_vf_disabled(vf)) { vsi = ice_get_vf_vsi(vf); - if (WARN_ON(!vsi)) + if (!vsi) { + dev_dbg(dev, "VF is already removed\n"); return -EINVAL; + } ice_vsi_stop_lan_tx_rings(vsi, ICE_NO_RESET, vf->vf_id); ice_vsi_stop_all_rx_rings(vsi); dev_dbg(dev, "VF is already disabled, there is no need for resetting it, telling VM, all is fine %d\n", -- cgit v1.2.3 From 357628e68f5c08ad578a718dc62a0031e06dbe91 Mon Sep 17 00:00:00 2001 From: Xianting Tian Date: Thu, 11 Aug 2022 15:41:45 +0800 Subject: RISC-V: kexec: Fixup use of smp_processor_id() in preemptible context Use __smp_processor_id() to avoid check the preemption context when CONFIG_DEBUG_PREEMPT enabled, as we will enter crash kernel and no return. Without the patch, [ 103.781044] sysrq: Trigger a crash [ 103.784625] Kernel panic - not syncing: sysrq triggered crash [ 103.837634] CPU1: off [ 103.889668] CPU2: off [ 103.933479] CPU3: off [ 103.939424] Starting crashdump kernel... [ 103.943442] BUG: using smp_processor_id() in preemptible [00000000] code: sh/346 [ 103.950884] caller is debug_smp_processor_id+0x1c/0x26 [ 103.956051] CPU: 0 PID: 346 Comm: sh Kdump: loaded Not tainted 5.10.113-00002-gce03f03bf4ec-dirty #149 [ 103.965355] Call Trace: [ 103.967805] [] walk_stackframe+0x0/0xa2 [ 103.973206] [] show_stack+0x32/0x3e [ 103.978258] [] dump_stack_lvl+0x72/0x8e [ 103.983655] [] dump_stack+0x14/0x1c [ 103.988705] [] check_preemption_disabled+0x9e/0xaa [ 103.995057] [] debug_smp_processor_id+0x1c/0x26 [ 104.001150] [] machine_kexec+0x22/0xd0 [ 104.006463] [] __crash_kexec+0x6a/0xa4 [ 104.011774] [] panic+0xfc/0x2b0 [ 104.016480] [] sysrq_reset_seq_param_set+0x0/0x70 [ 104.022745] [] __handle_sysrq+0x8c/0x154 [ 104.028229] [] write_sysrq_trigger+0x5a/0x6a [ 104.034061] [] proc_reg_write+0x58/0xd4 [ 104.039459] [] vfs_write+0x7e/0x254 [ 104.044509] [] ksys_write+0x58/0xbe [ 104.049558] [] sys_write+0xe/0x16 [ 104.054434] [] ret_from_syscall+0x0/0x2 [ 104.067863] Will call new kernel at ecc00000 from hart id 0 [ 104.074939] FDT image at fc5ee000 [ 104.079523] Bye... With the patch we can got clear output, [ 67.740553] sysrq: Trigger a crash [ 67.744166] Kernel panic - not syncing: sysrq triggered crash [ 67.809123] CPU1: off [ 67.865210] CPU2: off [ 67.909075] CPU3: off [ 67.919123] Starting crashdump kernel... [ 67.924900] Will call new kernel at ecc00000 from hart id 0 [ 67.932045] FDT image at fc5ee000 [ 67.935560] Bye... Fixes: 0e105f1d0037 ("riscv: use hart id instead of cpu id on machine_kexec") Reviewed-by: Guo Ren Reviewed-by: Heiko Stuebner Reviewed-by: Atish Patra Signed-off-by: Xianting Tian Link: https://lore.kernel.org/r/20220811074150.3020189-2-xianting.tian@linux.alibaba.com Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt --- arch/riscv/kernel/machine_kexec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/machine_kexec.c b/arch/riscv/kernel/machine_kexec.c index df8e24559035..86d1b5f9dfb5 100644 --- a/arch/riscv/kernel/machine_kexec.c +++ b/arch/riscv/kernel/machine_kexec.c @@ -171,7 +171,7 @@ machine_kexec(struct kimage *image) struct kimage_arch *internal = &image->arch; unsigned long jump_addr = (unsigned long) image->start; unsigned long first_ind_entry = (unsigned long) &image->head; - unsigned long this_cpu_id = smp_processor_id(); + unsigned long this_cpu_id = __smp_processor_id(); unsigned long this_hart_id = cpuid_to_hartid_map(this_cpu_id); unsigned long fdt_addr = internal->fdt_addr; void *control_code_buffer = page_address(image->control_code_page); -- cgit v1.2.3 From 59c026c359c30f116fef6ee958e24d04983efbb0 Mon Sep 17 00:00:00 2001 From: Xianting Tian Date: Thu, 11 Aug 2022 15:41:46 +0800 Subject: RISC-V: Fixup get incorrect user mode PC for kernel mode regs When use 'echo c > /proc/sysrq-trigger' to trigger kdump, riscv_crash_save_regs() will be called to save regs for vmcore, we found "epc" value 00ffffffa5537400 is not a valid kernel virtual address, but is a user virtual address. Other regs(eg, ra, sp, gp...) are correct kernel virtual address. Actually 0x00ffffffb0dd9400 is the user mode PC of 'PID: 113 Comm: sh', which is saved in the task's stack. [ 21.201701] CPU: 0 PID: 113 Comm: sh Kdump: loaded Not tainted 5.18.9 #45 [ 21.201979] Hardware name: riscv-virtio,qemu (DT) [ 21.202160] epc : 00ffffffa5537400 ra : ffffffff80088640 sp : ff20000010333b90 [ 21.202435] gp : ffffffff810dde38 tp : ff6000000226c200 t0 : ffffffff8032be7c [ 21.202707] t1 : 0720072007200720 t2 : 30203a7375746174 s0 : ff20000010333cf0 [ 21.202973] s1 : 0000000000000000 a0 : ff20000010333b98 a1 : 0000000000000001 [ 21.203243] a2 : 0000000000000010 a3 : 0000000000000000 a4 : 28c8f0aeffea4e00 [ 21.203519] a5 : 28c8f0aeffea4e00 a6 : 0000000000000009 a7 : ffffffff8035c9b8 [ 21.203794] s2 : ffffffff810df0a8 s3 : ffffffff810df718 s4 : ff20000010333b98 [ 21.204062] s5 : 0000000000000000 s6 : 0000000000000007 s7 : ffffffff80c4a468 [ 21.204331] s8 : 00ffffffef451410 s9 : 0000000000000007 s10: 00aaaaaac0510700 [ 21.204606] s11: 0000000000000001 t3 : ff60000001218f00 t4 : ff60000001218f00 [ 21.204876] t5 : ff60000001218000 t6 : ff200000103338b8 [ 21.205079] status: 0000000200000020 badaddr: 0000000000000000 cause: 0000000000000008 With the incorrect PC, the backtrace showed by crash tool as below, the first stack frame is abnormal, crash> bt PID: 113 TASK: ff60000002269600 CPU: 0 COMMAND: "sh" #0 [ff2000001039bb90] __efistub_.Ldebug_info0 at 00ffffffa5537400 <-- Abnormal #1 [ff2000001039bcf0] panic at ffffffff806578ba #2 [ff2000001039bd50] sysrq_reset_seq_param_set at ffffffff8038c030 #3 [ff2000001039bda0] __handle_sysrq at ffffffff8038c5f8 #4 [ff2000001039be00] write_sysrq_trigger at ffffffff8038cad8 #5 [ff2000001039be20] proc_reg_write at ffffffff801b7edc #6 [ff2000001039be40] vfs_write at ffffffff80152ba6 #7 [ff2000001039be80] ksys_write at ffffffff80152ece #8 [ff2000001039bed0] sys_write at ffffffff80152f46 With the patch, we can get current kernel mode PC, the output as below, [ 17.607658] CPU: 0 PID: 113 Comm: sh Kdump: loaded Not tainted 5.18.9 #42 [ 17.607937] Hardware name: riscv-virtio,qemu (DT) [ 17.608150] epc : ffffffff800078f8 ra : ffffffff8008862c sp : ff20000010333b90 [ 17.608441] gp : ffffffff810dde38 tp : ff6000000226c200 t0 : ffffffff8032be68 [ 17.608741] t1 : 0720072007200720 t2 : 666666666666663c s0 : ff20000010333cf0 [ 17.609025] s1 : 0000000000000000 a0 : ff20000010333b98 a1 : 0000000000000001 [ 17.609320] a2 : 0000000000000010 a3 : 0000000000000000 a4 : 0000000000000000 [ 17.609601] a5 : ff60000001c78000 a6 : 000000000000003c a7 : ffffffff8035c9a4 [ 17.609894] s2 : ffffffff810df0a8 s3 : ffffffff810df718 s4 : ff20000010333b98 [ 17.610186] s5 : 0000000000000000 s6 : 0000000000000007 s7 : ffffffff80c4a468 [ 17.610469] s8 : 00ffffffca281410 s9 : 0000000000000007 s10: 00aaaaaab5bb6700 [ 17.610755] s11: 0000000000000001 t3 : ff60000001218f00 t4 : ff60000001218f00 [ 17.611041] t5 : ff60000001218000 t6 : ff20000010333988 [ 17.611255] status: 0000000200000020 badaddr: 0000000000000000 cause: 0000000000000008 With the correct PC, the backtrace showed by crash tool as below, crash> bt PID: 113 TASK: ff6000000226c200 CPU: 0 COMMAND: "sh" #0 [ff20000010333b90] riscv_crash_save_regs at ffffffff800078f8 <--- Normal #1 [ff20000010333cf0] panic at ffffffff806578c6 #2 [ff20000010333d50] sysrq_reset_seq_param_set at ffffffff8038c03c #3 [ff20000010333da0] __handle_sysrq at ffffffff8038c604 #4 [ff20000010333e00] write_sysrq_trigger at ffffffff8038cae4 #5 [ff20000010333e20] proc_reg_write at ffffffff801b7ee8 #6 [ff20000010333e40] vfs_write at ffffffff80152bb2 #7 [ff20000010333e80] ksys_write at ffffffff80152eda #8 [ff20000010333ed0] sys_write at ffffffff80152f52 Fixes: e53d28180d4d ("RISC-V: Add kdump support") Co-developed-by: Guo Ren Signed-off-by: Xianting Tian Link: https://lore.kernel.org/r/20220811074150.3020189-3-xianting.tian@linux.alibaba.com Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt --- arch/riscv/kernel/crash_save_regs.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/crash_save_regs.S b/arch/riscv/kernel/crash_save_regs.S index 7832fb763aba..b2a1908c0463 100644 --- a/arch/riscv/kernel/crash_save_regs.S +++ b/arch/riscv/kernel/crash_save_regs.S @@ -44,7 +44,7 @@ SYM_CODE_START(riscv_crash_save_regs) REG_S t6, PT_T6(a0) /* x31 */ csrr t1, CSR_STATUS - csrr t2, CSR_EPC + auipc t2, 0x0 csrr t3, CSR_TVAL csrr t4, CSR_CAUSE -- cgit v1.2.3 From ad943893d5f1d0aeea892bf7b781cf8062b36d58 Mon Sep 17 00:00:00 2001 From: Xianting Tian Date: Thu, 11 Aug 2022 15:41:47 +0800 Subject: RISC-V: Fixup schedule out issue in machine_crash_shutdown() Current task of executing crash kexec will be schedule out when panic is triggered by RCU Stall, as it needs to wait rcu completion. It lead to inability to enter the crash system. The implementation of machine_crash_shutdown() is non-standard for RISC-V according to other Arch's implementation(eg, x86, arm64), we need to send IPI to stop secondary harts. [224521.877268] rcu: INFO: rcu_preempt detected stalls on CPUs/tasks: [224521.883471] rcu: 0-...0: (3 GPs behind) idle=cfa/0/0x1 softirq=3968793/3968793 fqs=2495 [224521.891742] (detected by 2, t=5255 jiffies, g=60855593, q=328) [224521.897754] Task dump for CPU 0: [224521.901074] task:swapper/0 state:R running task stack: 0 pid: 0 ppid: 0 flags:0x00000008 [224521.911090] Call Trace: [224521.913638] [] __schedule+0x208/0x5ea [224521.918957] Kernel panic - not syncing: RCU Stall [224521.923773] bad: scheduling from the idle thread! [224521.928571] CPU: 2 PID: 0 Comm: swapper/2 Kdump: loaded Tainted: G O 5.10.113-yocto-standard #1 [224521.938658] Call Trace: [224521.941200] [] walk_stackframe+0x0/0xaa [224521.946689] [] show_stack+0x32/0x3e [224521.951830] [] dump_stack_lvl+0x7e/0xa2 [224521.957317] [] dump_stack+0x14/0x1c [224521.962459] [] dequeue_task_idle+0x2c/0x40 [224521.968207] [] __schedule+0x41e/0x5ea [224521.973520] [] schedule+0x34/0xe4 [224521.978487] [] schedule_timeout+0xc6/0x170 [224521.984234] [] wait_for_completion+0x98/0xf2 [224521.990157] [] __wait_rcu_gp+0x148/0x14a [224521.995733] [] synchronize_rcu+0x5c/0x66 [224522.001307] [] rcu_sync_enter+0x54/0xe6 [224522.006795] [] percpu_down_write+0x32/0x11c [224522.012629] [] _cpu_down+0x92/0x21a [224522.017771] [] smp_shutdown_nonboot_cpus+0x90/0x118 [224522.024299] [] machine_crash_shutdown+0x30/0x4a [224522.030483] [] __crash_kexec+0x62/0xa6 [224522.035884] [] panic+0xfa/0x2b6 [224522.040678] [] rcu_sched_clock_irq+0xc26/0xcb8 [224522.046774] [] update_process_times+0x62/0x8a [224522.052785] [] tick_sched_timer+0x9e/0x102 [224522.058533] [] __hrtimer_run_queues+0x16a/0x318 [224522.064716] [] hrtimer_interrupt+0xd4/0x228 [224522.070551] [] riscv_timer_interrupt+0x3c/0x48 [224522.076646] [] handle_percpu_devid_irq+0xb0/0x24c [224522.083004] [] __handle_domain_irq+0xa8/0x122 [224522.089014] [] riscv_intc_irq+0x38/0x60 [224522.094501] [] ret_from_exception+0x0/0xc [224522.100161] [] rcu_eqs_enter.constprop.0+0x8c/0xb8 With the patch, it can enter crash system when RCU Stall occur. Fixes: e53d28180d4d ("RISC-V: Add kdump support") Signed-off-by: Xianting Tian Link: https://lore.kernel.org/r/20220811074150.3020189-4-xianting.tian@linux.alibaba.com Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt --- arch/riscv/kernel/machine_kexec.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kernel/machine_kexec.c b/arch/riscv/kernel/machine_kexec.c index 86d1b5f9dfb5..ee79e6839b86 100644 --- a/arch/riscv/kernel/machine_kexec.c +++ b/arch/riscv/kernel/machine_kexec.c @@ -138,19 +138,37 @@ void machine_shutdown(void) #endif } +/* Override the weak function in kernel/panic.c */ +void crash_smp_send_stop(void) +{ + static int cpus_stopped; + + /* + * This function can be called twice in panic path, but obviously + * we execute this only once. + */ + if (cpus_stopped) + return; + + smp_send_stop(); + cpus_stopped = 1; +} + /* * machine_crash_shutdown - Prepare to kexec after a kernel crash * * This function is called by crash_kexec just before machine_kexec - * below and its goal is similar to machine_shutdown, but in case of - * a kernel crash. Since we don't handle such cases yet, this function - * is empty. + * and its goal is to shutdown non-crashing cpus and save registers. */ void machine_crash_shutdown(struct pt_regs *regs) { + local_irq_disable(); + + /* shutdown non-crashing cpus */ + crash_smp_send_stop(); + crash_save_cpu(regs, smp_processor_id()); - machine_shutdown(); pr_info("Starting crashdump kernel...\n"); } -- cgit v1.2.3 From 76ad33e1b95f3db7a2fb6c3141dc82a8d05f80dc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 23 Jun 2022 13:29:05 +0200 Subject: riscv: traps_misaligned: do not duplicate stringify Use existing stringify macro from the kernel headers. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20220623112905.253157-1-krzysztof.kozlowski@linaro.org Signed-off-by: Palmer Dabbelt --- arch/riscv/kernel/traps_misaligned.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 46c4dafe3ba0..378f5b151443 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -150,9 +151,6 @@ #define PRECISION_S 0 #define PRECISION_D 1 -#define STR(x) XSTR(x) -#define XSTR(x) #x - #define DECLARE_UNPRIVILEGED_LOAD_FUNCTION(type, insn) \ static inline type load_##type(const type *addr) \ { \ @@ -207,9 +205,9 @@ static inline ulong get_insn(ulong mepc) asm ("and %[tmp], %[addr], 2\n" "bnez %[tmp], 1f\n" #if defined(CONFIG_64BIT) - STR(LWU) " %[insn], (%[addr])\n" + __stringify(LWU) " %[insn], (%[addr])\n" #else - STR(LW) " %[insn], (%[addr])\n" + __stringify(LW) " %[insn], (%[addr])\n" #endif "and %[tmp], %[insn], %[rvc_mask]\n" "beq %[tmp], %[rvc_mask], 2f\n" -- cgit v1.2.3 From 2024439bd5ceb145eeeb428b2a59e9b905153ac3 Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Thu, 11 Aug 2022 13:30:39 +0200 Subject: netfilter: nf_tables: fix scheduling-while-atomic splat nf_tables_check_loops() can be called from rhashtable list walk so cond_resched() cannot be used here. Fixes: 81ea01066741 ("netfilter: nf_tables: add rescheduling points during loop detection walks") Signed-off-by: Florian Westphal Signed-off-by: Pablo Neira Ayuso --- net/netfilter/nf_tables_api.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index 989c9782ecc3..d90434eadc1b 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -9426,13 +9426,9 @@ static int nf_tables_check_loops(const struct nft_ctx *ctx, break; } } - - cond_resched(); } list_for_each_entry(set, &ctx->table->sets, list) { - cond_resched(); - if (!nft_is_active_next(ctx->net, set)) continue; if (!(set->flags & NFT_SET_MAP) || -- cgit v1.2.3 From f9293ad46d8ba9909187a37b7215324420ad4596 Mon Sep 17 00:00:00 2001 From: Xianting Tian Date: Thu, 11 Aug 2022 15:41:48 +0800 Subject: RISC-V: Add modules to virtual kernel memory layout dump Modules always live before the kernel, MODULES_END is fixed but MODULES_VADDR isn't fixed, it depends on the kernel size. Let's add it to virtual kernel memory layout dump. As MODULES is only defined for CONFIG_64BIT, so we dump it when CONFIG_64BIT=y. eg, MODULES_VADDR - MODULES_END 0xffffffff01133000 - 0xffffffff80000000 Reviewed-by: Guo Ren Reviewed-by: Heiko Stuebner Signed-off-by: Xianting Tian Link: https://lore.kernel.org/r/20220811074150.3020189-5-xianting.tian@linux.alibaba.com Cc: stable@vger.kernel.org Fixes: 2bfc6cd81bd1 ("riscv: Move kernel mapping outside of linear mapping") Signed-off-by: Palmer Dabbelt --- arch/riscv/mm/init.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index d466ec670e1f..2c4a64e97aec 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -135,6 +135,10 @@ static void __init print_vm_layout(void) (unsigned long)VMEMMAP_END); print_ml("vmalloc", (unsigned long)VMALLOC_START, (unsigned long)VMALLOC_END); +#ifdef CONFIG_64BIT + print_ml("modules", (unsigned long)MODULES_VADDR, + (unsigned long)MODULES_END); +#endif print_ml("lowmem", (unsigned long)PAGE_OFFSET, (unsigned long)high_memory); if (IS_ENABLED(CONFIG_64BIT)) { -- cgit v1.2.3 From 0b2f3212b551a87fe936701fa0813032861a3308 Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Fri, 5 Aug 2022 10:59:57 +0200 Subject: netfilter: nfnetlink: re-enable conntrack expectation events To avoid allocation of the conntrack extension area when possible, the default behaviour was changed to only allocate the event extension if a userspace program is subscribed to a notification group. Problem is that while 'conntrack -E' does enable the event allocation behind the scenes, 'conntrack -E expect' does not: no expectation events are delivered unless user sets "net.netfilter.nf_conntrack_events" back to 1 (always on). Fix the autodetection to also consider EXP type group. We need to track the 6 event groups (3+3, new/update/destroy for events and for expectations each) independently, else we'd disable events again if an expectation group becomes empty while there is still an active event group. Fixes: 2794cdb0b97b ("netfilter: nfnetlink: allow to detect if ctnetlink listeners exist") Reported-by: Yi Chen Signed-off-by: Florian Westphal --- include/net/netns/conntrack.h | 2 +- net/netfilter/nfnetlink.c | 83 ++++++++++++++++++++++++++++++++++++------- 2 files changed, 72 insertions(+), 13 deletions(-) diff --git a/include/net/netns/conntrack.h b/include/net/netns/conntrack.h index 0677cd3de034..c396a3862e80 100644 --- a/include/net/netns/conntrack.h +++ b/include/net/netns/conntrack.h @@ -95,7 +95,7 @@ struct nf_ip_net { struct netns_ct { #ifdef CONFIG_NF_CONNTRACK_EVENTS - bool ctnetlink_has_listener; + u8 ctnetlink_has_listener; bool ecache_dwork_pending; #endif u8 sysctl_log_invalid; /* Log invalid packets */ diff --git a/net/netfilter/nfnetlink.c b/net/netfilter/nfnetlink.c index c24b1240908f..9c44518cb70f 100644 --- a/net/netfilter/nfnetlink.c +++ b/net/netfilter/nfnetlink.c @@ -44,6 +44,10 @@ MODULE_DESCRIPTION("Netfilter messages via netlink socket"); static unsigned int nfnetlink_pernet_id __read_mostly; +#ifdef CONFIG_NF_CONNTRACK_EVENTS +static DEFINE_SPINLOCK(nfnl_grp_active_lock); +#endif + struct nfnl_net { struct sock *nfnl; }; @@ -654,6 +658,44 @@ static void nfnetlink_rcv(struct sk_buff *skb) netlink_rcv_skb(skb, nfnetlink_rcv_msg); } +static void nfnetlink_bind_event(struct net *net, unsigned int group) +{ +#ifdef CONFIG_NF_CONNTRACK_EVENTS + int type, group_bit; + u8 v; + + /* All NFNLGRP_CONNTRACK_* group bits fit into u8. + * The other groups are not relevant and can be ignored. + */ + if (group >= 8) + return; + + type = nfnl_group2type[group]; + + switch (type) { + case NFNL_SUBSYS_CTNETLINK: + break; + case NFNL_SUBSYS_CTNETLINK_EXP: + break; + default: + return; + } + + group_bit = (1 << group); + + spin_lock(&nfnl_grp_active_lock); + v = READ_ONCE(net->ct.ctnetlink_has_listener); + if ((v & group_bit) == 0) { + v |= group_bit; + + /* read concurrently without nfnl_grp_active_lock held. */ + WRITE_ONCE(net->ct.ctnetlink_has_listener, v); + } + + spin_unlock(&nfnl_grp_active_lock); +#endif +} + static int nfnetlink_bind(struct net *net, int group) { const struct nfnetlink_subsystem *ss; @@ -670,28 +712,45 @@ static int nfnetlink_bind(struct net *net, int group) if (!ss) request_module_nowait("nfnetlink-subsys-%d", type); -#ifdef CONFIG_NF_CONNTRACK_EVENTS - if (type == NFNL_SUBSYS_CTNETLINK) { - nfnl_lock(NFNL_SUBSYS_CTNETLINK); - WRITE_ONCE(net->ct.ctnetlink_has_listener, true); - nfnl_unlock(NFNL_SUBSYS_CTNETLINK); - } -#endif + nfnetlink_bind_event(net, group); return 0; } static void nfnetlink_unbind(struct net *net, int group) { #ifdef CONFIG_NF_CONNTRACK_EVENTS + int type, group_bit; + if (group <= NFNLGRP_NONE || group > NFNLGRP_MAX) return; - if (nfnl_group2type[group] == NFNL_SUBSYS_CTNETLINK) { - nfnl_lock(NFNL_SUBSYS_CTNETLINK); - if (!nfnetlink_has_listeners(net, group)) - WRITE_ONCE(net->ct.ctnetlink_has_listener, false); - nfnl_unlock(NFNL_SUBSYS_CTNETLINK); + type = nfnl_group2type[group]; + + switch (type) { + case NFNL_SUBSYS_CTNETLINK: + break; + case NFNL_SUBSYS_CTNETLINK_EXP: + break; + default: + return; + } + + /* ctnetlink_has_listener is u8 */ + if (group >= 8) + return; + + group_bit = (1 << group); + + spin_lock(&nfnl_grp_active_lock); + if (!nfnetlink_has_listeners(net, group)) { + u8 v = READ_ONCE(net->ct.ctnetlink_has_listener); + + v &= ~group_bit; + + /* read concurrently without nfnl_grp_active_lock held. */ + WRITE_ONCE(net->ct.ctnetlink_has_listener, v); } + spin_unlock(&nfnl_grp_active_lock); #endif } -- cgit v1.2.3 From 788177e76589e6441d43691f1a075feec2e25962 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sun, 26 Jun 2022 07:34:36 +0900 Subject: riscv/purgatory: hard-code obj-y in Makefile The purgatory/ directory is entirely guarded in arch/riscv/Kbuild. CONFIG_ARCH_HAS_KEXEC_PURGATORY is bool type. $(CONFIG_ARCH_HAS_KEXEC_PURGATORY) is always 'y' when Kbuild visits this Makefile for building. Signed-off-by: Masahiro Yamada Link: https://lore.kernel.org/r/20220625223438.835408-1-masahiroy@kernel.org Signed-off-by: Palmer Dabbelt --- arch/riscv/purgatory/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/purgatory/Makefile b/arch/riscv/purgatory/Makefile index d4df200f7edf..c2d14e2f345d 100644 --- a/arch/riscv/purgatory/Makefile +++ b/arch/riscv/purgatory/Makefile @@ -92,4 +92,4 @@ quiet_cmd_bin2c = BIN2C $@ $(obj)/kexec-purgatory.c: $(obj)/purgatory.ro $(obj)/purgatory.chk FORCE $(call if_changed,bin2c) -obj-$(CONFIG_ARCH_HAS_KEXEC_PURGATORY) += kexec-purgatory.o +obj-y += kexec-purgatory.o -- cgit v1.2.3 From d8357e3bf8f7aabd98bf4dc2709ee877b741cefc Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sun, 26 Jun 2022 07:34:37 +0900 Subject: riscv/purgatory: Omit use of bin2c The .incbin assembler directive is much faster than bin2c + $(CC). Do similar refactoring as in commit 4c0f032d4963 ("s390/purgatory: Omit use of bin2c"). Please note the .quad directive matches to size_t in C (both 8 byte) because the purgatory is compiled only for the 64-bit kernel. (KEXEC_FILE depends on 64BIT). Signed-off-by: Masahiro Yamada Link: https://lore.kernel.org/r/20220625223438.835408-2-masahiroy@kernel.org Signed-off-by: Palmer Dabbelt --- arch/riscv/Kconfig | 1 - arch/riscv/purgatory/.gitignore | 1 - arch/riscv/purgatory/Makefile | 8 +------- arch/riscv/purgatory/kexec-purgatory.S | 14 ++++++++++++++ scripts/remove-stale-files | 2 ++ 5 files changed, 17 insertions(+), 9 deletions(-) create mode 100644 arch/riscv/purgatory/kexec-purgatory.S diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 3d49317f5019..ed66c31e4655 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -494,7 +494,6 @@ config KEXEC_FILE config ARCH_HAS_KEXEC_PURGATORY def_bool KEXEC_FILE - select BUILD_BIN2C depends on CRYPTO=y depends on CRYPTO_SHA256=y diff --git a/arch/riscv/purgatory/.gitignore b/arch/riscv/purgatory/.gitignore index 38d7d1bda4d7..6e4dfb024ad2 100644 --- a/arch/riscv/purgatory/.gitignore +++ b/arch/riscv/purgatory/.gitignore @@ -1,4 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only purgatory.chk purgatory.ro -kexec-purgatory.c diff --git a/arch/riscv/purgatory/Makefile b/arch/riscv/purgatory/Makefile index c2d14e2f345d..dd58e1d99397 100644 --- a/arch/riscv/purgatory/Makefile +++ b/arch/riscv/purgatory/Makefile @@ -84,12 +84,6 @@ $(obj)/purgatory.ro: $(PURGATORY_OBJS) FORCE $(obj)/purgatory.chk: $(obj)/purgatory.ro FORCE $(call if_changed,ld) -targets += kexec-purgatory.c - -quiet_cmd_bin2c = BIN2C $@ - cmd_bin2c = $(objtree)/scripts/bin2c kexec_purgatory < $< > $@ - -$(obj)/kexec-purgatory.c: $(obj)/purgatory.ro $(obj)/purgatory.chk FORCE - $(call if_changed,bin2c) +$(obj)/kexec-purgatory.o: $(obj)/purgatory.ro $(obj)/purgatory.chk obj-y += kexec-purgatory.o diff --git a/arch/riscv/purgatory/kexec-purgatory.S b/arch/riscv/purgatory/kexec-purgatory.S new file mode 100644 index 000000000000..0e9188815718 --- /dev/null +++ b/arch/riscv/purgatory/kexec-purgatory.S @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + + .section .rodata, "a" + + .align 8 +kexec_purgatory: + .globl kexec_purgatory + .incbin "arch/riscv/purgatory/purgatory.ro" +.Lkexec_purgatroy_end: + + .align 8 +kexec_purgatory_size: + .globl kexec_purgatory_size + .quad .Lkexec_purgatroy_end - kexec_purgatory diff --git a/scripts/remove-stale-files b/scripts/remove-stale-files index 379e86c71bed..e1cd6effad61 100755 --- a/scripts/remove-stale-files +++ b/scripts/remove-stale-files @@ -40,6 +40,8 @@ if [ -n "${building_out_of_srctree}" ]; then done fi +rm -f arch/riscv/purgatory/kexec-purgatory.c + rm -f scripts/extract-cert rm -f arch/x86/purgatory/kexec-purgatory.c -- cgit v1.2.3 From 271c5ca826e0c3c53e0eb4032f8eaedea1ee391c Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Tue, 9 Aug 2022 17:23:53 +0200 Subject: netfilter: nf_tables: really skip inactive sets when allocating name While looping to build the bitmap of used anonymous set names, check the current set in the iteration, instead of the one that is being created. Fixes: 37a9cc525525 ("netfilter: nf_tables: add generation mask to sets") Signed-off-by: Pablo Neira Ayuso --- net/netfilter/nf_tables_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index d90434eadc1b..1b9459a364ba 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -3907,7 +3907,7 @@ cont: list_for_each_entry(i, &ctx->table->sets, list) { int tmp; - if (!nft_is_active_next(ctx->net, set)) + if (!nft_is_active_next(ctx->net, i)) continue; if (!sscanf(i->name, name, &tmp)) continue; -- cgit v1.2.3 From 3ed159c984079baedff740505d609badb8538e0d Mon Sep 17 00:00:00 2001 From: Anuj Gupta Date: Thu, 11 Aug 2022 14:44:59 +0530 Subject: io_uring: fix error handling for io_uring_cmd Commit 97b388d70b53 ("io_uring: handle completions in the core") moved the error handling from handler to core. But for io_uring_cmd handler we end up completing more than once (both in handler and in core) leading to use_after_free. Change io_uring_cmd handler to avoid calling io_uring_cmd_done in case of error. Fixes: 97b388d70b53 ("io_uring: handle completions in the core") Signed-off-by: Anuj Gupta Signed-off-by: Kanchan Joshi Link: https://lore.kernel.org/r/20220811091459.6929-1-anuj20.g@samsung.com [axboe: fix ret vs req typo] Signed-off-by: Jens Axboe --- io_uring/uring_cmd.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/io_uring/uring_cmd.c b/io_uring/uring_cmd.c index 849d9708d612..ee7036f2241f 100644 --- a/io_uring/uring_cmd.c +++ b/io_uring/uring_cmd.c @@ -106,7 +106,9 @@ int io_uring_cmd(struct io_kiocb *req, unsigned int issue_flags) } if (ret != -EIOCBQUEUED) { - io_uring_cmd_done(ioucmd, ret, 0); + if (ret < 0) + req_set_fail(req); + io_req_set_res(req, ret, 0); return IOU_OK; } -- cgit v1.2.3 From da2634e89caa40d7546b0566ab80ff31567861c9 Mon Sep 17 00:00:00 2001 From: Stefan Metzmacher Date: Thu, 11 Aug 2022 09:11:14 +0200 Subject: io_uring: consistently make use of io_notif_to_data() This makes the assignment typesafe. It prepares changing io_kiocb_to_cmd() in the next commit. Signed-off-by: Stefan Metzmacher Link: https://lore.kernel.org/r/8da6e9d12cf95ad4bc73274406d12bca7aabf72e.1660201408.git.metze@samba.org Signed-off-by: Jens Axboe --- io_uring/notif.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/io_uring/notif.c b/io_uring/notif.c index b5f989dff9de..48d29dead62a 100644 --- a/io_uring/notif.c +++ b/io_uring/notif.c @@ -100,7 +100,7 @@ __cold int io_notif_unregister(struct io_ring_ctx *ctx) if (!notif) continue; - nd = io_kiocb_to_cmd(notif); + nd = io_notif_to_data(notif); slot->notif = NULL; if (!refcount_dec_and_test(&nd->uarg.refcnt)) continue; -- cgit v1.2.3 From 09992025dacd258c823f50e82db09d7ef06cdac4 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 11 Aug 2022 15:44:45 +0200 Subject: spi: meson-spicc: add local pow2 clock ops to preserve rate between messages At the end of a message, the HW gets a reset in meson_spicc_unprepare_transfer(), this resets the SPICC_CONREG register and notably the value set by the Common Clock Framework. This is problematic because: - the register value CCF can be different from the corresponding CCF cached rate - CCF is allowed to change the clock rate whenever the HW state This introduces: - local pow2 clock ops checking the HW state before allowing a clock operation - separation of legacy pow2 clock patch and new enhanced clock path - SPICC_CONREG datarate value is now value kepts across messages It has been checked that: - SPICC_CONREG datarate value is kept across messages - CCF is only allowed to change the SPICC_CONREG datarate value when busy - SPICC_CONREG datarate value is correct for each transfer This didn't appear before commit 3e0cf4d3fc29 ("spi: meson-spicc: add a linear clock divider support") because we recalculated and wrote the rate for each xfer. Fixes: 3e0cf4d3fc29 ("spi: meson-spicc: add a linear clock divider support") Reported-by: Da Xue Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220811134445.678446-1-narmstrong@baylibre.com Signed-off-by: Mark Brown --- drivers/spi/spi-meson-spicc.c | 129 +++++++++++++++++++++++++++++++++--------- 1 file changed, 101 insertions(+), 28 deletions(-) diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index 0bc7daa7afc8..e4cb52e1fe26 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -156,6 +156,7 @@ struct meson_spicc_device { void __iomem *base; struct clk *core; struct clk *pclk; + struct clk_divider pow2_div; struct clk *clk; struct spi_message *message; struct spi_transfer *xfer; @@ -168,6 +169,8 @@ struct meson_spicc_device { unsigned long xfer_remain; }; +#define pow2_clk_to_spicc(_div) container_of(_div, struct meson_spicc_device, pow2_div) + static void meson_spicc_oen_enable(struct meson_spicc_device *spicc) { u32 conf; @@ -421,7 +424,7 @@ static int meson_spicc_prepare_message(struct spi_master *master, { struct meson_spicc_device *spicc = spi_master_get_devdata(master); struct spi_device *spi = message->spi; - u32 conf = 0; + u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK; /* Store current message */ spicc->message = message; @@ -458,8 +461,6 @@ static int meson_spicc_prepare_message(struct spi_master *master, /* Select CS */ conf |= FIELD_PREP(SPICC_CS_MASK, spi->chip_select); - /* Default Clock rate core/4 */ - /* Default 8bit word */ conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1); @@ -476,12 +477,16 @@ static int meson_spicc_prepare_message(struct spi_master *master, static int meson_spicc_unprepare_transfer(struct spi_master *master) { struct meson_spicc_device *spicc = spi_master_get_devdata(master); + u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK; /* Disable all IRQs */ writel(0, spicc->base + SPICC_INTREG); device_reset_optional(&spicc->pdev->dev); + /* Set default configuration, keeping datarate field */ + writel_relaxed(conf, spicc->base + SPICC_CONREG); + return 0; } @@ -518,14 +523,60 @@ static void meson_spicc_cleanup(struct spi_device *spi) * Clk path for G12A series: * pclk -> pow2 fixed div -> pow2 div -> mux -> out * pclk -> enh fixed div -> enh div -> mux -> out + * + * The pow2 divider is tied to the controller HW state, and the + * divider is only valid when the controller is initialized. + * + * A set of clock ops is added to make sure we don't read/set this + * clock rate while the controller is in an unknown state. */ -static int meson_spicc_clk_init(struct meson_spicc_device *spicc) +static unsigned long meson_spicc_pow2_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_divider *divider = to_clk_divider(hw); + struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider); + + if (!spicc->master->cur_msg || !spicc->master->busy) + return 0; + + return clk_divider_ops.recalc_rate(hw, parent_rate); +} + +static int meson_spicc_pow2_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_divider *divider = to_clk_divider(hw); + struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider); + + if (!spicc->master->cur_msg || !spicc->master->busy) + return -EINVAL; + + return clk_divider_ops.determine_rate(hw, req); +} + +static int meson_spicc_pow2_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_divider *divider = to_clk_divider(hw); + struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider); + + if (!spicc->master->cur_msg || !spicc->master->busy) + return -EINVAL; + + return clk_divider_ops.set_rate(hw, rate, parent_rate); +} + +const struct clk_ops meson_spicc_pow2_clk_ops = { + .recalc_rate = meson_spicc_pow2_recalc_rate, + .determine_rate = meson_spicc_pow2_determine_rate, + .set_rate = meson_spicc_pow2_set_rate, +}; + +static int meson_spicc_pow2_clk_init(struct meson_spicc_device *spicc) { struct device *dev = &spicc->pdev->dev; - struct clk_fixed_factor *pow2_fixed_div, *enh_fixed_div; - struct clk_divider *pow2_div, *enh_div; - struct clk_mux *mux; + struct clk_fixed_factor *pow2_fixed_div; struct clk_init_data init; struct clk *clk; struct clk_parent_data parent_data[2]; @@ -560,31 +611,45 @@ static int meson_spicc_clk_init(struct meson_spicc_device *spicc) if (WARN_ON(IS_ERR(clk))) return PTR_ERR(clk); - pow2_div = devm_kzalloc(dev, sizeof(*pow2_div), GFP_KERNEL); - if (!pow2_div) - return -ENOMEM; - snprintf(name, sizeof(name), "%s#pow2_div", dev_name(dev)); init.name = name; - init.ops = &clk_divider_ops; - init.flags = CLK_SET_RATE_PARENT; + init.ops = &meson_spicc_pow2_clk_ops; + /* + * Set NOCACHE here to make sure we read the actual HW value + * since we reset the HW after each transfer. + */ + init.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE; parent_data[0].hw = &pow2_fixed_div->hw; init.num_parents = 1; - pow2_div->shift = 16, - pow2_div->width = 3, - pow2_div->flags = CLK_DIVIDER_POWER_OF_TWO, - pow2_div->reg = spicc->base + SPICC_CONREG; - pow2_div->hw.init = &init; + spicc->pow2_div.shift = 16, + spicc->pow2_div.width = 3, + spicc->pow2_div.flags = CLK_DIVIDER_POWER_OF_TWO, + spicc->pow2_div.reg = spicc->base + SPICC_CONREG; + spicc->pow2_div.hw.init = &init; - clk = devm_clk_register(dev, &pow2_div->hw); - if (WARN_ON(IS_ERR(clk))) - return PTR_ERR(clk); + spicc->clk = devm_clk_register(dev, &spicc->pow2_div.hw); + if (WARN_ON(IS_ERR(spicc->clk))) + return PTR_ERR(spicc->clk); - if (!spicc->data->has_enhance_clk_div) { - spicc->clk = clk; - return 0; - } + return 0; +} + +static int meson_spicc_enh_clk_init(struct meson_spicc_device *spicc) +{ + struct device *dev = &spicc->pdev->dev; + struct clk_fixed_factor *enh_fixed_div; + struct clk_divider *enh_div; + struct clk_mux *mux; + struct clk_init_data init; + struct clk *clk; + struct clk_parent_data parent_data[2]; + char name[64]; + + memset(&init, 0, sizeof(init)); + memset(&parent_data, 0, sizeof(parent_data)); + + init.parent_data = parent_data; /* algorithm for enh div: rate = freq / 2 / (N + 1) */ @@ -637,7 +702,7 @@ static int meson_spicc_clk_init(struct meson_spicc_device *spicc) snprintf(name, sizeof(name), "%s#sel", dev_name(dev)); init.name = name; init.ops = &clk_mux_ops; - parent_data[0].hw = &pow2_div->hw; + parent_data[0].hw = &spicc->pow2_div.hw; parent_data[1].hw = &enh_div->hw; init.num_parents = 2; init.flags = CLK_SET_RATE_PARENT; @@ -754,12 +819,20 @@ static int meson_spicc_probe(struct platform_device *pdev) meson_spicc_oen_enable(spicc); - ret = meson_spicc_clk_init(spicc); + ret = meson_spicc_pow2_clk_init(spicc); if (ret) { - dev_err(&pdev->dev, "clock registration failed\n"); + dev_err(&pdev->dev, "pow2 clock registration failed\n"); goto out_clk; } + if (spicc->data->has_enhance_clk_div) { + ret = meson_spicc_enh_clk_init(spicc); + if (ret) { + dev_err(&pdev->dev, "clock registration failed\n"); + goto out_clk; + } + } + ret = devm_spi_register_master(&pdev->dev, master); if (ret) { dev_err(&pdev->dev, "spi master registration failed\n"); -- cgit v1.2.3 From 2fd92c7b8fe2cfc634613dc093d0f507c7389ea8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 11 Aug 2022 09:38:26 +0300 Subject: spi: dt-bindings: Drop Pratyush Yadav Emails to Pratyush Yadav bounce ("550 Invalid recipient"). Generic SPI properties should be maintained by subsystem maintainer (Mark). Add recent contributor Vaishnav Achath to the Cadence SPI bindings. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220811063826.7620-1-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown --- .../devicetree/bindings/spi/cdns,qspi-nor-peripheral-props.yaml | 2 +- Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 2 +- Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor-peripheral-props.yaml index 553601a441a7..510b82c177c0 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor-peripheral-props.yaml @@ -10,7 +10,7 @@ description: See spi-peripheral-props.yaml for more info. maintainers: - - Pratyush Yadav + - Vaishnav Achath properties: # cdns,qspi-nor.yaml diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index 0a537fa3a641..4707294d8f59 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Cadence Quad SPI controller maintainers: - - Pratyush Yadav + - Vaishnav Achath allOf: - $ref: spi-controller.yaml# diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index ce048e782e80..a4abe1588005 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -16,7 +16,7 @@ description: their own separate schema that should be referenced from here. maintainers: - - Pratyush Yadav + - Mark Brown properties: reg: -- cgit v1.2.3 From 2cfe9bbec56ea579135cdd92409fff371841904f Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Tue, 5 Jul 2022 23:01:43 +0200 Subject: riscv: dts: sifive unmatched: Add PWM controlled LEDs This adds the two PWM controlled LEDs to the HiFive Unmatched device tree. D12 is just a regular green diode, but D2 is an RGB diode with 3 PWM inputs controlling the three different colours. Signed-off-by: Emil Renner Berthing Reviewed-by: Geert Uytterhoeven Acked-by: Pavel Machek Tested-by: Ron Economos Link: https://lore.kernel.org/r/20220705210143.315151-5-emil.renner.berthing@canonical.com Signed-off-by: Palmer Dabbelt --- .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts index 1f386b07a832..07387f9c135c 100644 --- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts +++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts @@ -4,6 +4,8 @@ #include "fu740-c000.dtsi" #include #include +#include +#include /* Clock frequency (in Hz) of the PCB crystal for rtcclk */ #define RTCCLK_FREQ 1000000 @@ -44,6 +46,46 @@ compatible = "gpio-poweroff"; gpios = <&gpio 2 GPIO_ACTIVE_LOW>; }; + + led-controller-1 { + compatible = "pwm-leds"; + + led-d12 { + pwms = <&pwm0 0 7812500 PWM_POLARITY_INVERTED>; + active-low; + color = ; + max-brightness = <255>; + label = "d12"; + }; + }; + + led-controller-2 { + compatible = "pwm-leds-multicolor"; + + multi-led { + color = ; + max-brightness = <255>; + label = "d2"; + + led-red { + pwms = <&pwm0 2 7812500 PWM_POLARITY_INVERTED>; + active-low; + color = ; + }; + + led-green { + pwms = <&pwm0 1 7812500 PWM_POLARITY_INVERTED>; + active-low; + color = ; + }; + + led-blue { + pwms = <&pwm0 3 7812500 PWM_POLARITY_INVERTED>; + active-low; + color = ; + }; + }; + }; }; &uart0 { -- cgit v1.2.3 From a208acf0eac857dc8cdaddd63a4e18ed03f91786 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Thu, 7 Jul 2022 20:55:28 +0200 Subject: riscv: dts: starfive: correct number of external interrupts The PLIC integrated on the Vic_U7_Core integrated on the StarFive JH7100 SoC actually supports 133 external interrupts. 127 of these are exposed to the outside world; the remainder are used by other devices that are part of the core-complex such as the L2 cache controller. But all 133 interrupts are external interrupts as far as the PLIC is concerned. Fix the property so that the driver can manage these additional interrupts, which is important since the interrupts for the L2 cache controller are enabled by default. Fixes: ec85362fb121 ("RISC-V: Add initial StarFive JH7100 device tree") Signed-off-by: Mark Kettenis Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220707185529.19509-1-kettenis@openbsd.org Signed-off-by: Palmer Dabbelt --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index c617a61e26e2..000447482aca 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -130,7 +130,7 @@ interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; - riscv,ndev = <127>; + riscv,ndev = <133>; }; clkgen: clock-controller@11800000 { -- cgit v1.2.3 From da6d2128e56a50a0d497c8e41ca1d33d88bcc0aa Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Thu, 14 Jul 2022 08:18:11 +0100 Subject: RISC-V: Declare cpu_ops_spinwait in The cpu_ops_spinwait is used in a couple of places in arch/riscv and is causing a sparse warning due to no declaration. Add this to with the others to fix the following: arch/riscv/kernel/cpu_ops_spinwait.c:16:29: warning: symbol 'cpu_ops_spinwait' was not declared. Should it be static? Signed-off-by: Ben Dooks Link: https://lore.kernel.org/r/20220714071811.187491-1-ben.dooks@sifive.com [Palmer: Drop the extern from cpu_ops.c] Fixes: 2ffc48fc7071 ("RISC-V: Move spinwait booting method to its own config") Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt --- arch/riscv/include/asm/cpu_ops.h | 1 + arch/riscv/kernel/cpu_ops.c | 4 +--- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/cpu_ops.h b/arch/riscv/include/asm/cpu_ops.h index 134590f1b843..aa128466c4d4 100644 --- a/arch/riscv/include/asm/cpu_ops.h +++ b/arch/riscv/include/asm/cpu_ops.h @@ -38,6 +38,7 @@ struct cpu_operations { #endif }; +extern const struct cpu_operations cpu_ops_spinwait; extern const struct cpu_operations *cpu_ops[NR_CPUS]; void __init cpu_set_ops(int cpu); diff --git a/arch/riscv/kernel/cpu_ops.c b/arch/riscv/kernel/cpu_ops.c index 170d07e57721..f92c0e6eddb1 100644 --- a/arch/riscv/kernel/cpu_ops.c +++ b/arch/riscv/kernel/cpu_ops.c @@ -15,9 +15,7 @@ const struct cpu_operations *cpu_ops[NR_CPUS] __ro_after_init; extern const struct cpu_operations cpu_ops_sbi; -#ifdef CONFIG_RISCV_BOOT_SPINWAIT -extern const struct cpu_operations cpu_ops_spinwait; -#else +#ifndef CONFIG_RISCV_BOOT_SPINWAIT const struct cpu_operations cpu_ops_spinwait = { .name = "", .cpu_prepare = NULL, -- cgit v1.2.3 From e4aa991c05aedc3ead92d1352af86db74090dc3c Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 13 Jul 2022 22:53:06 +0100 Subject: RISC-V: cpu_ops_spinwait.c should include head.h Running sparse shows cpu_ops_spinwait.c is missing two definitions found in head.h, so include it to stop the following warnings: arch/riscv/kernel/cpu_ops_spinwait.c:15:6: warning: symbol '__cpu_spinwait_stack_pointer' was not declared. Should it be static? arch/riscv/kernel/cpu_ops_spinwait.c:16:6: warning: symbol '__cpu_spinwait_task_pointer' was not declared. Should it be static? Signed-off-by: Ben Dooks Link: https://lore.kernel.org/r/20220713215306.94675-1-ben.dooks@sifive.com Fixes: c78f94f35cf6 ("RISC-V: Use __cpu_up_stack/task_pointer only for spinwait method") Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt --- arch/riscv/kernel/cpu_ops_spinwait.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/kernel/cpu_ops_spinwait.c b/arch/riscv/kernel/cpu_ops_spinwait.c index 3ade9152a3c7..d98d19226b5f 100644 --- a/arch/riscv/kernel/cpu_ops_spinwait.c +++ b/arch/riscv/kernel/cpu_ops_spinwait.c @@ -11,6 +11,8 @@ #include #include +#include "head.h" + const struct cpu_operations cpu_ops_spinwait; void *__cpu_spinwait_stack_pointer[NR_CPUS] __section(".data"); void *__cpu_spinwait_task_pointer[NR_CPUS] __section(".data"); -- cgit v1.2.3 From 87df2b5cbc84554df49ccfd9170103729d5a0ab4 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 14 Jul 2022 09:02:36 +0100 Subject: riscv: ensure cpu_ops_sbi is declared Sparse complains that cpu_ops_sbi is used undeclared: arch/riscv/kernel/cpu_ops_sbi.c:17:29: warning: symbol 'cpu_ops_sbi' was not declared. Should it be static? Fix the warning by adding cpu_ops_sbi to cpu_ops_sbi.h & including that where used. Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20220714080235.3853374-1-conor.dooley@microchip.com Signed-off-by: Palmer Dabbelt --- arch/riscv/include/asm/cpu_ops_sbi.h | 2 ++ arch/riscv/kernel/cpu_ops.c | 1 + 2 files changed, 3 insertions(+) diff --git a/arch/riscv/include/asm/cpu_ops_sbi.h b/arch/riscv/include/asm/cpu_ops_sbi.h index 56e4b76d09ff..d6e4665b3195 100644 --- a/arch/riscv/include/asm/cpu_ops_sbi.h +++ b/arch/riscv/include/asm/cpu_ops_sbi.h @@ -10,6 +10,8 @@ #include #include +extern const struct cpu_operations cpu_ops_sbi; + /** * struct sbi_hart_boot_data - Hart specific boot used during booting and * cpu hotplug. diff --git a/arch/riscv/kernel/cpu_ops.c b/arch/riscv/kernel/cpu_ops.c index f92c0e6eddb1..8275f237a59d 100644 --- a/arch/riscv/kernel/cpu_ops.c +++ b/arch/riscv/kernel/cpu_ops.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include -- cgit v1.2.3 From 07fc958b0cfcd8e44f0de13625a551dd16b97eb4 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Thu, 11 Aug 2022 11:54:53 -0700 Subject: perf offcpu: Check process id for the given workload Current task filter checks task->pid which is different for each thread. But we want to profile all the threads in the process. So let's compare process id (or thread-group id: tgid) instead. Before: $ sudo perf record --off-cpu -- perf bench sched messaging -t $ sudo perf report --stat | grep -A1 offcpu offcpu-time stats: SAMPLE events: 2 After: $ sudo perf record --off-cpu -- perf bench sched messaging -t $ sudo perf report --stat | grep -A1 offcpu offcpu-time stats: SAMPLE events: 850 Signed-off-by: Namhyung Kim Cc: Blake Jones Cc: Hao Luo Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Milian Wolff Cc: Peter Zijlstra Cc: Song Liu Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20220811185456.194721-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/bpf_off_cpu.c | 1 + tools/perf/util/bpf_skel/off_cpu.bpf.c | 8 +++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/bpf_off_cpu.c b/tools/perf/util/bpf_off_cpu.c index f289b7713598..7dbcb025da87 100644 --- a/tools/perf/util/bpf_off_cpu.c +++ b/tools/perf/util/bpf_off_cpu.c @@ -78,6 +78,7 @@ static void off_cpu_start(void *arg) u8 val = 1; skel->bss->has_task = 1; + skel->bss->uses_tgid = 1; fd = bpf_map__fd(skel->maps.task_filter); pid = perf_thread_map__pid(evlist->core.threads, 0); bpf_map_update_elem(fd, &pid, &val, BPF_ANY); diff --git a/tools/perf/util/bpf_skel/off_cpu.bpf.c b/tools/perf/util/bpf_skel/off_cpu.bpf.c index cc6d7fd55118..143a8b7acf87 100644 --- a/tools/perf/util/bpf_skel/off_cpu.bpf.c +++ b/tools/perf/util/bpf_skel/off_cpu.bpf.c @@ -85,6 +85,7 @@ int enabled = 0; int has_cpu = 0; int has_task = 0; int has_cgroup = 0; +int uses_tgid = 0; const volatile bool has_prev_state = false; const volatile bool needs_cgroup = false; @@ -144,7 +145,12 @@ static inline int can_record(struct task_struct *t, int state) if (has_task) { __u8 *ok; - __u32 pid = t->pid; + __u32 pid; + + if (uses_tgid) + pid = t->tgid; + else + pid = t->pid; ok = bpf_map_lookup_elem(&task_filter, &pid); if (!ok) -- cgit v1.2.3 From d6f415ca33e132d14743c36ad4e2b63dc8ad0b18 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Thu, 11 Aug 2022 11:54:54 -0700 Subject: perf offcpu: Parse process id separately The current target code uses thread id for tracking tasks because perf_events need to be opened for each task. But we can use tgid in BPF maps and check it easily. Signed-off-by: Namhyung Kim Cc: Blake Jones Cc: Hao Luo Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Milian Wolff Cc: Peter Zijlstra Cc: Song Liu Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20220811185456.194721-3-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/bpf_off_cpu.c | 45 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 43 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/bpf_off_cpu.c b/tools/perf/util/bpf_off_cpu.c index 7dbcb025da87..f7ee0c7a53f0 100644 --- a/tools/perf/util/bpf_off_cpu.c +++ b/tools/perf/util/bpf_off_cpu.c @@ -11,6 +11,7 @@ #include "util/cpumap.h" #include "util/thread_map.h" #include "util/cgroup.h" +#include "util/strlist.h" #include #include "bpf_skel/off_cpu.skel.h" @@ -125,6 +126,8 @@ int off_cpu_prepare(struct evlist *evlist, struct target *target, { int err, fd, i; int ncpus = 1, ntasks = 1, ncgrps = 1; + struct strlist *pid_slist = NULL; + struct str_node *pos; if (off_cpu_config(evlist) < 0) { pr_err("Failed to config off-cpu BPF event\n"); @@ -143,7 +146,26 @@ int off_cpu_prepare(struct evlist *evlist, struct target *target, bpf_map__set_max_entries(skel->maps.cpu_filter, ncpus); } - if (target__has_task(target)) { + if (target->pid) { + pid_slist = strlist__new(target->pid, NULL); + if (!pid_slist) { + pr_err("Failed to create a strlist for pid\n"); + return -1; + } + + ntasks = 0; + strlist__for_each_entry(pos, pid_slist) { + char *end_ptr; + int pid = strtol(pos->s, &end_ptr, 10); + + if (pid == INT_MIN || pid == INT_MAX || + (*end_ptr != '\0' && *end_ptr != ',')) + continue; + + ntasks++; + } + bpf_map__set_max_entries(skel->maps.task_filter, ntasks); + } else if (target__has_task(target)) { ntasks = perf_thread_map__nr(evlist->core.threads); bpf_map__set_max_entries(skel->maps.task_filter, ntasks); } @@ -185,7 +207,26 @@ int off_cpu_prepare(struct evlist *evlist, struct target *target, } } - if (target__has_task(target)) { + if (target->pid) { + u8 val = 1; + + skel->bss->has_task = 1; + skel->bss->uses_tgid = 1; + fd = bpf_map__fd(skel->maps.task_filter); + + strlist__for_each_entry(pos, pid_slist) { + char *end_ptr; + u32 tgid; + int pid = strtol(pos->s, &end_ptr, 10); + + if (pid == INT_MIN || pid == INT_MAX || + (*end_ptr != '\0' && *end_ptr != ',')) + continue; + + tgid = pid; + bpf_map_update_elem(fd, &tgid, &val, BPF_ANY); + } + } else if (target__has_task(target)) { u32 pid; u8 val = 1; -- cgit v1.2.3 From d23477637ac6d29f946461a2fa5eb616cfa5d3f0 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Thu, 11 Aug 2022 11:54:55 -0700 Subject: perf offcpu: Track child processes When -p option used or a workload is given, it needs to handle child processes. The perf_event can inherit those task events automatically. We can add a new BPF program in task_newtask tracepoint to track child processes. Before: $ sudo perf record --off-cpu -- perf bench sched messaging $ sudo perf report --stat | grep -A1 offcpu offcpu-time stats: SAMPLE events: 1 After: $ sudo perf record -a --off-cpu -- perf bench sched messaging $ sudo perf report --stat | grep -A1 offcpu offcpu-time stats: SAMPLE events: 856 Signed-off-by: Namhyung Kim Cc: Blake Jones Cc: Hao Luo Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Milian Wolff Cc: Peter Zijlstra Cc: Song Liu Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20220811185456.194721-4-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/bpf_off_cpu.c | 7 +++++++ tools/perf/util/bpf_skel/off_cpu.bpf.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/tools/perf/util/bpf_off_cpu.c b/tools/perf/util/bpf_off_cpu.c index f7ee0c7a53f0..c257813e674e 100644 --- a/tools/perf/util/bpf_off_cpu.c +++ b/tools/perf/util/bpf_off_cpu.c @@ -17,6 +17,7 @@ #include "bpf_skel/off_cpu.skel.h" #define MAX_STACKS 32 +#define MAX_PROC 4096 /* we don't need actual timestamp, just want to put the samples at last */ #define OFF_CPU_TIMESTAMP (~0ull << 32) @@ -164,10 +165,16 @@ int off_cpu_prepare(struct evlist *evlist, struct target *target, ntasks++; } + + if (ntasks < MAX_PROC) + ntasks = MAX_PROC; + bpf_map__set_max_entries(skel->maps.task_filter, ntasks); } else if (target__has_task(target)) { ntasks = perf_thread_map__nr(evlist->core.threads); bpf_map__set_max_entries(skel->maps.task_filter, ntasks); + } else if (target__none(target)) { + bpf_map__set_max_entries(skel->maps.task_filter, MAX_PROC); } if (evlist__first(evlist)->cgrp) { diff --git a/tools/perf/util/bpf_skel/off_cpu.bpf.c b/tools/perf/util/bpf_skel/off_cpu.bpf.c index 143a8b7acf87..c4ba2bcf179f 100644 --- a/tools/perf/util/bpf_skel/off_cpu.bpf.c +++ b/tools/perf/util/bpf_skel/off_cpu.bpf.c @@ -12,6 +12,9 @@ #define TASK_INTERRUPTIBLE 0x0001 #define TASK_UNINTERRUPTIBLE 0x0002 +/* create a new thread */ +#define CLONE_THREAD 0x10000 + #define MAX_STACKS 32 #define MAX_ENTRIES 102400 @@ -220,6 +223,33 @@ next: return 0; } +SEC("tp_btf/task_newtask") +int on_newtask(u64 *ctx) +{ + struct task_struct *task; + u64 clone_flags; + u32 pid; + u8 val = 1; + + if (!uses_tgid) + return 0; + + task = (struct task_struct *)bpf_get_current_task(); + + pid = BPF_CORE_READ(task, tgid); + if (!bpf_map_lookup_elem(&task_filter, &pid)) + return 0; + + task = (struct task_struct *)ctx[0]; + clone_flags = ctx[1]; + + pid = task->tgid; + if (!(clone_flags & CLONE_THREAD)) + bpf_map_update_elem(&task_filter, &pid, &val, BPF_NOEXIST); + + return 0; +} + SEC("tp_btf/sched_switch") int on_switch(u64 *ctx) { -- cgit v1.2.3 From ade1d0307b2fb3d9192398e9b638b1bb6ed36028 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Thu, 11 Aug 2022 11:54:56 -0700 Subject: perf offcpu: Update offcpu test for child process Record off-cpu data with perf bench sched messaging workload and count the number of offcpu-time events. Also update the test script not to run next tests if failed already and revise the error messages. $ sudo ./perf test offcpu -v 88: perf record offcpu profiling tests : --- start --- test child forked, pid 344780 Checking off-cpu privilege Basic off-cpu test Basic off-cpu test [Success] Child task off-cpu test Child task off-cpu test [Success] test child finished with 0 ---- end ---- perf record offcpu profiling tests: Ok Signed-off-by: Namhyung Kim Cc: Blake Jones Cc: Hao Luo Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Milian Wolff Cc: Peter Zijlstra Cc: Song Liu Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20220811185456.194721-5-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/shell/record_offcpu.sh | 57 +++++++++++++++++++++++++++++---- 1 file changed, 50 insertions(+), 7 deletions(-) diff --git a/tools/perf/tests/shell/record_offcpu.sh b/tools/perf/tests/shell/record_offcpu.sh index 96e0739f7478..d2eba583a2ac 100755 --- a/tools/perf/tests/shell/record_offcpu.sh +++ b/tools/perf/tests/shell/record_offcpu.sh @@ -19,20 +19,26 @@ trap_cleanup() { } trap trap_cleanup exit term int -test_offcpu() { - echo "Basic off-cpu test" +test_offcpu_priv() { + echo "Checking off-cpu privilege" + if [ `id -u` != 0 ] then - echo "Basic off-cpu test [Skipped permission]" + echo "off-cpu test [Skipped permission]" err=2 return fi - if perf record --off-cpu -o ${perfdata} --quiet true 2>&1 | grep BUILD_BPF_SKEL + if perf record --off-cpu -o /dev/null --quiet true 2>&1 | grep BUILD_BPF_SKEL then - echo "Basic off-cpu test [Skipped missing BPF support]" + echo "off-cpu test [Skipped missing BPF support]" err=2 return fi +} + +test_offcpu_basic() { + echo "Basic off-cpu test" + if ! perf record --off-cpu -e dummy -o ${perfdata} sleep 1 2> /dev/null then echo "Basic off-cpu test [Failed record]" @@ -41,7 +47,7 @@ test_offcpu() { fi if ! perf evlist -i ${perfdata} | grep -q "offcpu-time" then - echo "Basic off-cpu test [Failed record]" + echo "Basic off-cpu test [Failed no event]" err=1 return fi @@ -54,7 +60,44 @@ test_offcpu() { echo "Basic off-cpu test [Success]" } -test_offcpu +test_offcpu_child() { + echo "Child task off-cpu test" + + # perf bench sched messaging creates 400 processes + if ! perf record --off-cpu -e dummy -o ${perfdata} -- \ + perf bench sched messaging -g 10 > /dev/null 2&>1 + then + echo "Child task off-cpu test [Failed record]" + err=1 + return + fi + if ! perf evlist -i ${perfdata} | grep -q "offcpu-time" + then + echo "Child task off-cpu test [Failed no event]" + err=1 + return + fi + # each process waits for read and write, so it should be more than 800 events + if ! perf report -i ${perfdata} -s comm -q -n -t ';' --percent-limit=90 | \ + awk -F ";" '{ if (NF > 3 && int($3) < 800) exit 1; }' + then + echo "Child task off-cpu test [Failed invalid output]" + err=1 + return + fi + echo "Child task off-cpu test [Success]" +} + + +test_offcpu_priv + +if [ $err = 0 ]; then + test_offcpu_basic +fi + +if [ $err = 0 ]; then + test_offcpu_child +fi cleanup exit $err -- cgit v1.2.3 From b60cf8e59e61133b6c9514ff8d8c8d7049d040ef Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Wed, 3 Aug 2022 19:54:00 +0100 Subject: dt-bindings: riscv: fix SiFive l2-cache's cache-sets Fix device tree schema validation error messages for the SiFive Unmatched: ' cache-sets:0:0: 1024 was expected'. The existing bindings allow for just 1024 cache-sets but the fu740 on Unmatched the has 2048 cache-sets. The ISA itself permits any arbitrary power of two, however this is not supported by dt-schema. The RTL for the IP, to which the number of cache-sets is a tunable parameter, has been released publicly so speculatively adding a small number of "reasonable" values seems unwise also. Instead, as the binding only supports two distinct controllers: add 2048 and explicitly lock it to the fu740's l2 cache while limiting 1024 to the l2 cache on the fu540. Fixes: af951c3a113b ("dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740") Reported-by: Atul Khare Signed-off-by: Conor Dooley Reviewed-by: Krzysztof Kozlowski Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220803185359.942928-1-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml index e2d330bd4608..69cdab18d629 100644 --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml @@ -46,7 +46,7 @@ properties: const: 2 cache-sets: - const: 1024 + enum: [1024, 2048] cache-size: const: 2097152 @@ -84,6 +84,8 @@ then: description: | Must contain entries for DirError, DataError and DataFail signals. maxItems: 3 + cache-sets: + const: 1024 else: properties: @@ -91,6 +93,8 @@ else: description: | Must contain entries for DirError, DataError, DataFail, DirFail signals. minItems: 4 + cache-sets: + const: 2048 additionalProperties: false -- cgit v1.2.3 From 3a8b54298cbee5d56a710f70863226b0ed84aa27 Mon Sep 17 00:00:00 2001 From: Kewei Xu Date: Sat, 6 Aug 2022 18:02:48 +0800 Subject: dt-bindings: i2c: update bindings for mt8188 soc Add a DT binding documentation for the mt8188 soc. Signed-off-by: Kewei Xu Reviewed-by: Matthias Brugger Acked-by: Rob Herring Reviewed-by: Qii Wang Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml index 16a1a3118204..4e730fb7be56 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml @@ -27,6 +27,7 @@ properties: - const: mediatek,mt8173-i2c - const: mediatek,mt8183-i2c - const: mediatek,mt8186-i2c + - const: mediatek,mt8188-i2c - const: mediatek,mt8192-i2c - items: - enum: -- cgit v1.2.3 From 1b48006ed477827848a2b14d70c764fb280c595d Mon Sep 17 00:00:00 2001 From: Kewei Xu Date: Sat, 6 Aug 2022 18:02:49 +0800 Subject: i2c: mediatek: add i2c compatible for MT8188 Add i2c compatible for MT8188 and added mt_i2c_regs_v3[], since MT8188 i2c OFFSET_SLAVE_ADDR register changed from 0x04 to 0x94. Signed-off-by: Kewei Xu Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Qii Wang Signed-off-by: Wolfram Sang --- drivers/i2c/busses/i2c-mt65xx.c | 43 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c index 8e6985354fd5..bd8abba3d1c9 100644 --- a/drivers/i2c/busses/i2c-mt65xx.c +++ b/drivers/i2c/busses/i2c-mt65xx.c @@ -229,6 +229,35 @@ static const u16 mt_i2c_regs_v2[] = { [OFFSET_DCM_EN] = 0xf88, }; +static const u16 mt_i2c_regs_v3[] = { + [OFFSET_DATA_PORT] = 0x0, + [OFFSET_INTR_MASK] = 0x8, + [OFFSET_INTR_STAT] = 0xc, + [OFFSET_CONTROL] = 0x10, + [OFFSET_TRANSFER_LEN] = 0x14, + [OFFSET_TRANSAC_LEN] = 0x18, + [OFFSET_DELAY_LEN] = 0x1c, + [OFFSET_TIMING] = 0x20, + [OFFSET_START] = 0x24, + [OFFSET_EXT_CONF] = 0x28, + [OFFSET_LTIMING] = 0x2c, + [OFFSET_HS] = 0x30, + [OFFSET_IO_CONFIG] = 0x34, + [OFFSET_FIFO_ADDR_CLR] = 0x38, + [OFFSET_SDA_TIMING] = 0x3c, + [OFFSET_TRANSFER_LEN_AUX] = 0x44, + [OFFSET_CLOCK_DIV] = 0x48, + [OFFSET_SOFTRESET] = 0x50, + [OFFSET_MULTI_DMA] = 0x8c, + [OFFSET_SCL_MIS_COMP_POINT] = 0x90, + [OFFSET_SLAVE_ADDR] = 0x94, + [OFFSET_DEBUGSTAT] = 0xe4, + [OFFSET_DEBUGCTRL] = 0xe8, + [OFFSET_FIFO_STAT] = 0xf4, + [OFFSET_FIFO_THRESH] = 0xf8, + [OFFSET_DCM_EN] = 0xf88, +}; + struct mtk_i2c_compatible { const struct i2c_adapter_quirks *quirks; const u16 *regs; @@ -442,6 +471,19 @@ static const struct mtk_i2c_compatible mt8186_compat = { .max_dma_support = 36, }; +static const struct mtk_i2c_compatible mt8188_compat = { + .regs = mt_i2c_regs_v3, + .pmic_i2c = 0, + .dcm = 0, + .auto_restart = 1, + .aux_len_reg = 1, + .timing_adjust = 1, + .dma_sync = 0, + .ltiming_adjust = 1, + .apdma_sync = 1, + .max_dma_support = 36, +}; + static const struct mtk_i2c_compatible mt8192_compat = { .quirks = &mt8183_i2c_quirks, .regs = mt_i2c_regs_v2, @@ -465,6 +507,7 @@ static const struct of_device_id mtk_i2c_of_match[] = { { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat }, + { .compatible = "mediatek,mt8188-i2c", .data = &mt8188_compat }, { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat }, {} }; -- cgit v1.2.3 From 663bb7b9795fcd8b039b5a43990857580f4b816c Mon Sep 17 00:00:00 2001 From: Chris Pringle Date: Thu, 11 Aug 2022 09:21:41 +0100 Subject: i2c: kempld: Support ACPI I2C device declaration Adds an ACPI companion to the KEMPLD I2C driver so that it correctly detects any I2C devices nested under the KEMPLD's ACPI node (SBRG.CPLD). This allows I2C devices attached to the KEMPLD I2C adapter to be declared and instantiated via ACPI. Signed-off-by: Chris Pringle Signed-off-by: Wolfram Sang --- drivers/i2c/busses/i2c-kempld.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/i2c/busses/i2c-kempld.c b/drivers/i2c/busses/i2c-kempld.c index 5bbb7f0d7852..cf857cf22507 100644 --- a/drivers/i2c/busses/i2c-kempld.c +++ b/drivers/i2c/busses/i2c-kempld.c @@ -303,6 +303,7 @@ static int kempld_i2c_probe(struct platform_device *pdev) i2c->dev = &pdev->dev; i2c->adap = kempld_i2c_adapter; i2c->adap.dev.parent = i2c->dev; + ACPI_COMPANION_SET(&i2c->adap.dev, ACPI_COMPANION(&pdev->dev)); i2c_set_adapdata(&i2c->adap, i2c); platform_set_drvdata(pdev, i2c); -- cgit v1.2.3 From ea1558ce149d286eaf2c0800a93b7efa2adda094 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 11 Aug 2022 09:10:30 +0200 Subject: i2c: move drivers from strlcpy to strscpy Follow the advice of the below link and prefer 'strscpy'. Conversion is easy because no driver used the return value and has been done with a simple sed invocation. Link: https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=V6A6G1oUZcprmknw@mail.gmail.com/ Signed-off-by: Wolfram Sang Signed-off-by: Wolfram Sang --- drivers/i2c/busses/i2c-altera.c | 2 +- drivers/i2c/busses/i2c-aspeed.c | 2 +- drivers/i2c/busses/i2c-au1550.c | 2 +- drivers/i2c/busses/i2c-axxia.c | 2 +- drivers/i2c/busses/i2c-bcm-kona.c | 2 +- drivers/i2c/busses/i2c-brcmstb.c | 2 +- drivers/i2c/busses/i2c-cbus-gpio.c | 2 +- drivers/i2c/busses/i2c-cht-wc.c | 2 +- drivers/i2c/busses/i2c-cros-ec-tunnel.c | 2 +- drivers/i2c/busses/i2c-davinci.c | 2 +- drivers/i2c/busses/i2c-digicolor.c | 2 +- drivers/i2c/busses/i2c-eg20t.c | 2 +- drivers/i2c/busses/i2c-emev2.c | 2 +- drivers/i2c/busses/i2c-exynos5.c | 2 +- drivers/i2c/busses/i2c-gpio.c | 2 +- drivers/i2c/busses/i2c-highlander.c | 2 +- drivers/i2c/busses/i2c-hix5hd2.c | 2 +- drivers/i2c/busses/i2c-i801.c | 4 ++-- drivers/i2c/busses/i2c-ibm_iic.c | 2 +- drivers/i2c/busses/i2c-icy.c | 2 +- drivers/i2c/busses/i2c-imx-lpi2c.c | 2 +- drivers/i2c/busses/i2c-lpc2k.c | 2 +- drivers/i2c/busses/i2c-meson.c | 2 +- drivers/i2c/busses/i2c-mt65xx.c | 2 +- drivers/i2c/busses/i2c-mt7621.c | 2 +- drivers/i2c/busses/i2c-mv64xxx.c | 2 +- drivers/i2c/busses/i2c-mxs.c | 2 +- drivers/i2c/busses/i2c-nvidia-gpu.c | 2 +- drivers/i2c/busses/i2c-omap.c | 2 +- drivers/i2c/busses/i2c-opal.c | 4 ++-- drivers/i2c/busses/i2c-parport.c | 2 +- drivers/i2c/busses/i2c-pxa.c | 2 +- drivers/i2c/busses/i2c-qcom-geni.c | 2 +- drivers/i2c/busses/i2c-qup.c | 2 +- drivers/i2c/busses/i2c-rcar.c | 2 +- drivers/i2c/busses/i2c-riic.c | 2 +- drivers/i2c/busses/i2c-rk3x.c | 2 +- drivers/i2c/busses/i2c-s3c2410.c | 2 +- drivers/i2c/busses/i2c-sh_mobile.c | 2 +- drivers/i2c/busses/i2c-simtec.c | 2 +- drivers/i2c/busses/i2c-taos-evm.c | 2 +- drivers/i2c/busses/i2c-tegra-bpmp.c | 2 +- drivers/i2c/busses/i2c-tegra.c | 2 +- drivers/i2c/busses/i2c-uniphier-f.c | 2 +- drivers/i2c/busses/i2c-uniphier.c | 2 +- drivers/i2c/busses/i2c-versatile.c | 2 +- drivers/i2c/busses/i2c-wmt.c | 2 +- 47 files changed, 49 insertions(+), 49 deletions(-) diff --git a/drivers/i2c/busses/i2c-altera.c b/drivers/i2c/busses/i2c-altera.c index 354cf7e45c4a..50e7f3f670b6 100644 --- a/drivers/i2c/busses/i2c-altera.c +++ b/drivers/i2c/busses/i2c-altera.c @@ -447,7 +447,7 @@ static int altr_i2c_probe(struct platform_device *pdev) mutex_unlock(&idev->isr_mutex); i2c_set_adapdata(&idev->adapter, idev); - strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); + strscpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); idev->adapter.owner = THIS_MODULE; idev->adapter.algo = &altr_i2c_algo; idev->adapter.dev.parent = &pdev->dev; diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c index 771e53d3d197..185dedfebbac 100644 --- a/drivers/i2c/busses/i2c-aspeed.c +++ b/drivers/i2c/busses/i2c-aspeed.c @@ -1022,7 +1022,7 @@ static int aspeed_i2c_probe_bus(struct platform_device *pdev) bus->adap.algo = &aspeed_i2c_algo; bus->adap.dev.parent = &pdev->dev; bus->adap.dev.of_node = pdev->dev.of_node; - strlcpy(bus->adap.name, pdev->name, sizeof(bus->adap.name)); + strscpy(bus->adap.name, pdev->name, sizeof(bus->adap.name)); i2c_set_adapdata(&bus->adap, bus); bus->dev = &pdev->dev; diff --git a/drivers/i2c/busses/i2c-au1550.c b/drivers/i2c/busses/i2c-au1550.c index 22aed922552b..99bd24d0e6a5 100644 --- a/drivers/i2c/busses/i2c-au1550.c +++ b/drivers/i2c/busses/i2c-au1550.c @@ -321,7 +321,7 @@ i2c_au1550_probe(struct platform_device *pdev) priv->adap.algo = &au1550_algo; priv->adap.algo_data = priv; priv->adap.dev.parent = &pdev->dev; - strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name)); + strscpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name)); /* Now, set up the PSC for SMBus PIO mode. */ i2c_au1550_setup(priv); diff --git a/drivers/i2c/busses/i2c-axxia.c b/drivers/i2c/busses/i2c-axxia.c index 5294b73beca8..bdf3b50de8ad 100644 --- a/drivers/i2c/busses/i2c-axxia.c +++ b/drivers/i2c/busses/i2c-axxia.c @@ -783,7 +783,7 @@ static int axxia_i2c_probe(struct platform_device *pdev) } i2c_set_adapdata(&idev->adapter, idev); - strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); + strscpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); idev->adapter.owner = THIS_MODULE; idev->adapter.algo = &axxia_i2c_algo; idev->adapter.bus_recovery_info = &axxia_i2c_recovery_info; diff --git a/drivers/i2c/busses/i2c-bcm-kona.c b/drivers/i2c/busses/i2c-bcm-kona.c index 16bf41f1f086..f3e369f0fd40 100644 --- a/drivers/i2c/busses/i2c-bcm-kona.c +++ b/drivers/i2c/busses/i2c-bcm-kona.c @@ -839,7 +839,7 @@ static int bcm_kona_i2c_probe(struct platform_device *pdev) adap = &dev->adapter; i2c_set_adapdata(adap, dev); adap->owner = THIS_MODULE; - strlcpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name)); + strscpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name)); adap->algo = &bcm_algo; adap->dev.parent = &pdev->dev; adap->dev.of_node = pdev->dev.of_node; diff --git a/drivers/i2c/busses/i2c-brcmstb.c b/drivers/i2c/busses/i2c-brcmstb.c index 2ae187e2b642..69383be47905 100644 --- a/drivers/i2c/busses/i2c-brcmstb.c +++ b/drivers/i2c/busses/i2c-brcmstb.c @@ -674,7 +674,7 @@ static int brcmstb_i2c_probe(struct platform_device *pdev) adap = &dev->adapter; i2c_set_adapdata(adap, dev); adap->owner = THIS_MODULE; - strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name)); + strscpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name)); adap->algo = &brcmstb_i2c_algo; adap->dev.parent = &pdev->dev; adap->dev.of_node = pdev->dev.of_node; diff --git a/drivers/i2c/busses/i2c-cbus-gpio.c b/drivers/i2c/busses/i2c-cbus-gpio.c index f8639a4457d2..d97c61eec95c 100644 --- a/drivers/i2c/busses/i2c-cbus-gpio.c +++ b/drivers/i2c/busses/i2c-cbus-gpio.c @@ -245,7 +245,7 @@ static int cbus_i2c_probe(struct platform_device *pdev) adapter->nr = pdev->id; adapter->timeout = HZ; adapter->algo = &cbus_i2c_algo; - strlcpy(adapter->name, "CBUS I2C adapter", sizeof(adapter->name)); + strscpy(adapter->name, "CBUS I2C adapter", sizeof(adapter->name)); spin_lock_init(&chost->lock); chost->dev = &pdev->dev; diff --git a/drivers/i2c/busses/i2c-cht-wc.c b/drivers/i2c/busses/i2c-cht-wc.c index de15f09c9b47..190abdc46dd3 100644 --- a/drivers/i2c/busses/i2c-cht-wc.c +++ b/drivers/i2c/busses/i2c-cht-wc.c @@ -404,7 +404,7 @@ static int cht_wc_i2c_adap_i2c_probe(struct platform_device *pdev) adap->adapter.class = I2C_CLASS_HWMON; adap->adapter.algo = &cht_wc_i2c_adap_algo; adap->adapter.lock_ops = &cht_wc_i2c_adap_lock_ops; - strlcpy(adap->adapter.name, "PMIC I2C Adapter", + strscpy(adap->adapter.name, "PMIC I2C Adapter", sizeof(adap->adapter.name)); adap->adapter.dev.parent = &pdev->dev; diff --git a/drivers/i2c/busses/i2c-cros-ec-tunnel.c b/drivers/i2c/busses/i2c-cros-ec-tunnel.c index 892213d51f43..4e787dc709f9 100644 --- a/drivers/i2c/busses/i2c-cros-ec-tunnel.c +++ b/drivers/i2c/busses/i2c-cros-ec-tunnel.c @@ -267,7 +267,7 @@ static int ec_i2c_probe(struct platform_device *pdev) bus->dev = dev; bus->adap.owner = THIS_MODULE; - strlcpy(bus->adap.name, "cros-ec-i2c-tunnel", sizeof(bus->adap.name)); + strscpy(bus->adap.name, "cros-ec-i2c-tunnel", sizeof(bus->adap.name)); bus->adap.algo = &ec_i2c_algorithm; bus->adap.algo_data = bus; bus->adap.dev.parent = &pdev->dev; diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c index 9e09db31a937..471c47db546b 100644 --- a/drivers/i2c/busses/i2c-davinci.c +++ b/drivers/i2c/busses/i2c-davinci.c @@ -845,7 +845,7 @@ static int davinci_i2c_probe(struct platform_device *pdev) i2c_set_adapdata(adap, dev); adap->owner = THIS_MODULE; adap->class = I2C_CLASS_DEPRECATED; - strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name)); + strscpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name)); adap->algo = &i2c_davinci_algo; adap->dev.parent = &pdev->dev; adap->timeout = DAVINCI_I2C_TIMEOUT; diff --git a/drivers/i2c/busses/i2c-digicolor.c b/drivers/i2c/busses/i2c-digicolor.c index 60c838c7c454..50925d97fa42 100644 --- a/drivers/i2c/busses/i2c-digicolor.c +++ b/drivers/i2c/busses/i2c-digicolor.c @@ -322,7 +322,7 @@ static int dc_i2c_probe(struct platform_device *pdev) if (ret < 0) return ret; - strlcpy(i2c->adap.name, "Conexant Digicolor I2C adapter", + strscpy(i2c->adap.name, "Conexant Digicolor I2C adapter", sizeof(i2c->adap.name)); i2c->adap.owner = THIS_MODULE; i2c->adap.algo = &dc_i2c_algorithm; diff --git a/drivers/i2c/busses/i2c-eg20t.c b/drivers/i2c/busses/i2c-eg20t.c index 321b2770feab..4914bfbee2a9 100644 --- a/drivers/i2c/busses/i2c-eg20t.c +++ b/drivers/i2c/busses/i2c-eg20t.c @@ -773,7 +773,7 @@ static int pch_i2c_probe(struct pci_dev *pdev, pch_adap->owner = THIS_MODULE; pch_adap->class = I2C_CLASS_HWMON; - strlcpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name)); + strscpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name)); pch_adap->algo = &pch_algorithm; pch_adap->algo_data = &adap_info->pch_data[i]; diff --git a/drivers/i2c/busses/i2c-emev2.c b/drivers/i2c/busses/i2c-emev2.c index bdff0e6345d9..f2e537b137b2 100644 --- a/drivers/i2c/busses/i2c-emev2.c +++ b/drivers/i2c/busses/i2c-emev2.c @@ -371,7 +371,7 @@ static int em_i2c_probe(struct platform_device *pdev) if (IS_ERR(priv->base)) return PTR_ERR(priv->base); - strlcpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name)); + strscpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name)); priv->sclk = devm_clk_get(&pdev->dev, "sclk"); if (IS_ERR(priv->sclk)) diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c index b812d1090c0f..4a6260d04db2 100644 --- a/drivers/i2c/busses/i2c-exynos5.c +++ b/drivers/i2c/busses/i2c-exynos5.c @@ -802,7 +802,7 @@ static int exynos5_i2c_probe(struct platform_device *pdev) if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock)) i2c->op_clock = I2C_MAX_STANDARD_MODE_FREQ; - strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name)); + strscpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name)); i2c->adap.owner = THIS_MODULE; i2c->adap.algo = &exynos5_i2c_algorithm; i2c->adap.retries = 3; diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c index 7a048abbf92b..b1985c1667e1 100644 --- a/drivers/i2c/busses/i2c-gpio.c +++ b/drivers/i2c/busses/i2c-gpio.c @@ -436,7 +436,7 @@ static int i2c_gpio_probe(struct platform_device *pdev) adap->owner = THIS_MODULE; if (np) - strlcpy(adap->name, dev_name(dev), sizeof(adap->name)); + strscpy(adap->name, dev_name(dev), sizeof(adap->name)); else snprintf(adap->name, sizeof(adap->name), "i2c-gpio%d", pdev->id); diff --git a/drivers/i2c/busses/i2c-highlander.c b/drivers/i2c/busses/i2c-highlander.c index a2add128d084..4374a8677271 100644 --- a/drivers/i2c/busses/i2c-highlander.c +++ b/drivers/i2c/busses/i2c-highlander.c @@ -402,7 +402,7 @@ static int highlander_i2c_probe(struct platform_device *pdev) i2c_set_adapdata(adap, dev); adap->owner = THIS_MODULE; adap->class = I2C_CLASS_HWMON; - strlcpy(adap->name, "HL FPGA I2C adapter", sizeof(adap->name)); + strscpy(adap->name, "HL FPGA I2C adapter", sizeof(adap->name)); adap->algo = &highlander_i2c_algo; adap->dev.parent = &pdev->dev; adap->nr = pdev->id; diff --git a/drivers/i2c/busses/i2c-hix5hd2.c b/drivers/i2c/busses/i2c-hix5hd2.c index 61ae58f57047..0e34cbaca22d 100644 --- a/drivers/i2c/busses/i2c-hix5hd2.c +++ b/drivers/i2c/busses/i2c-hix5hd2.c @@ -423,7 +423,7 @@ static int hix5hd2_i2c_probe(struct platform_device *pdev) } clk_prepare_enable(priv->clk); - strlcpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name)); + strscpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name)); priv->dev = &pdev->dev; priv->adap.owner = THIS_MODULE; priv->adap.algo = &hix5hd2_i2c_algorithm; diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c index 81d0da2547bd..a176296f4fff 100644 --- a/drivers/i2c/busses/i2c-i801.c +++ b/drivers/i2c/busses/i2c-i801.c @@ -1116,7 +1116,7 @@ static void dmi_check_onboard_device(u8 type, const char *name, memset(&info, 0, sizeof(struct i2c_board_info)); info.addr = dmi_devices[i].i2c_addr; - strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); + strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); i2c_new_client_device(adap, &info); break; } @@ -1267,7 +1267,7 @@ static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv) memset(&info, 0, sizeof(struct i2c_board_info)); info.addr = dell_lis3lv02d_devices[i].i2c_addr; - strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE); + strscpy(info.type, "lis3lv02d", I2C_NAME_SIZE); i2c_new_client_device(&priv->adapter, &info); } diff --git a/drivers/i2c/busses/i2c-ibm_iic.c b/drivers/i2c/busses/i2c-ibm_iic.c index 9f71daf6db64..eeb80e34f9ad 100644 --- a/drivers/i2c/busses/i2c-ibm_iic.c +++ b/drivers/i2c/busses/i2c-ibm_iic.c @@ -738,7 +738,7 @@ static int iic_probe(struct platform_device *ofdev) adap = &dev->adap; adap->dev.parent = &ofdev->dev; adap->dev.of_node = of_node_get(np); - strlcpy(adap->name, "IBM IIC", sizeof(adap->name)); + strscpy(adap->name, "IBM IIC", sizeof(adap->name)); i2c_set_adapdata(adap, dev); adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; adap->algo = &iic_algo; diff --git a/drivers/i2c/busses/i2c-icy.c b/drivers/i2c/busses/i2c-icy.c index 5dae7cab7260..febcb6f01d4d 100644 --- a/drivers/i2c/busses/i2c-icy.c +++ b/drivers/i2c/busses/i2c-icy.c @@ -141,7 +141,7 @@ static int icy_probe(struct zorro_dev *z, i2c->adapter.owner = THIS_MODULE; /* i2c->adapter.algo assigned by i2c_pcf_add_bus() */ i2c->adapter.algo_data = algo_data; - strlcpy(i2c->adapter.name, "ICY I2C Zorro adapter", + strscpy(i2c->adapter.name, "ICY I2C Zorro adapter", sizeof(i2c->adapter.name)); if (!devm_request_mem_region(&z->dev, diff --git a/drivers/i2c/busses/i2c-imx-lpi2c.c b/drivers/i2c/busses/i2c-imx-lpi2c.c index 8b9ba055c418..b51ab3cad2b1 100644 --- a/drivers/i2c/busses/i2c-imx-lpi2c.c +++ b/drivers/i2c/busses/i2c-imx-lpi2c.c @@ -558,7 +558,7 @@ static int lpi2c_imx_probe(struct platform_device *pdev) lpi2c_imx->adapter.algo = &lpi2c_imx_algo; lpi2c_imx->adapter.dev.parent = &pdev->dev; lpi2c_imx->adapter.dev.of_node = pdev->dev.of_node; - strlcpy(lpi2c_imx->adapter.name, pdev->name, + strscpy(lpi2c_imx->adapter.name, pdev->name, sizeof(lpi2c_imx->adapter.name)); lpi2c_imx->clk = devm_clk_get(&pdev->dev, NULL); diff --git a/drivers/i2c/busses/i2c-lpc2k.c b/drivers/i2c/busses/i2c-lpc2k.c index 4e30c5267142..8fff6fbb7065 100644 --- a/drivers/i2c/busses/i2c-lpc2k.c +++ b/drivers/i2c/busses/i2c-lpc2k.c @@ -417,7 +417,7 @@ static int i2c_lpc2k_probe(struct platform_device *pdev) i2c_set_adapdata(&i2c->adap, i2c); i2c->adap.owner = THIS_MODULE; - strlcpy(i2c->adap.name, "LPC2K I2C adapter", sizeof(i2c->adap.name)); + strscpy(i2c->adap.name, "LPC2K I2C adapter", sizeof(i2c->adap.name)); i2c->adap.algo = &i2c_lpc2k_algorithm; i2c->adap.dev.parent = &pdev->dev; i2c->adap.dev.of_node = pdev->dev.of_node; diff --git a/drivers/i2c/busses/i2c-meson.c b/drivers/i2c/busses/i2c-meson.c index 61cc5b2462c6..889eff06b78f 100644 --- a/drivers/i2c/busses/i2c-meson.c +++ b/drivers/i2c/busses/i2c-meson.c @@ -502,7 +502,7 @@ static int meson_i2c_probe(struct platform_device *pdev) return ret; } - strlcpy(i2c->adap.name, "Meson I2C adapter", + strscpy(i2c->adap.name, "Meson I2C adapter", sizeof(i2c->adap.name)); i2c->adap.owner = THIS_MODULE; i2c->adap.algo = &meson_i2c_algorithm; diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c index bd8abba3d1c9..fc7bfd98156b 100644 --- a/drivers/i2c/busses/i2c-mt65xx.c +++ b/drivers/i2c/busses/i2c-mt65xx.c @@ -1432,7 +1432,7 @@ static int mtk_i2c_probe(struct platform_device *pdev) speed_clk = I2C_MT65XX_CLK_MAIN; } - strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); + strscpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); ret = mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk)); if (ret) { diff --git a/drivers/i2c/busses/i2c-mt7621.c b/drivers/i2c/busses/i2c-mt7621.c index cfe6de8175dd..20eda5738ac4 100644 --- a/drivers/i2c/busses/i2c-mt7621.c +++ b/drivers/i2c/busses/i2c-mt7621.c @@ -312,7 +312,7 @@ static int mtk_i2c_probe(struct platform_device *pdev) adap->dev.parent = &pdev->dev; i2c_set_adapdata(adap, i2c); adap->dev.of_node = pdev->dev.of_node; - strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name)); + strscpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name)); platform_set_drvdata(pdev, i2c); diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c index 103a05ecc3d6..047dfef7a657 100644 --- a/drivers/i2c/busses/i2c-mv64xxx.c +++ b/drivers/i2c/busses/i2c-mv64xxx.c @@ -989,7 +989,7 @@ mv64xxx_i2c_probe(struct platform_device *pd) if (IS_ERR(drv_data->reg_base)) return PTR_ERR(drv_data->reg_base); - strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter", + strscpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter", sizeof(drv_data->adapter.name)); init_waitqueue_head(&drv_data->waitq); diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c index 68f67d084c63..5af5cffc444e 100644 --- a/drivers/i2c/busses/i2c-mxs.c +++ b/drivers/i2c/busses/i2c-mxs.c @@ -838,7 +838,7 @@ static int mxs_i2c_probe(struct platform_device *pdev) return err; adap = &i2c->adapter; - strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name)); + strscpy(adap->name, "MXS I2C adapter", sizeof(adap->name)); adap->owner = THIS_MODULE; adap->algo = &mxs_i2c_algo; adap->quirks = &mxs_i2c_quirks; diff --git a/drivers/i2c/busses/i2c-nvidia-gpu.c b/drivers/i2c/busses/i2c-nvidia-gpu.c index 6920c1b9a126..12e330cd7635 100644 --- a/drivers/i2c/busses/i2c-nvidia-gpu.c +++ b/drivers/i2c/busses/i2c-nvidia-gpu.c @@ -299,7 +299,7 @@ static int gpu_i2c_probe(struct pci_dev *pdev, const struct pci_device_id *id) i2c_set_adapdata(&i2cd->adapter, i2cd); i2cd->adapter.owner = THIS_MODULE; - strlcpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter", + strscpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter", sizeof(i2cd->adapter.name)); i2cd->adapter.algo = &gpu_i2c_algorithm; i2cd->adapter.quirks = &gpu_i2c_quirks; diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index d4f6c6d60683..f9ae520aed22 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -1488,7 +1488,7 @@ omap_i2c_probe(struct platform_device *pdev) i2c_set_adapdata(adap, omap); adap->owner = THIS_MODULE; adap->class = I2C_CLASS_DEPRECATED; - strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); + strscpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); adap->algo = &omap_i2c_algo; adap->quirks = &omap_i2c_quirks; adap->dev.parent = &pdev->dev; diff --git a/drivers/i2c/busses/i2c-opal.c b/drivers/i2c/busses/i2c-opal.c index 6eb0f50c5d28..9f773b4f5ed8 100644 --- a/drivers/i2c/busses/i2c-opal.c +++ b/drivers/i2c/busses/i2c-opal.c @@ -220,9 +220,9 @@ static int i2c_opal_probe(struct platform_device *pdev) adapter->dev.of_node = of_node_get(pdev->dev.of_node); pname = of_get_property(pdev->dev.of_node, "ibm,port-name", NULL); if (pname) - strlcpy(adapter->name, pname, sizeof(adapter->name)); + strscpy(adapter->name, pname, sizeof(adapter->name)); else - strlcpy(adapter->name, "opal", sizeof(adapter->name)); + strscpy(adapter->name, "opal", sizeof(adapter->name)); platform_set_drvdata(pdev, adapter); rc = i2c_add_adapter(adapter); diff --git a/drivers/i2c/busses/i2c-parport.c b/drivers/i2c/busses/i2c-parport.c index 231145c48728..0af86a542568 100644 --- a/drivers/i2c/busses/i2c-parport.c +++ b/drivers/i2c/busses/i2c-parport.c @@ -308,7 +308,7 @@ static void i2c_parport_attach(struct parport *port) /* Fill the rest of the structure */ adapter->adapter.owner = THIS_MODULE; adapter->adapter.class = I2C_CLASS_HWMON; - strlcpy(adapter->adapter.name, "Parallel port adapter", + strscpy(adapter->adapter.name, "Parallel port adapter", sizeof(adapter->adapter.name)); adapter->algo_data = parport_algo_data; /* Slow down if we can't sense SCL */ diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c index 690188a9ffff..b605b6e43cb9 100644 --- a/drivers/i2c/busses/i2c-pxa.c +++ b/drivers/i2c/busses/i2c-pxa.c @@ -1403,7 +1403,7 @@ static int i2c_pxa_probe(struct platform_device *dev) spin_lock_init(&i2c->lock); init_waitqueue_head(&i2c->wait); - strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name)); + strscpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name)); i2c->clk = devm_clk_get(&dev->dev, NULL); if (IS_ERR(i2c->clk)) { diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c index 1bef67fe4b25..84a77512614d 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -817,7 +817,7 @@ static int geni_i2c_probe(struct platform_device *pdev) i2c_set_adapdata(&gi2c->adap, gi2c); gi2c->adap.dev.parent = dev; gi2c->adap.dev.of_node = dev->of_node; - strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name)); + strscpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name)); ret = geni_icc_get(&gi2c->se, "qup-memory"); if (ret) diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c index 69e9f3ecf87d..2e153f2f71b6 100644 --- a/drivers/i2c/busses/i2c-qup.c +++ b/drivers/i2c/busses/i2c-qup.c @@ -1878,7 +1878,7 @@ nodma: qup->adap.dev.of_node = pdev->dev.of_node; qup->is_last = true; - strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name)); + strscpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name)); pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC); pm_runtime_use_autosuspend(qup->dev); diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c index 6e7be9d9f504..cef82b205c26 100644 --- a/drivers/i2c/busses/i2c-rcar.c +++ b/drivers/i2c/busses/i2c-rcar.c @@ -1076,7 +1076,7 @@ static int rcar_i2c_probe(struct platform_device *pdev) adap->bus_recovery_info = &rcar_i2c_bri; adap->quirks = &rcar_i2c_quirks; i2c_set_adapdata(adap, priv); - strlcpy(adap->name, pdev->name, sizeof(adap->name)); + strscpy(adap->name, pdev->name, sizeof(adap->name)); /* Init DMA */ sg_init_table(&priv->sg, 1); diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index cded77e06670..ecba1dfc1278 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -448,7 +448,7 @@ static int riic_i2c_probe(struct platform_device *pdev) adap = &riic->adapter; i2c_set_adapdata(adap, riic); - strlcpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name)); + strscpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name)); adap->owner = THIS_MODULE; adap->algo = &riic_algo; adap->dev.parent = &pdev->dev; diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c index 989040a73626..2e98e7793bba 100644 --- a/drivers/i2c/busses/i2c-rk3x.c +++ b/drivers/i2c/busses/i2c-rk3x.c @@ -1240,7 +1240,7 @@ static int rk3x_i2c_probe(struct platform_device *pdev) /* use common interface to get I2C timing properties */ i2c_parse_fw_timings(&pdev->dev, &i2c->t, true); - strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name)); + strscpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name)); i2c->adap.owner = THIS_MODULE; i2c->adap.algo = &rk3x_i2c_algorithm; i2c->adap.retries = 3; diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c index b49a1b170bb2..36dab9cd208c 100644 --- a/drivers/i2c/busses/i2c-s3c2410.c +++ b/drivers/i2c/busses/i2c-s3c2410.c @@ -1076,7 +1076,7 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev) else s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c); - strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); + strscpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); i2c->adap.owner = THIS_MODULE; i2c->adap.algo = &s3c24xx_i2c_algorithm; i2c->adap.retries = 2; diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c index 72f024a0c363..29330ee64c9c 100644 --- a/drivers/i2c/busses/i2c-sh_mobile.c +++ b/drivers/i2c/busses/i2c-sh_mobile.c @@ -940,7 +940,7 @@ static int sh_mobile_i2c_probe(struct platform_device *dev) adap->nr = dev->id; adap->dev.of_node = dev->dev.of_node; - strlcpy(adap->name, dev->name, sizeof(adap->name)); + strscpy(adap->name, dev->name, sizeof(adap->name)); spin_lock_init(&pd->lock); init_waitqueue_head(&pd->wait); diff --git a/drivers/i2c/busses/i2c-simtec.c b/drivers/i2c/busses/i2c-simtec.c index 458c7bcf1d24..87701744752f 100644 --- a/drivers/i2c/busses/i2c-simtec.c +++ b/drivers/i2c/busses/i2c-simtec.c @@ -99,7 +99,7 @@ static int simtec_i2c_probe(struct platform_device *dev) pd->adap.algo_data = &pd->bit; pd->adap.dev.parent = &dev->dev; - strlcpy(pd->adap.name, "Simtec I2C", sizeof(pd->adap.name)); + strscpy(pd->adap.name, "Simtec I2C", sizeof(pd->adap.name)); pd->bit.data = pd; pd->bit.setsda = simtec_i2c_setsda; diff --git a/drivers/i2c/busses/i2c-taos-evm.c b/drivers/i2c/busses/i2c-taos-evm.c index b4050f5b6746..b0f0120793e1 100644 --- a/drivers/i2c/busses/i2c-taos-evm.c +++ b/drivers/i2c/busses/i2c-taos-evm.c @@ -239,7 +239,7 @@ static int taos_connect(struct serio *serio, struct serio_driver *drv) dev_err(&serio->dev, "TAOS EVM identification failed\n"); goto exit_close; } - strlcpy(adapter->name, name, sizeof(adapter->name)); + strscpy(adapter->name, name, sizeof(adapter->name)); /* Turn echo off for better performance */ taos->state = TAOS_STATE_EOFF; diff --git a/drivers/i2c/busses/i2c-tegra-bpmp.c b/drivers/i2c/busses/i2c-tegra-bpmp.c index ec0c7cad4240..95139985b2d5 100644 --- a/drivers/i2c/busses/i2c-tegra-bpmp.c +++ b/drivers/i2c/busses/i2c-tegra-bpmp.c @@ -305,7 +305,7 @@ static int tegra_bpmp_i2c_probe(struct platform_device *pdev) i2c_set_adapdata(&i2c->adapter, i2c); i2c->adapter.owner = THIS_MODULE; - strlcpy(i2c->adapter.name, "Tegra BPMP I2C adapter", + strscpy(i2c->adapter.name, "Tegra BPMP I2C adapter", sizeof(i2c->adapter.name)); i2c->adapter.algo = &tegra_bpmp_i2c_algo; i2c->adapter.dev.parent = &pdev->dev; diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 2941e42aa6a0..031c78ac42e6 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -1825,7 +1825,7 @@ static int tegra_i2c_probe(struct platform_device *pdev) if (i2c_dev->hw->supports_bus_clear) i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info; - strlcpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev), + strscpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev), sizeof(i2c_dev->adapter.name)); err = i2c_add_numbered_adapter(&i2c_dev->adapter); diff --git a/drivers/i2c/busses/i2c-uniphier-f.c b/drivers/i2c/busses/i2c-uniphier-f.c index cb4666c54a23..d7b622891e52 100644 --- a/drivers/i2c/busses/i2c-uniphier-f.c +++ b/drivers/i2c/busses/i2c-uniphier-f.c @@ -564,7 +564,7 @@ static int uniphier_fi2c_probe(struct platform_device *pdev) priv->adap.algo = &uniphier_fi2c_algo; priv->adap.dev.parent = dev; priv->adap.dev.of_node = dev->of_node; - strlcpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name)); + strscpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name)); priv->adap.bus_recovery_info = &uniphier_fi2c_bus_recovery_info; i2c_set_adapdata(&priv->adap, priv); platform_set_drvdata(pdev, priv); diff --git a/drivers/i2c/busses/i2c-uniphier.c b/drivers/i2c/busses/i2c-uniphier.c index ee00a44bf4c7..e3ebae381f08 100644 --- a/drivers/i2c/busses/i2c-uniphier.c +++ b/drivers/i2c/busses/i2c-uniphier.c @@ -358,7 +358,7 @@ static int uniphier_i2c_probe(struct platform_device *pdev) priv->adap.algo = &uniphier_i2c_algo; priv->adap.dev.parent = dev; priv->adap.dev.of_node = dev->of_node; - strlcpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name)); + strscpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name)); priv->adap.bus_recovery_info = &uniphier_i2c_bus_recovery_info; i2c_set_adapdata(&priv->adap, priv); platform_set_drvdata(pdev, priv); diff --git a/drivers/i2c/busses/i2c-versatile.c b/drivers/i2c/busses/i2c-versatile.c index 8d980b1374a8..1ab419f8fa52 100644 --- a/drivers/i2c/busses/i2c-versatile.c +++ b/drivers/i2c/busses/i2c-versatile.c @@ -79,7 +79,7 @@ static int i2c_versatile_probe(struct platform_device *dev) writel(SCL | SDA, i2c->base + I2C_CONTROLS); i2c->adap.owner = THIS_MODULE; - strlcpy(i2c->adap.name, "Versatile I2C adapter", sizeof(i2c->adap.name)); + strscpy(i2c->adap.name, "Versatile I2C adapter", sizeof(i2c->adap.name)); i2c->adap.algo_data = &i2c->algo; i2c->adap.dev.parent = &dev->dev; i2c->adap.dev.of_node = dev->dev.of_node; diff --git a/drivers/i2c/busses/i2c-wmt.c b/drivers/i2c/busses/i2c-wmt.c index 88f5aafdce5b..7d4bc8736079 100644 --- a/drivers/i2c/busses/i2c-wmt.c +++ b/drivers/i2c/busses/i2c-wmt.c @@ -413,7 +413,7 @@ static int wmt_i2c_probe(struct platform_device *pdev) adap = &i2c_dev->adapter; i2c_set_adapdata(adap, i2c_dev); - strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name)); + strscpy(adap->name, "WMT I2C adapter", sizeof(adap->name)); adap->owner = THIS_MODULE; adap->algo = &wmt_i2c_algo; adap->dev.parent = &pdev->dev; -- cgit v1.2.3 From 0b0221d9cd330e3d9c4cb0a257b92af2a6ca2ed0 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 11 Aug 2022 14:08:08 +0200 Subject: i2c: move core from strlcpy to strscpy Follow the advice of the below link and prefer 'strscpy'. Conversion is easy because no code used the return value. It has been done with a simple sed invocation. Link: https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=V6A6G1oUZcprmknw@mail.gmail.com/ Signed-off-by: Wolfram Sang Signed-off-by: Wolfram Sang --- drivers/i2c/i2c-core-base.c | 2 +- drivers/i2c/i2c-smbus.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c index 10f35f942066..91007558bcb2 100644 --- a/drivers/i2c/i2c-core-base.c +++ b/drivers/i2c/i2c-core-base.c @@ -933,7 +933,7 @@ i2c_new_client_device(struct i2c_adapter *adap, struct i2c_board_info const *inf client->init_irq = i2c_dev_irq_from_resources(info->resources, info->num_resources); - strlcpy(client->name, info->type, sizeof(client->name)); + strscpy(client->name, info->type, sizeof(client->name)); status = i2c_check_addr_validity(client->addr, client->flags); if (status) { diff --git a/drivers/i2c/i2c-smbus.c b/drivers/i2c/i2c-smbus.c index 775332945ad0..8ba9b59a3c40 100644 --- a/drivers/i2c/i2c-smbus.c +++ b/drivers/i2c/i2c-smbus.c @@ -391,7 +391,7 @@ void i2c_register_spd(struct i2c_adapter *adap) unsigned short addr_list[2]; memset(&info, 0, sizeof(struct i2c_board_info)); - strlcpy(info.type, name, I2C_NAME_SIZE); + strscpy(info.type, name, I2C_NAME_SIZE); addr_list[0] = 0x50 + n; addr_list[1] = I2C_CLIENT_END; -- cgit v1.2.3 From 9bbebdf77890358304c7b55a02228cf00deec4cb Mon Sep 17 00:00:00 2001 From: Luca Ceresoli Date: Mon, 8 Aug 2022 16:17:00 +0200 Subject: docs: i2c: i2c-protocol: update introductory paragraph This sentence dates back to the pre-git era and it does not look very professional... As there is no clear definition of "finished", and given this page is already a pretty good overview, not to mention it is not the kernel responsibility to document the protocol in detail, let's update the text accordingly. Signed-off-by: Luca Ceresoli Signed-off-by: Wolfram Sang --- Documentation/i2c/i2c-protocol.rst | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/i2c/i2c-protocol.rst b/Documentation/i2c/i2c-protocol.rst index b2092f8f815d..9ecf03f5de33 100644 --- a/Documentation/i2c/i2c-protocol.rst +++ b/Documentation/i2c/i2c-protocol.rst @@ -2,7 +2,8 @@ The I2C Protocol ================ -This document describes the I2C protocol. Or will, when it is finished :-) +This document is an overview of the basic I2C transactions and the kernel +APIs to perform them. Key to symbols ============== -- cgit v1.2.3 From 24d129d4f2bd01a085eb18ac7abb5612796209d8 Mon Sep 17 00:00:00 2001 From: Luca Ceresoli Date: Mon, 8 Aug 2022 16:17:01 +0200 Subject: docs: i2c: i2c-protocol,smbus-protocol: remove nonsense words "as usual" does not mean much here, especially as these are introductory sections and 10-bit addressing hasn't been introduced yet. Signed-off-by: Luca Ceresoli Signed-off-by: Wolfram Sang --- Documentation/i2c/i2c-protocol.rst | 2 +- Documentation/i2c/smbus-protocol.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/i2c/i2c-protocol.rst b/Documentation/i2c/i2c-protocol.rst index 9ecf03f5de33..7ffada1f3335 100644 --- a/Documentation/i2c/i2c-protocol.rst +++ b/Documentation/i2c/i2c-protocol.rst @@ -13,7 +13,7 @@ S Start condition P Stop condition Rd/Wr (1 bit) Read/Write bit. Rd equals 1, Wr equals 0. A, NA (1 bit) Acknowledge (ACK) and Not Acknowledge (NACK) bit -Addr (7 bits) I2C 7 bit address. Note that this can be expanded as usual to +Addr (7 bits) I2C 7 bit address. Note that this can be expanded to get a 10 bit I2C address. Comm (8 bits) Command byte, a data byte which often selects a register on the device. diff --git a/Documentation/i2c/smbus-protocol.rst b/Documentation/i2c/smbus-protocol.rst index 00d8e17d0aca..55e209c7e520 100644 --- a/Documentation/i2c/smbus-protocol.rst +++ b/Documentation/i2c/smbus-protocol.rst @@ -41,7 +41,7 @@ Sr Repeated start condition, used to switch from write to P Stop condition Rd/Wr (1 bit) Read/Write bit. Rd equals 1, Wr equals 0. A, NA (1 bit) Acknowledge (ACK) and Not Acknowledge (NACK) bit -Addr (7 bits) I2C 7 bit address. Note that this can be expanded as usual to +Addr (7 bits) I2C 7 bit address. Note that this can be expanded to get a 10 bit I2C address. Comm (8 bits) Command byte, a data byte which often selects a register on the device. -- cgit v1.2.3 From 0721ceee2fa7e64c1bc83b2d7aa4b8f284bc7aa0 Mon Sep 17 00:00:00 2001 From: Luca Ceresoli Date: Mon, 8 Aug 2022 16:17:02 +0200 Subject: docs: i2c: i2c-protocol: remove unused legend items "Comm", "Count", "DataLow", "DataHigh" are not used in this section. Signed-off-by: Luca Ceresoli Signed-off-by: Wolfram Sang --- Documentation/i2c/i2c-protocol.rst | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/Documentation/i2c/i2c-protocol.rst b/Documentation/i2c/i2c-protocol.rst index 7ffada1f3335..df0febfe6410 100644 --- a/Documentation/i2c/i2c-protocol.rst +++ b/Documentation/i2c/i2c-protocol.rst @@ -15,11 +15,7 @@ Rd/Wr (1 bit) Read/Write bit. Rd equals 1, Wr equals 0. A, NA (1 bit) Acknowledge (ACK) and Not Acknowledge (NACK) bit Addr (7 bits) I2C 7 bit address. Note that this can be expanded to get a 10 bit I2C address. -Comm (8 bits) Command byte, a data byte which often selects a register on - the device. -Data (8 bits) A plain data byte. Sometimes, I write DataLow, DataHigh - for 16 bit data. -Count (8 bits) A data byte containing the length of a block operation. +Data (8 bits) A plain data byte. [..] Data sent by I2C device, as opposed to data sent by the host adapter. -- cgit v1.2.3 From 6c12ec2772fa01516fde5685644b129c6f236ce2 Mon Sep 17 00:00:00 2001 From: Luca Ceresoli Date: Mon, 8 Aug 2022 16:17:03 +0200 Subject: docs: i2c: smbus-protocol: improve DataLow/DataHigh definition Use a more professional wording. Signed-off-by: Luca Ceresoli Reviewed-by: Bagas Sanjaya Signed-off-by: Wolfram Sang --- Documentation/i2c/smbus-protocol.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/i2c/smbus-protocol.rst b/Documentation/i2c/smbus-protocol.rst index 55e209c7e520..4942c4cad4ad 100644 --- a/Documentation/i2c/smbus-protocol.rst +++ b/Documentation/i2c/smbus-protocol.rst @@ -45,8 +45,8 @@ Addr (7 bits) I2C 7 bit address. Note that this can be expanded to get a 10 bit I2C address. Comm (8 bits) Command byte, a data byte which often selects a register on the device. -Data (8 bits) A plain data byte. Sometimes, I write DataLow, DataHigh - for 16 bit data. +Data (8 bits) A plain data byte. DataLow and DataHigh represent the low and + high byte of a 16 bit word. Count (8 bits) A data byte containing the length of a block operation. [..] Data sent by I2C device, as opposed to data sent by the host -- cgit v1.2.3 From 43310e279d7b40c84bd41b30f2fa53d9bc05b268 Mon Sep 17 00:00:00 2001 From: Luca Ceresoli Date: Mon, 8 Aug 2022 16:17:04 +0200 Subject: docs: i2c: instantiating-devices: add syntax coloring to dts and C blocks These blocks can be nicely coloured via Sphinx. Signed-off-by: Luca Ceresoli Signed-off-by: Wolfram Sang --- Documentation/i2c/instantiating-devices.rst | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/Documentation/i2c/instantiating-devices.rst b/Documentation/i2c/instantiating-devices.rst index 890c9360ce19..3ea056a95812 100644 --- a/Documentation/i2c/instantiating-devices.rst +++ b/Documentation/i2c/instantiating-devices.rst @@ -31,7 +31,9 @@ Declare the I2C devices via devicetree On platforms using devicetree, the declaration of I2C devices is done in subnodes of the master controller. -Example:: +Example: + +.. code-block:: dts i2c1: i2c@400a0000 { /* ... master properties skipped ... */ @@ -71,7 +73,9 @@ code. Instantiating I2C devices via board files is done with an array of struct i2c_board_info which is registered by calling i2c_register_board_info(). -Example (from omap2 h4):: +Example (from omap2 h4): + +.. code-block:: c static struct i2c_board_info h4_i2c_board_info[] __initdata = { { @@ -111,7 +115,9 @@ bus in advance, so the method 1 described above can't be used. Instead, you can instantiate your I2C devices explicitly. This is done by filling a struct i2c_board_info and calling i2c_new_client_device(). -Example (from the sfe4001 network driver):: +Example (from the sfe4001 network driver): + +.. code-block:: c static struct i2c_board_info sfe4001_hwmon_info = { I2C_BOARD_INFO("max6647", 0x4e), @@ -136,7 +142,9 @@ it may have different addresses from one board to the next (manufacturer changing its design without notice). In this case, you can call i2c_new_scanned_device() instead of i2c_new_client_device(). -Example (from the nxp OHCI driver):: +Example (from the nxp OHCI driver): + +.. code-block:: c static const unsigned short normal_i2c[] = { 0x2c, 0x2d, I2C_CLIENT_END }; -- cgit v1.2.3 From 3dbe5829408bc1586f75b4667ef60e5aab0209c7 Mon Sep 17 00:00:00 2001 From: Yipeng Zou Date: Thu, 21 Jul 2022 14:58:20 +0800 Subject: riscv:uprobe fix SR_SPIE set/clear handling In riscv the process of uprobe going to clear spie before exec the origin insn,and set spie after that.But When access the page which origin insn has been placed a page fault may happen and irq was disabled in arch_uprobe_pre_xol function,It cause a WARN as follows. There is no need to clear/set spie in arch_uprobe_pre/post/abort_xol. We can just remove it. [ 31.684157] BUG: sleeping function called from invalid context at kernel/locking/rwsem.c:1488 [ 31.684677] in_atomic(): 0, irqs_disabled(): 1, non_block: 0, pid: 76, name: work [ 31.684929] preempt_count: 0, expected: 0 [ 31.685969] CPU: 2 PID: 76 Comm: work Tainted: G [ 31.686542] Hardware name: riscv-virtio,qemu (DT) [ 31.686797] Call Trace: [ 31.687053] [] dump_backtrace+0x30/0x38 [ 31.687699] [] show_stack+0x40/0x4c [ 31.688141] [] dump_stack_lvl+0x44/0x5c [ 31.688396] [] dump_stack+0x18/0x20 [ 31.688653] [] __might_resched+0x114/0x122 [ 31.688948] [] __might_sleep+0x50/0x7a [ 31.689435] [] down_read+0x30/0x130 [ 31.689728] [] do_page_fault+0x166/x446 [ 31.689997] [] ret_from_exception+0x0/0xc Fixes: 74784081aac8 ("riscv: Add uprobes supported") Signed-off-by: Yipeng Zou Reviewed-by: Guo Ren Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220721065820.245755-1-zouyipeng@huawei.com Signed-off-by: Palmer Dabbelt --- arch/riscv/kernel/probes/uprobes.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/riscv/kernel/probes/uprobes.c b/arch/riscv/kernel/probes/uprobes.c index 7a057b5f0adc..c976a21cd4bd 100644 --- a/arch/riscv/kernel/probes/uprobes.c +++ b/arch/riscv/kernel/probes/uprobes.c @@ -59,8 +59,6 @@ int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) instruction_pointer_set(regs, utask->xol_vaddr); - regs->status &= ~SR_SPIE; - return 0; } @@ -72,8 +70,6 @@ int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) instruction_pointer_set(regs, utask->vaddr + auprobe->insn_size); - regs->status |= SR_SPIE; - return 0; } @@ -111,8 +107,6 @@ void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) * address. */ instruction_pointer_set(regs, utask->vaddr); - - regs->status &= ~SR_SPIE; } bool arch_uretprobe_is_alive(struct return_instance *ret, enum rp_check ctx, -- cgit v1.2.3 From 55bdfb8b55ae4bff4864d61a250abe0af86adc69 Mon Sep 17 00:00:00 2001 From: Luca Ceresoli Date: Mon, 8 Aug 2022 16:17:07 +0200 Subject: docs: i2c: i2c-sysfs: improve wording Improve wording in a couple sentences. Signed-off-by: Luca Ceresoli [wsa: improved a little more] Signed-off-by: Wolfram Sang --- Documentation/i2c/i2c-sysfs.rst | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/Documentation/i2c/i2c-sysfs.rst b/Documentation/i2c/i2c-sysfs.rst index 6b68b95cd427..dd75008b44c8 100644 --- a/Documentation/i2c/i2c-sysfs.rst +++ b/Documentation/i2c/i2c-sysfs.rst @@ -51,11 +51,10 @@ Google Pixel 3 phone for example:: ``i2c-2`` is an I2C bus whose number is 2, and ``2-0049`` is an I2C device on bus 2 address 0x49 bound with a kernel driver. -Terminologies -============= +Terminology +=========== -First, let us define a couple of terminologies to avoid confusions in the later -sections. +First, let us define some terms to avoid confusion in later sections. (Physical) I2C Bus Controller ----------------------------- @@ -117,7 +116,7 @@ Walk through Logical I2C Bus For the following content, we will use a more complex I2C topology as an example. Here is a brief graph for the I2C topology. If you do not understand -this graph at the first glance, do not be afraid to continue reading this doc +this graph at first glance, do not be afraid to continue reading this doc and review it when you finish reading. :: -- cgit v1.2.3 From fe99b819487dba848cddd3d4bf4beb8e653d7e9c Mon Sep 17 00:00:00 2001 From: Luca Ceresoli Date: Mon, 8 Aug 2022 16:17:08 +0200 Subject: docs: i2c: i2c-sysfs: fix hyperlinks dts files cannot be linked conveniently, thus replace them with literal formatting. The links to other rst pages are broken, fix them using the proper syntax. Fixes: 31df7195b100 ("Documentation: i2c: Add doc for I2C sysfs") Signed-off-by: Luca Ceresoli Signed-off-by: Wolfram Sang --- Documentation/i2c/i2c-sysfs.rst | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/Documentation/i2c/i2c-sysfs.rst b/Documentation/i2c/i2c-sysfs.rst index dd75008b44c8..78c54c658fa1 100644 --- a/Documentation/i2c/i2c-sysfs.rst +++ b/Documentation/i2c/i2c-sysfs.rst @@ -99,9 +99,7 @@ Caveat This may be a confusing part for people who only know about the physical I2C design of a board. It is actually possible to rename the I2C bus physical number to a different number in logical I2C bus level in Device Tree Source (DTS) under -section ``aliases``. See -`arch/arm/boot/dts/nuvoton-npcm730-gsj.dts -<../../arch/arm/boot/dts/nuvoton-npcm730-gsj.dts>`_ +section ``aliases``. See ``arch/arm/boot/dts/nuvoton-npcm730-gsj.dts`` for an example of DTS file. Best Practice: **(To kernel software developers)** It is better to keep the I2C @@ -289,8 +287,7 @@ MUX channel 0, and all the way to ``i2c-19`` for the MUX channel 3. The kernel software developer is able to pin the fanout MUX channels to a static logical I2C bus number in the DTS. This doc will not go through the details on how to implement this in DTS, but we can see an example in: -`arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts -<../../arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts>`_ +``arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts`` In the above example, there is an 8-channel I2C MUX at address 0x70 on physical I2C bus 2. The channel 2 of the MUX is defined as ``imux18`` in DTS, @@ -382,13 +379,9 @@ Sysfs for the I2C sensor device:: For more info on the Hwmon Sysfs, refer to the doc: -`Naming and data format standards for sysfs files -<../hwmon/sysfs-interface.rst>`_ +../hwmon/sysfs-interface.rst Instantiate I2C Devices in I2C Sysfs ------------------------------------ -Refer to the doc: - -`How to instantiate I2C devices, Method 4: Instantiate from user-space -`_ +Refer to section "Method 4: Instantiate from user-space" of instantiating-devices.rst -- cgit v1.2.3 From bf952a290f7a9d818204b9b68e861655f8b15a65 Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Fri, 22 Jul 2022 09:50:44 -0700 Subject: RISC-V: Add SSTC extension CSR details This patch just introduces the required CSR fields related to the SSTC extension. Reviewed-by: Anup Patel Signed-off-by: Atish Patra Link: https://lore.kernel.org/r/20220722165047.519994-2-atishp@rivosinc.com Signed-off-by: Palmer Dabbelt --- arch/riscv/include/asm/csr.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 6d85655e7edf..34f4eaf326c4 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -235,6 +235,9 @@ #define CSR_SIP 0x144 #define CSR_SATP 0x180 +#define CSR_STIMECMP 0x14D +#define CSR_STIMECMPH 0x15D + #define CSR_VSSTATUS 0x200 #define CSR_VSIE 0x204 #define CSR_VSTVEC 0x205 @@ -244,6 +247,8 @@ #define CSR_VSTVAL 0x243 #define CSR_VSIP 0x244 #define CSR_VSATP 0x280 +#define CSR_VSTIMECMP 0x24D +#define CSR_VSTIMECMPH 0x25D #define CSR_HSTATUS 0x600 #define CSR_HEDELEG 0x602 -- cgit v1.2.3 From 464b0187ff94fcc629fe7cd350e16a3b9e80ed9e Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Fri, 22 Jul 2022 09:50:45 -0700 Subject: RISC-V: Enable sstc extension parsing from DT The ISA extension framework now allows parsing any multi-letter ISA extension. Enable that for sstc extension. Reviewed-by: Anup Patel Signed-off-by: Atish Patra Link: https://lore.kernel.org/r/20220722165047.519994-3-atishp@rivosinc.com Signed-off-by: Palmer Dabbelt --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 4e2486881840..b186fff75198 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -53,6 +53,7 @@ extern unsigned long elf_hwcap; enum riscv_isa_ext_id { RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, RISCV_ISA_EXT_SVPBMT, + RISCV_ISA_EXT_SSTC, RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index fba9e9f46a8c..0016d9337fe0 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -89,6 +89,7 @@ int riscv_of_parent_hartid(struct device_node *node) static struct riscv_isa_ext_data isa_ext_arr[] = { __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), + __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), }; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index a6f62a6d1edd..d1d83cd9fd4b 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -199,6 +199,7 @@ void __init riscv_fill_hwcap(void) } else { SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); + SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); } #undef SET_ISA_EXT_MAP } -- cgit v1.2.3 From 9f7a8ff6391fd5363363b8e5c8b1462a07922368 Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Fri, 22 Jul 2022 09:50:46 -0700 Subject: RISC-V: Prefer sstc extension if available RISC-V ISA has sstc extension which allows updating the next clock event via a CSR (stimecmp) instead of an SBI call. This should happen dynamically if sstc extension is available. Otherwise, it will fallback to SBI call to maintain backward compatibility. Reviewed-by: Anup Patel Signed-off-by: Atish Patra Reviewed-by: Guo Ren Link: https://lore.kernel.org/r/20220722165047.519994-4-atishp@rivosinc.com Signed-off-by: Palmer Dabbelt --- drivers/clocksource/timer-riscv.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 593d5a957b69..05f6cf067289 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -7,6 +7,9 @@ * either be read from the "time" and "timeh" CSRs, and can use the SBI to * setup events, or directly accessed using MMIO registers. */ + +#define pr_fmt(fmt) "riscv-timer: " fmt + #include #include #include @@ -20,14 +23,28 @@ #include #include #include +#include #include #include +static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available); + static int riscv_clock_next_event(unsigned long delta, struct clock_event_device *ce) { + u64 next_tval = get_cycles64() + delta; + csr_set(CSR_IE, IE_TIE); - sbi_set_timer(get_cycles64() + delta); + if (static_branch_likely(&riscv_sstc_available)) { +#if defined(CONFIG_32BIT) + csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF); + csr_write(CSR_STIMECMPH, next_tval >> 32); +#else + csr_write(CSR_STIMECMP, next_tval); +#endif + } else + sbi_set_timer(next_tval); + return 0; } @@ -165,6 +182,12 @@ static int __init riscv_timer_init_dt(struct device_node *n) if (error) pr_err("cpu hp setup state failed for RISCV timer [%d]\n", error); + + if (riscv_isa_extension_available(NULL, SSTC)) { + pr_info("Timer interrupt in S-mode is available via sstc extension\n"); + static_branch_enable(&riscv_sstc_available); + } + return error; } -- cgit v1.2.3 From 696d0a4cb8009af7bb3b45dc4d94679a7c9a2318 Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Thu, 11 Aug 2022 20:04:09 +0300 Subject: perf script: Fix missing guest option documentation The 'perf script' documentation is missing several options relating to guests. Add them. Fixes: 15a108af1a18b597 ("perf script: Allow specifying the files to process guest samples") Signed-off-by: Adrian Hunter Cc: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Link: https://lore.kernel.org/r/20220811170411.84154-2-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Documentation/perf-script.txt | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/tools/perf/Documentation/perf-script.txt b/tools/perf/Documentation/perf-script.txt index 4c95e79e2c39..48ee42a891b6 100644 --- a/tools/perf/Documentation/perf-script.txt +++ b/tools/perf/Documentation/perf-script.txt @@ -487,6 +487,29 @@ include::itrace.txt[] For itrace only show specified functions and their callees for itrace. Multiple functions can be separated by comma. +--guestmount=:: + Guest OS root file system mount directory. Users mount guest OS + root directories under by a specific filesystem access method, + typically, sshfs. + For example, start 2 guest OS, one's pid is 8888 and the other's is 9999: +[verse] + $ mkdir \~/guestmount + $ cd \~/guestmount + $ sshfs -o allow_other,direct_io -p 5551 localhost:/ 8888/ + $ sshfs -o allow_other,direct_io -p 5552 localhost:/ 9999/ + $ perf script --guestmount=~/guestmount + +--guestkallsyms=:: + Guest OS /proc/kallsyms file copy. perf reads it to get guest + kernel symbols. Users copy it out from guest OS. + +--guestmodules=:: + Guest OS /proc/modules file copy. perf reads it to get guest + kernel module information. Users copy it out from guest OS. + +--guestvmlinux=:: + Guest OS kernel vmlinux. + --switch-on EVENT_NAME:: Only consider events after this event is found. -- cgit v1.2.3 From d9ca43c06fb76d2829675b764093c7094ab636f0 Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Thu, 11 Aug 2022 20:04:10 +0300 Subject: perf inject: Fix missing guestmount option documentation The 'perf inject' documentation is missing the guestmount option. Add it. Fixes: 97406a7e4fa6e5ca ("perf inject: Add support for injecting guest sideband events") Signed-off-by: Adrian Hunter Cc: Adrian Hunter Cc: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Link: https://lore.kernel.org/r/20220811170411.84154-3-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Documentation/perf-inject.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/tools/perf/Documentation/perf-inject.txt b/tools/perf/Documentation/perf-inject.txt index 646aa31586ed..c741ca2107b1 100644 --- a/tools/perf/Documentation/perf-inject.txt +++ b/tools/perf/Documentation/perf-inject.txt @@ -102,6 +102,18 @@ include::itrace.txt[] should be used, and also --buildid-all and --switch-events may be useful. +--guestmount=:: + Guest OS root file system mount directory. Users mount guest OS + root directories under by a specific filesystem access method, + typically, sshfs. + For example, start 2 guest OS, one's pid is 8888 and the other's is 9999: +[verse] + $ mkdir \~/guestmount + $ cd \~/guestmount + $ sshfs -o allow_other,direct_io -p 5551 localhost:/ 8888/ + $ sshfs -o allow_other,direct_io -p 5552 localhost:/ 9999/ + $ perf inject --guestmount=~/guestmount + SEE ALSO -------- linkperf:perf-record[1], linkperf:perf-report[1], linkperf:perf-archive[1], -- cgit v1.2.3 From 53e76d35f797b2975ad9b2934e668e59abba1f10 Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Thu, 11 Aug 2022 20:04:11 +0300 Subject: perf tools: Tidy guest option documentation Move common guest options into include files. Use attribute substitution to customize an example, using "[verse]" to define the block instead of a "literal" block which does not permit substitution. Signed-off-by: Adrian Hunter Cc: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Link: https://lore.kernel.org/r/20220811170411.84154-4-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Documentation/guest-files.txt | 16 ++++++++++++++++ tools/perf/Documentation/guestmount.txt | 11 +++++++++++ tools/perf/Documentation/perf-inject.txt | 14 +++----------- tools/perf/Documentation/perf-kvm.txt | 25 +++++-------------------- tools/perf/Documentation/perf-script.txt | 29 +++-------------------------- 5 files changed, 38 insertions(+), 57 deletions(-) create mode 100644 tools/perf/Documentation/guest-files.txt create mode 100644 tools/perf/Documentation/guestmount.txt diff --git a/tools/perf/Documentation/guest-files.txt b/tools/perf/Documentation/guest-files.txt new file mode 100644 index 000000000000..8cc0b092f996 --- /dev/null +++ b/tools/perf/Documentation/guest-files.txt @@ -0,0 +1,16 @@ +include::guestmount.txt[] + +--guestkallsyms=:: + Guest OS /proc/kallsyms file copy. perf reads it to get guest + kernel symbols. Users copy it out from guest OS. + +--guestmodules=:: + Guest OS /proc/modules file copy. perf reads it to get guest + kernel module information. Users copy it out from guest OS. + +--guestvmlinux=:: + Guest OS kernel vmlinux. + +--guest-code:: + Indicate that guest code can be found in the hypervisor process, + which is a common case for KVM test programs. diff --git a/tools/perf/Documentation/guestmount.txt b/tools/perf/Documentation/guestmount.txt new file mode 100644 index 000000000000..6edf12363add --- /dev/null +++ b/tools/perf/Documentation/guestmount.txt @@ -0,0 +1,11 @@ +--guestmount=:: + Guest OS root file system mount directory. Users mount guest OS + root directories under by a specific filesystem access method, + typically, sshfs. + For example, start 2 guest OS, one's pid is 8888 and the other's is 9999: +[verse] + $ mkdir \~/guestmount + $ cd \~/guestmount + $ sshfs -o allow_other,direct_io -p 5551 localhost:/ 8888/ + $ sshfs -o allow_other,direct_io -p 5552 localhost:/ 9999/ + $ perf {GMEXAMPLECMD} --guestmount=~/guestmount {GMEXAMPLESUBCMD} diff --git a/tools/perf/Documentation/perf-inject.txt b/tools/perf/Documentation/perf-inject.txt index c741ca2107b1..ffc293fdf61d 100644 --- a/tools/perf/Documentation/perf-inject.txt +++ b/tools/perf/Documentation/perf-inject.txt @@ -102,17 +102,9 @@ include::itrace.txt[] should be used, and also --buildid-all and --switch-events may be useful. ---guestmount=:: - Guest OS root file system mount directory. Users mount guest OS - root directories under by a specific filesystem access method, - typically, sshfs. - For example, start 2 guest OS, one's pid is 8888 and the other's is 9999: -[verse] - $ mkdir \~/guestmount - $ cd \~/guestmount - $ sshfs -o allow_other,direct_io -p 5551 localhost:/ 8888/ - $ sshfs -o allow_other,direct_io -p 5552 localhost:/ 9999/ - $ perf inject --guestmount=~/guestmount +:GMEXAMPLECMD: inject +:GMEXAMPLESUBCMD: +include::guestmount.txt[] SEE ALSO -------- diff --git a/tools/perf/Documentation/perf-kvm.txt b/tools/perf/Documentation/perf-kvm.txt index 83c742adf86e..2ad3f5d9f72b 100644 --- a/tools/perf/Documentation/perf-kvm.txt +++ b/tools/perf/Documentation/perf-kvm.txt @@ -77,26 +77,11 @@ OPTIONS Collect host side performance profile. --guest:: Collect guest side performance profile. ---guestmount=:: - Guest os root file system mount directory. Users mounts guest os - root directories under by a specific filesystem access method, - typically, sshfs. For example, start 2 guest os. The one's pid is 8888 - and the other's is 9999. - #mkdir ~/guestmount; cd ~/guestmount - #sshfs -o allow_other,direct_io -p 5551 localhost:/ 8888/ - #sshfs -o allow_other,direct_io -p 5552 localhost:/ 9999/ - #perf kvm --host --guest --guestmount=~/guestmount top ---guestkallsyms=:: - Guest os /proc/kallsyms file copy. 'perf' kvm' reads it to get guest - kernel symbols. Users copy it out from guest os. ---guestmodules=:: - Guest os /proc/modules file copy. 'perf' kvm' reads it to get guest - kernel module information. Users copy it out from guest os. ---guestvmlinux=:: - Guest os kernel vmlinux. ---guest-code:: - Indicate that guest code can be found in the hypervisor process, - which is a common case for KVM test programs. + +:GMEXAMPLECMD: kvm --host --guest +:GMEXAMPLESUBCMD: top +include::guest-files.txt[] + -v:: --verbose:: Be more verbose (show counter open errors, etc). diff --git a/tools/perf/Documentation/perf-script.txt b/tools/perf/Documentation/perf-script.txt index 48ee42a891b6..68e37de5fae4 100644 --- a/tools/perf/Documentation/perf-script.txt +++ b/tools/perf/Documentation/perf-script.txt @@ -487,29 +487,6 @@ include::itrace.txt[] For itrace only show specified functions and their callees for itrace. Multiple functions can be separated by comma. ---guestmount=:: - Guest OS root file system mount directory. Users mount guest OS - root directories under by a specific filesystem access method, - typically, sshfs. - For example, start 2 guest OS, one's pid is 8888 and the other's is 9999: -[verse] - $ mkdir \~/guestmount - $ cd \~/guestmount - $ sshfs -o allow_other,direct_io -p 5551 localhost:/ 8888/ - $ sshfs -o allow_other,direct_io -p 5552 localhost:/ 9999/ - $ perf script --guestmount=~/guestmount - ---guestkallsyms=:: - Guest OS /proc/kallsyms file copy. perf reads it to get guest - kernel symbols. Users copy it out from guest OS. - ---guestmodules=:: - Guest OS /proc/modules file copy. perf reads it to get guest - kernel module information. Users copy it out from guest OS. - ---guestvmlinux=:: - Guest OS kernel vmlinux. - --switch-on EVENT_NAME:: Only consider events after this event is found. @@ -530,9 +507,9 @@ include::itrace.txt[] The known limitations include exception handing such as setjmp/longjmp will have calls/returns not match. ---guest-code:: - Indicate that guest code can be found in the hypervisor process, - which is a common case for KVM test programs. +:GMEXAMPLECMD: script +:GMEXAMPLESUBCMD: +include::guest-files.txt[] SEE ALSO -------- -- cgit v1.2.3 From acc1b919f47926b089be21b8aaa29ec91fef0aa2 Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Mon, 11 Jul 2022 10:46:28 -0700 Subject: RISC-V: Fix counter restart during overflow for RV32 Pass the upper half of the initial value of the counter correctly for RV32. Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") Signed-off-by: Atish Patra Reviewed-by: Guo Ren Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220711174632.4186047-2-atishp@rivosinc.com Signed-off-by: Palmer Dabbelt --- drivers/perf/riscv_pmu_sbi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index dca3537a8dcc..0cb694b794ae 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -525,8 +525,13 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, hwc = &event->hw; max_period = riscv_pmu_ctr_get_width_mask(event); init_val = local64_read(&hwc->prev_count) & max_period; +#if defined(CONFIG_32BIT) + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, + flag, init_val, init_val >> 32, 0); +#else sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, flag, init_val, 0, 0); +#endif } ctr_ovf_mask = ctr_ovf_mask >> 1; idx++; -- cgit v1.2.3 From 133a6d1fe7d7ad8393af025c4dde379c0616661f Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Mon, 11 Jul 2022 10:46:29 -0700 Subject: RISC-V: Update user page mapping only once during start Currently, riscv_pmu_event_set_period updates the userpage mapping. However, the caller of riscv_pmu_event_set_period should update the userpage mapping because the counter can not be updated/started from set_period function in counter overflow path. Invoke the perf_event_update_userpage at the caller so that it doesn't get invoked twice during counter start path. Fixes: f5bfa23f576f ("RISC-V: Add a perf core library for pmu drivers") Reviewed-by: Anup Patel Signed-off-by: Atish Patra Reviewed-by: Guo Ren Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220711174632.4186047-3-atishp@rivosinc.com Signed-off-by: Palmer Dabbelt --- drivers/perf/riscv_pmu.c | 1 - drivers/perf/riscv_pmu_sbi.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c index b2b8d2074ed0..130b9f1a40e0 100644 --- a/drivers/perf/riscv_pmu.c +++ b/drivers/perf/riscv_pmu.c @@ -170,7 +170,6 @@ int riscv_pmu_event_set_period(struct perf_event *event) left = (max_period >> 1); local64_set(&hwc->prev_count, (u64)-left); - perf_event_update_userpage(event); return overflow; } diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 0cb694b794ae..3735337a4cfb 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -532,6 +532,7 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, flag, init_val, 0, 0); #endif + perf_event_update_userpage(event); } ctr_ovf_mask = ctr_ovf_mask >> 1; idx++; -- cgit v1.2.3 From 0209b5830bea42dd3ce33ab0397231e67ec3b751 Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Mon, 11 Jul 2022 10:46:30 -0700 Subject: RISC-V: Fix SBI PMU calls for RV32 Some of the SBI PMU calls does not pass 64bit arguments correctly and not under RV32 compile time flags. Currently, this doesn't create any incorrect results as RV64 ignores any value in the additional register and qemu doesn't support raw events. Fix those SBI calls in order to set correct values for RV32. Fixes: e9991434596f ("RISC-V: Add perf platform driver based on SBI PMU extension") Signed-off-by: Atish Patra Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220711174632.4186047-4-atishp@rivosinc.com Signed-off-by: Palmer Dabbelt --- drivers/perf/riscv_pmu_sbi.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 3735337a4cfb..bae614c73b14 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -274,8 +274,13 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event) cflags |= SBI_PMU_CFG_FLAG_SET_UINH; /* retrieve the available counter index */ +#if defined(CONFIG_32BIT) + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, cmask, + cflags, hwc->event_base, hwc->config, hwc->config >> 32); +#else ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, cmask, cflags, hwc->event_base, hwc->config, 0); +#endif if (ret.error) { pr_debug("Not able to find a counter for event %lx config %llx\n", hwc->event_base, hwc->config); @@ -417,8 +422,13 @@ static void pmu_sbi_ctr_start(struct perf_event *event, u64 ival) struct hw_perf_event *hwc = &event->hw; unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE; +#if defined(CONFIG_32BIT) ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx, 1, flag, ival, ival >> 32, 0); +#else + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx, + 1, flag, ival, 0, 0); +#endif if (ret.error && (ret.error != SBI_ERR_ALREADY_STARTED)) pr_err("Starting counter idx %d failed with error %d\n", hwc->idx, sbi_err_map_linux_errno(ret.error)); -- cgit v1.2.3 From 63ba67ebdfd403ef53aa0fefde3a42e505516e8c Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Mon, 11 Jul 2022 10:46:31 -0700 Subject: RISC-V: Move counter info definition to sbi header file Counter info encoding format is defined by the SBI specificaiton. KVM implementation of SBI PMU extension will also leverage this definition. Move the definition to common sbi header file from the sbi pmu driver. Signed-off-by: Atish Patra Link: https://lore.kernel.org/r/20220711174632.4186047-5-atishp@rivosinc.com Signed-off-by: Palmer Dabbelt --- arch/riscv/include/asm/sbi.h | 14 ++++++++++++++ drivers/perf/riscv_pmu_sbi.c | 14 -------------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 9e3c2cf1edaf..d633ac0f5a32 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -122,6 +122,20 @@ enum sbi_ext_pmu_fid { SBI_EXT_PMU_COUNTER_FW_READ, }; +union sbi_pmu_ctr_info { + unsigned long value; + struct { + unsigned long csr:12; + unsigned long width:6; +#if __riscv_xlen == 32 + unsigned long reserved:13; +#else + unsigned long reserved:45; +#endif + unsigned long type:1; + }; +}; + #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(55, 0) #define RISCV_PMU_RAW_EVENT_IDX 0x20000 diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index bae614c73b14..24124546844c 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -21,20 +21,6 @@ #include #include -union sbi_pmu_ctr_info { - unsigned long value; - struct { - unsigned long csr:12; - unsigned long width:6; -#if __riscv_xlen == 32 - unsigned long reserved:13; -#else - unsigned long reserved:45; -#endif - unsigned long type:1; - }; -}; - /* * RISC-V doesn't have hetergenous harts yet. This need to be part of * per_cpu in case of harts with different pmu counters -- cgit v1.2.3 From f829ee7595b5e9a9e5e1cc802224391c61072b38 Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Mon, 11 Jul 2022 10:46:32 -0700 Subject: RISC-V: Improve SBI definitions Fixed few typos and bit fields not aligned with the spec. Define other related macros that will be useful in the future. Signed-off-by: Atish Patra Link: https://lore.kernel.org/r/20220711174632.4186047-6-atishp@rivosinc.com Signed-off-by: Palmer Dabbelt --- arch/riscv/include/asm/sbi.h | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index d633ac0f5a32..2a0ef738695e 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -136,7 +136,7 @@ union sbi_pmu_ctr_info { }; }; -#define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(55, 0) +#define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0) #define RISCV_PMU_RAW_EVENT_IDX 0x20000 /** General pmu event codes specified in SBI PMU extension */ @@ -203,12 +203,26 @@ enum sbi_pmu_ctr_type { SBI_PMU_CTR_TYPE_FW, }; +/* Helper macros to decode event idx */ +#define SBI_PMU_EVENT_IDX_OFFSET 20 +#define SBI_PMU_EVENT_IDX_MASK 0xFFFFF +#define SBI_PMU_EVENT_IDX_CODE_MASK 0xFFFF +#define SBI_PMU_EVENT_IDX_TYPE_MASK 0xF0000 +#define SBI_PMU_EVENT_RAW_IDX 0x20000 +#define SBI_PMU_FIXED_CTR_MASK 0x07 + +#define SBI_PMU_EVENT_CACHE_ID_CODE_MASK 0xFFF8 +#define SBI_PMU_EVENT_CACHE_OP_ID_CODE_MASK 0x06 +#define SBI_PMU_EVENT_CACHE_RESULT_ID_CODE_MASK 0x01 + +#define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF + /* Flags defined for config matching function */ #define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0) #define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1) #define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2) #define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3) -#define SBI_PMU_CFG_FLAG_SET_VSNH (1 << 4) +#define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4) #define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5) #define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6) #define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7) -- cgit v1.2.3 From 4a88c4ec3c2c6743cc4424b51e66a0c034afe507 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Thu, 11 Aug 2022 19:06:38 -0300 Subject: perf arm64: Add missing -I for tools/arch/arm64/include/ to find asm/sysreg.h when building arm_spe.h This cures a current problem where tools/perf/util/arm-spe.c isn't finding a ARM64 specific asm header, so lets add it for now to make progress. Adding a .o specific rule seems clunky, lets try and find if this is really the right solution. Signed-off-by: Leo Yan Reported-by: Suzuki K Poulose Tested-by: Arnaldo Carvalho de Melo Cc: Catalin Marinas Cc: Anshuman Khandual Cc: Will Deacon Cc: James Morse Link: https://lore.kernel.org/lkml/20220811124825.GA868014@leoy-huanghe.lan Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/Build | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/perf/util/Build b/tools/perf/util/Build index d8fe514c9ec9..9dfae1bda9cc 100644 --- a/tools/perf/util/Build +++ b/tools/perf/util/Build @@ -289,6 +289,7 @@ CFLAGS_hweight.o += -Wno-unused-parameter -DETC_PERFCONFIG="BUILD_STR($(ET CFLAGS_parse-events.o += -Wno-redundant-decls CFLAGS_expr.o += -Wno-redundant-decls CFLAGS_header.o += -include $(OUTPUT)PERF-VERSION-FILE +CFLAGS_arm-spe.o += -I$(srctree)/tools/arch/arm64/include/ $(OUTPUT)util/kallsyms.o: ../lib/symbol/kallsyms.c FORCE $(call rule_mkdir) -- cgit v1.2.3 From 2e21bcf0514a3623b41962bf424dec061c02ebc6 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 11 Aug 2022 14:24:37 +0800 Subject: perf tools: Sync addition of PERF_MEM_SNOOPX_PEER Add a flag to the 'perf mem' data struct to signal that a request caused a cache-to-cache transfer of a line from a peer of the requestor and wasn't sourced from a lower cache level. The line being moved from one peer cache to another has latency and performance implications. On Arm64 Neoverse systems the data source can indicate a cache-to-cache transfer but not if the line is dirty or clean, so instead of overloading HITM define a new flag that indicates this type of transfer. Committer notes: This really is not syncing with the kernel since the patch to the kernel wasn't merged. But we're going ahead of this as it seems trivial and is just a matter of the perf kernel maintainers to give their ack or for us to find another way of expressing this in the perf records synthesized in userspace from the ARM64 hardware traces. Reviewed-by: Leo Yan Signed-off-by: Ali Saidi Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Anshuman Khandual Cc: German Gomez Cc: Gustavo A. R. Silva Cc: Ian Rogers Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Like Xu Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Timothy Hayes Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220811062451.435810-2-leo.yan@linaro.org Signed-off-by: Leo Yan Signed-off-by: Arnaldo Carvalho de Melo --- tools/include/uapi/linux/perf_event.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/include/uapi/linux/perf_event.h b/tools/include/uapi/linux/perf_event.h index 4653834f078f..e2b77fbca91e 100644 --- a/tools/include/uapi/linux/perf_event.h +++ b/tools/include/uapi/linux/perf_event.h @@ -1310,7 +1310,7 @@ union perf_mem_data_src { #define PERF_MEM_SNOOP_SHIFT 19 #define PERF_MEM_SNOOPX_FWD 0x01 /* forward */ -/* 1 free */ +#define PERF_MEM_SNOOPX_PEER 0x02 /* xfer from peer */ #define PERF_MEM_SNOOPX_SHIFT 38 /* locked instruction */ -- cgit v1.2.3 From f78d6250db1a4bd81b9f998a93ea24eb8d4c1908 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Thu, 11 Aug 2022 14:24:38 +0800 Subject: perf mem: Print snoop peer flag Since PERF_MEM_SNOOPX_PEER flag is a new snoop type, print this flag if it is set. Before: memstress 3603 [020] 122.463754: 1 l1d-miss: 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP N/A|TLB Walker hit|LCK No|BLK N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) memstress 3603 [020] 122.463754: 1 l1d-access: 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP N/A|TLB Walker hit|LCK No|BLK N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) memstress 3603 [020] 122.463754: 1 llc-miss: 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP N/A|TLB Walker hit|LCK No|BLK N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) memstress 3603 [020] 122.463754: 1 llc-access: 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP N/A|TLB Walker hit|LCK No|BLK N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) memstress 3603 [020] 122.463754: 1 tlb-access: 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP N/A|TLB Walker hit|LCK No|BLK N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) memstress 3603 [020] 122.463754: 1 memory: 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP N/A|TLB Walker hit|LCK No|BLK N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) After: memstress 3603 [020] 122.463754: 1 l1d-miss: 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP Peer|TLB Walker hit|LCK No|BLK N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) memstress 3603 [020] 122.463754: 1 l1d-access: 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP Peer|TLB Walker hit|LCK No|BLK N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) memstress 3603 [020] 122.463754: 1 llc-miss: 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP Peer|TLB Walker hit|LCK No|BLK N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) memstress 3603 [020] 122.463754: 1 llc-access: 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP Peer|TLB Walker hit|LCK No|BLK N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) memstress 3603 [020] 122.463754: 1 tlb-access: 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP Peer|TLB Walker hit|LCK No|BLK N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) memstress 3603 [020] 122.463754: 1 memory: 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP Peer|TLB Walker hit|LCK No|BLK N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) Reviewed-by: Ali Saidi Reviewed-by: Kajol Jain Signed-off-by: Leo Yan Tested-by: Ali Saidi Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Anshuman Khandual Cc: German Gomez Cc: Gustavo A. R. Silva Cc: Ian Rogers Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Like Xu Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Timothy Hayes Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220811062451.435810-3-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/mem-events.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index c3c21a9c350b..5dca1882c284 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -410,6 +410,11 @@ static const char * const snoop_access[] = { "HitM", }; +static const char * const snoopx_access[] = { + "Fwd", + "Peer", +}; + int perf_mem__snp_scnprintf(char *out, size_t sz, struct mem_info *mem_info) { size_t i, l = 0; @@ -430,13 +435,20 @@ int perf_mem__snp_scnprintf(char *out, size_t sz, struct mem_info *mem_info) } l += scnprintf(out + l, sz - l, snoop_access[i]); } - if (mem_info && - (mem_info->data_src.mem_snoopx & PERF_MEM_SNOOPX_FWD)) { + + m = 0; + if (mem_info) + m = mem_info->data_src.mem_snoopx; + + for (i = 0; m && i < ARRAY_SIZE(snoopx_access); i++, m >>= 1) { + if (!(m & 0x1)) + continue; + if (l) { strcat(out, " or "); l += 4; } - l += scnprintf(out + l, sz - l, "Fwd"); + l += scnprintf(out + l, sz - l, snoopx_access[i]); } if (*out == '\0') -- cgit v1.2.3 From 4e6430cbb1a9f1dc0a698f93026b6178da437798 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 11 Aug 2022 14:24:39 +0800 Subject: perf arm-spe: Use SPE data source for neoverse cores When synthesizing data from SPE, augment the type with source information for Arm Neoverse cores. The field is IMPLDEF but the Neoverse cores all use the same encoding. I can't find encoding information for any other SPE implementations to unify their choices with Arm's thus that is left for future work. This change populates the mem_lvl_num for Neoverse cores as well as the deprecated mem_lvl namespace. Reviewed-by: German Gomez Reviewed-by: Leo Yan Signed-off-by: Ali Saidi Tested-by: Leo Yan Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Anshuman Khandual Cc: Gustavo A. R. Silva Cc: Ian Rogers Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Like Xu Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Timothy Hayes Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220811062451.435810-4-leo.yan@linaro.org Signed-off-by: Leo Yan Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/arm-spe-decoder/arm-spe-decoder.c | 1 + tools/perf/util/arm-spe-decoder/arm-spe-decoder.h | 12 ++ tools/perf/util/arm-spe.c | 130 +++++++++++++++++++--- 3 files changed, 127 insertions(+), 16 deletions(-) diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c index 5e390a1a79ab..091987dd3966 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c +++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c @@ -220,6 +220,7 @@ static int arm_spe_read_record(struct arm_spe_decoder *decoder) break; case ARM_SPE_DATA_SOURCE: + decoder->record.source = payload; break; case ARM_SPE_BAD: break; diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h index 69b31084d6be..46a61df1145b 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h +++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h @@ -29,6 +29,17 @@ enum arm_spe_op_type { ARM_SPE_ST = 1 << 1, }; +enum arm_spe_neoverse_data_source { + ARM_SPE_NV_L1D = 0x0, + ARM_SPE_NV_L2 = 0x8, + ARM_SPE_NV_PEER_CORE = 0x9, + ARM_SPE_NV_LOCAL_CLUSTER = 0xa, + ARM_SPE_NV_SYS_CACHE = 0xb, + ARM_SPE_NV_PEER_CLUSTER = 0xc, + ARM_SPE_NV_REMOTE = 0xd, + ARM_SPE_NV_DRAM = 0xe, +}; + struct arm_spe_record { enum arm_spe_sample_type type; int err; @@ -40,6 +51,7 @@ struct arm_spe_record { u64 virt_addr; u64 phys_addr; u64 context_id; + u16 source; }; struct arm_spe_insn; diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index d040406f3314..22dcfe07e886 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -34,6 +34,7 @@ #include "arm-spe-decoder/arm-spe-decoder.h" #include "arm-spe-decoder/arm-spe-pkt-decoder.h" +#include "../../arch/arm64/include/asm/cputype.h" #define MAX_TIMESTAMP (~0ULL) struct arm_spe { @@ -45,6 +46,7 @@ struct arm_spe { struct perf_session *session; struct machine *machine; u32 pmu_type; + u64 midr; struct perf_tsc_conversion tc; @@ -387,35 +389,128 @@ static int arm_spe__synth_instruction_sample(struct arm_spe_queue *speq, return arm_spe_deliver_synth_event(spe, speq, event, &sample); } -static u64 arm_spe__synth_data_source(const struct arm_spe_record *record) +static const struct midr_range neoverse_spe[] = { + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), + {}, +}; + +static void arm_spe__synth_data_source_neoverse(const struct arm_spe_record *record, + union perf_mem_data_src *data_src) { - union perf_mem_data_src data_src = { 0 }; + /* + * Even though four levels of cache hierarchy are possible, no known + * production Neoverse systems currently include more than three levels + * so for the time being we assume three exist. If a production system + * is built with four the this function would have to be changed to + * detect the number of levels for reporting. + */ - if (record->op == ARM_SPE_LD) - data_src.mem_op = PERF_MEM_OP_LOAD; - else if (record->op == ARM_SPE_ST) - data_src.mem_op = PERF_MEM_OP_STORE; - else - return 0; + /* + * We have no data on the hit level or data source for stores in the + * Neoverse SPE records. + */ + if (record->op & ARM_SPE_ST) { + data_src->mem_lvl = PERF_MEM_LVL_NA; + data_src->mem_lvl_num = PERF_MEM_LVLNUM_NA; + data_src->mem_snoop = PERF_MEM_SNOOP_NA; + return; + } + + switch (record->source) { + case ARM_SPE_NV_L1D: + data_src->mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT; + data_src->mem_lvl_num = PERF_MEM_LVLNUM_L1; + data_src->mem_snoop = PERF_MEM_SNOOP_NONE; + break; + case ARM_SPE_NV_L2: + data_src->mem_lvl = PERF_MEM_LVL_L2 | PERF_MEM_LVL_HIT; + data_src->mem_lvl_num = PERF_MEM_LVLNUM_L2; + data_src->mem_snoop = PERF_MEM_SNOOP_NONE; + break; + case ARM_SPE_NV_PEER_CORE: + data_src->mem_lvl = PERF_MEM_LVL_L2 | PERF_MEM_LVL_HIT; + data_src->mem_lvl_num = PERF_MEM_LVLNUM_L2; + data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER; + break; + /* + * We don't know if this is L1, L2 but we do know it was a cache-2-cache + * transfer, so set SNOOPX_PEER + */ + case ARM_SPE_NV_LOCAL_CLUSTER: + case ARM_SPE_NV_PEER_CLUSTER: + data_src->mem_lvl = PERF_MEM_LVL_L3 | PERF_MEM_LVL_HIT; + data_src->mem_lvl_num = PERF_MEM_LVLNUM_L3; + data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER; + break; + /* + * System cache is assumed to be L3 + */ + case ARM_SPE_NV_SYS_CACHE: + data_src->mem_lvl = PERF_MEM_LVL_L3 | PERF_MEM_LVL_HIT; + data_src->mem_lvl_num = PERF_MEM_LVLNUM_L3; + data_src->mem_snoop = PERF_MEM_SNOOP_HIT; + break; + /* + * We don't know what level it hit in, except it came from the other + * socket + */ + case ARM_SPE_NV_REMOTE: + data_src->mem_lvl = PERF_MEM_LVL_REM_CCE1; + data_src->mem_lvl_num = PERF_MEM_LVLNUM_ANY_CACHE; + data_src->mem_remote = PERF_MEM_REMOTE_REMOTE; + data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER; + break; + case ARM_SPE_NV_DRAM: + data_src->mem_lvl = PERF_MEM_LVL_LOC_RAM | PERF_MEM_LVL_HIT; + data_src->mem_lvl_num = PERF_MEM_LVLNUM_RAM; + data_src->mem_snoop = PERF_MEM_SNOOP_NONE; + break; + default: + break; + } +} +static void arm_spe__synth_data_source_generic(const struct arm_spe_record *record, + union perf_mem_data_src *data_src) +{ if (record->type & (ARM_SPE_LLC_ACCESS | ARM_SPE_LLC_MISS)) { - data_src.mem_lvl = PERF_MEM_LVL_L3; + data_src->mem_lvl = PERF_MEM_LVL_L3; if (record->type & ARM_SPE_LLC_MISS) - data_src.mem_lvl |= PERF_MEM_LVL_MISS; + data_src->mem_lvl |= PERF_MEM_LVL_MISS; else - data_src.mem_lvl |= PERF_MEM_LVL_HIT; + data_src->mem_lvl |= PERF_MEM_LVL_HIT; } else if (record->type & (ARM_SPE_L1D_ACCESS | ARM_SPE_L1D_MISS)) { - data_src.mem_lvl = PERF_MEM_LVL_L1; + data_src->mem_lvl = PERF_MEM_LVL_L1; if (record->type & ARM_SPE_L1D_MISS) - data_src.mem_lvl |= PERF_MEM_LVL_MISS; + data_src->mem_lvl |= PERF_MEM_LVL_MISS; else - data_src.mem_lvl |= PERF_MEM_LVL_HIT; + data_src->mem_lvl |= PERF_MEM_LVL_HIT; } if (record->type & ARM_SPE_REMOTE_ACCESS) - data_src.mem_lvl |= PERF_MEM_LVL_REM_CCE1; + data_src->mem_lvl |= PERF_MEM_LVL_REM_CCE1; +} + +static u64 arm_spe__synth_data_source(const struct arm_spe_record *record, u64 midr) +{ + union perf_mem_data_src data_src = { 0 }; + bool is_neoverse = is_midr_in_range(midr, neoverse_spe); + + if (record->op == ARM_SPE_LD) + data_src.mem_op = PERF_MEM_OP_LOAD; + else if (record->op == ARM_SPE_ST) + data_src.mem_op = PERF_MEM_OP_STORE; + else + return 0; + + if (is_neoverse) + arm_spe__synth_data_source_neoverse(record, &data_src); + else + arm_spe__synth_data_source_generic(record, &data_src); if (record->type & (ARM_SPE_TLB_ACCESS | ARM_SPE_TLB_MISS)) { data_src.mem_dtlb = PERF_MEM_TLB_WK; @@ -436,7 +531,7 @@ static int arm_spe_sample(struct arm_spe_queue *speq) u64 data_src; int err; - data_src = arm_spe__synth_data_source(record); + data_src = arm_spe__synth_data_source(record, spe->midr); if (spe->sample_flc) { if (record->type & ARM_SPE_L1D_MISS) { @@ -1178,6 +1273,8 @@ int arm_spe_process_auxtrace_info(union perf_event *event, struct perf_record_auxtrace_info *auxtrace_info = &event->auxtrace_info; size_t min_sz = sizeof(u64) * ARM_SPE_AUXTRACE_PRIV_MAX; struct perf_record_time_conv *tc = &session->time_conv; + const char *cpuid = perf_env__cpuid(session->evlist->env); + u64 midr = strtol(cpuid, NULL, 16); struct arm_spe *spe; int err; @@ -1197,6 +1294,7 @@ int arm_spe_process_auxtrace_info(union perf_event *event, spe->machine = &session->machines.host; /* No kvm support */ spe->auxtrace_type = auxtrace_info->type; spe->pmu_type = auxtrace_info->priv[ARM_SPE_PMU_TYPE]; + spe->midr = midr; spe->timeless_decoding = arm_spe__is_timeless_decoding(spe); -- cgit v1.2.3 From e843dec53ac87d6faab1c144dad9a097997a0e83 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Thu, 11 Aug 2022 14:24:40 +0800 Subject: perf mem: Add statistics for peer snooping Since the flag PERF_MEM_SNOOPX_PEER is added to support cache snooping from peer cache line, it can come from a peer core, a peer cluster, or a remote NUMA node. This patch adds statistics for the flag PERF_MEM_SNOOPX_PEER. Note, we take PERF_MEM_SNOOPX_PEER as an affiliated info, it needs to cooperate with cache level statistics. Therefore, we account the load operations for both the cache level's metrics (e.g. ld_l2hit, ld_llchit, etc.) and peer related metrics when flag PERF_MEM_SNOOPX_PEER is set. So three new metrics are introduced: 'lcl_peer' is for local cache access, the metric 'rmt_peer' is for remote access (includes remote DRAM and any caches in remote node), and the metric 'tot_peer' is accounting the sum value of 'lcl_peer' and 'rmt_peer'. Reviewed-by: Ali Saidi Signed-off-by: Leo Yan Tested-by: Ali Saidi Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Anshuman Khandual Cc: German Gomez Cc: Gustavo A. R. Silva Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Like Xu Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Timothy Hayes Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220811062451.435810-5-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/mem-events.c | 28 +++++++++++++++++++++++++--- tools/perf/util/mem-events.h | 3 +++ 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index 5dca1882c284..764883183519 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -525,6 +525,7 @@ int c2c_decode_stats(struct c2c_stats *stats, struct mem_info *mi) u64 op = data_src->mem_op; u64 lvl = data_src->mem_lvl; u64 snoop = data_src->mem_snoop; + u64 snoopx = data_src->mem_snoopx; u64 lock = data_src->mem_lock; u64 blk = data_src->mem_blk; /* @@ -544,6 +545,12 @@ do { \ stats->tot_hitm++; \ } while (0) +#define PEER_INC(__f) \ +do { \ + stats->__f++; \ + stats->tot_peer++; \ +} while (0) + #define P(a, b) PERF_MEM_##a##_##b stats->nr_entries++; @@ -567,12 +574,20 @@ do { \ if (lvl & P(LVL, IO)) stats->ld_io++; if (lvl & P(LVL, LFB)) stats->ld_fbhit++; if (lvl & P(LVL, L1 )) stats->ld_l1hit++; - if (lvl & P(LVL, L2 )) stats->ld_l2hit++; + if (lvl & P(LVL, L2)) { + stats->ld_l2hit++; + + if (snoopx & P(SNOOPX, PEER)) + PEER_INC(lcl_peer); + } if (lvl & P(LVL, L3 )) { if (snoop & P(SNOOP, HITM)) HITM_INC(lcl_hitm); else stats->ld_llchit++; + + if (snoopx & P(SNOOPX, PEER)) + PEER_INC(lcl_peer); } if (lvl & P(LVL, LOC_RAM)) { @@ -597,10 +612,14 @@ do { \ if ((lvl & P(LVL, REM_CCE1)) || (lvl & P(LVL, REM_CCE2)) || mrem) { - if (snoop & P(SNOOP, HIT)) + if (snoop & P(SNOOP, HIT)) { stats->rmt_hit++; - else if (snoop & P(SNOOP, HITM)) + } else if (snoop & P(SNOOP, HITM)) { HITM_INC(rmt_hitm); + } else if (snoopx & P(SNOOPX, PEER)) { + stats->rmt_hit++; + PEER_INC(rmt_peer); + } } if ((lvl & P(LVL, MISS))) @@ -664,6 +683,9 @@ void c2c_add_stats(struct c2c_stats *stats, struct c2c_stats *add) stats->lcl_hitm += add->lcl_hitm; stats->rmt_hitm += add->rmt_hitm; stats->tot_hitm += add->tot_hitm; + stats->lcl_peer += add->lcl_peer; + stats->rmt_peer += add->rmt_peer; + stats->tot_peer += add->tot_peer; stats->rmt_hit += add->rmt_hit; stats->lcl_dram += add->lcl_dram; stats->rmt_dram += add->rmt_dram; diff --git a/tools/perf/util/mem-events.h b/tools/perf/util/mem-events.h index 8a8b568baeee..12372309d60e 100644 --- a/tools/perf/util/mem-events.h +++ b/tools/perf/util/mem-events.h @@ -78,6 +78,9 @@ struct c2c_stats { u32 lcl_hitm; /* count of loads with local HITM */ u32 rmt_hitm; /* count of loads with remote HITM */ u32 tot_hitm; /* count of loads with local and remote HITM */ + u32 lcl_peer; /* count of loads with local peer cache */ + u32 rmt_peer; /* count of loads with remote peer cache */ + u32 tot_peer; /* count of loads with local and remote peer cache */ u32 rmt_hit; /* count of loads with remote hit clean; */ u32 lcl_dram; /* count of loads miss to local DRAM */ u32 rmt_dram; /* count of loads miss to remote DRAM */ -- cgit v1.2.3 From 3ef1fc17b31b7f701e8392efe8032333a2a5e6a5 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Thu, 11 Aug 2022 14:24:41 +0800 Subject: perf c2c: Output statistics for peer snooping This patch outputs statistics for peer snooping for whole trace events and global shared cache line. Reviewed-by: Ali Saidi Signed-off-by: Leo Yan Tested-by: Ali Saidi Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Anshuman Khandual Cc: German Gomez Cc: Gustavo A. R. Silva Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Like Xu Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Timothy Hayes Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220811062451.435810-6-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-c2c.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c index 4898ee57d156..37bebeb6c11b 100644 --- a/tools/perf/builtin-c2c.c +++ b/tools/perf/builtin-c2c.c @@ -2202,6 +2202,8 @@ static void print_c2c__display_stats(FILE *out) fprintf(out, " Load LLC Misses : %10d\n", llc_misses); fprintf(out, " Load access blocked by data : %10d\n", stats->blk_data); fprintf(out, " Load access blocked by address : %10d\n", stats->blk_addr); + fprintf(out, " Load HIT Local Peer : %10d\n", stats->lcl_peer); + fprintf(out, " Load HIT Remote Peer : %10d\n", stats->rmt_peer); fprintf(out, " LLC Misses to Local DRAM : %10.1f%%\n", ((double)stats->lcl_dram/(double)llc_misses) * 100.); fprintf(out, " LLC Misses to Remote DRAM : %10.1f%%\n", ((double)stats->rmt_dram/(double)llc_misses) * 100.); fprintf(out, " LLC Misses to Remote cache (HIT) : %10.1f%%\n", ((double)stats->rmt_hit /(double)llc_misses) * 100.); @@ -2230,6 +2232,7 @@ static void print_shared_cacheline_info(FILE *out) fprintf(out, " L1D hits on shared lines : %10d\n", stats->ld_l1hit); fprintf(out, " L2D hits on shared lines : %10d\n", stats->ld_l2hit); fprintf(out, " LLC hits on shared lines : %10d\n", stats->ld_llchit + stats->lcl_hitm); + fprintf(out, " Load hits on peer cache or nodes : %10d\n", stats->lcl_peer + stats->rmt_peer); fprintf(out, " Locked Access on shared lines : %10d\n", stats->locks); fprintf(out, " Blocked Access on shared lines : %10d\n", stats->blk_data + stats->blk_addr); fprintf(out, " Store HITs on shared lines : %10d\n", stats->store); -- cgit v1.2.3 From 63e74ab5e4e35da7ec4d62b5209c8f654447ba87 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Thu, 11 Aug 2022 14:24:42 +0800 Subject: perf c2c: Add dimensions for peer load operations This patch adds three dimensions for peer load operations of 'lcl_peer', 'rmt_peer' and 'tot_peer'. These three dimensions will be used in the shared data cache line table. Reviewed-by: Ali Saidi Signed-off-by: Leo Yan Tested-by: Ali Saidi Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Anshuman Khandual Cc: German Gomez Cc: Gustavo A. R. Silva Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Like Xu Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Timothy Hayes Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220811062451.435810-7-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-c2c.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c index 37bebeb6c11b..99c0c7307a4a 100644 --- a/tools/perf/builtin-c2c.c +++ b/tools/perf/builtin-c2c.c @@ -650,6 +650,9 @@ __f ## _cmp(struct perf_hpp_fmt *fmt __maybe_unused, \ STAT_FN(rmt_hitm) STAT_FN(lcl_hitm) +STAT_FN(rmt_peer) +STAT_FN(lcl_peer) +STAT_FN(tot_peer) STAT_FN(store) STAT_FN(st_l1hit) STAT_FN(st_l1miss) @@ -1360,6 +1363,30 @@ static struct c2c_dimension dim_rmt_hitm = { .width = 7, }; +static struct c2c_dimension dim_tot_peer = { + .header = HEADER_SPAN("------- Load Peer -------", "Total", 2), + .name = "tot_peer", + .cmp = tot_peer_cmp, + .entry = tot_peer_entry, + .width = 7, +}; + +static struct c2c_dimension dim_lcl_peer = { + .header = HEADER_SPAN_LOW("Local"), + .name = "lcl_peer", + .cmp = lcl_peer_cmp, + .entry = lcl_peer_entry, + .width = 7, +}; + +static struct c2c_dimension dim_rmt_peer = { + .header = HEADER_SPAN_LOW("Remote"), + .name = "rmt_peer", + .cmp = rmt_peer_cmp, + .entry = rmt_peer_entry, + .width = 7, +}; + static struct c2c_dimension dim_cl_rmt_hitm = { .header = HEADER_SPAN("----- HITM -----", "Rmt", 1), .name = "cl_rmt_hitm", @@ -1672,6 +1699,9 @@ static struct c2c_dimension *dimensions[] = { &dim_tot_hitm, &dim_lcl_hitm, &dim_rmt_hitm, + &dim_tot_peer, + &dim_lcl_peer, + &dim_rmt_peer, &dim_cl_lcl_hitm, &dim_cl_rmt_hitm, &dim_tot_stores, -- cgit v1.2.3 From 9082282fce7215868b3702da77f7eb9339310e7a Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Thu, 11 Aug 2022 14:24:43 +0800 Subject: perf c2c: Add dimensions of peer metrics for cache line view This patch adds dimensions of peer ops, which will be used for Shared cache line distribution pareto. It adds the percentage dimensions for local and remote peer operations, and the dimensions for accounting operation numbers which is used for stdio mode. Reviewed-by: Ali Saidi Signed-off-by: Leo Yan Tested-by: Ali Saidi Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Anshuman Khandual Cc: German Gomez Cc: Gustavo A. R. Silva Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Like Xu Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Timothy Hayes Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220811062451.435810-8-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-c2c.c | 102 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c index 99c0c7307a4a..dd47f068b8da 100644 --- a/tools/perf/builtin-c2c.c +++ b/tools/perf/builtin-c2c.c @@ -902,6 +902,8 @@ static double percent_ ## __f(struct c2c_hist_entry *c2c_he) \ PERCENT_FN(rmt_hitm) PERCENT_FN(lcl_hitm) +PERCENT_FN(rmt_peer) +PERCENT_FN(lcl_peer) PERCENT_FN(st_l1hit) PERCENT_FN(st_l1miss) PERCENT_FN(st_na) @@ -968,6 +970,68 @@ percent_lcl_hitm_cmp(struct perf_hpp_fmt *fmt __maybe_unused, return per_left - per_right; } +static int +percent_lcl_peer_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + int width = c2c_width(fmt, hpp, he->hists); + double per = PERCENT(he, lcl_peer); + char buf[10]; + + return scnprintf(hpp->buf, hpp->size, "%*s", width, PERC_STR(buf, per)); +} + +static int +percent_lcl_peer_color(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + return percent_color(fmt, hpp, he, percent_lcl_peer); +} + +static int64_t +percent_lcl_peer_cmp(struct perf_hpp_fmt *fmt __maybe_unused, + struct hist_entry *left, struct hist_entry *right) +{ + double per_left; + double per_right; + + per_left = PERCENT(left, lcl_peer); + per_right = PERCENT(right, lcl_peer); + + return per_left - per_right; +} + +static int +percent_rmt_peer_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + int width = c2c_width(fmt, hpp, he->hists); + double per = PERCENT(he, rmt_peer); + char buf[10]; + + return scnprintf(hpp->buf, hpp->size, "%*s", width, PERC_STR(buf, per)); +} + +static int +percent_rmt_peer_color(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + return percent_color(fmt, hpp, he, percent_rmt_peer); +} + +static int64_t +percent_rmt_peer_cmp(struct perf_hpp_fmt *fmt __maybe_unused, + struct hist_entry *left, struct hist_entry *right) +{ + double per_left; + double per_right; + + per_left = PERCENT(left, rmt_peer); + per_right = PERCENT(right, rmt_peer); + + return per_left - per_right; +} + static int percent_stores_l1hit_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, struct hist_entry *he) @@ -1403,6 +1467,22 @@ static struct c2c_dimension dim_cl_lcl_hitm = { .width = 7, }; +static struct c2c_dimension dim_cl_rmt_peer = { + .header = HEADER_SPAN("----- Peer -----", "Rmt", 1), + .name = "cl_rmt_peer", + .cmp = rmt_peer_cmp, + .entry = rmt_peer_entry, + .width = 7, +}; + +static struct c2c_dimension dim_cl_lcl_peer = { + .header = HEADER_SPAN_LOW("Lcl"), + .name = "cl_lcl_peer", + .cmp = lcl_peer_cmp, + .entry = lcl_peer_entry, + .width = 7, +}; + static struct c2c_dimension dim_tot_stores = { .header = HEADER_BOTH("Total", "Stores"), .name = "tot_stores", @@ -1547,6 +1627,24 @@ static struct c2c_dimension dim_percent_lcl_hitm = { .width = 7, }; +static struct c2c_dimension dim_percent_rmt_peer = { + .header = HEADER_SPAN("-- Peer Snoop --", "Rmt", 1), + .name = "percent_rmt_peer", + .cmp = percent_rmt_peer_cmp, + .entry = percent_rmt_peer_entry, + .color = percent_rmt_peer_color, + .width = 7, +}; + +static struct c2c_dimension dim_percent_lcl_peer = { + .header = HEADER_SPAN_LOW("Lcl"), + .name = "percent_lcl_peer", + .cmp = percent_lcl_peer_cmp, + .entry = percent_lcl_peer_entry, + .color = percent_lcl_peer_color, + .width = 7, +}; + static struct c2c_dimension dim_percent_stores_l1hit = { .header = HEADER_SPAN("------- Store Refs ------", "L1 Hit", 2), .name = "percent_stores_l1hit", @@ -1704,6 +1802,8 @@ static struct c2c_dimension *dimensions[] = { &dim_rmt_peer, &dim_cl_lcl_hitm, &dim_cl_rmt_hitm, + &dim_cl_lcl_peer, + &dim_cl_rmt_peer, &dim_tot_stores, &dim_stores_l1hit, &dim_stores_l1miss, @@ -1721,6 +1821,8 @@ static struct c2c_dimension *dimensions[] = { &dim_percent_hitm, &dim_percent_rmt_hitm, &dim_percent_lcl_hitm, + &dim_percent_rmt_peer, + &dim_percent_lcl_peer, &dim_percent_stores_l1hit, &dim_percent_stores_l1miss, &dim_percent_stores_na, -- cgit v1.2.3 From 682352e59bf197a3e56e6c236683ab3a96a6952b Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Thu, 11 Aug 2022 14:24:44 +0800 Subject: perf c2c: Add mean dimensions for peer operations This patch adds two dimensions for the mean value of peer operations. Reviewed-by: Ali Saidi Signed-off-by: Leo Yan Tested-by: Ali Saidi Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Anshuman Khandual Cc: German Gomez Cc: Gustavo A. R. Silva Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Like Xu Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Timothy Hayes Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220811062451.435810-9-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-c2c.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c index dd47f068b8da..8dd9218a052f 100644 --- a/tools/perf/builtin-c2c.c +++ b/tools/perf/builtin-c2c.c @@ -55,6 +55,8 @@ struct c2c_hists { struct compute_stats { struct stats lcl_hitm; struct stats rmt_hitm; + struct stats lcl_peer; + struct stats rmt_peer; struct stats load; }; @@ -154,6 +156,8 @@ static void *c2c_he_zalloc(size_t size) init_stats(&c2c_he->cstats.lcl_hitm); init_stats(&c2c_he->cstats.rmt_hitm); + init_stats(&c2c_he->cstats.lcl_peer); + init_stats(&c2c_he->cstats.rmt_peer); init_stats(&c2c_he->cstats.load); return &c2c_he->he; @@ -253,6 +257,10 @@ static void compute_stats(struct c2c_hist_entry *c2c_he, update_stats(&cstats->rmt_hitm, weight); else if (stats->lcl_hitm) update_stats(&cstats->lcl_hitm, weight); + else if (stats->rmt_peer) + update_stats(&cstats->rmt_peer, weight); + else if (stats->lcl_peer) + update_stats(&cstats->lcl_peer, weight); else if (stats->load) update_stats(&cstats->load, weight); } @@ -1280,6 +1288,8 @@ __func(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, struct hist_entry *he) \ MEAN_ENTRY(mean_rmt_entry, rmt_hitm); MEAN_ENTRY(mean_lcl_entry, lcl_hitm); MEAN_ENTRY(mean_load_entry, load); +MEAN_ENTRY(mean_rmt_peer_entry, rmt_peer); +MEAN_ENTRY(mean_lcl_peer_entry, lcl_peer); static int cpucnt_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, @@ -1750,6 +1760,22 @@ static struct c2c_dimension dim_mean_load = { .width = 8, }; +static struct c2c_dimension dim_mean_rmt_peer = { + .header = HEADER_SPAN("---------- cycles ----------", "rmt peer", 2), + .name = "mean_rmt_peer", + .cmp = empty_cmp, + .entry = mean_rmt_peer_entry, + .width = 8, +}; + +static struct c2c_dimension dim_mean_lcl_peer = { + .header = HEADER_SPAN_LOW("lcl peer"), + .name = "mean_lcl_peer", + .cmp = empty_cmp, + .entry = mean_lcl_peer_entry, + .width = 8, +}; + static struct c2c_dimension dim_cpucnt = { .header = HEADER_BOTH("cpu", "cnt"), .name = "cpucnt", @@ -1835,6 +1861,8 @@ static struct c2c_dimension *dimensions[] = { &dim_node, &dim_mean_rmt, &dim_mean_lcl, + &dim_mean_rmt_peer, + &dim_mean_lcl_peer, &dim_mean_load, &dim_cpucnt, &dim_srcline, -- cgit v1.2.3 From c82ccc3a3d57d7f40083c7c560b726b7b919206f Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Thu, 11 Aug 2022 14:24:45 +0800 Subject: perf c2c: Use explicit names for display macros Perf c2c tool has an assumption that it heavily depends on HITM snoop type to detect cache false sharing, unfortunately, HITM is not supported on some architectures. Essentially, perf c2c tool wants to find some very costly snooping operations for false cache sharing, this means it's not necessarily to stick using HITM tags and we can explore other snooping types (e.g. SNOOPX_PEER). For this reason, this patch renames HITM related display macros with suffix '_HITM', so it can be distinct if later add more display types for on other snooping type. Reviewed-by: Ali Saidi Signed-off-by: Leo Yan Tested-by: Ali Saidi Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Anshuman Khandual Cc: German Gomez Cc: Gustavo A. R. Silva Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Like Xu Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Timothy Hayes Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220811062451.435810-10-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-c2c.c | 58 ++++++++++++++++++++++++------------------------ 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c index 8dd9218a052f..cbeb1878a71c 100644 --- a/tools/perf/builtin-c2c.c +++ b/tools/perf/builtin-c2c.c @@ -115,16 +115,16 @@ struct perf_c2c { }; enum { - DISPLAY_LCL, - DISPLAY_RMT, - DISPLAY_TOT, + DISPLAY_LCL_HITM, + DISPLAY_RMT_HITM, + DISPLAY_TOT_HITM, DISPLAY_MAX, }; static const char *display_str[DISPLAY_MAX] = { - [DISPLAY_LCL] = "Local", - [DISPLAY_RMT] = "Remote", - [DISPLAY_TOT] = "Total", + [DISPLAY_LCL_HITM] = "Local", + [DISPLAY_RMT_HITM] = "Remote", + [DISPLAY_TOT_HITM] = "Total", }; static const struct option c2c_options[] = { @@ -811,15 +811,15 @@ static double percent_hitm(struct c2c_hist_entry *c2c_he) total = &hists->stats; switch (c2c.display) { - case DISPLAY_RMT: + case DISPLAY_RMT_HITM: st = stats->rmt_hitm; tot = total->rmt_hitm; break; - case DISPLAY_LCL: + case DISPLAY_LCL_HITM: st = stats->lcl_hitm; tot = total->lcl_hitm; break; - case DISPLAY_TOT: + case DISPLAY_TOT_HITM: st = stats->tot_hitm; tot = total->tot_hitm; default: @@ -1217,15 +1217,15 @@ node_entry(struct perf_hpp_fmt *fmt __maybe_unused, struct perf_hpp *hpp, advance_hpp(hpp, ret); switch (c2c.display) { - case DISPLAY_RMT: + case DISPLAY_RMT_HITM: ret = display_metrics(hpp, stats->rmt_hitm, c2c_he->stats.rmt_hitm); break; - case DISPLAY_LCL: + case DISPLAY_LCL_HITM: ret = display_metrics(hpp, stats->lcl_hitm, c2c_he->stats.lcl_hitm); break; - case DISPLAY_TOT: + case DISPLAY_TOT_HITM: ret = display_metrics(hpp, stats->tot_hitm, c2c_he->stats.tot_hitm); break; @@ -1606,9 +1606,9 @@ static struct c2c_dimension dim_tot_loads = { }; static struct c2c_header percent_hitm_header[] = { - [DISPLAY_LCL] = HEADER_BOTH("Lcl", "Hitm"), - [DISPLAY_RMT] = HEADER_BOTH("Rmt", "Hitm"), - [DISPLAY_TOT] = HEADER_BOTH("Tot", "Hitm"), + [DISPLAY_LCL_HITM] = HEADER_BOTH("Lcl", "Hitm"), + [DISPLAY_RMT_HITM] = HEADER_BOTH("Rmt", "Hitm"), + [DISPLAY_TOT_HITM] = HEADER_BOTH("Tot", "Hitm"), }; static struct c2c_dimension dim_percent_hitm = { @@ -2101,15 +2101,15 @@ static bool he__display(struct hist_entry *he, struct c2c_stats *stats) c2c_he = container_of(he, struct c2c_hist_entry, he); switch (c2c.display) { - case DISPLAY_LCL: + case DISPLAY_LCL_HITM: he->filtered = filter_display(c2c_he->stats.lcl_hitm, stats->lcl_hitm); break; - case DISPLAY_RMT: + case DISPLAY_RMT_HITM: he->filtered = filter_display(c2c_he->stats.rmt_hitm, stats->rmt_hitm); break; - case DISPLAY_TOT: + case DISPLAY_TOT_HITM: he->filtered = filter_display(c2c_he->stats.tot_hitm, stats->tot_hitm); break; @@ -2132,13 +2132,13 @@ static inline bool is_valid_hist_entry(struct hist_entry *he) return true; switch (c2c.display) { - case DISPLAY_LCL: + case DISPLAY_LCL_HITM: has_record = !!c2c_he->stats.lcl_hitm; break; - case DISPLAY_RMT: + case DISPLAY_RMT_HITM: has_record = !!c2c_he->stats.rmt_hitm; break; - case DISPLAY_TOT: + case DISPLAY_TOT_HITM: has_record = !!c2c_he->stats.tot_hitm; break; default: @@ -2835,11 +2835,11 @@ static int setup_display(const char *str) const char *display = str ?: "tot"; if (!strcmp(display, "tot")) - c2c.display = DISPLAY_TOT; + c2c.display = DISPLAY_TOT_HITM; else if (!strcmp(display, "rmt")) - c2c.display = DISPLAY_RMT; + c2c.display = DISPLAY_RMT_HITM; else if (!strcmp(display, "lcl")) - c2c.display = DISPLAY_LCL; + c2c.display = DISPLAY_LCL_HITM; else { pr_err("failed: unknown display type: %s\n", str); return -1; @@ -2927,9 +2927,9 @@ static int setup_coalesce(const char *coalesce, bool no_source) return -1; if (asprintf(&c2c.cl_resort, "offset,%s", - c2c.display == DISPLAY_TOT ? + c2c.display == DISPLAY_TOT_HITM ? "tot_hitm" : - c2c.display == DISPLAY_RMT ? + c2c.display == DISPLAY_RMT_HITM ? "rmt_hitm,lcl_hitm" : "lcl_hitm,rmt_hitm") < 0) return -ENOMEM; @@ -3087,11 +3087,11 @@ static int perf_c2c__report(int argc, const char **argv) "ld_rmthit,rmt_hitm," "dram_lcl,dram_rmt"; - if (c2c.display == DISPLAY_TOT) + if (c2c.display == DISPLAY_TOT_HITM) sort_str = "tot_hitm"; - else if (c2c.display == DISPLAY_RMT) + else if (c2c.display == DISPLAY_RMT_HITM) sort_str = "rmt_hitm"; - else if (c2c.display == DISPLAY_LCL) + else if (c2c.display == DISPLAY_LCL_HITM) sort_str = "lcl_hitm"; c2c_hists__reinit(&c2c.hists, output_str, sort_str); -- cgit v1.2.3 From 2be0bc7529f8b5fb63f441167bd8875d71902b17 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Thu, 11 Aug 2022 14:24:46 +0800 Subject: perf c2c: Rename dimension from 'percent_hitm' to 'percent_costly_snoop' Use more general naming for the main sort dimension, this can allow us not to sort only on HITM snoop type, so it can be extended to support other costly snooping operations. So rename the dimension to the prefix 'percent_costly_". Reviewed-by: Ali Saidi Signed-off-by: Leo Yan Tested-by: Ali Saidi Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Anshuman Khandual Cc: German Gomez Cc: Gustavo A. R. Silva Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Like Xu Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Timothy Hayes Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220811062451.435810-11-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-c2c.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c index cbeb1878a71c..66ff834516a2 100644 --- a/tools/perf/builtin-c2c.c +++ b/tools/perf/builtin-c2c.c @@ -798,7 +798,7 @@ percent_color(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, return hpp_color_scnprintf(hpp, "%*.2f%%", width - 1, per); } -static double percent_hitm(struct c2c_hist_entry *c2c_he) +static double percent_costly_snoop(struct c2c_hist_entry *c2c_he) { struct c2c_hists *hists; struct c2c_stats *stats; @@ -838,8 +838,8 @@ static double percent_hitm(struct c2c_hist_entry *c2c_he) }) static int -percent_hitm_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, - struct hist_entry *he) +percent_costly_snoop_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) { struct c2c_hist_entry *c2c_he; int width = c2c_width(fmt, hpp, he->hists); @@ -847,20 +847,20 @@ percent_hitm_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, double per; c2c_he = container_of(he, struct c2c_hist_entry, he); - per = percent_hitm(c2c_he); + per = percent_costly_snoop(c2c_he); return scnprintf(hpp->buf, hpp->size, "%*s", width, PERC_STR(buf, per)); } static int -percent_hitm_color(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, - struct hist_entry *he) +percent_costly_snoop_color(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) { - return percent_color(fmt, hpp, he, percent_hitm); + return percent_color(fmt, hpp, he, percent_costly_snoop); } static int64_t -percent_hitm_cmp(struct perf_hpp_fmt *fmt __maybe_unused, - struct hist_entry *left, struct hist_entry *right) +percent_costly_snoop_cmp(struct perf_hpp_fmt *fmt __maybe_unused, + struct hist_entry *left, struct hist_entry *right) { struct c2c_hist_entry *c2c_left; struct c2c_hist_entry *c2c_right; @@ -870,8 +870,8 @@ percent_hitm_cmp(struct perf_hpp_fmt *fmt __maybe_unused, c2c_left = container_of(left, struct c2c_hist_entry, he); c2c_right = container_of(right, struct c2c_hist_entry, he); - per_left = percent_hitm(c2c_left); - per_right = percent_hitm(c2c_right); + per_left = percent_costly_snoop(c2c_left); + per_right = percent_costly_snoop(c2c_right); return per_left - per_right; } @@ -1605,17 +1605,17 @@ static struct c2c_dimension dim_tot_loads = { .width = 7, }; -static struct c2c_header percent_hitm_header[] = { +static struct c2c_header percent_costly_snoop_header[] = { [DISPLAY_LCL_HITM] = HEADER_BOTH("Lcl", "Hitm"), [DISPLAY_RMT_HITM] = HEADER_BOTH("Rmt", "Hitm"), [DISPLAY_TOT_HITM] = HEADER_BOTH("Tot", "Hitm"), }; -static struct c2c_dimension dim_percent_hitm = { - .name = "percent_hitm", - .cmp = percent_hitm_cmp, - .entry = percent_hitm_entry, - .color = percent_hitm_color, +static struct c2c_dimension dim_percent_costly_snoop = { + .name = "percent_costly_snoop", + .cmp = percent_costly_snoop_cmp, + .entry = percent_costly_snoop_entry, + .color = percent_costly_snoop_color, .width = 7, }; @@ -1844,7 +1844,7 @@ static struct c2c_dimension *dimensions[] = { &dim_ld_rmthit, &dim_tot_recs, &dim_tot_loads, - &dim_percent_hitm, + &dim_percent_costly_snoop, &dim_percent_rmt_hitm, &dim_percent_lcl_hitm, &dim_percent_rmt_peer, @@ -2748,7 +2748,7 @@ static int ui_quirks(void) nodestr = "CL"; } - dim_percent_hitm.header = percent_hitm_header[c2c.display]; + dim_percent_costly_snoop.header = percent_costly_snoop_header[c2c.display]; /* Fix the zero line for dcacheline column. */ buf = fill_line("Cacheline", dim_dcacheline.width + @@ -3076,7 +3076,7 @@ static int perf_c2c__report(int argc, const char **argv) "dcacheline," "dcacheline_node," "dcacheline_count," - "percent_hitm," + "percent_costly_snoop," "tot_hitm,lcl_hitm,rmt_hitm," "tot_recs," "tot_loads," -- cgit v1.2.3 From 7c10b65a42d7bcbc6d3082fa2db257cce8a58c08 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Thu, 11 Aug 2022 14:24:47 +0800 Subject: perf c2c: Refactor node header The node header array contains 3 items, each item is used for one of the 3 flavors for node accessing info. To extend sorting on other snooping type and not always stick to HITMs, the second header string "Node{cpus %hitms %stores}" should be adjusted (e.g. it's changed as "Node{cpus %peer %stores}"). For this reason, this patch changes the node header array to three flat variables and uses switch-case in function setup_nodes_header(), thus it is easier for altering the header string. Reviewed-by: Ali Saidi Signed-off-by: Leo Yan Tested-by: Ali Saidi Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Anshuman Khandual Cc: German Gomez Cc: Gustavo A. R. Silva Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Like Xu Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Timothy Hayes Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220811062451.435810-12-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-c2c.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c index 66ff834516a2..49a9b8480b41 100644 --- a/tools/perf/builtin-c2c.c +++ b/tools/perf/builtin-c2c.c @@ -1723,12 +1723,6 @@ static struct c2c_dimension dim_dso = { .se = &sort_dso, }; -static struct c2c_header header_node[3] = { - HEADER_LOW("Node"), - HEADER_LOW("Node{cpus %hitms %stores}"), - HEADER_LOW("Node{cpu list}"), -}; - static struct c2c_dimension dim_node = { .name = "node", .cmp = empty_cmp, @@ -2229,9 +2223,27 @@ static int resort_cl_cb(struct hist_entry *he, void *arg __maybe_unused) return 0; } +static struct c2c_header header_node_0 = HEADER_LOW("Node"); +static struct c2c_header header_node_1 = HEADER_LOW("Node{cpus %hitms %stores}"); +static struct c2c_header header_node_2 = HEADER_LOW("Node{cpu list}"); + static void setup_nodes_header(void) { - dim_node.header = header_node[c2c.node_info]; + switch (c2c.node_info) { + case 0: + dim_node.header = header_node_0; + break; + case 1: + dim_node.header = header_node_1; + break; + case 2: + dim_node.header = header_node_2; + break; + default: + break; + } + + return; } static int setup_nodes(struct perf_session *session) -- cgit v1.2.3 From faa30dfab5bc6c033994366b24bd805b1cced4ee Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Thu, 11 Aug 2022 14:24:48 +0800 Subject: perf c2c: Refactor display string The display type is shown by combination the display string array and a suffix string "HITMs", which is not friendly to extend display for other sorting type (e.g. extension for peer operations). This patch moves the suffix string "HITMs" into display string array for HITM types, so it can allow us to not necessarily to output string "HITMs" for new incoming display type. Reviewed-by: Ali Saidi Signed-off-by: Leo Yan Tested-by: Ali Saidi Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Anshuman Khandual Cc: German Gomez Cc: Gustavo A. R. Silva Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Like Xu Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Timothy Hayes Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220811062451.435810-13-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-c2c.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c index 49a9b8480b41..8b7c1fd35380 100644 --- a/tools/perf/builtin-c2c.c +++ b/tools/perf/builtin-c2c.c @@ -122,9 +122,9 @@ enum { }; static const char *display_str[DISPLAY_MAX] = { - [DISPLAY_LCL_HITM] = "Local", - [DISPLAY_RMT_HITM] = "Remote", - [DISPLAY_TOT_HITM] = "Total", + [DISPLAY_LCL_HITM] = "Local HITMs", + [DISPLAY_RMT_HITM] = "Remote HITMs", + [DISPLAY_TOT_HITM] = "Total HITMs", }; static const struct option c2c_options[] = { @@ -2489,7 +2489,7 @@ static void print_c2c_info(FILE *out, struct perf_session *session) fprintf(out, "%-36s: %s\n", first ? " Events" : "", evsel__name(evsel)); first = false; } - fprintf(out, " Cachelines sort on : %s HITMs\n", + fprintf(out, " Cachelines sort on : %s\n", display_str[c2c.display]); fprintf(out, " Cacheline data grouping : %s\n", c2c.cl_sort); } @@ -2646,7 +2646,7 @@ static int perf_c2c_browser__title(struct hist_browser *browser, { scnprintf(bf, size, "Shared Data Cache Line Table " - "(%lu entries, sorted on %s HITMs)", + "(%lu entries, sorted on %s)", browser->nr_non_filtered_entries, display_str[c2c.display]); return 0; -- cgit v1.2.3 From f37c5d914e39bdaf86505d6f1c1973418b44a6c6 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Thu, 11 Aug 2022 14:24:49 +0800 Subject: perf c2c: Sort on peer snooping for load operations This patch adds a new option 'peer' so can sort on the cache hit for peer snooping. For displaying with option 'peer', the "Shared Data Cache Line Table" and "Shared Cache Line Distribution Pareto" both sort with the metrics "tot_peer". As result, we can get the 'peer' display: # perf c2c report -d peer --coalesce tid,pid,iaddr,dso -N --stdio ================================================= Shared Data Cache Line Table ================================================= # # ----------- Cacheline ---------- Peer ------- Load Peer ------- Total Total Total --------- Stores -------- ----- Core Load Hit ----- - LLC Load Hit -- - RMT Load Hit -- --- Load Dram ---- # Index Address Node PA cnt Snoop Total Local Remote records Loads Stores L1Hit L1Miss N/A FB L1 L2 LclHit LclHitm RmtHit RmtHitm Lcl Rmt # ..... .................. .... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ........ ....... ........ ....... ........ ........ # 0 0xaaaac17d6000 N/A 0 100.00% 99 99 0 18851 18851 0 0 0 0 0 18752 0 99 0 0 0 0 0 ================================================= Shared Cache Line Distribution Pareto ================================================= # # -- Peer Snoop -- ------- Store Refs ------ --------- Data address --------- ---------- cycles ---------- Total cpu Shared # Num Rmt Lcl L1 Hit L1 Miss N/A Offset Node PA cnt Pid Tid Code address rmt peer lcl peer load records cnt Symbol Object Source:Line Node{cpus %peers %stores} # ..... ....... ....... ....... ....... ....... .................. .... ...... ....... ................. .................. ........ ........ ........ ....... ........ ...................... ................ ............... .... # ---------------------------------------------------------------------- 0 0 99 0 0 0 0xaaaac17d6000 ---------------------------------------------------------------------- 0.00% 3.03% 0.00% 0.00% 0.00% 0x20 N/A 0 3603 3603:memstress 0xaaaac17c25ac 0 376 41 9314 2 [.] 0x00000000000025ac memstress memstress[25ac] 0{ 2 100.0% n/a} 0.00% 3.03% 0.00% 0.00% 0.00% 0x20 N/A 0 3603 3606:memstress 0xaaaac17c25ac 0 375 44 9155 1 [.] 0x00000000000025ac memstress memstress[25ac] 0{ 1 100.0% n/a} 0.00% 48.48% 0.00% 0.00% 0.00% 0x29 N/A 0 3603 3606:memstress 0xaaaac17c3e88 0 180 170 65 1 [.] 0x0000000000003e88 memstress memstress[3e88] 0{ 1 100.0% n/a} 0.00% 45.45% 0.00% 0.00% 0.00% 0x29 N/A 0 3603 3603:memstress 0xaaaac17c3e88 0 180 175 70 2 [.] 0x0000000000003e88 memstress memstress[3e88] 0{ 2 100.0% n/a} Reviewed-by: Ali Saidi Signed-off-by: Leo Yan Tested-by: Ali Saidi Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Anshuman Khandual Cc: German Gomez Cc: Gustavo A. R. Silva Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Like Xu Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Timothy Hayes Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220811062451.435810-14-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-c2c.c | 135 ++++++++++++++++++++++++++++++++++------------- 1 file changed, 99 insertions(+), 36 deletions(-) diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c index 8b7c1fd35380..f7a961e55a92 100644 --- a/tools/perf/builtin-c2c.c +++ b/tools/perf/builtin-c2c.c @@ -118,6 +118,7 @@ enum { DISPLAY_LCL_HITM, DISPLAY_RMT_HITM, DISPLAY_TOT_HITM, + DISPLAY_SNP_PEER, DISPLAY_MAX, }; @@ -125,6 +126,7 @@ static const char *display_str[DISPLAY_MAX] = { [DISPLAY_LCL_HITM] = "Local HITMs", [DISPLAY_RMT_HITM] = "Remote HITMs", [DISPLAY_TOT_HITM] = "Total HITMs", + [DISPLAY_SNP_PEER] = "Peer Snoop", }; static const struct option c2c_options[] = { @@ -822,6 +824,11 @@ static double percent_costly_snoop(struct c2c_hist_entry *c2c_he) case DISPLAY_TOT_HITM: st = stats->tot_hitm; tot = total->tot_hitm; + break; + case DISPLAY_SNP_PEER: + st = stats->tot_peer; + tot = total->tot_peer; + break; default: break; } @@ -1229,6 +1236,10 @@ node_entry(struct perf_hpp_fmt *fmt __maybe_unused, struct perf_hpp *hpp, ret = display_metrics(hpp, stats->tot_hitm, c2c_he->stats.tot_hitm); break; + case DISPLAY_SNP_PEER: + ret = display_metrics(hpp, stats->tot_peer, + c2c_he->stats.tot_peer); + break; default: break; } @@ -1609,6 +1620,7 @@ static struct c2c_header percent_costly_snoop_header[] = { [DISPLAY_LCL_HITM] = HEADER_BOTH("Lcl", "Hitm"), [DISPLAY_RMT_HITM] = HEADER_BOTH("Rmt", "Hitm"), [DISPLAY_TOT_HITM] = HEADER_BOTH("Tot", "Hitm"), + [DISPLAY_SNP_PEER] = HEADER_BOTH("Peer", "Snoop"), }; static struct c2c_dimension dim_percent_costly_snoop = { @@ -2107,6 +2119,10 @@ static bool he__display(struct hist_entry *he, struct c2c_stats *stats) he->filtered = filter_display(c2c_he->stats.tot_hitm, stats->tot_hitm); break; + case DISPLAY_SNP_PEER: + he->filtered = filter_display(c2c_he->stats.tot_peer, + stats->tot_peer); + break; default: break; } @@ -2135,6 +2151,8 @@ static inline bool is_valid_hist_entry(struct hist_entry *he) case DISPLAY_TOT_HITM: has_record = !!c2c_he->stats.tot_hitm; break; + case DISPLAY_SNP_PEER: + has_record = !!c2c_he->stats.tot_peer; default: break; } @@ -2224,7 +2242,10 @@ static int resort_cl_cb(struct hist_entry *he, void *arg __maybe_unused) } static struct c2c_header header_node_0 = HEADER_LOW("Node"); -static struct c2c_header header_node_1 = HEADER_LOW("Node{cpus %hitms %stores}"); +static struct c2c_header header_node_1_hitms_stores = + HEADER_LOW("Node{cpus %hitms %stores}"); +static struct c2c_header header_node_1_peers_stores = + HEADER_LOW("Node{cpus %peers %stores}"); static struct c2c_header header_node_2 = HEADER_LOW("Node{cpu list}"); static void setup_nodes_header(void) @@ -2234,7 +2255,10 @@ static void setup_nodes_header(void) dim_node.header = header_node_0; break; case 1: - dim_node.header = header_node_1; + if (c2c.display == DISPLAY_SNP_PEER) + dim_node.header = header_node_1_peers_stores; + else + dim_node.header = header_node_1_hitms_stores; break; case 2: dim_node.header = header_node_2; @@ -2308,13 +2332,14 @@ static int setup_nodes(struct perf_session *session) } #define HAS_HITMS(__h) ((__h)->stats.lcl_hitm || (__h)->stats.rmt_hitm) +#define HAS_PEER(__h) ((__h)->stats.lcl_peer || (__h)->stats.rmt_peer) static int resort_shared_cl_cb(struct hist_entry *he, void *arg __maybe_unused) { struct c2c_hist_entry *c2c_he; c2c_he = container_of(he, struct c2c_hist_entry, he); - if (HAS_HITMS(c2c_he)) { + if (HAS_HITMS(c2c_he) || HAS_PEER(c2c_he)) { c2c.shared_clines++; c2c_add_stats(&c2c.shared_clines_stats, &c2c_he->stats); } @@ -2447,13 +2472,22 @@ static void print_pareto(FILE *out) int ret; const char *cl_output; - cl_output = "cl_num," - "cl_rmt_hitm," - "cl_lcl_hitm," - "cl_stores_l1hit," - "cl_stores_l1miss," - "cl_stores_na," - "dcacheline"; + if (c2c.display != DISPLAY_SNP_PEER) + cl_output = "cl_num," + "cl_rmt_hitm," + "cl_lcl_hitm," + "cl_stores_l1hit," + "cl_stores_l1miss," + "cl_stores_na," + "dcacheline"; + else + cl_output = "cl_num," + "cl_rmt_peer," + "cl_lcl_peer," + "cl_stores_l1hit," + "cl_stores_l1miss," + "cl_stores_na," + "dcacheline"; perf_hpp_list__init(&hpp_list); ret = hpp_list__parse(&hpp_list, cl_output, NULL); @@ -2852,6 +2886,8 @@ static int setup_display(const char *str) c2c.display = DISPLAY_RMT_HITM; else if (!strcmp(display, "lcl")) c2c.display = DISPLAY_LCL_HITM; + else if (!strcmp(display, "peer")) + c2c.display = DISPLAY_SNP_PEER; else { pr_err("failed: unknown display type: %s\n", str); return -1; @@ -2898,10 +2934,12 @@ static int build_cl_output(char *cl_sort, bool no_source) } if (asprintf(&c2c.cl_output, - "%s%s%s%s%s%s%s%s%s%s", + "%s%s%s%s%s%s%s%s%s%s%s%s", c2c.use_stdio ? "cl_num_empty," : "", - "percent_rmt_hitm," - "percent_lcl_hitm," + c2c.display == DISPLAY_SNP_PEER ? "percent_rmt_peer," + "percent_lcl_peer," : + "percent_rmt_hitm," + "percent_lcl_hitm,", "percent_stores_l1hit," "percent_stores_l1miss," "percent_stores_na," @@ -2909,8 +2947,10 @@ static int build_cl_output(char *cl_sort, bool no_source) add_pid ? "pid," : "", add_tid ? "tid," : "", add_iaddr ? "iaddr," : "", - "mean_rmt," - "mean_lcl," + c2c.display == DISPLAY_SNP_PEER ? "mean_rmt_peer," + "mean_lcl_peer," : + "mean_rmt," + "mean_lcl,", "mean_load," "tot_recs," "cpucnt,", @@ -2931,6 +2971,7 @@ err: static int setup_coalesce(const char *coalesce, bool no_source) { const char *c = coalesce ?: coalesce_default; + const char *sort_str = NULL; if (asprintf(&c2c.cl_sort, "offset,%s", c) < 0) return -ENOMEM; @@ -2938,12 +2979,16 @@ static int setup_coalesce(const char *coalesce, bool no_source) if (build_cl_output(c2c.cl_sort, no_source)) return -1; - if (asprintf(&c2c.cl_resort, "offset,%s", - c2c.display == DISPLAY_TOT_HITM ? - "tot_hitm" : - c2c.display == DISPLAY_RMT_HITM ? - "rmt_hitm,lcl_hitm" : - "lcl_hitm,rmt_hitm") < 0) + if (c2c.display == DISPLAY_TOT_HITM) + sort_str = "tot_hitm"; + else if (c2c.display == DISPLAY_RMT_HITM) + sort_str = "rmt_hitm,lcl_hitm"; + else if (c2c.display == DISPLAY_LCL_HITM) + sort_str = "lcl_hitm,rmt_hitm"; + else if (c2c.display == DISPLAY_SNP_PEER) + sort_str = "tot_peer"; + + if (asprintf(&c2c.cl_resort, "offset,%s", sort_str) < 0) return -ENOMEM; pr_debug("coalesce sort fields: %s\n", c2c.cl_sort); @@ -2989,7 +3034,7 @@ static int perf_c2c__report(int argc, const char **argv) "print_type,threshold[,print_limit],order,sort_key[,branch],value", callchain_help, &parse_callchain_opt, callchain_default_opt), - OPT_STRING('d', "display", &display, "Switch HITM output type", "lcl,rmt"), + OPT_STRING('d', "display", &display, "Switch HITM output type", "tot,lcl,rmt,peer"), OPT_STRING('c', "coalesce", &coalesce, "coalesce fields", "coalesce fields: pid,tid,iaddr,dso"), OPT_BOOLEAN('f', "force", &symbol_conf.force, "don't complain, do it"), @@ -3084,20 +3129,36 @@ static int perf_c2c__report(int argc, const char **argv) goto out_mem2node; } - output_str = "cl_idx," - "dcacheline," - "dcacheline_node," - "dcacheline_count," - "percent_costly_snoop," - "tot_hitm,lcl_hitm,rmt_hitm," - "tot_recs," - "tot_loads," - "tot_stores," - "stores_l1hit,stores_l1miss,stores_na," - "ld_fbhit,ld_l1hit,ld_l2hit," - "ld_lclhit,lcl_hitm," - "ld_rmthit,rmt_hitm," - "dram_lcl,dram_rmt"; + if (c2c.display != DISPLAY_SNP_PEER) + output_str = "cl_idx," + "dcacheline," + "dcacheline_node," + "dcacheline_count," + "percent_costly_snoop," + "tot_hitm,lcl_hitm,rmt_hitm," + "tot_recs," + "tot_loads," + "tot_stores," + "stores_l1hit,stores_l1miss,stores_na," + "ld_fbhit,ld_l1hit,ld_l2hit," + "ld_lclhit,lcl_hitm," + "ld_rmthit,rmt_hitm," + "dram_lcl,dram_rmt"; + else + output_str = "cl_idx," + "dcacheline," + "dcacheline_node," + "dcacheline_count," + "percent_costly_snoop," + "tot_peer,lcl_peer,rmt_peer," + "tot_recs," + "tot_loads," + "tot_stores," + "stores_l1hit,stores_l1miss,stores_na," + "ld_fbhit,ld_l1hit,ld_l2hit," + "ld_lclhit,lcl_hitm," + "ld_rmthit,rmt_hitm," + "dram_lcl,dram_rmt"; if (c2c.display == DISPLAY_TOT_HITM) sort_str = "tot_hitm"; @@ -3105,6 +3166,8 @@ static int perf_c2c__report(int argc, const char **argv) sort_str = "rmt_hitm"; else if (c2c.display == DISPLAY_LCL_HITM) sort_str = "lcl_hitm"; + else if (c2c.display == DISPLAY_SNP_PEER) + sort_str = "tot_peer"; c2c_hists__reinit(&c2c.hists, output_str, sort_str); -- cgit v1.2.3 From ead42a0f9b93c3447a24be08a9e80941e99b8a50 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Thu, 11 Aug 2022 14:24:50 +0800 Subject: perf c2c: Use 'peer' as default display for Arm64 Since Arm64 arch doesn't support HITMs flags, this patch changes to use 'peer' as default display if user doesn't specify any type; for other arches, it still uses 'tot' as default display type if user doesn't specify it. This patch changes to call perf_session__new() in an earlier place, so session environment can be initialized ahead and arch info can be used for setting display type. Suggested-by: Ali Saidi Reviewed-by: Ali Saidi Signed-off-by: Leo Yan Tested-by: Ali Saidi Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Anshuman Khandual Cc: German Gomez Cc: Gustavo A. R. Silva Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Like Xu Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Timothy Hayes Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220811062451.435810-15-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-c2c.c | 36 ++++++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c index f7a961e55a92..653e13b5037e 100644 --- a/tools/perf/builtin-c2c.c +++ b/tools/perf/builtin-c2c.c @@ -2878,7 +2878,7 @@ static int setup_callchain(struct evlist *evlist) static int setup_display(const char *str) { - const char *display = str ?: "tot"; + const char *display = str; if (!strcmp(display, "tot")) c2c.display = DISPLAY_TOT_HITM; @@ -3068,27 +3068,39 @@ static int perf_c2c__report(int argc, const char **argv) data.path = input_name; data.force = symbol_conf.force; + session = perf_session__new(&data, &c2c.tool); + if (IS_ERR(session)) { + err = PTR_ERR(session); + pr_debug("Error creating perf session\n"); + goto out; + } + + /* + * Use the 'tot' as default display type if user doesn't specify it; + * since Arm64 platform doesn't support HITMs flag, use 'peer' as the + * default display type. + */ + if (!display) { + if (!strcmp(perf_env__arch(&session->header.env), "arm64")) + display = "peer"; + else + display = "tot"; + } + err = setup_display(display); if (err) - goto out; + goto out_session; err = setup_coalesce(coalesce, no_source); if (err) { pr_debug("Failed to initialize hists\n"); - goto out; + goto out_session; } err = c2c_hists__init(&c2c.hists, "dcacheline", 2); if (err) { pr_debug("Failed to initialize hists\n"); - goto out; - } - - session = perf_session__new(&data, &c2c.tool); - if (IS_ERR(session)) { - err = PTR_ERR(session); - pr_debug("Error creating perf session\n"); - goto out; + goto out_session; } session->itrace_synth_opts = &itrace_synth_opts; @@ -3096,7 +3108,7 @@ static int perf_c2c__report(int argc, const char **argv) err = setup_nodes(session); if (err) { pr_err("Failed setup nodes\n"); - goto out; + goto out_session; } err = mem2node__init(&c2c.mem2node, &session->header.env); -- cgit v1.2.3 From e754dd7e8be86e1adc9d4d13fb1105b848c11752 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Thu, 11 Aug 2022 14:24:51 +0800 Subject: perf c2c: Update documentation for new display option 'peer' Since the new display option 'peer' is introduced, this patch is to update the documentation to reflect it. Reviewed-by: Ali Saidi Signed-off-by: Leo Yan Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Anshuman Khandual Cc: German Gomez Cc: Gustavo A. R. Silva Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Like Xu Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Timothy Hayes Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220811062451.435810-16-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Documentation/perf-c2c.txt | 31 ++++++++++++++++++++++++------- 1 file changed, 24 insertions(+), 7 deletions(-) diff --git a/tools/perf/Documentation/perf-c2c.txt b/tools/perf/Documentation/perf-c2c.txt index 6f69173731aa..f1f7ae6b08d1 100644 --- a/tools/perf/Documentation/perf-c2c.txt +++ b/tools/perf/Documentation/perf-c2c.txt @@ -109,7 +109,9 @@ REPORT OPTIONS -d:: --display:: - Switch to HITM type (rmt, lcl) to display and sort on. Total HITMs as default. + Switch to HITM type (rmt, lcl) or peer snooping type (peer) to display + and sort on. Total HITMs (tot) as default, except Arm64 uses peer mode + as default. --stitch-lbr:: Show callgraph with stitched LBRs, which may have more complete @@ -174,12 +176,18 @@ For each cacheline in the 1) list we display following data: Cacheline - cacheline address (hex number) - Rmt/Lcl Hitm + Rmt/Lcl Hitm (Display with HITM types) - cacheline percentage of all Remote/Local HITM accesses - LLC Load Hitm - Total, LclHitm, RmtHitm + Peer Snoop (Display with peer type) + - cacheline percentage of all peer accesses + + LLC Load Hitm - Total, LclHitm, RmtHitm (For display with HITM types) - count of Total/Local/Remote load HITMs + Load Peer - Total, Local, Remote (For display with peer type) + - count of Total/Local/Remote load from peer cache or DRAM + Total records - sum of all cachelines accesses @@ -201,16 +209,21 @@ For each cacheline in the 1) list we display following data: - count of LLC load accesses, includes LLC hits and LLC HITMs RMT Load Hit - RmtHit, RmtHitm - - count of remote load accesses, includes remote hits and remote HITMs + - count of remote load accesses, includes remote hits and remote HITMs; + on Arm neoverse cores, RmtHit is used to account remote accesses, + includes remote DRAM or any upward cache level in remote node Load Dram - Lcl, Rmt - count of local and remote DRAM accesses For each offset in the 2) list we display following data: - HITM - Rmt, Lcl + HITM - Rmt, Lcl (Display with HITM types) - % of Remote/Local HITM accesses for given offset within cacheline + Peer Snoop - Rmt, Lcl (Display with peer type) + - % of Remote/Local peer accesses for given offset within cacheline + Store Refs - L1 Hit, L1 Miss, N/A - % of store accesses that hit L1, missed L1 and N/A (no available) memory level for given offset within cacheline @@ -227,9 +240,12 @@ For each offset in the 2) list we display following data: Code address - code address responsible for the accesses - cycles - rmt hitm, lcl hitm, load + cycles - rmt hitm, lcl hitm, load (Display with HITM types) - sum of cycles for given accesses - Remote/Local HITM and generic load + cycles - rmt peer, lcl peer, load (Display with peer type) + - sum of cycles for given accesses - Remote/Local peer load and generic load + cpu cnt - number of cpus that participated on the access @@ -251,7 +267,8 @@ The 'Node' field displays nodes that accesses given cacheline offset. Its output comes in 3 flavors: - node IDs separated by ',' - node IDs with stats for each ID, in following format: - Node{cpus %hitms %stores} + Node{cpus %hitms %stores} (Display with HITM types) + Node{cpus %peers %stores} (Display with peer type) - node IDs with list of affected CPUs in following format: Node{cpu list} -- cgit v1.2.3 From dcb45fd7f501f86481473bde14fa0a9069ad5cdc Mon Sep 17 00:00:00 2001 From: Ronnie Sahlberg Date: Tue, 9 Aug 2022 12:11:49 +1000 Subject: cifs: Do not use tcon->cfid directly, use the cfid we get from open_cached_dir They are the same right now but tcon-> will later point to a different type of struct containing a list of cfids. Signed-off-by: Ronnie Sahlberg Reviewed-by: Paulo Alcantara (SUSE) Signed-off-by: Steve French --- fs/cifs/smb2inode.c | 4 ++-- fs/cifs/smb2pdu.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/fs/cifs/smb2inode.c b/fs/cifs/smb2inode.c index f6f9fc3f2e2d..09f01f70e020 100644 --- a/fs/cifs/smb2inode.c +++ b/fs/cifs/smb2inode.c @@ -519,9 +519,9 @@ smb2_query_path_info(const unsigned int xid, struct cifs_tcon *tcon, rc = open_cached_dir(xid, tcon, full_path, cifs_sb, &cfid); /* If it is a root and its handle is cached then use it */ if (!rc) { - if (tcon->cfid.file_all_info_is_valid) { + if (cfid->file_all_info_is_valid) { move_smb2_info_to_cifs(data, - &tcon->cfid.file_all_info); + &cfid->file_all_info); } else { rc = SMB2_query_info(xid, tcon, cfid->fid->persistent_fid, diff --git a/fs/cifs/smb2pdu.c b/fs/cifs/smb2pdu.c index 7c200b938267..9b31ea946d45 100644 --- a/fs/cifs/smb2pdu.c +++ b/fs/cifs/smb2pdu.c @@ -1979,7 +1979,7 @@ SMB2_tdis(const unsigned int xid, struct cifs_tcon *tcon) } spin_unlock(&ses->chan_lock); - close_cached_dir_lease(&tcon->cfid); + invalidate_all_cached_dirs(tcon); rc = smb2_plain_req_init(SMB2_TREE_DISCONNECT, tcon, ses->server, (void **) &req, -- cgit v1.2.3 From 5efdd9122eff772eae2feae9f0fc0ec02d4846a3 Mon Sep 17 00:00:00 2001 From: Steve French Date: Thu, 11 Aug 2022 00:53:00 -0500 Subject: smb3: allow deferred close timeout to be configurable Deferred close can be a very useful feature for allowing caching data for read, and for minimizing the number of reopens needed for a file that is repeatedly opened and close but there are workloads where its default (1 second, similar to actimeo/acregmax) is much too small. Allow the user to configure the amount of time we can defer sending the final smb3 close when we have a handle lease on the file (rather than forcing it to depend on value of actimeo which is often unrelated, and less safe). Adds new mount parameter "closetimeo=" which is the maximum number of seconds we can wait before sending an SMB3 close when we have a handle lease for it. Default value also is set to slightly larger at 5 seconds (although some other clients use larger default this should still help). Suggested-by: Bharath SM Reviewed-by: Bharath SM Reviewed-by: Shyam Prasad N Reviewed-by: Paulo Alcantara (SUSE) Signed-off-by: Steve French --- fs/cifs/cifsfs.c | 1 + fs/cifs/connect.c | 2 ++ fs/cifs/file.c | 4 ++-- fs/cifs/fs_context.c | 9 +++++++++ fs/cifs/fs_context.h | 8 ++++++++ 5 files changed, 22 insertions(+), 2 deletions(-) diff --git a/fs/cifs/cifsfs.c b/fs/cifs/cifsfs.c index 945fb083cea7..f54d8bf2732a 100644 --- a/fs/cifs/cifsfs.c +++ b/fs/cifs/cifsfs.c @@ -693,6 +693,7 @@ cifs_show_options(struct seq_file *s, struct dentry *root) seq_printf(s, ",acdirmax=%lu", cifs_sb->ctx->acdirmax / HZ); seq_printf(s, ",acregmax=%lu", cifs_sb->ctx->acregmax / HZ); } + seq_printf(s, ",closetimeo=%lu", cifs_sb->ctx->closetimeo / HZ); if (tcon->ses->chan_max > 1) seq_printf(s, ",multichannel,max_channels=%zu", diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c index 7f205a9a2de4..9111c025bcb8 100644 --- a/fs/cifs/connect.c +++ b/fs/cifs/connect.c @@ -2681,6 +2681,8 @@ compare_mount_options(struct super_block *sb, struct cifs_mnt_data *mnt_data) return 0; if (old->ctx->acdirmax != new->ctx->acdirmax) return 0; + if (old->ctx->closetimeo != new->ctx->closetimeo) + return 0; return 1; } diff --git a/fs/cifs/file.c b/fs/cifs/file.c index 42f2639a1a66..2c5eae7d31f4 100644 --- a/fs/cifs/file.c +++ b/fs/cifs/file.c @@ -964,12 +964,12 @@ int cifs_close(struct inode *inode, struct file *file) * So, Increase the ref count to avoid use-after-free. */ if (!mod_delayed_work(deferredclose_wq, - &cfile->deferred, cifs_sb->ctx->acregmax)) + &cfile->deferred, cifs_sb->ctx->closetimeo)) cifsFileInfo_get(cfile); } else { /* Deferred close for files */ queue_delayed_work(deferredclose_wq, - &cfile->deferred, cifs_sb->ctx->acregmax); + &cfile->deferred, cifs_sb->ctx->closetimeo); cfile->deferred_close_scheduled = true; spin_unlock(&cinode->deferred_lock); return 0; diff --git a/fs/cifs/fs_context.c b/fs/cifs/fs_context.c index 8dc0d923ef6a..0e13dec86b25 100644 --- a/fs/cifs/fs_context.c +++ b/fs/cifs/fs_context.c @@ -147,6 +147,7 @@ const struct fs_parameter_spec smb3_fs_parameters[] = { fsparam_u32("actimeo", Opt_actimeo), fsparam_u32("acdirmax", Opt_acdirmax), fsparam_u32("acregmax", Opt_acregmax), + fsparam_u32("closetimeo", Opt_closetimeo), fsparam_u32("echo_interval", Opt_echo_interval), fsparam_u32("max_credits", Opt_max_credits), fsparam_u32("handletimeout", Opt_handletimeout), @@ -1074,6 +1075,13 @@ static int smb3_fs_context_parse_param(struct fs_context *fc, } ctx->acdirmax = ctx->acregmax = HZ * result.uint_32; break; + case Opt_closetimeo: + ctx->closetimeo = HZ * result.uint_32; + if (ctx->closetimeo > SMB3_MAX_DCLOSETIMEO) { + cifs_errorf(fc, "closetimeo too large\n"); + goto cifs_parse_mount_err; + } + break; case Opt_echo_interval: ctx->echo_interval = result.uint_32; break; @@ -1521,6 +1529,7 @@ int smb3_init_fs_context(struct fs_context *fc) ctx->acregmax = CIFS_DEF_ACTIMEO; ctx->acdirmax = CIFS_DEF_ACTIMEO; + ctx->closetimeo = SMB3_DEF_DCLOSETIMEO; /* Most clients set timeout to 0, allows server to use its default */ ctx->handle_timeout = 0; /* See MS-SMB2 spec section 2.2.14.2.12 */ diff --git a/fs/cifs/fs_context.h b/fs/cifs/fs_context.h index 5f093cb7e9b9..bbaee4c2281f 100644 --- a/fs/cifs/fs_context.h +++ b/fs/cifs/fs_context.h @@ -125,6 +125,7 @@ enum cifs_param { Opt_actimeo, Opt_acdirmax, Opt_acregmax, + Opt_closetimeo, Opt_echo_interval, Opt_max_credits, Opt_snapshot, @@ -247,6 +248,8 @@ struct smb3_fs_context { /* attribute cache timemout for files and directories in jiffies */ unsigned long acregmax; unsigned long acdirmax; + /* timeout for deferred close of files in jiffies */ + unsigned long closetimeo; struct smb_version_operations *ops; struct smb_version_values *vals; char *prepath; @@ -279,4 +282,9 @@ static inline struct smb3_fs_context *smb3_fc2context(const struct fs_context *f extern int smb3_fs_context_dup(struct smb3_fs_context *new_ctx, struct smb3_fs_context *ctx); extern void smb3_update_mnt_flags(struct cifs_sb_info *cifs_sb); +/* + * max deferred close timeout (jiffies) - 2^30 + */ +#define SMB3_MAX_DCLOSETIMEO (1 << 30) +#define SMB3_DEF_DCLOSETIMEO (5 * HZ) /* Can increase later, other clients use larger */ #endif -- cgit v1.2.3 From 9e31678fb403eae0f4fe37c6374be098835c73cd Mon Sep 17 00:00:00 2001 From: Bharath SM Date: Thu, 11 Aug 2022 19:46:11 +0000 Subject: SMB3: fix lease break timeout when multiple deferred close handles for the same file. Solution is to send lease break ack immediately even in case of deferred close handles to avoid lease break request timing out and let deferred closed handle gets closed as scheduled. Later patches could optimize cases where we then close some of these handles sooner for the cases where lease break is to 'none' Cc: stable@kernel.org Signed-off-by: Bharath SM Signed-off-by: Steve French --- fs/cifs/file.c | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-) diff --git a/fs/cifs/file.c b/fs/cifs/file.c index 2c5eae7d31f4..c00f71884b82 100644 --- a/fs/cifs/file.c +++ b/fs/cifs/file.c @@ -5061,8 +5061,6 @@ void cifs_oplock_break(struct work_struct *work) struct TCP_Server_Info *server = tcon->ses->server; int rc = 0; bool purge_cache = false; - bool is_deferred = false; - struct cifs_deferred_close *dclose; wait_on_bit(&cinode->flags, CIFS_INODE_PENDING_WRITERS, TASK_UNINTERRUPTIBLE); @@ -5098,22 +5096,6 @@ void cifs_oplock_break(struct work_struct *work) cifs_dbg(VFS, "Push locks rc = %d\n", rc); oplock_break_ack: - /* - * When oplock break is received and there are no active - * file handles but cached, then schedule deferred close immediately. - * So, new open will not use cached handle. - */ - spin_lock(&CIFS_I(inode)->deferred_lock); - is_deferred = cifs_is_deferred_close(cfile, &dclose); - spin_unlock(&CIFS_I(inode)->deferred_lock); - if (is_deferred && - cfile->deferred_close_scheduled && - delayed_work_pending(&cfile->deferred)) { - if (cancel_delayed_work(&cfile->deferred)) { - _cifsFileInfo_put(cfile, false, false); - goto oplock_break_done; - } - } /* * releasing stale oplock after recent reconnect of smb session using * a now incorrect file handle is not a data integrity issue but do @@ -5125,7 +5107,7 @@ oplock_break_ack: cinode); cifs_dbg(FYI, "Oplock release rc = %d\n", rc); } -oplock_break_done: + _cifsFileInfo_put(cfile, false /* do not wait for ourself */, false); cifs_done_oplock_break(cinode); } -- cgit v1.2.3 From a63ec83c462b5b1439f71ace751e8985dfb3fcab Mon Sep 17 00:00:00 2001 From: Ronnie Sahlberg Date: Thu, 11 Aug 2022 19:04:29 -0500 Subject: cifs: Add constructor/destructors for tcon->cfid and move the structure definitions into cached_dir.h Reviewed-by: Paulo Alcantara (SUSE) Signed-off-by: Ronnie Sahlberg Signed-off-by: Steve French --- fs/cifs/cached_dir.c | 110 +++++++++++++++++++++++++++++++-------------------- fs/cifs/cached_dir.h | 38 ++++++++++++++++++ fs/cifs/cifsglob.h | 38 +----------------- fs/cifs/misc.c | 20 +++++----- fs/cifs/smb2inode.c | 4 +- fs/cifs/smb2ops.c | 8 ++-- 6 files changed, 121 insertions(+), 97 deletions(-) diff --git a/fs/cifs/cached_dir.c b/fs/cifs/cached_dir.c index 753b850b6f87..78e8deb82a0a 100644 --- a/fs/cifs/cached_dir.c +++ b/fs/cifs/cached_dir.c @@ -18,7 +18,7 @@ int open_cached_dir(unsigned int xid, struct cifs_tcon *tcon, const char *path, struct cifs_sb_info *cifs_sb, - struct cached_fid **cfid) + struct cached_fid **ret_cfid) { struct cifs_ses *ses; struct TCP_Server_Info *server; @@ -35,6 +35,7 @@ int open_cached_dir(unsigned int xid, struct cifs_tcon *tcon, u8 oplock = SMB2_OPLOCK_LEVEL_II; struct cifs_fid *pfid; struct dentry *dentry; + struct cached_fid *cfid; if (tcon == NULL || tcon->nohandlecache || is_smb1_server(tcon->ses->server)) @@ -51,12 +52,13 @@ int open_cached_dir(unsigned int xid, struct cifs_tcon *tcon, dentry = cifs_sb->root; - mutex_lock(&tcon->cfid.fid_mutex); - if (tcon->cfid.is_valid) { + cfid = tcon->cfid; + mutex_lock(&cfid->fid_mutex); + if (cfid->is_valid) { cifs_dbg(FYI, "found a cached root file handle\n"); - *cfid = &tcon->cfid; - kref_get(&tcon->cfid.refcount); - mutex_unlock(&tcon->cfid.fid_mutex); + *ret_cfid = cfid; + kref_get(&cfid->refcount); + mutex_unlock(&cfid->fid_mutex); return 0; } @@ -67,7 +69,7 @@ int open_cached_dir(unsigned int xid, struct cifs_tcon *tcon, * thus causing a deadlock */ - mutex_unlock(&tcon->cfid.fid_mutex); + mutex_unlock(&cfid->fid_mutex); if (smb3_encryption_required(tcon)) flags |= CIFS_TRANSFORM_REQ; @@ -75,7 +77,7 @@ int open_cached_dir(unsigned int xid, struct cifs_tcon *tcon, if (!server->ops->new_lease_key) return -EIO; - pfid = tcon->cfid.fid; + pfid = &cfid->fid; server->ops->new_lease_key(pfid); memset(rqst, 0, sizeof(rqst)); @@ -118,14 +120,14 @@ int open_cached_dir(unsigned int xid, struct cifs_tcon *tcon, rc = compound_send_recv(xid, ses, server, flags, 2, rqst, resp_buftype, rsp_iov); - mutex_lock(&tcon->cfid.fid_mutex); + mutex_lock(&cfid->fid_mutex); /* * Now we need to check again as the cached root might have * been successfully re-opened from a concurrent process */ - if (tcon->cfid.is_valid) { + if (cfid->is_valid) { /* work was already done */ /* stash fids for close() later */ @@ -138,9 +140,9 @@ int open_cached_dir(unsigned int xid, struct cifs_tcon *tcon, * caller expects this func to set the fid in cfid to valid * cached root, so increment the refcount. */ - kref_get(&tcon->cfid.refcount); + kref_get(&cfid->refcount); - mutex_unlock(&tcon->cfid.fid_mutex); + mutex_unlock(&cfid->fid_mutex); if (rc == 0) { /* close extra handle outside of crit sec */ @@ -170,11 +172,11 @@ int open_cached_dir(unsigned int xid, struct cifs_tcon *tcon, oparms.fid->mid = le64_to_cpu(o_rsp->hdr.MessageId); #endif /* CIFS_DEBUG2 */ - tcon->cfid.tcon = tcon; - tcon->cfid.is_valid = true; - tcon->cfid.dentry = dentry; + cfid->tcon = tcon; + cfid->is_valid = true; + cfid->dentry = dentry; dget(dentry); - kref_init(&tcon->cfid.refcount); + kref_init(&cfid->refcount); /* BB TBD check to see if oplock level check can be removed below */ if (o_rsp->OplockLevel == SMB2_OPLOCK_LEVEL_LEASE) { @@ -182,8 +184,8 @@ int open_cached_dir(unsigned int xid, struct cifs_tcon *tcon, * See commit 2f94a3125b87. Increment the refcount when we * get a lease for root, release it if lease break occurs */ - kref_get(&tcon->cfid.refcount); - tcon->cfid.has_lease = true; + kref_get(&cfid->refcount); + cfid->has_lease = true; smb2_parse_contexts(server, o_rsp, &oparms.fid->epoch, oparms.fid->lease_key, &oplock, @@ -198,37 +200,41 @@ int open_cached_dir(unsigned int xid, struct cifs_tcon *tcon, le16_to_cpu(qi_rsp->OutputBufferOffset), sizeof(struct smb2_file_all_info), &rsp_iov[1], sizeof(struct smb2_file_all_info), - (char *)&tcon->cfid.file_all_info)) - tcon->cfid.file_all_info_is_valid = true; - tcon->cfid.time = jiffies; + (char *)&cfid->file_all_info)) + cfid->file_all_info_is_valid = true; + cfid->time = jiffies; oshr_exit: - mutex_unlock(&tcon->cfid.fid_mutex); + mutex_unlock(&cfid->fid_mutex); oshr_free: SMB2_open_free(&rqst[0]); SMB2_query_info_free(&rqst[1]); free_rsp_buf(resp_buftype[0], rsp_iov[0].iov_base); free_rsp_buf(resp_buftype[1], rsp_iov[1].iov_base); if (rc == 0) - *cfid = &tcon->cfid; + *ret_cfid = cfid; return rc; } int open_cached_dir_by_dentry(struct cifs_tcon *tcon, struct dentry *dentry, - struct cached_fid **cfid) + struct cached_fid **ret_cfid) { - mutex_lock(&tcon->cfid.fid_mutex); - if (tcon->cfid.dentry == dentry) { + struct cached_fid *cfid; + + cfid = tcon->cfid; + + mutex_lock(&cfid->fid_mutex); + if (cfid->dentry == dentry) { cifs_dbg(FYI, "found a cached root file handle by dentry\n"); - *cfid = &tcon->cfid; - kref_get(&tcon->cfid.refcount); - mutex_unlock(&tcon->cfid.fid_mutex); + *ret_cfid = cfid; + kref_get(&cfid->refcount); + mutex_unlock(&cfid->fid_mutex); return 0; } - mutex_unlock(&tcon->cfid.fid_mutex); + mutex_unlock(&cfid->fid_mutex); return -ENOENT; } @@ -241,8 +247,8 @@ smb2_close_cached_fid(struct kref *ref) if (cfid->is_valid) { cifs_dbg(FYI, "clear cached root file handle\n"); - SMB2_close(0, cfid->tcon, cfid->fid->persistent_fid, - cfid->fid->volatile_fid); + SMB2_close(0, cfid->tcon, cfid->fid.persistent_fid, + cfid->fid.volatile_fid); } /* @@ -312,7 +318,7 @@ void close_all_cached_dirs(struct cifs_sb_info *cifs_sb) tcon = tlink_tcon(tlink); if (IS_ERR(tcon)) continue; - cfid = &tcon->cfid; + cfid = tcon->cfid; mutex_lock(&cfid->fid_mutex); if (cfid->dentry) { dput(cfid->dentry); @@ -328,12 +334,12 @@ void close_all_cached_dirs(struct cifs_sb_info *cifs_sb) */ void invalidate_all_cached_dirs(struct cifs_tcon *tcon) { - mutex_lock(&tcon->cfid.fid_mutex); - tcon->cfid.is_valid = false; + mutex_lock(&tcon->cfid->fid_mutex); + tcon->cfid->is_valid = false; /* cached handle is not valid, so SMB2_CLOSE won't be sent below */ - close_cached_dir_lease_locked(&tcon->cfid); - memset(tcon->cfid.fid, 0, sizeof(struct cifs_fid)); - mutex_unlock(&tcon->cfid.fid_mutex); + close_cached_dir_lease_locked(tcon->cfid); + memset(&tcon->cfid->fid, 0, sizeof(struct cifs_fid)); + mutex_unlock(&tcon->cfid->fid_mutex); } static void @@ -347,16 +353,34 @@ smb2_cached_lease_break(struct work_struct *work) int cached_dir_lease_break(struct cifs_tcon *tcon, __u8 lease_key[16]) { - if (tcon->cfid.is_valid && + if (tcon->cfid->is_valid && !memcmp(lease_key, - tcon->cfid.fid->lease_key, + tcon->cfid->fid.lease_key, SMB2_LEASE_KEY_SIZE)) { - tcon->cfid.time = 0; - INIT_WORK(&tcon->cfid.lease_break, + tcon->cfid->time = 0; + INIT_WORK(&tcon->cfid->lease_break, smb2_cached_lease_break); queue_work(cifsiod_wq, - &tcon->cfid.lease_break); + &tcon->cfid->lease_break); return true; } return false; } + +struct cached_fid *init_cached_dir(void) +{ + struct cached_fid *cfid; + + cfid = kzalloc(sizeof(*cfid), GFP_KERNEL); + if (!cfid) + return NULL; + INIT_LIST_HEAD(&cfid->dirents.entries); + mutex_init(&cfid->dirents.de_mutex); + mutex_init(&cfid->fid_mutex); + return cfid; +} + +void free_cached_dir(struct cifs_tcon *tcon) +{ + kfree(tcon->cfid); +} diff --git a/fs/cifs/cached_dir.h b/fs/cifs/cached_dir.h index 51c6b968f8b6..89c0343d7e26 100644 --- a/fs/cifs/cached_dir.h +++ b/fs/cifs/cached_dir.h @@ -9,6 +9,44 @@ #define _CACHED_DIR_H +struct cached_dirent { + struct list_head entry; + char *name; + int namelen; + loff_t pos; + + struct cifs_fattr fattr; +}; + +struct cached_dirents { + bool is_valid:1; + bool is_failed:1; + struct dir_context *ctx; /* + * Only used to make sure we only take entries + * from a single context. Never dereferenced. + */ + struct mutex de_mutex; + int pos; /* Expected ctx->pos */ + struct list_head entries; +}; + +struct cached_fid { + bool is_valid:1; /* Do we have a useable root fid */ + bool file_all_info_is_valid:1; + bool has_lease:1; + unsigned long time; /* jiffies of when lease was taken */ + struct kref refcount; + struct cifs_fid fid; + struct mutex fid_mutex; + struct cifs_tcon *tcon; + struct dentry *dentry; + struct work_struct lease_break; + struct smb2_file_all_info file_all_info; + struct cached_dirents dirents; +}; + +extern struct cached_fid *init_cached_dir(void); +extern void free_cached_dir(struct cifs_tcon *tcon); extern int open_cached_dir(unsigned int xid, struct cifs_tcon *tcon, const char *path, struct cifs_sb_info *cifs_sb, diff --git a/fs/cifs/cifsglob.h b/fs/cifs/cifsglob.h index 8b82f13d11e0..bc0ee2d4b47b 100644 --- a/fs/cifs/cifsglob.h +++ b/fs/cifs/cifsglob.h @@ -1128,42 +1128,6 @@ struct cifs_fattr { u32 cf_cifstag; }; -struct cached_dirent { - struct list_head entry; - char *name; - int namelen; - loff_t pos; - - struct cifs_fattr fattr; -}; - -struct cached_dirents { - bool is_valid:1; - bool is_failed:1; - struct dir_context *ctx; /* - * Only used to make sure we only take entries - * from a single context. Never dereferenced. - */ - struct mutex de_mutex; - int pos; /* Expected ctx->pos */ - struct list_head entries; -}; - -struct cached_fid { - bool is_valid:1; /* Do we have a useable root fid */ - bool file_all_info_is_valid:1; - bool has_lease:1; - unsigned long time; /* jiffies of when lease was taken */ - struct kref refcount; - struct cifs_fid *fid; - struct mutex fid_mutex; - struct cifs_tcon *tcon; - struct dentry *dentry; - struct work_struct lease_break; - struct smb2_file_all_info file_all_info; - struct cached_dirents dirents; -}; - /* * there is one of these for each connection to a resource on a particular * session @@ -1257,7 +1221,7 @@ struct cifs_tcon { struct fscache_volume *fscache; /* cookie for share */ #endif struct list_head pending_opens; /* list of incomplete opens */ - struct cached_fid cfid; /* Cached root fid */ + struct cached_fid *cfid; /* Cached root fid */ /* BB add field for back pointer to sb struct(s)? */ #ifdef CONFIG_CIFS_DFS_UPCALL struct list_head ulist; /* cache update list */ diff --git a/fs/cifs/misc.c b/fs/cifs/misc.c index ea0405cfaee3..3f4f3d1a378f 100644 --- a/fs/cifs/misc.c +++ b/fs/cifs/misc.c @@ -23,6 +23,7 @@ #include "dns_resolve.h" #endif #include "fs_context.h" +#include "cached_dir.h" extern mempool_t *cifs_sm_req_poolp; extern mempool_t *cifs_req_poolp; @@ -116,13 +117,11 @@ tconInfoAlloc(void) ret_buf = kzalloc(sizeof(*ret_buf), GFP_KERNEL); if (!ret_buf) return NULL; - ret_buf->cfid.fid = kzalloc(sizeof(*ret_buf->cfid.fid), GFP_KERNEL); - if (!ret_buf->cfid.fid) { + ret_buf->cfid = init_cached_dir(); + if (!ret_buf->cfid) { kfree(ret_buf); return NULL; } - INIT_LIST_HEAD(&ret_buf->cfid.dirents.entries); - mutex_init(&ret_buf->cfid.dirents.de_mutex); atomic_inc(&tconInfoAllocCount); ret_buf->status = TID_NEW; @@ -131,7 +130,6 @@ tconInfoAlloc(void) INIT_LIST_HEAD(&ret_buf->openFileList); INIT_LIST_HEAD(&ret_buf->tcon_list); spin_lock_init(&ret_buf->open_file_lock); - mutex_init(&ret_buf->cfid.fid_mutex); spin_lock_init(&ret_buf->stat_lock); atomic_set(&ret_buf->num_local_opens, 0); atomic_set(&ret_buf->num_remote_opens, 0); @@ -140,17 +138,17 @@ tconInfoAlloc(void) } void -tconInfoFree(struct cifs_tcon *buf_to_free) +tconInfoFree(struct cifs_tcon *tcon) { - if (buf_to_free == NULL) { + if (tcon == NULL) { cifs_dbg(FYI, "Null buffer passed to tconInfoFree\n"); return; } + free_cached_dir(tcon); atomic_dec(&tconInfoAllocCount); - kfree(buf_to_free->nativeFileSystem); - kfree_sensitive(buf_to_free->password); - kfree(buf_to_free->cfid.fid); - kfree(buf_to_free); + kfree(tcon->nativeFileSystem); + kfree_sensitive(tcon->password); + kfree(tcon); } struct smb_hdr * diff --git a/fs/cifs/smb2inode.c b/fs/cifs/smb2inode.c index 09f01f70e020..9696184a09e3 100644 --- a/fs/cifs/smb2inode.c +++ b/fs/cifs/smb2inode.c @@ -524,8 +524,8 @@ smb2_query_path_info(const unsigned int xid, struct cifs_tcon *tcon, &cfid->file_all_info); } else { rc = SMB2_query_info(xid, tcon, - cfid->fid->persistent_fid, - cfid->fid->volatile_fid, smb2_data); + cfid->fid.persistent_fid, + cfid->fid.volatile_fid, smb2_data); if (!rc) move_smb2_info_to_cifs(data, smb2_data); } diff --git a/fs/cifs/smb2ops.c b/fs/cifs/smb2ops.c index 8cb1eed1dd63..6507761a8040 100644 --- a/fs/cifs/smb2ops.c +++ b/fs/cifs/smb2ops.c @@ -722,7 +722,7 @@ smb3_qfs_tcon(const unsigned int xid, struct cifs_tcon *tcon, rc = open_cached_dir(xid, tcon, "", cifs_sb, &cfid); if (rc == 0) - memcpy(&fid, cfid->fid, sizeof(struct cifs_fid)); + memcpy(&fid, &cfid->fid, sizeof(struct cifs_fid)); else rc = SMB2_open(xid, &oparms, &srch_path, &oplock, NULL, NULL, NULL, NULL); @@ -784,7 +784,7 @@ smb2_is_path_accessible(const unsigned int xid, struct cifs_tcon *tcon, struct cifs_open_parms oparms; struct cifs_fid fid; - if ((*full_path == 0) && tcon->cfid.is_valid) + if ((*full_path == 0) && tcon->cfid->is_valid) return 0; utf16_path = cifs_convert_path_to_utf16(full_path, cifs_sb); @@ -2457,8 +2457,8 @@ smb2_query_info_compound(const unsigned int xid, struct cifs_tcon *tcon, if (cfid) { rc = SMB2_query_info_init(tcon, server, &rqst[1], - cfid->fid->persistent_fid, - cfid->fid->volatile_fid, + cfid->fid.persistent_fid, + cfid->fid.volatile_fid, class, type, 0, output_len, 0, NULL); -- cgit v1.2.3 From 28e112afa44ad0814120d41c68fa72372a2cd2c2 Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Tue, 12 Jul 2022 12:25:57 +0800 Subject: LoongArch: cpuinfo: Fix a warning for CONFIG_CPUMASK_OFFSTACK When CONFIG_CPUMASK_OFFSTACK and CONFIG_DEBUG_PER_CPU_MAPS is selected, cpu_max_bits_warn() generates a runtime warning similar as below while we show /proc/cpuinfo. Fix this by using nr_cpu_ids (the runtime limit) instead of NR_CPUS to iterate CPUs. [ 3.052463] ------------[ cut here ]------------ [ 3.059679] WARNING: CPU: 3 PID: 1 at include/linux/cpumask.h:108 show_cpuinfo+0x5e8/0x5f0 [ 3.070072] Modules linked in: efivarfs autofs4 [ 3.076257] CPU: 0 PID: 1 Comm: systemd Not tainted 5.19-rc5+ #1052 [ 3.084034] Hardware name: Loongson Loongson-3A5000-7A1000-1w-V0.1-CRB/Loongson-LS3A5000-7A1000-1w-EVB-V1.21, BIOS Loongson-UDK2018-V2.0.04082-beta7 04/27 [ 3.099465] Stack : 9000000100157b08 9000000000f18530 9000000000cf846c 9000000100154000 [ 3.109127] 9000000100157a50 0000000000000000 9000000100157a58 9000000000ef7430 [ 3.118774] 90000001001578e8 0000000000000040 0000000000000020 ffffffffffffffff [ 3.128412] 0000000000aaaaaa 1ab25f00eec96a37 900000010021de80 900000000101c890 [ 3.138056] 0000000000000000 0000000000000000 0000000000000000 0000000000aaaaaa [ 3.147711] ffff8000339dc220 0000000000000001 0000000006ab4000 0000000000000000 [ 3.157364] 900000000101c998 0000000000000004 9000000000ef7430 0000000000000000 [ 3.167012] 0000000000000009 000000000000006c 0000000000000000 0000000000000000 [ 3.176641] 9000000000d3de08 9000000001639390 90000000002086d8 00007ffff0080286 [ 3.186260] 00000000000000b0 0000000000000004 0000000000000000 0000000000071c1c [ 3.195868] ... [ 3.199917] Call Trace: [ 3.203941] [<90000000002086d8>] show_stack+0x38/0x14c [ 3.210666] [<9000000000cf846c>] dump_stack_lvl+0x60/0x88 [ 3.217625] [<900000000023d268>] __warn+0xd0/0x100 [ 3.223958] [<9000000000cf3c90>] warn_slowpath_fmt+0x7c/0xcc [ 3.231150] [<9000000000210220>] show_cpuinfo+0x5e8/0x5f0 [ 3.238080] [<90000000004f578c>] seq_read_iter+0x354/0x4b4 [ 3.245098] [<90000000004c2e90>] new_sync_read+0x17c/0x1c4 [ 3.252114] [<90000000004c5174>] vfs_read+0x138/0x1d0 [ 3.258694] [<90000000004c55f8>] ksys_read+0x70/0x100 [ 3.265265] [<9000000000cfde9c>] do_syscall+0x7c/0x94 [ 3.271820] [<9000000000202fe4>] handle_syscall+0xc4/0x160 [ 3.281824] ---[ end trace 8b484262b4b8c24c ]--- Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen --- arch/loongarch/kernel/proc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/loongarch/kernel/proc.c b/arch/loongarch/kernel/proc.c index 1effc73850fe..5c67cc4fd56d 100644 --- a/arch/loongarch/kernel/proc.c +++ b/arch/loongarch/kernel/proc.c @@ -106,7 +106,7 @@ static void *c_start(struct seq_file *m, loff_t *pos) { unsigned long i = *pos; - return i < NR_CPUS ? (void *)(i + 1) : NULL; + return i < nr_cpu_ids ? (void *)(i + 1) : NULL; } static void *c_next(struct seq_file *m, void *v, loff_t *pos) -- cgit v1.2.3 From f30d1f495cc117c0264d71a4d636ee72dd8acb16 Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Sat, 6 Aug 2022 15:19:32 +0800 Subject: LoongArch: Adjust arch/loongarch/Kconfig 1, ACPI, EFI and SMP are mandatories for LoongArch, select them unconditionally to avoid various build errors for 'make randconfig'. 2, Move the MMU_GATHER_MERGE_VMAS selection to the correct place. Reported-by: kernel test robot Signed-off-by: Huacai Chen --- arch/loongarch/Kconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig index 83fe390f8449..4ea781e44425 100644 --- a/arch/loongarch/Kconfig +++ b/arch/loongarch/Kconfig @@ -2,6 +2,7 @@ config LOONGARCH bool default y + select ACPI select ACPI_GENERIC_GSI if ACPI select ACPI_SYSTEM_POWER_STATES_SUPPORT if ACPI select ARCH_BINFMT_ELF_STATE @@ -51,6 +52,7 @@ config LOONGARCH select ARCH_WANTS_NO_INSTR select BUILDTIME_TABLE_SORT select COMMON_CLK + select EFI select GENERIC_CLOCKEVENTS select GENERIC_CMOS_UPDATE select GENERIC_CPU_AUTOPROBE @@ -95,6 +97,7 @@ config LOONGARCH select HAVE_VIRT_CPU_ACCOUNTING_GEN if !SMP select IRQ_FORCED_THREADING select IRQ_LOONGARCH_CPU + select MMU_GATHER_MERGE_VMAS if MMU select MODULES_USE_ELF_RELA if MODULES select NEED_PER_CPU_EMBED_FIRST_CHUNK select NEED_PER_CPU_PAGE_FIRST_CHUNK @@ -102,13 +105,13 @@ config LOONGARCH select OF_EARLY_FLATTREE select PERF_USE_VMALLOC select RTC_LIB + select SMP select SPARSE_IRQ select SYSCTL_EXCEPTION_TRACE select SWIOTLB select TRACE_IRQFLAGS_SUPPORT select USE_PERCPU_NUMA_NODE_ID select ZONE_DMA32 - select MMU_GATHER_MERGE_VMAS if MMU config 32BIT bool -- cgit v1.2.3 From aafcac81b0e3f0d7383a78c6249e90e166ac8e6d Mon Sep 17 00:00:00 2001 From: Yang Li Date: Sat, 6 Aug 2022 15:19:33 +0800 Subject: LoongArch: Fix unsigned comparison with less than zero The return value from the call to get_timer_irq() is int, which can be a negative error code. However, the return value is being assigned to an unsigned int variable 'irq', so making 'irq' an int. Eliminate the following coccicheck warning: ./arch/loongarch/kernel/time.c:146:5-8: WARNING: Unsigned expression compared with zero: irq < 0 Reported-by: Abaci Robot Signed-off-by: Yang Li Signed-off-by: Huacai Chen --- arch/loongarch/kernel/time.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/loongarch/kernel/time.c b/arch/loongarch/kernel/time.c index 79dc5eddf504..786735dcc8d6 100644 --- a/arch/loongarch/kernel/time.c +++ b/arch/loongarch/kernel/time.c @@ -135,7 +135,7 @@ static int get_timer_irq(void) int constant_clockevent_init(void) { - unsigned int irq; + int irq; unsigned int cpu = smp_processor_id(); unsigned long min_delta = 0x600; unsigned long max_delta = (1UL << 48) - 1; -- cgit v1.2.3 From 5e8be07ca8f7f49d49c6d5d44f69caaa2fa4b660 Mon Sep 17 00:00:00 2001 From: Qing Zhang Date: Sat, 6 Aug 2022 15:19:32 +0800 Subject: LoongArch: Requires __force attributes for any casts This fix a warning when "make C=2": arch/loongarch/kernel/ptrace.c: note: in included file (through include/linux/uaccess.h, include/linux/sched/task.h, include/linux/sched/signal.h, include/linux/ptrace.h, include/linux/audit.h): ./arch/loongarch/include/asm/uaccess.h:232:32: warning: incorrect type in argument 2 (different address spaces) ./arch/loongarch/include/asm/uaccess.h:232:32: expected void const *from ./arch/loongarch/include/asm/uaccess.h:232:32: got void const [noderef] __user *from Reported-by: kernel test robot Signed-off-by: Qing Zhang Signed-off-by: Huacai Chen --- arch/loongarch/include/asm/uaccess.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/loongarch/include/asm/uaccess.h b/arch/loongarch/include/asm/uaccess.h index 2b44edc604a2..a8ae2af4025a 100644 --- a/arch/loongarch/include/asm/uaccess.h +++ b/arch/loongarch/include/asm/uaccess.h @@ -229,13 +229,13 @@ extern unsigned long __copy_user(void *to, const void *from, __kernel_size_t n); static inline unsigned long __must_check raw_copy_from_user(void *to, const void __user *from, unsigned long n) { - return __copy_user(to, from, n); + return __copy_user(to, (__force const void *)from, n); } static inline unsigned long __must_check raw_copy_to_user(void __user *to, const void *from, unsigned long n) { - return __copy_user(to, from, n); + return __copy_user((__force void *)to, from, n); } #define INLINE_COPY_FROM_USER -- cgit v1.2.3 From ab2579d79529b8ed34f26a374a352f12ce24d5df Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Thu, 11 Aug 2022 20:52:12 +0800 Subject: LoongArch: Jump to the link address before enable PG The kernel entry points of both boot CPU (i.e., kernel_entry) and non- boot CPUs (i.e., smpboot_entry) may be physical address from BootLoader (in DA mode or identity-mapping PG mode). So we should jump to the link address before PG enabled (because DA is disabled at the same time) and just after DMW configured. Specifically: With some older firmwares, non-boot CPUs started with PG enabled, but this need firmware cooperation in the form of a temporary page table, which is deemed unnecessary. OTOH, latest firmware versions configure the non-boot CPUs to start in DA mode, so kernel-side changes are needed. Reviewed-by: WANG Xuerui Signed-off-by: Huacai Chen --- arch/loongarch/kernel/head.S | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/loongarch/kernel/head.S b/arch/loongarch/kernel/head.S index 7062cdf0e33e..c60eb66793e3 100644 --- a/arch/loongarch/kernel/head.S +++ b/arch/loongarch/kernel/head.S @@ -21,6 +21,12 @@ SYM_CODE_START(kernel_entry) # kernel entry point csrwr t0, LOONGARCH_CSR_DMWIN0 li.d t0, CSR_DMW1_INIT # CA, PLV0, 0x9000 xxxx xxxx xxxx csrwr t0, LOONGARCH_CSR_DMWIN1 + + /* We might not get launched at the address the kernel is linked to, + so we jump there. */ + la.abs t0, 0f + jr t0 +0: /* Enable PG */ li.w t0, 0xb0 # PLV=0, IE=0, PG=1 csrwr t0, LOONGARCH_CSR_CRMD @@ -29,11 +35,6 @@ SYM_CODE_START(kernel_entry) # kernel entry point li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0 csrwr t0, LOONGARCH_CSR_EUEN - /* We might not get launched at the address the kernel is linked to, - so we jump there. */ - la.abs t0, 0f - jr t0 -0: la t0, __bss_start # clear .bss st.d zero, t0, 0 la t1, __bss_stop - LONGSIZE @@ -74,6 +75,11 @@ SYM_CODE_START(smpboot_entry) csrwr t0, LOONGARCH_CSR_DMWIN0 li.d t0, CSR_DMW1_INIT # CA, PLV0 csrwr t0, LOONGARCH_CSR_DMWIN1 + + la.abs t0, 0f + jr t0 +0: + /* Enable PG */ li.w t0, 0xb0 # PLV=0, IE=0, PG=1 csrwr t0, LOONGARCH_CSR_CRMD li.w t0, 0x04 # PLV=0, PIE=1, PWE=0 @@ -85,9 +91,6 @@ SYM_CODE_START(smpboot_entry) ld.d sp, t0, CPU_BOOT_STACK ld.d tp, t0, CPU_BOOT_TINFO - la.abs t0, 0f - jr t0 -0: bl start_secondary SYM_CODE_END(smpboot_entry) -- cgit v1.2.3 From e9e7ff16d7f098f6fa9394e9d2b191c01ba0d5f6 Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Tue, 19 Jul 2022 10:53:13 +0800 Subject: LoongArch: Parse MADT to get multi-processor information Parse MADT to get multi-processor information, in order to fix the boot problem and cpu-hotplug problem for SMP platform. Signed-off-by: Huacai Chen --- arch/loongarch/include/asm/bootinfo.h | 2 +- arch/loongarch/include/asm/irq.h | 2 -- arch/loongarch/kernel/acpi.c | 38 +++++++++++++++++++++++++++++++++++ arch/loongarch/kernel/smp.c | 5 +---- 4 files changed, 40 insertions(+), 7 deletions(-) diff --git a/arch/loongarch/include/asm/bootinfo.h b/arch/loongarch/include/asm/bootinfo.h index 9b8d49d9e61b..e02ac4af7f6e 100644 --- a/arch/loongarch/include/asm/bootinfo.h +++ b/arch/loongarch/include/asm/bootinfo.h @@ -28,10 +28,10 @@ struct loongson_board_info { struct loongson_system_configuration { int nr_cpus; int nr_nodes; - int nr_io_pics; int boot_cpu_id; int cores_per_node; int cores_per_package; + unsigned long cores_io_master; const char *cpuname; }; diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h index 149b2123e7f4..f6c2455b4584 100644 --- a/arch/loongarch/include/asm/irq.h +++ b/arch/loongarch/include/asm/irq.h @@ -82,8 +82,6 @@ extern struct acpi_vector_group msi_group[MAX_IO_PICS]; #define GSI_MAX_PCH_IRQ (LOONGSON_PCH_IRQ_BASE + 256 - 1) extern int find_pch_pic(u32 gsi); -extern int eiointc_get_node(int id); - struct acpi_madt_lio_pic; struct acpi_madt_eio_pic; struct acpi_madt_ht_pic; diff --git a/arch/loongarch/kernel/acpi.c b/arch/loongarch/kernel/acpi.c index 03aa14581d0a..f1c928648a4a 100644 --- a/arch/loongarch/kernel/acpi.c +++ b/arch/loongarch/kernel/acpi.c @@ -104,6 +104,39 @@ static int set_processor_mask(u32 id, u32 flags) } #endif +static int __init +acpi_parse_processor(union acpi_subtable_headers *header, const unsigned long end) +{ + struct acpi_madt_core_pic *processor = NULL; + + processor = (struct acpi_madt_core_pic *)header; + if (BAD_MADT_ENTRY(processor, end)) + return -EINVAL; + + acpi_table_print_madt_entry(&header->common); +#ifdef CONFIG_SMP + set_processor_mask(processor->core_id, processor->flags); +#endif + + return 0; +} + +static int __init +acpi_parse_eio_master(union acpi_subtable_headers *header, const unsigned long end) +{ + static int core = 0; + struct acpi_madt_eio_pic *eiointc = NULL; + + eiointc = (struct acpi_madt_eio_pic *)header; + if (BAD_MADT_ENTRY(eiointc, end)) + return -EINVAL; + + core = eiointc->node * CORES_PER_EIO_NODE; + set_bit(core, &(loongson_sysconf.cores_io_master)); + + return 0; +} + static void __init acpi_process_madt(void) { #ifdef CONFIG_SMP @@ -114,6 +147,11 @@ static void __init acpi_process_madt(void) __cpu_logical_map[i] = -1; } #endif + acpi_table_parse_madt(ACPI_MADT_TYPE_CORE_PIC, + acpi_parse_processor, MAX_CORE_PIC); + + acpi_table_parse_madt(ACPI_MADT_TYPE_EIO_PIC, + acpi_parse_eio_master, MAX_IO_PICS); loongson_sysconf.nr_cpus = num_processors; } diff --git a/arch/loongarch/kernel/smp.c b/arch/loongarch/kernel/smp.c index 09743103d9b3..b5fab308dcf2 100644 --- a/arch/loongarch/kernel/smp.c +++ b/arch/loongarch/kernel/smp.c @@ -242,10 +242,7 @@ void loongson3_smp_finish(void) static bool io_master(int cpu) { - if (cpu == 0) - return true; - - return false; + return test_bit(cpu, &loongson_sysconf.cores_io_master); } int loongson3_cpu_disable(void) -- cgit v1.2.3 From 57fc7323a8e7c2e7c1d5795ab63cb3ffea3cfdfb Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Sat, 6 Aug 2022 15:19:33 +0800 Subject: LoongArch: Add PCI controller support Loongson64 based systems are PC-like systems which use PCI/PCIe as its I/O bus, This patch adds the PCI host controller support for LoongArch. Reviewed-by: WANG Xuerui Signed-off-by: Jianmin Lv Signed-off-by: Huacai Chen --- arch/loongarch/Kconfig | 7 ++ arch/loongarch/Makefile | 2 + arch/loongarch/include/asm/dma.h | 11 +++ arch/loongarch/include/asm/irq.h | 8 -- arch/loongarch/include/asm/page.h | 2 - arch/loongarch/include/asm/pci.h | 25 ++++++ arch/loongarch/pci/acpi.c | 175 ++++++++++++++++++++++++++++++++++++++ arch/loongarch/pci/pci.c | 101 ++++++++++++++++++++++ 8 files changed, 321 insertions(+), 10 deletions(-) create mode 100644 arch/loongarch/include/asm/dma.h create mode 100644 arch/loongarch/include/asm/pci.h create mode 100644 arch/loongarch/pci/acpi.c create mode 100644 arch/loongarch/pci/pci.c diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig index 4ea781e44425..5b4f7bdf69fa 100644 --- a/arch/loongarch/Kconfig +++ b/arch/loongarch/Kconfig @@ -4,6 +4,7 @@ config LOONGARCH default y select ACPI select ACPI_GENERIC_GSI if ACPI + select ACPI_MCFG if ACPI select ACPI_SYSTEM_POWER_STATES_SUPPORT if ACPI select ARCH_BINFMT_ELF_STATE select ARCH_ENABLE_MEMORY_HOTPLUG @@ -88,6 +89,7 @@ config LOONGARCH select HAVE_IRQ_TIME_ACCOUNTING select HAVE_MOD_ARCH_SPECIFIC select HAVE_NMI + select HAVE_PCI select HAVE_PERF_EVENTS select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_RSEQ @@ -103,6 +105,11 @@ config LOONGARCH select NEED_PER_CPU_PAGE_FIRST_CHUNK select OF select OF_EARLY_FLATTREE + select PCI + select PCI_DOMAINS_GENERIC + select PCI_ECAM if ACPI + select PCI_LOONGSON + select PCI_MSI_ARCH_FALLBACKS select PERF_USE_VMALLOC select RTC_LIB select SMP diff --git a/arch/loongarch/Makefile b/arch/loongarch/Makefile index fbe4277e6404..ec3de6191276 100644 --- a/arch/loongarch/Makefile +++ b/arch/loongarch/Makefile @@ -47,6 +47,8 @@ cflags-y += $(call cc-option, -mno-check-zero-division) load-y = 0x9000000000200000 bootvars-y = VMLINUX_LOAD_ADDRESS=$(load-y) +drivers-$(CONFIG_PCI) += arch/loongarch/pci/ + KBUILD_AFLAGS += $(cflags-y) KBUILD_CFLAGS += $(cflags-y) KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS=$(load-y) diff --git a/arch/loongarch/include/asm/dma.h b/arch/loongarch/include/asm/dma.h new file mode 100644 index 000000000000..1a8866319fe2 --- /dev/null +++ b/arch/loongarch/include/asm/dma.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2022 Loongson Technology Corporation Limited + */ +#ifndef __ASM_DMA_H +#define __ASM_DMA_H + +#define MAX_DMA_ADDRESS PAGE_OFFSET +#define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT)) + +#endif diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h index f6c2455b4584..4b130199ceae 100644 --- a/arch/loongarch/include/asm/irq.h +++ b/arch/loongarch/include/asm/irq.h @@ -98,16 +98,8 @@ struct irq_domain *htvec_acpi_init(struct irq_domain *parent, struct acpi_madt_ht_pic *acpi_htvec); int pch_lpc_acpi_init(struct irq_domain *parent, struct acpi_madt_lpc_pic *acpi_pchlpc); -#if IS_ENABLED(CONFIG_LOONGSON_PCH_MSI) int pch_msi_acpi_init(struct irq_domain *parent, struct acpi_madt_msi_pic *acpi_pchmsi); -#else -static inline int pch_msi_acpi_init(struct irq_domain *parent, - struct acpi_madt_msi_pic *acpi_pchmsi) -{ - return 0; -} -#endif int pch_pic_acpi_init(struct irq_domain *parent, struct acpi_madt_bio_pic *acpi_pchpic); int find_pch_pic(u32 gsi); diff --git a/arch/loongarch/include/asm/page.h b/arch/loongarch/include/asm/page.h index dc47fc724fa1..a37324ac460b 100644 --- a/arch/loongarch/include/asm/page.h +++ b/arch/loongarch/include/asm/page.h @@ -33,8 +33,6 @@ #include #include -#define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT)) - /* * It's normally defined only for FLATMEM config but it's * used in our early mem init code for all memory models. diff --git a/arch/loongarch/include/asm/pci.h b/arch/loongarch/include/asm/pci.h new file mode 100644 index 000000000000..846909d7e831 --- /dev/null +++ b/arch/loongarch/include/asm/pci.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2022 Loongson Technology Corporation Limited + */ +#ifndef _ASM_PCI_H +#define _ASM_PCI_H + +#include +#include +#include +#include + +#define PCIBIOS_MIN_IO 0x4000 +#define PCIBIOS_MIN_MEM 0x20000000 +#define PCIBIOS_MIN_CARDBUS_IO 0x4000 + +#define HAVE_PCI_MMAP +#define pcibios_assign_all_busses() 0 + +extern phys_addr_t mcfg_addr_init(int node); + +/* generic pci stuff */ +#include + +#endif /* _ASM_PCI_H */ diff --git a/arch/loongarch/pci/acpi.c b/arch/loongarch/pci/acpi.c new file mode 100644 index 000000000000..bf921487333c --- /dev/null +++ b/arch/loongarch/pci/acpi.c @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020-2022 Loongson Technology Corporation Limited + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +struct pci_root_info { + struct acpi_pci_root_info common; + struct pci_config_window *cfg; +}; + +void pcibios_add_bus(struct pci_bus *bus) +{ + acpi_pci_add_bus(bus); +} + +int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) +{ + struct pci_config_window *cfg = bridge->bus->sysdata; + struct acpi_device *adev = to_acpi_device(cfg->parent); + struct device *bus_dev = &bridge->bus->dev; + + ACPI_COMPANION_SET(&bridge->dev, adev); + set_dev_node(bus_dev, pa_to_nid(cfg->res.start)); + + return 0; +} + +int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) +{ + struct pci_config_window *cfg = bus->sysdata; + struct acpi_device *adev = to_acpi_device(cfg->parent); + struct acpi_pci_root *root = acpi_driver_data(adev); + + return root->segment; +} + +static void acpi_release_root_info(struct acpi_pci_root_info *ci) +{ + struct pci_root_info *info; + + info = container_of(ci, struct pci_root_info, common); + pci_ecam_free(info->cfg); + kfree(ci->ops); + kfree(info); +} + +static int acpi_prepare_root_resources(struct acpi_pci_root_info *ci) +{ + int status; + struct resource_entry *entry, *tmp; + struct acpi_device *device = ci->bridge; + + status = acpi_pci_probe_root_resources(ci); + if (status > 0) { + resource_list_for_each_entry_safe(entry, tmp, &ci->resources) { + if (entry->res->flags & IORESOURCE_MEM) { + entry->offset = ci->root->mcfg_addr & GENMASK_ULL(63, 40); + entry->res->start |= entry->offset; + entry->res->end |= entry->offset; + } + } + return status; + } + + resource_list_for_each_entry_safe(entry, tmp, &ci->resources) { + dev_dbg(&device->dev, + "host bridge window %pR (ignored)\n", entry->res); + resource_list_destroy_entry(entry); + } + + return 0; +} + +/* + * Lookup the bus range for the domain in MCFG, and set up config space + * mapping. + */ +static struct pci_config_window * +pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root) +{ + int ret, bus_shift; + u16 seg = root->segment; + struct device *dev = &root->device->dev; + struct resource cfgres; + struct resource *bus_res = &root->secondary; + struct pci_config_window *cfg; + const struct pci_ecam_ops *ecam_ops; + + ret = pci_mcfg_lookup(root, &cfgres, &ecam_ops); + if (ret < 0) { + dev_err(dev, "%04x:%pR ECAM region not found, use default value\n", seg, bus_res); + ecam_ops = &loongson_pci_ecam_ops; + root->mcfg_addr = mcfg_addr_init(0); + } + + bus_shift = ecam_ops->bus_shift ? : 20; + + cfgres.start = root->mcfg_addr + (bus_res->start << bus_shift); + cfgres.end = cfgres.start + (resource_size(bus_res) << bus_shift) - 1; + cfgres.flags = IORESOURCE_MEM; + + cfg = pci_ecam_create(dev, &cfgres, bus_res, ecam_ops); + if (IS_ERR(cfg)) { + dev_err(dev, "%04x:%pR error %ld mapping ECAM\n", seg, bus_res, PTR_ERR(cfg)); + return NULL; + } + + return cfg; +} + +struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) +{ + struct pci_bus *bus; + struct pci_root_info *info; + struct acpi_pci_root_ops *root_ops; + int domain = root->segment; + int busnum = root->secondary.start; + + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) { + pr_warn("pci_bus %04x:%02x: ignored (out of memory)\n", domain, busnum); + return NULL; + } + + root_ops = kzalloc(sizeof(*root_ops), GFP_KERNEL); + if (!root_ops) { + kfree(info); + return NULL; + } + + info->cfg = pci_acpi_setup_ecam_mapping(root); + if (!info->cfg) { + kfree(info); + kfree(root_ops); + return NULL; + } + + root_ops->release_info = acpi_release_root_info; + root_ops->prepare_resources = acpi_prepare_root_resources; + root_ops->pci_ops = (struct pci_ops *)&info->cfg->ops->pci_ops; + + bus = pci_find_bus(domain, busnum); + if (bus) { + memcpy(bus->sysdata, info->cfg, sizeof(struct pci_config_window)); + kfree(info); + } else { + struct pci_bus *child; + + bus = acpi_pci_root_create(root, root_ops, + &info->common, info->cfg); + if (!bus) { + kfree(info); + kfree(root_ops); + return NULL; + } + + pci_bus_size_bridges(bus); + pci_bus_assign_resources(bus); + list_for_each_entry(child, &bus->children, node) + pcie_bus_configure_settings(child); + } + + return bus; +} diff --git a/arch/loongarch/pci/pci.c b/arch/loongarch/pci/pci.c new file mode 100644 index 000000000000..e9b7c34d9b6d --- /dev/null +++ b/arch/loongarch/pci/pci.c @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2020-2022 Loongson Technology Corporation Limited + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCI_DEVICE_ID_LOONGSON_HOST 0x7a00 +#define PCI_DEVICE_ID_LOONGSON_DC1 0x7a06 +#define PCI_DEVICE_ID_LOONGSON_DC2 0x7a36 + +int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, + int reg, int len, u32 *val) +{ + struct pci_bus *bus_tmp = pci_find_bus(domain, bus); + + if (bus_tmp) + return bus_tmp->ops->read(bus_tmp, devfn, reg, len, val); + return -EINVAL; +} + +int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, + int reg, int len, u32 val) +{ + struct pci_bus *bus_tmp = pci_find_bus(domain, bus); + + if (bus_tmp) + return bus_tmp->ops->write(bus_tmp, devfn, reg, len, val); + return -EINVAL; +} + +phys_addr_t mcfg_addr_init(int node) +{ + return (((u64)node << 44) | MCFG_EXT_PCICFG_BASE); +} + +static int __init pcibios_init(void) +{ + unsigned int lsize; + + /* + * Set PCI cacheline size to that of the highest level in the + * cache hierarchy. + */ + lsize = cpu_dcache_line_size(); + lsize = cpu_vcache_line_size() ? : lsize; + lsize = cpu_scache_line_size() ? : lsize; + + BUG_ON(!lsize); + + pci_dfl_cache_line_size = lsize >> 2; + + pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize); + + return 0; +} + +subsys_initcall(pcibios_init); + +int pcibios_device_add(struct pci_dev *dev) +{ + int id; + struct irq_domain *dom; + + id = pci_domain_nr(dev->bus); + dom = irq_find_matching_fwnode(get_pch_msi_handle(id), DOMAIN_BUS_PCI_MSI); + dev_set_msi_domain(&dev->dev, dom); + + return 0; +} + +int pcibios_alloc_irq(struct pci_dev *dev) +{ + if (acpi_disabled) + return 0; + if (pci_dev_msi_enabled(dev)) + return 0; + return acpi_pci_irq_enable(dev); +} + +static void pci_fixup_vgadev(struct pci_dev *pdev) +{ + struct pci_dev *devp = NULL; + + while ((devp = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, devp))) { + if (devp->vendor != PCI_VENDOR_ID_LOONGSON) { + vga_set_default_device(devp); + dev_info(&pdev->dev, + "Overriding boot device as %X:%X\n", + devp->vendor, devp->device); + } + } +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, PCI_DEVICE_ID_LOONGSON_DC1, pci_fixup_vgadev); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, PCI_DEVICE_ID_LOONGSON_DC2, pci_fixup_vgadev); -- cgit v1.2.3 From dce6098b22d58e5b646b1c67174c53f5a6a05605 Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Sat, 6 Aug 2022 15:19:33 +0800 Subject: LoongArch: Add vDSO syscall __vdso_getcpu() We test 20 million times of getcpu(), the real syscall version take 25 seconds, while the vsyscall version take only 2.4 seconds. Signed-off-by: Rui Wang Signed-off-by: Huacai Chen --- arch/loongarch/include/asm/vdso.h | 1 + arch/loongarch/include/asm/vdso/vdso.h | 15 +++++++++++- arch/loongarch/kernel/vdso.c | 25 ++++++++++++-------- arch/loongarch/vdso/Makefile | 2 +- arch/loongarch/vdso/vdso.lds.S | 1 + arch/loongarch/vdso/vgetcpu.c | 43 ++++++++++++++++++++++++++++++++++ 6 files changed, 75 insertions(+), 12 deletions(-) create mode 100644 arch/loongarch/vdso/vgetcpu.c diff --git a/arch/loongarch/include/asm/vdso.h b/arch/loongarch/include/asm/vdso.h index 8f8a0f9a4953..d3ba35eb23e7 100644 --- a/arch/loongarch/include/asm/vdso.h +++ b/arch/loongarch/include/asm/vdso.h @@ -7,6 +7,7 @@ #ifndef __ASM_VDSO_H #define __ASM_VDSO_H +#include #include #include diff --git a/arch/loongarch/include/asm/vdso/vdso.h b/arch/loongarch/include/asm/vdso/vdso.h index 5a01643a65b3..3b55d32a0619 100644 --- a/arch/loongarch/include/asm/vdso/vdso.h +++ b/arch/loongarch/include/asm/vdso/vdso.h @@ -8,6 +8,18 @@ #include #include +#include + +struct vdso_pcpu_data { + u32 node; +} ____cacheline_aligned_in_smp; + +struct loongarch_vdso_data { + struct vdso_pcpu_data pdata[NR_CPUS]; + struct vdso_data data[CS_BASES]; /* Arch-independent data */ +}; + +#define VDSO_DATA_SIZE PAGE_ALIGN(sizeof(struct loongarch_vdso_data)) static inline unsigned long get_vdso_base(void) { @@ -24,7 +36,8 @@ static inline unsigned long get_vdso_base(void) static inline const struct vdso_data *get_vdso_data(void) { - return (const struct vdso_data *)(get_vdso_base() - PAGE_SIZE); + return (const struct vdso_data *)(get_vdso_base() + - VDSO_DATA_SIZE + SMP_CACHE_BYTES * NR_CPUS); } #endif /* __ASSEMBLY__ */ diff --git a/arch/loongarch/kernel/vdso.c b/arch/loongarch/kernel/vdso.c index e20c8ca87473..f32c38abd791 100644 --- a/arch/loongarch/kernel/vdso.c +++ b/arch/loongarch/kernel/vdso.c @@ -25,12 +25,14 @@ extern char vdso_start[], vdso_end[]; /* Kernel-provided data used by the VDSO. */ -static union loongarch_vdso_data { - u8 page[PAGE_SIZE]; - struct vdso_data data[CS_BASES]; +static union { + u8 page[VDSO_DATA_SIZE]; + struct loongarch_vdso_data vdata; } loongarch_vdso_data __page_aligned_data; -struct vdso_data *vdso_data = loongarch_vdso_data.data; + static struct page *vdso_pages[] = { NULL }; +struct vdso_data *vdso_data = loongarch_vdso_data.vdata.data; +struct vdso_pcpu_data *vdso_pdata = loongarch_vdso_data.vdata.pdata; static int vdso_mremap(const struct vm_special_mapping *sm, struct vm_area_struct *new_vma) { @@ -55,11 +57,14 @@ struct loongarch_vdso_info vdso_info = { static int __init init_vdso(void) { - unsigned long i, pfn; + unsigned long i, cpu, pfn; BUG_ON(!PAGE_ALIGNED(vdso_info.vdso)); BUG_ON(!PAGE_ALIGNED(vdso_info.size)); + for_each_possible_cpu(cpu) + vdso_pdata[cpu].node = cpu_to_node(cpu); + pfn = __phys_to_pfn(__pa_symbol(vdso_info.vdso)); for (i = 0; i < vdso_info.size / PAGE_SIZE; i++) vdso_info.code_mapping.pages[i] = pfn_to_page(pfn + i); @@ -93,9 +98,9 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) /* * Determine total area size. This includes the VDSO data itself - * and the data page. + * and the data pages. */ - vvar_size = PAGE_SIZE; + vvar_size = VDSO_DATA_SIZE; size = vvar_size + info->size; data_addr = get_unmapped_area(NULL, vdso_base(), size, 0, 0); @@ -103,7 +108,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) ret = data_addr; goto out; } - vdso_addr = data_addr + PAGE_SIZE; + vdso_addr = data_addr + VDSO_DATA_SIZE; vma = _install_special_mapping(mm, data_addr, vvar_size, VM_READ | VM_MAYREAD, @@ -115,8 +120,8 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) /* Map VDSO data page. */ ret = remap_pfn_range(vma, data_addr, - virt_to_phys(vdso_data) >> PAGE_SHIFT, - PAGE_SIZE, PAGE_READONLY); + virt_to_phys(&loongarch_vdso_data) >> PAGE_SHIFT, + vvar_size, PAGE_READONLY); if (ret) goto out; diff --git a/arch/loongarch/vdso/Makefile b/arch/loongarch/vdso/Makefile index 92e404032257..d89e2ac75f7b 100644 --- a/arch/loongarch/vdso/Makefile +++ b/arch/loongarch/vdso/Makefile @@ -6,7 +6,7 @@ ARCH_REL_TYPE_ABS := R_LARCH_32|R_LARCH_64|R_LARCH_MARK_LA|R_LARCH_JUMP_SLOT include $(srctree)/lib/vdso/Makefile -obj-vdso-y := elf.o vgettimeofday.o sigreturn.o +obj-vdso-y := elf.o vgetcpu.o vgettimeofday.o sigreturn.o # Common compiler flags between ABIs. ccflags-vdso := \ diff --git a/arch/loongarch/vdso/vdso.lds.S b/arch/loongarch/vdso/vdso.lds.S index 955f02de4a2d..56ad855896de 100644 --- a/arch/loongarch/vdso/vdso.lds.S +++ b/arch/loongarch/vdso/vdso.lds.S @@ -58,6 +58,7 @@ VERSION { LINUX_5.10 { global: + __vdso_getcpu; __vdso_clock_getres; __vdso_clock_gettime; __vdso_gettimeofday; diff --git a/arch/loongarch/vdso/vgetcpu.c b/arch/loongarch/vdso/vgetcpu.c new file mode 100644 index 000000000000..43a0078e4418 --- /dev/null +++ b/arch/loongarch/vdso/vgetcpu.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Fast user context implementation of getcpu() + */ + +#include +#include + +static __always_inline int read_cpu_id(void) +{ + int cpu_id; + + __asm__ __volatile__( + " rdtime.d $zero, %0\n" + : "=r" (cpu_id) + : + : "memory"); + + return cpu_id; +} + +static __always_inline const struct vdso_pcpu_data *get_pcpu_data(void) +{ + return (struct vdso_pcpu_data *)(get_vdso_base() - VDSO_DATA_SIZE); +} + +int __vdso_getcpu(unsigned int *cpu, unsigned int *node, struct getcpu_cache *unused) +{ + int cpu_id; + const struct vdso_pcpu_data *data; + + cpu_id = read_cpu_id(); + + if (cpu) + *cpu = cpu_id; + + if (node) { + data = get_pcpu_data(); + *node = data[cpu_id].node; + } + + return 0; +} -- cgit v1.2.3 From 49232773d8233ed70c4998851bc84e465fc1c788 Mon Sep 17 00:00:00 2001 From: Qing Zhang Date: Sat, 6 Aug 2022 16:10:02 +0800 Subject: LoongArch: Add guess unwinder support Name "guess unwinder" comes from x86, it scans the stack and reports every kernel text address it finds. Unwinders can be used by dump_stack() and other stacktrace functions. Three stages when we do unwind, 1) unwind_start(), the prapare of unwinding, fill unwind_state. 2) unwind_done(), judge whether the unwind process is finished or not. 3) unwind_next_frame(), unwind the next frame. Add get_stack_info() to get stack info. At present we have irq stack and task stack. The next_sp is the key info between two types of stacks. Dividing unwinder helps to add new unwinders in the future. Signed-off-by: Qing Zhang Signed-off-by: Huacai Chen --- arch/loongarch/Kconfig.debug | 9 +++++ arch/loongarch/include/asm/stacktrace.h | 15 ++++++++ arch/loongarch/include/asm/unwind.h | 36 ++++++++++++++++++ arch/loongarch/kernel/Makefile | 2 + arch/loongarch/kernel/process.c | 61 ++++++++++++++++++++++++++++++ arch/loongarch/kernel/traps.c | 21 +++++------ arch/loongarch/kernel/unwind_guess.c | 67 +++++++++++++++++++++++++++++++++ 7 files changed, 200 insertions(+), 11 deletions(-) create mode 100644 arch/loongarch/include/asm/unwind.h create mode 100644 arch/loongarch/kernel/unwind_guess.c diff --git a/arch/loongarch/Kconfig.debug b/arch/loongarch/Kconfig.debug index e69de29bb2d1..68634d4fa27b 100644 --- a/arch/loongarch/Kconfig.debug +++ b/arch/loongarch/Kconfig.debug @@ -0,0 +1,9 @@ +config UNWINDER_GUESS + bool "Guess unwinder" + help + This option enables the "guess" unwinder for unwinding kernel stack + traces. It scans the stack and reports every kernel text address it + finds. Some of the addresses it reports may be incorrect. + + While this option often produces false positives, it can still be + useful in many cases. diff --git a/arch/loongarch/include/asm/stacktrace.h b/arch/loongarch/include/asm/stacktrace.h index 6b5c2a7aa706..5820a0cabe3a 100644 --- a/arch/loongarch/include/asm/stacktrace.h +++ b/arch/loongarch/include/asm/stacktrace.h @@ -10,6 +10,21 @@ #include #include +enum stack_type { + STACK_TYPE_UNKNOWN, + STACK_TYPE_IRQ, + STACK_TYPE_TASK, +}; + +struct stack_info { + enum stack_type type; + unsigned long begin, end, next_sp; +}; + +bool in_irq_stack(unsigned long stack, struct stack_info *info); +bool in_task_stack(unsigned long stack, struct task_struct *task, struct stack_info *info); +int get_stack_info(unsigned long stack, struct task_struct *task, struct stack_info *info); + #define STR_LONG_L __stringify(LONG_L) #define STR_LONG_S __stringify(LONG_S) #define STR_LONGSIZE __stringify(LONGSIZE) diff --git a/arch/loongarch/include/asm/unwind.h b/arch/loongarch/include/asm/unwind.h new file mode 100644 index 000000000000..206fcbe24c0a --- /dev/null +++ b/arch/loongarch/include/asm/unwind.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Most of this ideas comes from x86. + * + * Copyright (C) 2022 Loongson Technology Corporation Limited + */ +#ifndef _ASM_UNWIND_H +#define _ASM_UNWIND_H + +#include + +#include + +struct unwind_state { + struct stack_info stack_info; + struct task_struct *task; + bool first, error; + unsigned long sp, pc; +}; + +void unwind_start(struct unwind_state *state, + struct task_struct *task, struct pt_regs *regs); +bool unwind_next_frame(struct unwind_state *state); +unsigned long unwind_get_return_address(struct unwind_state *state); + +static inline bool unwind_done(struct unwind_state *state) +{ + return state->stack_info.type == STACK_TYPE_UNKNOWN; +} + +static inline bool unwind_error(struct unwind_state *state) +{ + return state->error; +} + +#endif /* _ASM_UNWIND_H */ diff --git a/arch/loongarch/kernel/Makefile b/arch/loongarch/kernel/Makefile index 940de9173542..c5fa4adb23b6 100644 --- a/arch/loongarch/kernel/Makefile +++ b/arch/loongarch/kernel/Makefile @@ -22,4 +22,6 @@ obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_NUMA) += numa.o +obj-$(CONFIG_UNWINDER_GUESS) += unwind_guess.o + CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS) diff --git a/arch/loongarch/kernel/process.c b/arch/loongarch/kernel/process.c index bfa0dfe8b7d7..839f0e963152 100644 --- a/arch/loongarch/kernel/process.c +++ b/arch/loongarch/kernel/process.c @@ -44,6 +44,7 @@ #include #include #include +#include #include /* @@ -183,6 +184,66 @@ unsigned long __get_wchan(struct task_struct *task) return 0; } +bool in_irq_stack(unsigned long stack, struct stack_info *info) +{ + unsigned long nextsp; + unsigned long begin = (unsigned long)this_cpu_read(irq_stack); + unsigned long end = begin + IRQ_STACK_START; + + if (stack < begin || stack >= end) + return false; + + nextsp = *(unsigned long *)end; + if (nextsp & (SZREG - 1)) + return false; + + info->begin = begin; + info->end = end; + info->next_sp = nextsp; + info->type = STACK_TYPE_IRQ; + + return true; +} + +bool in_task_stack(unsigned long stack, struct task_struct *task, + struct stack_info *info) +{ + unsigned long begin = (unsigned long)task_stack_page(task); + unsigned long end = begin + THREAD_SIZE - 32; + + if (stack < begin || stack >= end) + return false; + + info->begin = begin; + info->end = end; + info->next_sp = 0; + info->type = STACK_TYPE_TASK; + + return true; +} + +int get_stack_info(unsigned long stack, struct task_struct *task, + struct stack_info *info) +{ + task = task ? : current; + + if (!stack || stack & (SZREG - 1)) + goto unknown; + + if (in_task_stack(stack, task, info)) + return 0; + + if (task != current) + goto unknown; + + if (in_irq_stack(stack, info)) + return 0; + +unknown: + info->type = STACK_TYPE_UNKNOWN; + return -EINVAL; +} + unsigned long stack_top(void) { unsigned long top = TASK_SIZE & PAGE_MASK; diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c index 1bf58c65e2bf..f65fdf90d29e 100644 --- a/arch/loongarch/kernel/traps.c +++ b/arch/loongarch/kernel/traps.c @@ -43,6 +43,7 @@ #include #include #include +#include #include "access-helper.h" @@ -64,19 +65,17 @@ static void show_backtrace(struct task_struct *task, const struct pt_regs *regs, const char *loglvl, bool user) { unsigned long addr; - unsigned long *sp = (unsigned long *)(regs->regs[3] & ~3); + struct unwind_state state; + struct pt_regs *pregs = (struct pt_regs *)regs; + + if (!task) + task = current; printk("%sCall Trace:", loglvl); -#ifdef CONFIG_KALLSYMS - printk("%s\n", loglvl); -#endif - while (!kstack_end(sp)) { - if (__get_addr(&addr, sp++, user)) { - printk("%s (Bad stack address)", loglvl); - break; - } - if (__kernel_text_address(addr)) - print_ip_sym(loglvl, addr); + for (unwind_start(&state, task, pregs); + !unwind_done(&state); unwind_next_frame(&state)) { + addr = unwind_get_return_address(&state); + print_ip_sym(loglvl, addr); } printk("%s\n", loglvl); } diff --git a/arch/loongarch/kernel/unwind_guess.c b/arch/loongarch/kernel/unwind_guess.c new file mode 100644 index 000000000000..5afa6064d73e --- /dev/null +++ b/arch/loongarch/kernel/unwind_guess.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Loongson Technology Corporation Limited + */ +#include + +#include + +unsigned long unwind_get_return_address(struct unwind_state *state) +{ + if (unwind_done(state)) + return 0; + else if (state->first) + return state->pc; + + return *(unsigned long *)(state->sp); +} +EXPORT_SYMBOL_GPL(unwind_get_return_address); + +void unwind_start(struct unwind_state *state, struct task_struct *task, + struct pt_regs *regs) +{ + memset(state, 0, sizeof(*state)); + + if (regs) { + state->sp = regs->regs[3]; + state->pc = regs->csr_era; + } + + state->task = task; + state->first = true; + + get_stack_info(state->sp, state->task, &state->stack_info); + + if (!unwind_done(state) && !__kernel_text_address(state->pc)) + unwind_next_frame(state); +} +EXPORT_SYMBOL_GPL(unwind_start); + +bool unwind_next_frame(struct unwind_state *state) +{ + struct stack_info *info = &state->stack_info; + unsigned long addr; + + if (unwind_done(state)) + return false; + + if (state->first) + state->first = false; + + do { + for (state->sp += sizeof(unsigned long); + state->sp < info->end; + state->sp += sizeof(unsigned long)) { + addr = *(unsigned long *)(state->sp); + + if (__kernel_text_address(addr)) + return true; + } + + state->sp = info->next_sp; + + } while (!get_stack_info(state->sp, state->task, info)); + + return false; +} +EXPORT_SYMBOL_GPL(unwind_next_frame); -- cgit v1.2.3 From 49aef111e2dae176a7708b532118f33f24289248 Mon Sep 17 00:00:00 2001 From: Qing Zhang Date: Sat, 6 Aug 2022 16:10:03 +0800 Subject: LoongArch: Add prologue unwinder support It unwind the stack frame based on prologue code analyze. CONFIG_KALLSYMS is needed, at least the address and length of each function. Three stages when we do unwind, 1) unwind_start(), the prapare of unwinding, fill unwind_state. 2) unwind_done(), judge whether the unwind process is finished or not. 3) unwind_next_frame(), unwind the next frame. Dividing unwinder helps to add new unwinders in the future, e.g.: unwinder_frame, unwinder_orc, .etc. Signed-off-by: Qing Zhang Signed-off-by: Huacai Chen --- arch/loongarch/Kconfig.debug | 20 ++++ arch/loongarch/include/asm/inst.h | 52 ++++++++++ arch/loongarch/include/asm/unwind.h | 8 +- arch/loongarch/kernel/Makefile | 1 + arch/loongarch/kernel/traps.c | 3 + arch/loongarch/kernel/unwind_prologue.c | 176 ++++++++++++++++++++++++++++++++ 6 files changed, 259 insertions(+), 1 deletion(-) create mode 100644 arch/loongarch/kernel/unwind_prologue.c diff --git a/arch/loongarch/Kconfig.debug b/arch/loongarch/Kconfig.debug index 68634d4fa27b..8d36aab53008 100644 --- a/arch/loongarch/Kconfig.debug +++ b/arch/loongarch/Kconfig.debug @@ -1,3 +1,11 @@ +choice + prompt "Choose kernel unwinder" + default UNWINDER_PROLOGUE if KALLSYMS + help + This determines which method will be used for unwinding kernel stack + traces for panics, oopses, bugs, warnings, perf, /proc//stack, + lockdep, and more. + config UNWINDER_GUESS bool "Guess unwinder" help @@ -7,3 +15,15 @@ config UNWINDER_GUESS While this option often produces false positives, it can still be useful in many cases. + +config UNWINDER_PROLOGUE + bool "Prologue unwinder" + depends on KALLSYMS + help + This option enables the "prologue" unwinder for unwinding kernel stack + traces. It unwind the stack frame based on prologue code analyze. Symbol + information is needed, at least the address and length of each function. + Some of the addresses it reports may be incorrect (but better than the + Guess unwinder). + +endchoice diff --git a/arch/loongarch/include/asm/inst.h b/arch/loongarch/include/asm/inst.h index 575d1bb66ffb..7b07cbb3188c 100644 --- a/arch/loongarch/include/asm/inst.h +++ b/arch/loongarch/include/asm/inst.h @@ -23,12 +23,33 @@ enum reg1i20_op { lu32id_op = 0x0b, }; +enum reg1i21_op { + beqz_op = 0x10, + bnez_op = 0x11, +}; + enum reg2i12_op { + addiw_op = 0x0a, + addid_op = 0x0b, lu52id_op = 0x0c, + ldb_op = 0xa0, + ldh_op = 0xa1, + ldw_op = 0xa2, + ldd_op = 0xa3, + stb_op = 0xa4, + sth_op = 0xa5, + stw_op = 0xa6, + std_op = 0xa7, }; enum reg2i16_op { jirl_op = 0x13, + beq_op = 0x16, + bne_op = 0x17, + blt_op = 0x18, + bge_op = 0x19, + bltu_op = 0x1a, + bgeu_op = 0x1b, }; struct reg0i26_format { @@ -110,6 +131,37 @@ enum loongarch_gpr { LOONGARCH_GPR_MAX }; +#define is_imm12_negative(val) is_imm_negative(val, 12) + +static inline bool is_imm_negative(unsigned long val, unsigned int bit) +{ + return val & (1UL << (bit - 1)); +} + +static inline bool is_branch_ins(union loongarch_instruction *ip) +{ + return ip->reg1i21_format.opcode >= beqz_op && + ip->reg1i21_format.opcode <= bgeu_op; +} + +static inline bool is_ra_save_ins(union loongarch_instruction *ip) +{ + /* st.d $ra, $sp, offset */ + return ip->reg2i12_format.opcode == std_op && + ip->reg2i12_format.rj == LOONGARCH_GPR_SP && + ip->reg2i12_format.rd == LOONGARCH_GPR_RA && + !is_imm12_negative(ip->reg2i12_format.immediate); +} + +static inline bool is_stack_alloc_ins(union loongarch_instruction *ip) +{ + /* addi.d $sp, $sp, -imm */ + return ip->reg2i12_format.opcode == addid_op && + ip->reg2i12_format.rj == LOONGARCH_GPR_SP && + ip->reg2i12_format.rd == LOONGARCH_GPR_SP && + is_imm12_negative(ip->reg2i12_format.immediate); +} + u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm); u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm); u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, unsigned long pc, unsigned long dest); diff --git a/arch/loongarch/include/asm/unwind.h b/arch/loongarch/include/asm/unwind.h index 206fcbe24c0a..6af4718bdf01 100644 --- a/arch/loongarch/include/asm/unwind.h +++ b/arch/loongarch/include/asm/unwind.h @@ -11,11 +11,17 @@ #include +enum unwinder_type { + UNWINDER_GUESS, + UNWINDER_PROLOGUE, +}; + struct unwind_state { + char type; /* UNWINDER_XXX */ struct stack_info stack_info; struct task_struct *task; bool first, error; - unsigned long sp, pc; + unsigned long sp, pc, ra; }; void unwind_start(struct unwind_state *state, diff --git a/arch/loongarch/kernel/Makefile b/arch/loongarch/kernel/Makefile index c5fa4adb23b6..918600e7b30f 100644 --- a/arch/loongarch/kernel/Makefile +++ b/arch/loongarch/kernel/Makefile @@ -23,5 +23,6 @@ obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_NUMA) += numa.o obj-$(CONFIG_UNWINDER_GUESS) += unwind_guess.o +obj-$(CONFIG_UNWINDER_PROLOGUE) += unwind_prologue.o CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS) diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c index f65fdf90d29e..aa1c95aaf595 100644 --- a/arch/loongarch/kernel/traps.c +++ b/arch/loongarch/kernel/traps.c @@ -71,6 +71,9 @@ static void show_backtrace(struct task_struct *task, const struct pt_regs *regs, if (!task) task = current; + if (user_mode(regs)) + state.type = UNWINDER_GUESS; + printk("%sCall Trace:", loglvl); for (unwind_start(&state, task, pregs); !unwind_done(&state); unwind_next_frame(&state)) { diff --git a/arch/loongarch/kernel/unwind_prologue.c b/arch/loongarch/kernel/unwind_prologue.c new file mode 100644 index 000000000000..b206d9159205 --- /dev/null +++ b/arch/loongarch/kernel/unwind_prologue.c @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Loongson Technology Corporation Limited + */ +#include + +#include +#include +#include + +unsigned long unwind_get_return_address(struct unwind_state *state) +{ + + if (unwind_done(state)) + return 0; + else if (state->type) + return state->pc; + else if (state->first) + return state->pc; + + return *(unsigned long *)(state->sp); + +} +EXPORT_SYMBOL_GPL(unwind_get_return_address); + +static bool unwind_by_guess(struct unwind_state *state) +{ + struct stack_info *info = &state->stack_info; + unsigned long addr; + + for (state->sp += sizeof(unsigned long); + state->sp < info->end; + state->sp += sizeof(unsigned long)) { + addr = *(unsigned long *)(state->sp); + if (__kernel_text_address(addr)) + return true; + } + + return false; +} + +static bool unwind_by_prologue(struct unwind_state *state) +{ + struct stack_info *info = &state->stack_info; + union loongarch_instruction *ip, *ip_end; + unsigned long frame_size = 0, frame_ra = -1; + unsigned long size, offset, pc = state->pc; + + if (state->sp >= info->end || state->sp < info->begin) + return false; + + if (!kallsyms_lookup_size_offset(pc, &size, &offset)) + return false; + + ip = (union loongarch_instruction *)(pc - offset); + ip_end = (union loongarch_instruction *)pc; + + while (ip < ip_end) { + if (is_stack_alloc_ins(ip)) { + frame_size = (1 << 12) - ip->reg2i12_format.immediate; + ip++; + break; + } + ip++; + } + + if (!frame_size) { + if (state->first) + goto first; + + return false; + } + + while (ip < ip_end) { + if (is_ra_save_ins(ip)) { + frame_ra = ip->reg2i12_format.immediate; + break; + } + if (is_branch_ins(ip)) + break; + ip++; + } + + if (frame_ra < 0) { + if (state->first) { + state->sp = state->sp + frame_size; + goto first; + } + return false; + } + + if (state->first) + state->first = false; + + state->pc = *(unsigned long *)(state->sp + frame_ra); + state->sp = state->sp + frame_size; + return !!__kernel_text_address(state->pc); + +first: + state->first = false; + if (state->pc == state->ra) + return false; + + state->pc = state->ra; + + return !!__kernel_text_address(state->ra); +} + +void unwind_start(struct unwind_state *state, struct task_struct *task, + struct pt_regs *regs) +{ + memset(state, 0, sizeof(*state)); + + if (regs && __kernel_text_address(regs->csr_era)) { + state->pc = regs->csr_era; + state->sp = regs->regs[3]; + state->ra = regs->regs[1]; + state->type = UNWINDER_PROLOGUE; + } + + state->task = task; + state->first = true; + + get_stack_info(state->sp, state->task, &state->stack_info); + + if (!unwind_done(state) && !__kernel_text_address(state->pc)) + unwind_next_frame(state); +} +EXPORT_SYMBOL_GPL(unwind_start); + +bool unwind_next_frame(struct unwind_state *state) +{ + struct stack_info *info = &state->stack_info; + struct pt_regs *regs; + unsigned long pc; + + if (unwind_done(state)) + return false; + + do { + switch (state->type) { + case UNWINDER_GUESS: + state->first = false; + if (unwind_by_guess(state)) + return true; + break; + + case UNWINDER_PROLOGUE: + if (unwind_by_prologue(state)) + return true; + + if (info->type == STACK_TYPE_IRQ && + info->end == state->sp) { + regs = (struct pt_regs *)info->next_sp; + pc = regs->csr_era; + + if (user_mode(regs) || !__kernel_text_address(pc)) + return false; + + state->pc = pc; + state->sp = regs->regs[3]; + state->ra = regs->regs[1]; + state->first = true; + get_stack_info(state->sp, state->task, info); + + return true; + } + } + + state->sp = info->next_sp; + + } while (!get_stack_info(state->sp, state->task, info)); + + return false; +} +EXPORT_SYMBOL_GPL(unwind_next_frame); -- cgit v1.2.3 From 93a4fa622eb061f75f87f0cf9609ab4e69c67d01 Mon Sep 17 00:00:00 2001 From: Qing Zhang Date: Sat, 6 Aug 2022 16:10:04 +0800 Subject: LoongArch: Add STACKTRACE support 1. Use common arch_stack_walk() infrastructure to avoid duplicated code and avoid taking care of the stack storage and filtering. 2. Add sched_ra (means sched return address) and sched_cfa (means sched call frame address) to thread_info, and store them in switch_to(). 3. Add __get_wchan() implementation. Now we can print the process stack and wait channel by cat /proc/*/stack and /proc/*/wchan. Signed-off-by: Qing Zhang Signed-off-by: Huacai Chen --- arch/loongarch/Kconfig | 5 +++++ arch/loongarch/include/asm/processor.h | 9 +++++++++ arch/loongarch/include/asm/switch_to.h | 14 ++++++++----- arch/loongarch/kernel/Makefile | 1 + arch/loongarch/kernel/asm-offsets.c | 2 ++ arch/loongarch/kernel/process.c | 29 +++++++++++++++++++++++++- arch/loongarch/kernel/stacktrace.c | 37 ++++++++++++++++++++++++++++++++++ arch/loongarch/kernel/switch.S | 2 ++ 8 files changed, 93 insertions(+), 6 deletions(-) create mode 100644 arch/loongarch/kernel/stacktrace.c diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig index 5b4f7bdf69fa..947cb633744b 100644 --- a/arch/loongarch/Kconfig +++ b/arch/loongarch/Kconfig @@ -42,6 +42,7 @@ config LOONGARCH select ARCH_MIGHT_HAVE_PC_PARPORT select ARCH_MIGHT_HAVE_PC_SERIO select ARCH_SPARSEMEM_ENABLE + select ARCH_STACKWALK select ARCH_SUPPORTS_ACPI select ARCH_SUPPORTS_ATOMIC_RMW select ARCH_SUPPORTS_HUGETLBFS @@ -151,6 +152,10 @@ config LOCKDEP_SUPPORT bool default y +config STACKTRACE_SUPPORT + bool + default y + # MACH_LOONGSON32 and MACH_LOONGSON64 are delibrately carried over from the # MIPS Loongson code, to preserve Loongson-specific code paths in drivers that # are shared between architectures, and specifically expecting the symbols. diff --git a/arch/loongarch/include/asm/processor.h b/arch/loongarch/include/asm/processor.h index 57ec45aa078e..1c4b4308378d 100644 --- a/arch/loongarch/include/asm/processor.h +++ b/arch/loongarch/include/asm/processor.h @@ -101,6 +101,10 @@ struct thread_struct { unsigned long reg23, reg24, reg25, reg26; /* s0-s3 */ unsigned long reg27, reg28, reg29, reg30, reg31; /* s4-s8 */ + /* __schedule() return address / call frame address */ + unsigned long sched_ra; + unsigned long sched_cfa; + /* CSR registers */ unsigned long csr_prmd; unsigned long csr_crmd; @@ -129,6 +133,9 @@ struct thread_struct { struct loongarch_fpu fpu FPU_ALIGN; }; +#define thread_saved_ra(tsk) (tsk->thread.sched_ra) +#define thread_saved_fp(tsk) (tsk->thread.sched_cfa) + #define INIT_THREAD { \ /* \ * Main processor registers \ @@ -145,6 +152,8 @@ struct thread_struct { .reg29 = 0, \ .reg30 = 0, \ .reg31 = 0, \ + .sched_ra = 0, \ + .sched_cfa = 0, \ .csr_crmd = 0, \ .csr_prmd = 0, \ .csr_euen = 0, \ diff --git a/arch/loongarch/include/asm/switch_to.h b/arch/loongarch/include/asm/switch_to.h index 2a8d04375574..43a5ab162d38 100644 --- a/arch/loongarch/include/asm/switch_to.h +++ b/arch/loongarch/include/asm/switch_to.h @@ -15,12 +15,15 @@ struct task_struct; * @prev: The task previously executed. * @next: The task to begin executing. * @next_ti: task_thread_info(next). + * @sched_ra: __schedule return address. + * @sched_cfa: __schedule call frame address. * * This function is used whilst scheduling to save the context of prev & load * the context of next. Returns prev. */ extern asmlinkage struct task_struct *__switch_to(struct task_struct *prev, - struct task_struct *next, struct thread_info *next_ti); + struct task_struct *next, struct thread_info *next_ti, + void *sched_ra, void *sched_cfa); /* * For newly created kernel threads switch_to() will return to @@ -28,10 +31,11 @@ extern asmlinkage struct task_struct *__switch_to(struct task_struct *prev, * That is, everything following __switch_to() will be skipped for new threads. * So everything that matters to new threads should be placed before __switch_to(). */ -#define switch_to(prev, next, last) \ -do { \ - lose_fpu_inatomic(1, prev); \ - (last) = __switch_to(prev, next, task_thread_info(next)); \ +#define switch_to(prev, next, last) \ +do { \ + lose_fpu_inatomic(1, prev); \ + (last) = __switch_to(prev, next, task_thread_info(next), \ + __builtin_return_address(0), __builtin_frame_address(0)); \ } while (0) #endif /* _ASM_SWITCH_TO_H */ diff --git a/arch/loongarch/kernel/Makefile b/arch/loongarch/kernel/Makefile index 918600e7b30f..e5be17009fe8 100644 --- a/arch/loongarch/kernel/Makefile +++ b/arch/loongarch/kernel/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_EFI) += efi.o obj-$(CONFIG_CPU_HAS_FPU) += fpu.o obj-$(CONFIG_MODULES) += module.o module-sections.o +obj-$(CONFIG_STACKTRACE) += stacktrace.o obj-$(CONFIG_PROC_FS) += proc.o diff --git a/arch/loongarch/kernel/asm-offsets.c b/arch/loongarch/kernel/asm-offsets.c index 20cd9e16a95a..eb350f3ffae5 100644 --- a/arch/loongarch/kernel/asm-offsets.c +++ b/arch/loongarch/kernel/asm-offsets.c @@ -103,6 +103,8 @@ void output_thread_defines(void) OFFSET(THREAD_REG29, task_struct, thread.reg29); OFFSET(THREAD_REG30, task_struct, thread.reg30); OFFSET(THREAD_REG31, task_struct, thread.reg31); + OFFSET(THREAD_SCHED_RA, task_struct, thread.sched_ra); + OFFSET(THREAD_SCHED_CFA, task_struct, thread.sched_cfa); OFFSET(THREAD_CSRCRMD, task_struct, thread.csr_crmd); OFFSET(THREAD_CSRPRMD, task_struct, diff --git a/arch/loongarch/kernel/process.c b/arch/loongarch/kernel/process.c index 839f0e963152..660492f064e7 100644 --- a/arch/loongarch/kernel/process.c +++ b/arch/loongarch/kernel/process.c @@ -135,6 +135,7 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) childregs = (struct pt_regs *) childksp - 1; /* Put the stack after the struct pt_regs. */ childksp = (unsigned long) childregs; + p->thread.sched_cfa = 0; p->thread.csr_euen = 0; p->thread.csr_crmd = csr_read32(LOONGARCH_CSR_CRMD); p->thread.csr_prmd = csr_read32(LOONGARCH_CSR_PRMD); @@ -145,6 +146,7 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) p->thread.reg23 = (unsigned long)args->fn; p->thread.reg24 = (unsigned long)args->fn_arg; p->thread.reg01 = (unsigned long)ret_from_kernel_thread; + p->thread.sched_ra = (unsigned long)ret_from_kernel_thread; memset(childregs, 0, sizeof(struct pt_regs)); childregs->csr_euen = p->thread.csr_euen; childregs->csr_crmd = p->thread.csr_crmd; @@ -161,6 +163,7 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) p->thread.reg03 = (unsigned long) childregs; p->thread.reg01 = (unsigned long) ret_from_fork; + p->thread.sched_ra = (unsigned long) ret_from_fork; /* * New tasks lose permission to use the fpu. This accelerates context @@ -181,7 +184,31 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) unsigned long __get_wchan(struct task_struct *task) { - return 0; + unsigned long pc; + struct unwind_state state; + + if (!try_get_task_stack(task)) + return 0; + + unwind_start(&state, task, NULL); + state.sp = thread_saved_fp(task); + get_stack_info(state.sp, state.task, &state.stack_info); + state.pc = thread_saved_ra(task); +#ifdef CONFIG_UNWINDER_PROLOGUE + state.type = UNWINDER_PROLOGUE; +#endif + for (; !unwind_done(&state); unwind_next_frame(&state)) { + pc = unwind_get_return_address(&state); + if (!pc) + break; + if (in_sched_functions(pc)) + continue; + break; + } + + put_task_stack(task); + + return pc; } bool in_irq_stack(unsigned long stack, struct stack_info *info) diff --git a/arch/loongarch/kernel/stacktrace.c b/arch/loongarch/kernel/stacktrace.c new file mode 100644 index 000000000000..e690c1c769f2 --- /dev/null +++ b/arch/loongarch/kernel/stacktrace.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Stack trace management functions + * + * Copyright (C) 2022 Loongson Technology Corporation Limited + */ +#include +#include + +#include +#include + +void arch_stack_walk(stack_trace_consume_fn consume_entry, void *cookie, + struct task_struct *task, struct pt_regs *regs) +{ + unsigned long addr; + struct pt_regs dummyregs; + struct unwind_state state; + + regs = &dummyregs; + + if (task == current) { + regs->regs[3] = (unsigned long)__builtin_frame_address(0); + regs->csr_era = (unsigned long)__builtin_return_address(0); + } else { + regs->regs[3] = thread_saved_fp(task); + regs->csr_era = thread_saved_ra(task); + } + + regs->regs[1] = 0; + for (unwind_start(&state, task, regs); + !unwind_done(&state); unwind_next_frame(&state)) { + addr = unwind_get_return_address(&state); + if (!addr || !consume_entry(cookie, addr)) + break; + } +} diff --git a/arch/loongarch/kernel/switch.S b/arch/loongarch/kernel/switch.S index 37e84ac8ffc2..43ebbc3990f7 100644 --- a/arch/loongarch/kernel/switch.S +++ b/arch/loongarch/kernel/switch.S @@ -21,6 +21,8 @@ SYM_FUNC_START(__switch_to) cpu_save_nonscratch a0 stptr.d ra, a0, THREAD_REG01 + stptr.d a3, a0, THREAD_SCHED_RA + stptr.d a4, a0, THREAD_SCHED_CFA move tp, a2 cpu_restore_nonscratch a1 -- cgit v1.2.3 From 4d7bf939df08218e682f7a42952eee3bad4dceb7 Mon Sep 17 00:00:00 2001 From: Qing Zhang Date: Sat, 6 Aug 2022 16:10:05 +0800 Subject: LoongArch: Add USER_STACKTRACE support To get the best stacktrace output, you can compile your userspace programs with frame pointers (at least glibc + the app you are tracing). 1, export "CC = gcc -fno-omit-frame-pointer"; 2, compile your programs with "CC"; 3, use uprobe to get stacktrace output. ... echo 'p:malloc /usr/lib64/libc.so.6:0x0a4704 size=%r4:u64' > uprobe_events echo 'p:free /usr/lib64/libc.so.6:0x0a4d50 ptr=%r4:x64' >> uprobe_events echo 'comm == "demo"' > ./events/uprobes/malloc/filter echo 'comm == "demo"' > ./events/uprobes/free/filter echo 1 > ./options/userstacktrace echo 1 > ./options/sym-userobj ... Signed-off-by: Qing Zhang Signed-off-by: Huacai Chen --- arch/loongarch/Kconfig | 1 + arch/loongarch/include/asm/stacktrace.h | 5 ++++ arch/loongarch/kernel/stacktrace.c | 41 +++++++++++++++++++++++++++++++++ 3 files changed, 47 insertions(+) diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig index 947cb633744b..2f110a00a930 100644 --- a/arch/loongarch/Kconfig +++ b/arch/loongarch/Kconfig @@ -119,6 +119,7 @@ config LOONGARCH select SWIOTLB select TRACE_IRQFLAGS_SUPPORT select USE_PERCPU_NUMA_NODE_ID + select USER_STACKTRACE_SUPPORT select ZONE_DMA32 config 32BIT diff --git a/arch/loongarch/include/asm/stacktrace.h b/arch/loongarch/include/asm/stacktrace.h index 5820a0cabe3a..f23adb15f418 100644 --- a/arch/loongarch/include/asm/stacktrace.h +++ b/arch/loongarch/include/asm/stacktrace.h @@ -21,6 +21,11 @@ struct stack_info { unsigned long begin, end, next_sp; }; +struct stack_frame { + unsigned long fp; + unsigned long ra; +}; + bool in_irq_stack(unsigned long stack, struct stack_info *info); bool in_task_stack(unsigned long stack, struct task_struct *task, struct stack_info *info); int get_stack_info(unsigned long stack, struct task_struct *task, struct stack_info *info); diff --git a/arch/loongarch/kernel/stacktrace.c b/arch/loongarch/kernel/stacktrace.c index e690c1c769f2..3a690f96f00c 100644 --- a/arch/loongarch/kernel/stacktrace.c +++ b/arch/loongarch/kernel/stacktrace.c @@ -6,6 +6,7 @@ */ #include #include +#include #include #include @@ -35,3 +36,43 @@ void arch_stack_walk(stack_trace_consume_fn consume_entry, void *cookie, break; } } + +static int +copy_stack_frame(unsigned long fp, struct stack_frame *frame) +{ + int ret = 1; + unsigned long err; + unsigned long __user *user_frame_tail; + + user_frame_tail = (unsigned long *)(fp - sizeof(struct stack_frame)); + if (!access_ok(user_frame_tail, sizeof(*frame))) + return 0; + + pagefault_disable(); + err = (__copy_from_user_inatomic(frame, user_frame_tail, sizeof(*frame))); + if (err || (unsigned long)user_frame_tail >= frame->fp) + ret = 0; + pagefault_enable(); + + return ret; +} + +void arch_stack_walk_user(stack_trace_consume_fn consume_entry, void *cookie, + const struct pt_regs *regs) +{ + unsigned long fp = regs->regs[22]; + + while (fp && !((unsigned long)fp & 0xf)) { + struct stack_frame frame; + + frame.fp = 0; + frame.ra = 0; + if (!copy_stack_frame(fp, &frame)) + break; + if (!frame.ra) + break; + if (!consume_entry(cookie, frame.ra)) + break; + fp = frame.fp; + } +} -- cgit v1.2.3 From 27b161a4c41139f3a686533a5fde4abba05273d4 Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Wed, 10 Aug 2022 14:22:39 +0800 Subject: LoongArch: Update Loongson-3 default config file 1, Add NVME related options; 2, Add compressed firmware support; 3, Add virtio drivers in order to run in qemu. Signed-off-by: Huacai Chen --- arch/loongarch/configs/loongson3_defconfig | 34 +++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/loongarch/configs/loongson3_defconfig b/arch/loongarch/configs/loongson3_defconfig index eb9149786b6b..3712552e18d3 100644 --- a/arch/loongarch/configs/loongson3_defconfig +++ b/arch/loongarch/configs/loongson3_defconfig @@ -278,6 +278,8 @@ CONFIG_NET_ACT_IPT=m CONFIG_NET_ACT_NAT=m CONFIG_NET_ACT_BPF=m CONFIG_OPENVSWITCH=m +CONFIG_VSOCKETS=m +CONFIG_VIRTIO_VSOCKETS=m CONFIG_NETLINK_DIAG=y CONFIG_CGROUP_NET_PRIO=y CONFIG_BT=m @@ -289,6 +291,7 @@ CONFIG_MAC80211=m CONFIG_RFKILL=m CONFIG_RFKILL_INPUT=y CONFIG_NET_9P=y +CONFIG_NET_9P_VIRTIO=y CONFIG_CEPH_LIB=m CONFIG_PCIEPORTBUS=y CONFIG_HOTPLUG_PCI_PCIE=y @@ -308,6 +311,8 @@ CONFIG_RAPIDIO_MPORT_CDEV=m CONFIG_UEVENT_HELPER=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_ZSTD=y CONFIG_MTD=m CONFIG_MTD_BLOCK=m CONFIG_MTD_CFI=m @@ -328,8 +333,19 @@ CONFIG_BLK_DEV_CRYPTOLOOP=y CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_VIRTIO_BLK=y CONFIG_BLK_DEV_RBD=m CONFIG_BLK_DEV_NVME=y +CONFIG_NVME_MULTIPATH=y +CONFIG_NVME_RDMA=m +CONFIG_NVME_FC=m +CONFIG_NVME_TCP=m +CONFIG_NVME_TARGET=m +CONFIG_NVME_TARGET_PASSTHRU=y +CONFIG_NVME_TARGET_LOOP=m +CONFIG_NVME_TARGET_RDMA=m +CONFIG_NVME_TARGET_FC=m +CONFIG_NVME_TARGET_TCP=m CONFIG_EEPROM_AT24=m CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=y @@ -359,6 +375,7 @@ CONFIG_SCSI_QLA_FC=m CONFIG_TCM_QLA2XXX=m CONFIG_SCSI_QLA_ISCSI=m CONFIG_SCSI_LPFC=m +CONFIG_SCSI_VIRTIO=m CONFIG_ATA=y CONFIG_SATA_AHCI=y CONFIG_SATA_AHCI_PLATFORM=y @@ -403,6 +420,7 @@ CONFIG_VXLAN=y CONFIG_RIONET=m CONFIG_TUN=m CONFIG_VETH=m +CONFIG_VIRTIO_NET=m # CONFIG_NET_VENDOR_3COM is not set # CONFIG_NET_VENDOR_ADAPTEC is not set # CONFIG_NET_VENDOR_AGERE is not set @@ -527,10 +545,12 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_RSA=y CONFIG_SERIAL_NONSTANDARD=y CONFIG_PRINTER=m +CONFIG_VIRTIO_CONSOLE=y CONFIG_IPMI_HANDLER=m CONFIG_IPMI_DEVICE_INTERFACE=m CONFIG_IPMI_SI=m CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_VIRTIO=m CONFIG_I2C_CHARDEV=y CONFIG_I2C_PIIX4=y CONFIG_I2C_GPIO=y @@ -568,6 +588,8 @@ CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_CIK=y CONFIG_DRM_AMDGPU_USERPTR=y CONFIG_DRM_AST=y +CONFIG_DRM_QXL=m +CONFIG_DRM_VIRTIO_GPU=m CONFIG_FB=y CONFIG_FB_EFI=y CONFIG_FB_RADEON=y @@ -637,7 +659,16 @@ CONFIG_UIO=m CONFIG_UIO_PDRV_GENIRQ=m CONFIG_UIO_DMEM_GENIRQ=m CONFIG_UIO_PCI_GENERIC=m -# CONFIG_VIRTIO_MENU is not set +CONFIG_VFIO=m +CONFIG_VFIO_PCI=m +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_BALLOON=m +CONFIG_VIRTIO_INPUT=m +CONFIG_VIRTIO_MMIO=m +CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y +CONFIG_VHOST_NET=m +CONFIG_VHOST_SCSI=m +CONFIG_VHOST_VSOCK=m CONFIG_COMEDI=m CONFIG_COMEDI_PCI_DRIVERS=m CONFIG_COMEDI_8255_PCI=m @@ -762,6 +793,7 @@ CONFIG_CRYPTO_USER_API_HASH=m CONFIG_CRYPTO_USER_API_SKCIPHER=m CONFIG_CRYPTO_USER_API_RNG=m CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_DEV_VIRTIO=m CONFIG_PRINTK_TIME=y CONFIG_STRIP_ASM_SYMS=y CONFIG_MAGIC_SYSRQ=y -- cgit v1.2.3 From 6e068820de9c912ebc6147f8149be130b0dabc39 Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Wed, 10 Aug 2022 15:41:14 +0800 Subject: docs/LoongArch: Add I14 description I14 is also a kind of immediate operand in instruction, like I8/I12/I16/ I21/I26, add it in the English documentation. Signed-off-by: Tiezhu Yang Signed-off-by: Huacai Chen --- Documentation/loongarch/introduction.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/loongarch/introduction.rst b/Documentation/loongarch/introduction.rst index 216b3f390e80..6c9160c4e9be 100644 --- a/Documentation/loongarch/introduction.rst +++ b/Documentation/loongarch/introduction.rst @@ -221,7 +221,7 @@ I26 Opcode + I26L + I26H =========== ========================== Rd is the destination register operand, while Rj, Rk and Ra ("a" stands for -"additional") are the source register operands. I8/I12/I16/I21/I26 are +"additional") are the source register operands. I8/I12/I14/I16/I21/I26 are immediate operands of respective width. The longer I21 and I26 are stored in separate higher and lower parts in the instruction word, denoted by the "L" and "H" suffixes. -- cgit v1.2.3 From 715355922212a3be8bfe5a94b5707a045ac6bf00 Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Wed, 10 Aug 2022 15:41:15 +0800 Subject: docs/zh_CN/LoongArch: Add I14 description I14 is also a kind of immediate operand in instruction, like I8/I12/I16/ I21/I26, add it in the Chinese documentation. Signed-off-by: Tiezhu Yang Signed-off-by: Huacai Chen --- Documentation/translations/zh_CN/loongarch/introduction.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/translations/zh_CN/loongarch/introduction.rst b/Documentation/translations/zh_CN/loongarch/introduction.rst index 11686ee0caeb..128878f5bb70 100644 --- a/Documentation/translations/zh_CN/loongarch/introduction.rst +++ b/Documentation/translations/zh_CN/loongarch/introduction.rst @@ -190,8 +190,8 @@ I26 Opcode + I26L + I26H =========== ========================== Opcode是指令操作码，Rj和Rk是源操作数（寄存器），Rd是目标操作数（寄存器），Ra是 -4R-type格式特有的附加操作数（寄存器）。I8/I12/I16/I21/I26分别是8位/12位/16位/ -21位/26位的立即数。其中较长的21位和26位立即数在指令字中被分割为高位部分与低位 +4R-type格式特有的附加操作数（寄存器）。I8/I12/I14/I16/I21/I26分别是8位/12位/14位/ +16位/21位/26位的立即数。其中较长的21位和26位立即数在指令字中被分割为高位部分与低位 部分，所以你们在这里的格式描述中能够看到I21L/I21H和I26L/I26H这样带后缀的表述。 指令列表 -- cgit v1.2.3 From b1c3497e604ddccea5af4071831ed0e4680fb35e Mon Sep 17 00:00:00 2001 From: Jane Malalane Date: Fri, 29 Jul 2022 08:04:16 +0100 Subject: x86/xen: Add support for HVMOP_set_evtchn_upcall_vector MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement support for the HVMOP_set_evtchn_upcall_vector hypercall in order to set the per-vCPU event channel vector callback on Linux and use it in preference of HVM_PARAM_CALLBACK_IRQ. If the per-VCPU vector setup is successful on BSP, use this method for the APs. If not, fallback to the global vector-type callback. Also register callback_irq at per-vCPU event channel setup to trick toolstack to think the domain is enlightened. Suggested-by: "Roger Pau Monné" Signed-off-by: Jane Malalane Reviewed-by: Boris Ostrovsky Link: https://lore.kernel.org/r/20220729070416.23306-1-jane.malalane@citrix.com Signed-off-by: Juergen Gross --- arch/x86/include/asm/xen/cpuid.h | 2 ++ arch/x86/include/asm/xen/events.h | 3 ++- arch/x86/xen/enlighten.c | 2 +- arch/x86/xen/enlighten_hvm.c | 24 ++++++++++++----- arch/x86/xen/suspend_hvm.c | 10 ++++++- drivers/xen/events/events_base.c | 53 +++++++++++++++++++++++++++++++++----- include/xen/hvm.h | 2 ++ include/xen/interface/hvm/hvm_op.h | 19 ++++++++++++++ 8 files changed, 100 insertions(+), 15 deletions(-) diff --git a/arch/x86/include/asm/xen/cpuid.h b/arch/x86/include/asm/xen/cpuid.h index 78e667a31d6c..6daa9b0c8d11 100644 --- a/arch/x86/include/asm/xen/cpuid.h +++ b/arch/x86/include/asm/xen/cpuid.h @@ -107,6 +107,8 @@ * ID field from 8 to 15 bits, allowing to target APIC IDs up 32768. */ #define XEN_HVM_CPUID_EXT_DEST_ID (1u << 5) +/* Per-vCPU event channel upcalls */ +#define XEN_HVM_CPUID_UPCALL_VECTOR (1u << 6) /* * Leaf 6 (0x40000x05) diff --git a/arch/x86/include/asm/xen/events.h b/arch/x86/include/asm/xen/events.h index 068d9b067c83..62bdceb594f1 100644 --- a/arch/x86/include/asm/xen/events.h +++ b/arch/x86/include/asm/xen/events.h @@ -23,7 +23,7 @@ static inline int xen_irqs_disabled(struct pt_regs *regs) /* No need for a barrier -- XCHG is a barrier on x86. */ #define xchg_xen_ulong(ptr, val) xchg((ptr), (val)) -extern int xen_have_vector_callback; +extern bool xen_have_vector_callback; /* * Events delivered via platform PCI interrupts are always @@ -34,4 +34,5 @@ static inline bool xen_support_evtchn_rebind(void) return (!xen_hvm_domain() || xen_have_vector_callback); } +extern bool xen_percpu_upcall; #endif /* _ASM_X86_XEN_EVENTS_H */ diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c index 30c6e986a6cd..b8db2148c07d 100644 --- a/arch/x86/xen/enlighten.c +++ b/arch/x86/xen/enlighten.c @@ -51,7 +51,7 @@ EXPORT_SYMBOL_GPL(xen_start_info); struct shared_info xen_dummy_shared_info; -__read_mostly int xen_have_vector_callback; +__read_mostly bool xen_have_vector_callback = true; EXPORT_SYMBOL_GPL(xen_have_vector_callback); /* diff --git a/arch/x86/xen/enlighten_hvm.c b/arch/x86/xen/enlighten_hvm.c index 28762f800596..1c1ac418484b 100644 --- a/arch/x86/xen/enlighten_hvm.c +++ b/arch/x86/xen/enlighten_hvm.c @@ -8,6 +8,8 @@ #include #include +#include +#include #include #include @@ -31,6 +33,9 @@ static unsigned long shared_info_pfn; +__ro_after_init bool xen_percpu_upcall; +EXPORT_SYMBOL_GPL(xen_percpu_upcall); + void xen_hvm_init_shared_info(void) { struct xen_add_to_physmap xatp; @@ -126,6 +131,9 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_xen_hvm_callback) { struct pt_regs *old_regs = set_irq_regs(regs); + if (xen_percpu_upcall) + ack_APIC_irq(); + inc_irq_stat(irq_hv_callback_count); xen_hvm_evtchn_do_upcall(); @@ -169,6 +177,15 @@ static int xen_cpu_up_prepare_hvm(unsigned int cpu) if (!xen_have_vector_callback) return 0; + if (xen_percpu_upcall) { + rc = xen_set_upcall_vector(cpu); + if (rc) { + WARN(1, "HVMOP_set_evtchn_upcall_vector" + " for CPU %d failed: %d\n", cpu, rc); + return rc; + } + } + if (xen_feature(XENFEAT_hvm_safe_pvclock)) xen_setup_timer(cpu); @@ -189,8 +206,6 @@ static int xen_cpu_dead_hvm(unsigned int cpu) return 0; } -static bool no_vector_callback __initdata; - static void __init xen_hvm_guest_init(void) { if (xen_pv_domain()) @@ -213,9 +228,6 @@ static void __init xen_hvm_guest_init(void) xen_panic_handler_init(); - if (!no_vector_callback && xen_feature(XENFEAT_hvm_callback_vector)) - xen_have_vector_callback = 1; - xen_hvm_smp_init(); WARN_ON(xen_cpuhp_setup(xen_cpu_up_prepare_hvm, xen_cpu_dead_hvm)); xen_unplug_emulated_devices(); @@ -241,7 +253,7 @@ early_param("xen_nopv", xen_parse_nopv); static __init int xen_parse_no_vector_callback(char *arg) { - no_vector_callback = true; + xen_have_vector_callback = false; return 0; } early_param("xen_no_vector_callback", xen_parse_no_vector_callback); diff --git a/arch/x86/xen/suspend_hvm.c b/arch/x86/xen/suspend_hvm.c index 9d548b0c772f..0c4f7554b7cc 100644 --- a/arch/x86/xen/suspend_hvm.c +++ b/arch/x86/xen/suspend_hvm.c @@ -5,6 +5,7 @@ #include #include #include +#include #include "xen-ops.h" @@ -14,6 +15,13 @@ void xen_hvm_post_suspend(int suspend_cancelled) xen_hvm_init_shared_info(); xen_vcpu_restore(); } - xen_setup_callback_vector(); + if (xen_percpu_upcall) { + unsigned int cpu; + + for_each_online_cpu(cpu) + BUG_ON(xen_set_upcall_vector(cpu)); + } else { + xen_setup_callback_vector(); + } xen_unplug_emulated_devices(); } diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_base.c index 46d9295d9a6e..206d4b466e44 100644 --- a/drivers/xen/events/events_base.c +++ b/drivers/xen/events/events_base.c @@ -45,6 +45,7 @@ #include #include #include +#include #include #endif #include @@ -2183,6 +2184,7 @@ static struct irq_chip xen_percpu_chip __read_mostly = { .irq_ack = ack_dynirq, }; +#ifdef CONFIG_X86 #ifdef CONFIG_XEN_PVHVM /* Vector callbacks are better than PCI interrupts to receive event * channel notifications because we can receive vector callbacks on any @@ -2195,11 +2197,48 @@ void xen_setup_callback_vector(void) callback_via = HVM_CALLBACK_VECTOR(HYPERVISOR_CALLBACK_VECTOR); if (xen_set_callback_via(callback_via)) { pr_err("Request for Xen HVM callback vector failed\n"); - xen_have_vector_callback = 0; + xen_have_vector_callback = false; } } } +/* + * Setup per-vCPU vector-type callbacks. If this setup is unavailable, + * fallback to the global vector-type callback. + */ +static __init void xen_init_setup_upcall_vector(void) +{ + if (!xen_have_vector_callback) + return; + + if ((cpuid_eax(xen_cpuid_base() + 4) & XEN_HVM_CPUID_UPCALL_VECTOR) && + !xen_set_upcall_vector(0)) + xen_percpu_upcall = true; + else if (xen_feature(XENFEAT_hvm_callback_vector)) + xen_setup_callback_vector(); + else + xen_have_vector_callback = false; +} + +int xen_set_upcall_vector(unsigned int cpu) +{ + int rc; + xen_hvm_evtchn_upcall_vector_t op = { + .vector = HYPERVISOR_CALLBACK_VECTOR, + .vcpu = per_cpu(xen_vcpu_id, cpu), + }; + + rc = HYPERVISOR_hvm_op(HVMOP_set_evtchn_upcall_vector, &op); + if (rc) + return rc; + + /* Trick toolstack to think we are enlightened. */ + if (!cpu) + rc = xen_set_callback_via(1); + + return rc; +} + static __init void xen_alloc_callback_vector(void) { if (!xen_have_vector_callback) @@ -2210,8 +2249,11 @@ static __init void xen_alloc_callback_vector(void) } #else void xen_setup_callback_vector(void) {} +static inline void xen_init_setup_upcall_vector(void) {} +int xen_set_upcall_vector(unsigned int cpu) {} static inline void xen_alloc_callback_vector(void) {} -#endif +#endif /* CONFIG_XEN_PVHVM */ +#endif /* CONFIG_X86 */ bool xen_fifo_events = true; module_param_named(fifo_events, xen_fifo_events, bool, 0); @@ -2271,10 +2313,9 @@ void __init xen_init_IRQ(void) if (xen_initial_domain()) pci_xen_initial_domain(); } - if (xen_feature(XENFEAT_hvm_callback_vector)) { - xen_setup_callback_vector(); - xen_alloc_callback_vector(); - } + xen_init_setup_upcall_vector(); + xen_alloc_callback_vector(); + if (xen_hvm_domain()) { native_init_IRQ(); diff --git a/include/xen/hvm.h b/include/xen/hvm.h index b7fd7fc9ad41..8da7a6747058 100644 --- a/include/xen/hvm.h +++ b/include/xen/hvm.h @@ -60,4 +60,6 @@ static inline int hvm_get_parameter(int idx, uint64_t *value) void xen_setup_callback_vector(void); +int xen_set_upcall_vector(unsigned int cpu); + #endif /* XEN_HVM_H__ */ diff --git a/include/xen/interface/hvm/hvm_op.h b/include/xen/interface/hvm/hvm_op.h index f3097e79bb03..03134bf3cec1 100644 --- a/include/xen/interface/hvm/hvm_op.h +++ b/include/xen/interface/hvm/hvm_op.h @@ -46,4 +46,23 @@ struct xen_hvm_get_mem_type { }; DEFINE_GUEST_HANDLE_STRUCT(xen_hvm_get_mem_type); +#if defined(__i386__) || defined(__x86_64__) + +/* + * HVMOP_set_evtchn_upcall_vector: Set a that should be used for event + * channel upcalls on the specified . If set, + * this vector will be used in preference to the + * domain global callback via (see + * HVM_PARAM_CALLBACK_IRQ). + */ +#define HVMOP_set_evtchn_upcall_vector 23 +struct xen_hvm_evtchn_upcall_vector { + uint32_t vcpu; + uint8_t vector; +}; +typedef struct xen_hvm_evtchn_upcall_vector xen_hvm_evtchn_upcall_vector_t; +DEFINE_GUEST_HANDLE_STRUCT(xen_hvm_evtchn_upcall_vector_t); + +#endif /* defined(__i386__) || defined(__x86_64__) */ + #endif /* __XEN_PUBLIC_HVM_HVM_OP_H__ */ -- cgit v1.2.3 From 9f414eb409daf4f778f011cf8266d36896bb930b Mon Sep 17 00:00:00 2001 From: Mikulas Patocka Date: Wed, 10 Aug 2022 09:00:42 -0400 Subject: rds: add missing barrier to release_refill The functions clear_bit and set_bit do not imply a memory barrier, thus it may be possible that the waitqueue_active function (which does not take any locks) is moved before clear_bit and it could miss a wakeup event. Fix this bug by adding a memory barrier after clear_bit. Signed-off-by: Mikulas Patocka Cc: stable@vger.kernel.org Signed-off-by: David S. Miller --- net/rds/ib_recv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/rds/ib_recv.c b/net/rds/ib_recv.c index 6fdedd9dbbc2..cfbf0e129cba 100644 --- a/net/rds/ib_recv.c +++ b/net/rds/ib_recv.c @@ -363,6 +363,7 @@ static int acquire_refill(struct rds_connection *conn) static void release_refill(struct rds_connection *conn) { clear_bit(RDS_RECV_REFILL, &conn->c_flags); + smp_mb__after_atomic(); /* We don't use wait_on_bit()/wake_up_bit() because our waking is in a * hot path and finding waiters is very rare. We don't want to walk -- cgit v1.2.3 From fc9be616bb8f3ed9cf560308f86904f5c06be205 Mon Sep 17 00:00:00 2001 From: SeongJae Park Date: Fri, 15 Jul 2022 22:51:06 +0000 Subject: xen-blkback: fix persistent grants negotiation Persistent grants feature can be used only when both backend and the frontend supports the feature. The feature was always supported by 'blkback', but commit aac8a70db24b ("xen-blkback: add a parameter for disabling of persistent grants") has introduced a parameter for disabling it runtime. To avoid the parameter be updated while being used by 'blkback', the commit caches the parameter into 'vbd->feature_gnt_persistent' in 'xen_vbd_create()', and then check if the guest also supports the feature and finally updates the field in 'connect_ring()'. However, 'connect_ring()' could be called before 'xen_vbd_create()', so later execution of 'xen_vbd_create()' can wrongly overwrite 'true' to 'vbd->feature_gnt_persistent'. As a result, 'blkback' could try to use 'persistent grants' feature even if the guest doesn't support the feature. This commit fixes the issue by moving the parameter value caching to 'xen_blkif_alloc()', which allocates the 'blkif'. Because the struct embeds 'vbd' object, which will be used by 'connect_ring()' later, this should be called before 'connect_ring()' and therefore this should be the right and safe place to do the caching. Fixes: aac8a70db24b ("xen-blkback: add a parameter for disabling of persistent grants") Cc: # 5.10.x Signed-off-by: Maximilian Heyne Signed-off-by: SeongJae Park Reviewed-by: Maximilian Heyne Reviewed-by: Juergen Gross Link: https://lore.kernel.org/r/20220715225108.193398-2-sj@kernel.org Signed-off-by: Juergen Gross --- drivers/block/xen-blkback/xenbus.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/block/xen-blkback/xenbus.c b/drivers/block/xen-blkback/xenbus.c index 97de13b14175..16c6785d260c 100644 --- a/drivers/block/xen-blkback/xenbus.c +++ b/drivers/block/xen-blkback/xenbus.c @@ -157,6 +157,11 @@ static int xen_blkif_alloc_rings(struct xen_blkif *blkif) return 0; } +/* Enable the persistent grants feature. */ +static bool feature_persistent = true; +module_param(feature_persistent, bool, 0644); +MODULE_PARM_DESC(feature_persistent, "Enables the persistent grants feature"); + static struct xen_blkif *xen_blkif_alloc(domid_t domid) { struct xen_blkif *blkif; @@ -181,6 +186,8 @@ static struct xen_blkif *xen_blkif_alloc(domid_t domid) __module_get(THIS_MODULE); INIT_WORK(&blkif->free_work, xen_blkif_deferred_free); + blkif->vbd.feature_gnt_persistent = feature_persistent; + return blkif; } @@ -472,12 +479,6 @@ static void xen_vbd_free(struct xen_vbd *vbd) vbd->bdev = NULL; } -/* Enable the persistent grants feature. */ -static bool feature_persistent = true; -module_param(feature_persistent, bool, 0644); -MODULE_PARM_DESC(feature_persistent, - "Enables the persistent grants feature"); - static int xen_vbd_create(struct xen_blkif *blkif, blkif_vdev_t handle, unsigned major, unsigned minor, int readonly, int cdrom) @@ -520,8 +521,6 @@ static int xen_vbd_create(struct xen_blkif *blkif, blkif_vdev_t handle, if (bdev_max_secure_erase_sectors(bdev)) vbd->discard_secure = true; - vbd->feature_gnt_persistent = feature_persistent; - pr_debug("Successful creation of handle=%04x (dom=%u)\n", handle, blkif->domid); return 0; -- cgit v1.2.3 From e94c6101e151b019b8babc518ac2a6ada644a5a1 Mon Sep 17 00:00:00 2001 From: Maximilian Heyne Date: Fri, 15 Jul 2022 22:51:07 +0000 Subject: xen-blkback: Apply 'feature_persistent' parameter when connect In some use cases[1], the backend is created while the frontend doesn't support the persistent grants feature, but later the frontend can be changed to support the feature and reconnect. In the past, 'blkback' enabled the persistent grants feature since it unconditionally checked if frontend supports the persistent grants feature for every connect ('connect_ring()') and decided whether it should use persistent grans or not. However, commit aac8a70db24b ("xen-blkback: add a parameter for disabling of persistent grants") has mistakenly changed the behavior. It made the frontend feature support check to not be repeated once it shown the 'feature_persistent' as 'false', or the frontend doesn't support persistent grants. This commit changes the behavior of the parameter to make effect for every connect, so that the previous workflow can work again as expected. [1] https://lore.kernel.org/xen-devel/CAJwUmVB6H3iTs-C+U=v-pwJB7-_ZRHPxHzKRJZ22xEPW7z8a=g@mail.gmail.com/ Reported-by: Andrii Chepurnyi Fixes: aac8a70db24b ("xen-blkback: add a parameter for disabling of persistent grants") Cc: # 5.10.x Signed-off-by: Maximilian Heyne Signed-off-by: SeongJae Park Reviewed-by: Maximilian Heyne Reviewed-by: Juergen Gross Link: https://lore.kernel.org/r/20220715225108.193398-3-sj@kernel.org Signed-off-by: Juergen Gross --- Documentation/ABI/testing/sysfs-driver-xen-blkback | 2 +- drivers/block/xen-blkback/xenbus.c | 9 +++------ 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-driver-xen-blkback b/Documentation/ABI/testing/sysfs-driver-xen-blkback index 7faf719af165..fac0f429a869 100644 --- a/Documentation/ABI/testing/sysfs-driver-xen-blkback +++ b/Documentation/ABI/testing/sysfs-driver-xen-blkback @@ -42,5 +42,5 @@ KernelVersion: 5.10 Contact: Maximilian Heyne Description: Whether to enable the persistent grants feature or not. Note - that this option only takes effect on newly created backends. + that this option only takes effect on newly connected backends. The default is Y (enable). diff --git a/drivers/block/xen-blkback/xenbus.c b/drivers/block/xen-blkback/xenbus.c index 16c6785d260c..ee7ad2fb432d 100644 --- a/drivers/block/xen-blkback/xenbus.c +++ b/drivers/block/xen-blkback/xenbus.c @@ -186,8 +186,6 @@ static struct xen_blkif *xen_blkif_alloc(domid_t domid) __module_get(THIS_MODULE); INIT_WORK(&blkif->free_work, xen_blkif_deferred_free); - blkif->vbd.feature_gnt_persistent = feature_persistent; - return blkif; } @@ -1086,10 +1084,9 @@ static int connect_ring(struct backend_info *be) xenbus_dev_fatal(dev, err, "unknown fe protocol %s", protocol); return -ENOSYS; } - if (blkif->vbd.feature_gnt_persistent) - blkif->vbd.feature_gnt_persistent = - xenbus_read_unsigned(dev->otherend, - "feature-persistent", 0); + + blkif->vbd.feature_gnt_persistent = feature_persistent && + xenbus_read_unsigned(dev->otherend, "feature-persistent", 0); blkif->vbd.overflow_max_grants = 0; -- cgit v1.2.3 From 402c43ea6b34a1b371ffeed9adf907402569eaf5 Mon Sep 17 00:00:00 2001 From: SeongJae Park Date: Fri, 15 Jul 2022 22:51:08 +0000 Subject: xen-blkfront: Apply 'feature_persistent' parameter when connect In some use cases[1], the backend is created while the frontend doesn't support the persistent grants feature, but later the frontend can be changed to support the feature and reconnect. In the past, 'blkback' enabled the persistent grants feature since it unconditionally checked if frontend supports the persistent grants feature for every connect ('connect_ring()') and decided whether it should use persistent grans or not. However, commit aac8a70db24b ("xen-blkback: add a parameter for disabling of persistent grants") has mistakenly changed the behavior. It made the frontend feature support check to not be repeated once it shown the 'feature_persistent' as 'false', or the frontend doesn't support persistent grants. Similar behavioral change has made on 'blkfront' by commit 74a852479c68 ("xen-blkfront: add a parameter for disabling of persistent grants"). This commit changes the behavior of the parameter to make effect for every connect, so that the previous behavior of 'blkfront' can be restored. [1] https://lore.kernel.org/xen-devel/CAJwUmVB6H3iTs-C+U=v-pwJB7-_ZRHPxHzKRJZ22xEPW7z8a=g@mail.gmail.com/ Fixes: 74a852479c68 ("xen-blkfront: add a parameter for disabling of persistent grants") Cc: # 5.10.x Signed-off-by: SeongJae Park Reviewed-by: Maximilian Heyne Reviewed-by: Juergen Gross Link: https://lore.kernel.org/r/20220715225108.193398-4-sj@kernel.org Signed-off-by: Juergen Gross --- Documentation/ABI/testing/sysfs-driver-xen-blkfront | 2 +- drivers/block/xen-blkfront.c | 4 +--- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-driver-xen-blkfront b/Documentation/ABI/testing/sysfs-driver-xen-blkfront index 7f646c58832e..4d36c5a10546 100644 --- a/Documentation/ABI/testing/sysfs-driver-xen-blkfront +++ b/Documentation/ABI/testing/sysfs-driver-xen-blkfront @@ -15,5 +15,5 @@ KernelVersion: 5.10 Contact: Maximilian Heyne Description: Whether to enable the persistent grants feature or not. Note - that this option only takes effect on newly created frontends. + that this option only takes effect on newly connected frontends. The default is Y (enable). diff --git a/drivers/block/xen-blkfront.c b/drivers/block/xen-blkfront.c index 3646c0cae672..4e763701b372 100644 --- a/drivers/block/xen-blkfront.c +++ b/drivers/block/xen-blkfront.c @@ -1988,8 +1988,6 @@ static int blkfront_probe(struct xenbus_device *dev, info->vdevice = vdevice; info->connected = BLKIF_STATE_DISCONNECTED; - info->feature_persistent = feature_persistent; - /* Front end dir is a number, which is used as the id. */ info->handle = simple_strtoul(strrchr(dev->nodename, '/')+1, NULL, 0); dev_set_drvdata(&dev->dev, info); @@ -2283,7 +2281,7 @@ static void blkfront_gather_backend_features(struct blkfront_info *info) if (xenbus_read_unsigned(info->xbdev->otherend, "feature-discard", 0)) blkfront_setup_discard(info); - if (info->feature_persistent) + if (feature_persistent) info->feature_persistent = !!xenbus_read_unsigned(info->xbdev->otherend, "feature-persistent", 0); -- cgit v1.2.3 From 32ad11127b95236dfc52375f3707853194a7f4b4 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 4 Aug 2022 10:11:33 +0300 Subject: xen/xenbus: fix return type in xenbus_file_read() This code tries to store -EFAULT in an unsigned int. The xenbus_file_read() function returns type ssize_t so the negative value is returned as a positive value to the user. This change forces another change to the min() macro. Originally, the min() macro used "unsigned" type which checkpatch complains about. Also unsigned type would break if "len" were not capped at MAX_RW_COUNT. Use size_t for the min(). (No effect on runtime for the min_t() change). Fixes: 2fb3683e7b16 ("xen: Add xenbus device driver") Signed-off-by: Dan Carpenter Reviewed-by: Oleksandr Tyshchenko Link: https://lore.kernel.org/r/YutxJUaUYRG/VLVc@kili Signed-off-by: Juergen Gross --- drivers/xen/xenbus/xenbus_dev_frontend.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/xen/xenbus/xenbus_dev_frontend.c b/drivers/xen/xenbus/xenbus_dev_frontend.c index 597af455a522..0792fda49a15 100644 --- a/drivers/xen/xenbus/xenbus_dev_frontend.c +++ b/drivers/xen/xenbus/xenbus_dev_frontend.c @@ -128,7 +128,7 @@ static ssize_t xenbus_file_read(struct file *filp, { struct xenbus_file_priv *u = filp->private_data; struct read_buffer *rb; - unsigned i; + ssize_t i; int ret; mutex_lock(&u->reply_mutex); @@ -148,7 +148,7 @@ again: rb = list_entry(u->read_buffers.next, struct read_buffer, list); i = 0; while (i < len) { - unsigned sz = min((unsigned)len - i, rb->len - rb->cons); + size_t sz = min_t(size_t, len - i, rb->len - rb->cons); ret = copy_to_user(ubuf + i, &rb->msg[rb->cons], sz); -- cgit v1.2.3 From ced3c74271bfedfb8e517c01b4dd7b9aad7020b0 Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Thu, 11 Aug 2022 20:09:18 +0800 Subject: xen/pciback: Fix comment typo The double `the' is duplicated in the comment, remove one. Signed-off-by: Jason Wang Reviewed-by: Juergen Gross Link: https://lore.kernel.org/r/20220811120918.17961-1-wangborong@cdjrlc.com Signed-off-by: Juergen Gross --- drivers/xen/xen-pciback/pciback_ops.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/xen/xen-pciback/pciback_ops.c b/drivers/xen/xen-pciback/pciback_ops.c index 3fbc21466a93..84e014490950 100644 --- a/drivers/xen/xen-pciback/pciback_ops.c +++ b/drivers/xen/xen-pciback/pciback_ops.c @@ -159,7 +159,7 @@ int xen_pcibk_enable_msi(struct xen_pcibk_device *pdev, return XEN_PCI_ERR_op_failed; } - /* The value the guest needs is actually the IDT vector, not the + /* The value the guest needs is actually the IDT vector, not * the local domain's IRQ number. */ op->value = dev->irq ? xen_pirq_from_irq(dev->irq) : 0; -- cgit v1.2.3 From 86d2155e48f6ce1aacbd01667176e5b915ae275c Mon Sep 17 00:00:00 2001 From: Jilin Yuan Date: Wed, 10 Aug 2022 21:59:01 +0800 Subject: skfp/h: fix repeated words in comments Delete the redundant word 'the'. Signed-off-by: Jilin Yuan Signed-off-by: David S. Miller --- drivers/net/fddi/skfp/h/hwmtm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/fddi/skfp/h/hwmtm.h b/drivers/net/fddi/skfp/h/hwmtm.h index 76c4a709d73d..e97db826cdd4 100644 --- a/drivers/net/fddi/skfp/h/hwmtm.h +++ b/drivers/net/fddi/skfp/h/hwmtm.h @@ -348,7 +348,7 @@ do { \ * This macro is invoked by the OS-specific before it left the * function mac_drv_rx_complete. This macro calls mac_drv_fill_rxd * if the number of used RxDs is equal or lower than the - * the given low water mark. + * given low water mark. * * para low_water low water mark of used RxD's * -- cgit v1.2.3 From bfc48f1b0505ffcb03a6d749139b7577d6b81ae0 Mon Sep 17 00:00:00 2001 From: Xin Xiong Date: Wed, 10 Aug 2022 23:29:13 +0800 Subject: net/sunrpc: fix potential memory leaks in rpc_sysfs_xprt_state_change() The issue happens on some error handling paths. When the function fails to grab the object `xprt`, it simply returns 0, forgetting to decrease the reference count of another object `xps`, which is increased by rpc_sysfs_xprt_kobj_get_xprt_switch(), causing refcount leaks. Also, the function forgets to check whether `xps` is valid before using it, which may result in NULL-dereferencing issues. Fix it by adding proper error handling code when either `xprt` or `xps` is NULL. Fixes: 5b7eb78486cd ("SUNRPC: take a xprt offline using sysfs") Signed-off-by: Xin Xiong Signed-off-by: Xin Tan Signed-off-by: David S. Miller --- net/sunrpc/sysfs.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/net/sunrpc/sysfs.c b/net/sunrpc/sysfs.c index 7330eb9a70cf..c65c90ad626a 100644 --- a/net/sunrpc/sysfs.c +++ b/net/sunrpc/sysfs.c @@ -291,8 +291,10 @@ static ssize_t rpc_sysfs_xprt_state_change(struct kobject *kobj, int offline = 0, online = 0, remove = 0; struct rpc_xprt_switch *xps = rpc_sysfs_xprt_kobj_get_xprt_switch(kobj); - if (!xprt) - return 0; + if (!xprt || !xps) { + count = 0; + goto out_put; + } if (!strncmp(buf, "offline", 7)) offline = 1; -- cgit v1.2.3 From aa6d1e5b502866a4364dfeb2cdecf7c258c400ee Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Wed, 10 Aug 2022 07:07:10 +0200 Subject: xen: remove XEN_SCRUB_PAGES in xen.config Commit 197ecb3802c0 ("xen/balloon: add runtime control for scrubbing ballooned out pages") changed config XEN_SCRUB_PAGES to config XEN_SCRUB_PAGES_DEFAULT. As xen.config sets 'XEN_BALLOON=y' and XEN_SCRUB_PAGES_DEFAULT defaults to yes, there is no further need to set this config in the xen.config file. Remove setting XEN_SCRUB_PAGES in xen.config, which is without effect since the commit above anyway. Signed-off-by: Lukas Bulwahn Reviewed-by: Juergen Gross Link: https://lore.kernel.org/r/20220810050712.9539-3-lukas.bulwahn@gmail.com Signed-off-by: Juergen Gross --- kernel/configs/xen.config | 1 - 1 file changed, 1 deletion(-) diff --git a/kernel/configs/xen.config b/kernel/configs/xen.config index ff756221f112..436f806aa1ed 100644 --- a/kernel/configs/xen.config +++ b/kernel/configs/xen.config @@ -34,7 +34,6 @@ CONFIG_INPUT_XEN_KBDDEV_FRONTEND=m CONFIG_XEN_SCSI_FRONTEND=m # others CONFIG_XEN_BALLOON=y -CONFIG_XEN_SCRUB_PAGES=y CONFIG_XEN_DEV_EVTCHN=m CONFIG_XEN_BLKDEV_FRONTEND=m CONFIG_XEN_NETDEV_FRONTEND=m -- cgit v1.2.3 From 5ad3134dcf5201c4d51c981e52557939256b02c7 Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Wed, 10 Aug 2022 07:07:12 +0200 Subject: MAINTAINERS: add xen config fragments to XEN HYPERVISOR sections Make changes to the xen config fragments reach the XEN HYPERVISOR maintainers and mailing list. Signed-off-by: Lukas Bulwahn Reviewed-by: Juergen Gross Link: https://lore.kernel.org/r/20220810050712.9539-5-lukas.bulwahn@gmail.com Signed-off-by: Juergen Gross --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c173a580ff77..bb2c16a9d147 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21906,12 +21906,14 @@ F: drivers/*/xen-*front.c F: drivers/xen/ F: include/uapi/xen/ F: include/xen/ +F: kernel/configs/xen.config XEN HYPERVISOR X86 M: Juergen Gross R: Boris Ostrovsky L: xen-devel@lists.xenproject.org (moderated for non-subscribers) S: Supported +F: arch/x86/configs/xen.config F: arch/x86/include/asm/pvclock-abi.h F: arch/x86/include/asm/xen/ F: arch/x86/platform/pvh/ -- cgit v1.2.3 From 95bb633048fab742230eb2cdf20b8e2676240a54 Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Thu, 11 Aug 2022 08:51:58 -0400 Subject: virtio_net: fix endian-ness for RSS Using native endian-ness for device supplied fields is wrong on BE platforms. Sparse warns about this. Fixes: 91f41f01d219 ("drivers/net/virtio_net: Added RSS hash report.") Cc: "Andrew Melnychenko" Signed-off-by: Michael S. Tsirkin Signed-off-by: David S. Miller --- drivers/net/virtio_net.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index 3b3eebad3977..d4e0a775b1ba 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c @@ -1199,7 +1199,7 @@ static void virtio_skb_set_hash(const struct virtio_net_hdr_v1_hash *hdr_hash, if (!hdr_hash || !skb) return; - switch ((int)hdr_hash->hash_report) { + switch (__le16_to_cpu(hdr_hash->hash_report)) { case VIRTIO_NET_HASH_REPORT_TCPv4: case VIRTIO_NET_HASH_REPORT_UDPv4: case VIRTIO_NET_HASH_REPORT_TCPv6: @@ -1217,7 +1217,7 @@ static void virtio_skb_set_hash(const struct virtio_net_hdr_v1_hash *hdr_hash, default: rss_hash_type = PKT_HASH_TYPE_NONE; } - skb_set_hash(skb, (unsigned int)hdr_hash->hash_value, rss_hash_type); + skb_set_hash(skb, __le32_to_cpu(hdr_hash->hash_value), rss_hash_type); } static void receive_buf(struct virtnet_info *vi, struct receive_queue *rq, -- cgit v1.2.3 From 9221b2898a5877f7e15442ccee7a4e59c6f03f0d Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Thu, 11 Aug 2022 19:52:59 +0800 Subject: net: ipa: Fix comment typo The double `is' is duplicated in the comment, remove one. Signed-off-by: Jason Wang Reviewed-by: Alex Elder Signed-off-by: David S. Miller --- drivers/net/ipa/ipa_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index a5b355384d4a..6f35438cda89 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -48,7 +48,7 @@ struct ipa; * * The offset of registers related to resource types is computed by a macro * that is supplied a parameter "rt". The "rt" represents a resource type, - * which is is a member of the ipa_resource_type_src enumerated type for + * which is a member of the ipa_resource_type_src enumerated type for * source endpoint resources or the ipa_resource_type_dst enumerated type * for destination endpoint resources. * -- cgit v1.2.3 From 0619d0fa6cedb32f0835e23ca774085128ccb2b8 Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Thu, 11 Aug 2022 19:56:20 +0800 Subject: bnx2x: Fix comment typo The double `the' is duplicated in the comment, remove one. Signed-off-by: Jason Wang Signed-off-by: David S. Miller --- drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c index 7071604f9984..02808513ffe4 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c @@ -13844,7 +13844,7 @@ static void bnx2x_check_kr2_wa(struct link_params *params, /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery * Since some switches tend to reinit the AN process and clear the - * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled + * advertised BP/NP after ~2 seconds causing the KR2 to be disabled * and recovered many times */ if (vars->check_kr2_recovery_cnt > 0) { -- cgit v1.2.3 From 75d8620d46f00fcece574dd70ea36acfdfcf171b Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Thu, 11 Aug 2022 19:57:01 +0800 Subject: net: cxgb3: Fix comment typo The double `the' is duplicated in the comment, remove one. Signed-off-by: Jason Wang Signed-off-by: David S. Miller --- drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c b/drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c index 84604aff53ce..89256b866840 100644 --- a/drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c +++ b/drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c @@ -243,7 +243,7 @@ static int cxgb_ulp_iscsi_ctl(struct adapter *adapter, unsigned int req, /* * on rx, the iscsi pdu has to be < rx page size and the - * the max rx data length programmed in TP + * max rx data length programmed in TP */ val = min(adapter->params.tp.rx_pg_size, ((t3_read_reg(adapter, A_TP_PARA_REG2)) >> -- cgit v1.2.3 From 40b4ac880e21d917da7f3752332fa57564a4c202 Mon Sep 17 00:00:00 2001 From: Li Qiong Date: Fri, 12 Aug 2022 11:09:54 +0800 Subject: net: lan966x: fix checking for return value of platform_get_irq_byname() The platform_get_irq_byname() returns non-zero IRQ number or negative error number. "if (irq)" always true, chang it to "if (irq > 0)" Signed-off-by: Li Qiong Signed-off-by: David S. Miller --- drivers/net/ethernet/microchip/lan966x/lan966x_main.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c index 1d6e3b641b2e..d928b75f3780 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -710,7 +710,7 @@ static void lan966x_cleanup_ports(struct lan966x *lan966x) disable_irq(lan966x->xtr_irq); lan966x->xtr_irq = -ENXIO; - if (lan966x->ana_irq) { + if (lan966x->ana_irq > 0) { disable_irq(lan966x->ana_irq); lan966x->ana_irq = -ENXIO; } @@ -718,10 +718,10 @@ static void lan966x_cleanup_ports(struct lan966x *lan966x) if (lan966x->fdma) devm_free_irq(lan966x->dev, lan966x->fdma_irq, lan966x); - if (lan966x->ptp_irq) + if (lan966x->ptp_irq > 0) devm_free_irq(lan966x->dev, lan966x->ptp_irq, lan966x); - if (lan966x->ptp_ext_irq) + if (lan966x->ptp_ext_irq > 0) devm_free_irq(lan966x->dev, lan966x->ptp_ext_irq, lan966x); } @@ -1049,7 +1049,7 @@ static int lan966x_probe(struct platform_device *pdev) } lan966x->ana_irq = platform_get_irq_byname(pdev, "ana"); - if (lan966x->ana_irq) { + if (lan966x->ana_irq > 0) { err = devm_request_threaded_irq(&pdev->dev, lan966x->ana_irq, NULL, lan966x_ana_irq_handler, IRQF_ONESHOT, "ana irq", lan966x); -- cgit v1.2.3 From aa0c680c3aa96a5f9f160d90dd95402ad578e2b0 Mon Sep 17 00:00:00 2001 From: Rafael Mendonca Date: Thu, 11 Aug 2022 20:23:37 -0300 Subject: block: Do not call blk_put_queue() if gendisk allocation fails Commit 6f8191fdf41d ("block: simplify disk shutdown") removed the call to blk_get_queue() during gendisk allocation but missed to remove the corresponding cleanup code blk_put_queue() for it. Thus, if the gendisk allocation fails, the request_queue refcount gets decremented and reaches 0, causing blk_mq_release() to be called with a hctx still alive. That triggers a WARNING report, as found by syzkaller: ------------[ cut here ]------------ WARNING: CPU: 0 PID: 23016 at block/blk-mq.c:3881 blk_mq_release+0xf8/0x3e0 block/blk-mq.c:3881 [...] stripped RIP: 0010:blk_mq_release+0xf8/0x3e0 block/blk-mq.c:3881 [...] stripped Call Trace: blk_release_queue+0x153/0x270 block/blk-sysfs.c:780 kobject_cleanup lib/kobject.c:673 [inline] kobject_release lib/kobject.c:704 [inline] kref_put include/linux/kref.h:65 [inline] kobject_put+0x1c8/0x540 lib/kobject.c:721 __alloc_disk_node+0x4f7/0x610 block/genhd.c:1388 __blk_mq_alloc_disk+0x13b/0x1f0 block/blk-mq.c:3961 loop_add+0x3e2/0xaf0 drivers/block/loop.c:1978 loop_control_ioctl+0x133/0x620 drivers/block/loop.c:2150 vfs_ioctl fs/ioctl.c:51 [inline] __do_sys_ioctl fs/ioctl.c:870 [inline] __se_sys_ioctl fs/ioctl.c:856 [inline] __x64_sys_ioctl+0x193/0x200 fs/ioctl.c:856 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x35/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd [...] stripped Fixes: 6f8191fdf41d ("block: simplify disk shutdown") Reported-by: syzbot+31c9594f6e43b9289b25@syzkaller.appspotmail.com Suggested-by: Hillf Danton Signed-off-by: Rafael Mendonca Reviewed-by: Christoph Hellwig Link: https://lore.kernel.org/r/20220811232338.254673-1-rafaelmendsr@gmail.com Signed-off-by: Jens Axboe --- block/genhd.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/block/genhd.c b/block/genhd.c index b901fea1d55a..d36fabf0abc1 100644 --- a/block/genhd.c +++ b/block/genhd.c @@ -1341,7 +1341,7 @@ struct gendisk *__alloc_disk_node(struct request_queue *q, int node_id, disk = kzalloc_node(sizeof(struct gendisk), GFP_KERNEL, node_id); if (!disk) - goto out_put_queue; + return NULL; if (bioset_init(&disk->bio_split, BIO_POOL_SIZE, 0, 0)) goto out_free_disk; @@ -1390,8 +1390,6 @@ out_free_bioset: bioset_exit(&disk->bio_split); out_free_disk: kfree(disk); -out_put_queue: - blk_put_queue(q); return NULL; } -- cgit v1.2.3 From 34575ded6874a9d228c1166243149c347a4012de Mon Sep 17 00:00:00 2001 From: Martin Liška Date: Fri, 12 Aug 2022 13:42:56 +0200 Subject: perf build-id: Fix coding style, replace 8 spaces by tabs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use tabs instead of 8 spaces for the indentation. Signed-off-by: Martin Liška Link: http://lore.kernel.org/lkml/2983e2e0-6850-ad59-79d8-efe83b22cffe@suse.cz Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/build-id.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/tools/perf/util/build-id.c b/tools/perf/util/build-id.c index 9e176146eb10..0cc68cdd84c8 100644 --- a/tools/perf/util/build-id.c +++ b/tools/perf/util/build-id.c @@ -652,17 +652,17 @@ static char *build_id_cache__find_debug(const char *sbuild_id, nsinfo__mountns_exit(&nsc); #ifdef HAVE_DEBUGINFOD_SUPPORT - if (realname == NULL) { - debuginfod_client* c = debuginfod_begin(); - if (c != NULL) { - int fd = debuginfod_find_debuginfo(c, - (const unsigned char*)sbuild_id, 0, - &realname); - if (fd >= 0) - close(fd); /* retaining reference by realname */ - debuginfod_end(c); - } - } + if (realname == NULL) { + debuginfod_client* c = debuginfod_begin(); + if (c != NULL) { + int fd = debuginfod_find_debuginfo(c, + (const unsigned char*)sbuild_id, 0, + &realname); + if (fd >= 0) + close(fd); /* retaining reference by realname */ + debuginfod_end(c); + } + } #endif out: -- cgit v1.2.3 From a072a7a0263ddc723305dfd975f931bcea4e4f5b Mon Sep 17 00:00:00 2001 From: Martin Liška Date: Fri, 12 Aug 2022 13:43:53 +0200 Subject: perf build-id: Print debuginfod queries if -v option is used MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When ending a 'perf record' session, the querying of a debuginfod server can take quite some time. Inform a user about it when -v options is used. Signed-off-by: Martin Liška Link: http://lore.kernel.org/lkml/325871cf-b71f-6237-8793-82182272ece8@suse.cz Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/build-id.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/build-id.c b/tools/perf/util/build-id.c index 0cc68cdd84c8..ec18ed5caf3e 100644 --- a/tools/perf/util/build-id.c +++ b/tools/perf/util/build-id.c @@ -653,7 +653,11 @@ static char *build_id_cache__find_debug(const char *sbuild_id, #ifdef HAVE_DEBUGINFOD_SUPPORT if (realname == NULL) { - debuginfod_client* c = debuginfod_begin(); + debuginfod_client* c; + + pr_debug("Downloading debug info with build id %s\n", sbuild_id); + + c = debuginfod_begin(); if (c != NULL) { int fd = debuginfod_find_debuginfo(c, (const unsigned char*)sbuild_id, 0, -- cgit v1.2.3 From 1bf7d836e57ba4943e33e163e730cd77ab837572 Mon Sep 17 00:00:00 2001 From: Martin Liška Date: Fri, 12 Aug 2022 13:40:49 +0200 Subject: perf record: Improve error message of -p not_existing_pid MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When one uses -p $not_existing_pid, the output of --help is printed: $ perf record -p 123456789 2>&1 | head -n3 Usage: perf record [] [] or: perf record [] -- [] Let's change it something similar what perf top -p $not_existing_pid prints: $ ./perf top -p 123456789 --stdio Error: Couldn't create thread/CPU maps: No such process Newly suggested error message: $ ./perf record -p 123456789 Couldn't create thread/CPU maps: No such process Signed-off-by: Martin Liška Tested-by: Arnaldo Carvalho de Melo Link: http://lore.kernel.org/lkml/8e00eda1-4de0-2c44-ce67-d4df48ac1f7c@suse.cz Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-record.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c index cf5c5379ceaa..4713f0f3a6cf 100644 --- a/tools/perf/builtin-record.c +++ b/tools/perf/builtin-record.c @@ -3996,8 +3996,15 @@ int cmd_record(int argc, const char **argv) arch__add_leaf_frame_record_opts(&rec->opts); err = -ENOMEM; - if (evlist__create_maps(rec->evlist, &rec->opts.target) < 0) - usage_with_options(record_usage, record_options); + if (evlist__create_maps(rec->evlist, &rec->opts.target) < 0) { + if (rec->opts.target.pid != NULL) { + pr_err("Couldn't create thread/CPU maps: %s\n", + errno == ENOENT ? "No such process" : str_error_r(errno, errbuf, sizeof(errbuf))); + goto out; + } + else + usage_with_options(record_usage, record_options); + } err = auxtrace_record__options(rec->itr, rec->evlist, &rec->opts); if (err) -- cgit v1.2.3 From 5a2f3dc31811e93be15522d9eb13ed61460b76c8 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Fri, 12 Aug 2022 16:19:23 +0200 Subject: netfilter: nf_tables: validate NFTA_SET_ELEM_OBJREF based on NFT_SET_OBJECT flag If the NFTA_SET_ELEM_OBJREF netlink attribute is present and NFT_SET_OBJECT flag is set on, report EINVAL. Move existing sanity check earlier to validate that NFT_SET_OBJECT requires NFTA_SET_ELEM_OBJREF. Fixes: 8aeff920dcc9 ("netfilter: nf_tables: add stateful object reference to set elements") Signed-off-by: Pablo Neira Ayuso --- net/netfilter/nf_tables_api.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index 1b9459a364ba..bcfe8120e014 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -5894,6 +5894,15 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, return -EINVAL; } + if (set->flags & NFT_SET_OBJECT) { + if (!nla[NFTA_SET_ELEM_OBJREF] && + !(flags & NFT_SET_ELEM_INTERVAL_END)) + return -EINVAL; + } else { + if (nla[NFTA_SET_ELEM_OBJREF]) + return -EINVAL; + } + if ((flags & NFT_SET_ELEM_INTERVAL_END) && (nla[NFTA_SET_ELEM_DATA] || nla[NFTA_SET_ELEM_OBJREF] || @@ -6032,10 +6041,6 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, } if (nla[NFTA_SET_ELEM_OBJREF] != NULL) { - if (!(set->flags & NFT_SET_OBJECT)) { - err = -EINVAL; - goto err_parse_key_end; - } obj = nft_obj_lookup(ctx->net, ctx->table, nla[NFTA_SET_ELEM_OBJREF], set->objtype, genmask); -- cgit v1.2.3 From 8f5cb44b1bae8520c0705ce348b30ffb1fdda43a Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Fri, 22 Jul 2022 09:50:47 -0700 Subject: RISC-V: KVM: Support sstc extension Sstc extension allows the guest to program the vstimecmp CSR directly instead of making an SBI call to the hypervisor to program the next event. The timer interrupt is also directly injected to the guest by the hardware in this case. To maintain backward compatibility, the hypervisors also update the vstimecmp in an SBI set_time call if the hardware supports it. Thus, the older kernels in guest also take advantage of the sstc extension. Reviewed-by: Anup Patel Signed-off-by: Atish Patra Acked-by: Anup Patel Link: https://lore.kernel.org/all/CAAhSdy2mb6wyqy0NAn9BcTWKMYEc0Z4zU3s3j7oNqBz6eDQ9sg@mail.gmail.com/ Signed-off-by: Palmer Dabbelt --- arch/riscv/include/asm/kvm_vcpu_timer.h | 7 ++ arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu.c | 8 +- arch/riscv/kvm/vcpu_timer.c | 144 ++++++++++++++++++++++++++++++-- 4 files changed, 153 insertions(+), 7 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_timer.h b/arch/riscv/include/asm/kvm_vcpu_timer.h index 50138e2eb91b..0d8fdb8ec63a 100644 --- a/arch/riscv/include/asm/kvm_vcpu_timer.h +++ b/arch/riscv/include/asm/kvm_vcpu_timer.h @@ -28,6 +28,11 @@ struct kvm_vcpu_timer { u64 next_cycles; /* Underlying hrtimer instance */ struct hrtimer hrt; + + /* Flag to check if sstc is enabled or not */ + bool sstc_enabled; + /* A function pointer to switch between stimecmp or hrtimer at runtime */ + int (*timer_next_event)(struct kvm_vcpu *vcpu, u64 ncycles); }; int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles); @@ -40,5 +45,7 @@ int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu); int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu); void kvm_riscv_guest_timer_init(struct kvm *kvm); +void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu); +bool kvm_riscv_vcpu_timer_pending(struct kvm_vcpu *vcpu); #endif diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 24b2a6e27698..7351417afd62 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -97,6 +97,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_I, KVM_RISCV_ISA_EXT_M, KVM_RISCV_ISA_EXT_SVPBMT, + KVM_RISCV_ISA_EXT_SSTC, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 5d271b597613..d0f08d5b4282 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -52,6 +52,7 @@ static const unsigned long kvm_isa_ext_arr[] = { RISCV_ISA_EXT_i, RISCV_ISA_EXT_m, RISCV_ISA_EXT_SVPBMT, + RISCV_ISA_EXT_SSTC, }; static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext) @@ -85,6 +86,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) case KVM_RISCV_ISA_EXT_C: case KVM_RISCV_ISA_EXT_I: case KVM_RISCV_ISA_EXT_M: + case KVM_RISCV_ISA_EXT_SSTC: return false; default: break; @@ -203,7 +205,7 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) { - return kvm_riscv_vcpu_has_interrupts(vcpu, 1UL << IRQ_VS_TIMER); + return kvm_riscv_vcpu_timer_pending(vcpu); } void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) @@ -785,6 +787,8 @@ static void kvm_riscv_vcpu_update_config(const unsigned long *isa) if (__riscv_isa_extension_available(isa, RISCV_ISA_EXT_SVPBMT)) henvcfg |= ENVCFG_PBMTE; + if (__riscv_isa_extension_available(isa, RISCV_ISA_EXT_SSTC)) + henvcfg |= ENVCFG_STCE; csr_write(CSR_HENVCFG, henvcfg); #ifdef CONFIG_32BIT csr_write(CSR_HENVCFGH, henvcfg >> 32); @@ -828,6 +832,8 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) vcpu->arch.isa); kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context); + kvm_riscv_vcpu_timer_save(vcpu); + csr->vsstatus = csr_read(CSR_VSSTATUS); csr->vsie = csr_read(CSR_VSIE); csr->vstvec = csr_read(CSR_VSTVEC); diff --git a/arch/riscv/kvm/vcpu_timer.c b/arch/riscv/kvm/vcpu_timer.c index 595043857049..16f50c46ba39 100644 --- a/arch/riscv/kvm/vcpu_timer.c +++ b/arch/riscv/kvm/vcpu_timer.c @@ -69,7 +69,18 @@ static int kvm_riscv_vcpu_timer_cancel(struct kvm_vcpu_timer *t) return 0; } -int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles) +static int kvm_riscv_vcpu_update_vstimecmp(struct kvm_vcpu *vcpu, u64 ncycles) +{ +#if defined(CONFIG_32BIT) + csr_write(CSR_VSTIMECMP, ncycles & 0xFFFFFFFF); + csr_write(CSR_VSTIMECMPH, ncycles >> 32); +#else + csr_write(CSR_VSTIMECMP, ncycles); +#endif + return 0; +} + +static int kvm_riscv_vcpu_update_hrtimer(struct kvm_vcpu *vcpu, u64 ncycles) { struct kvm_vcpu_timer *t = &vcpu->arch.timer; struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer; @@ -88,6 +99,65 @@ int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles) return 0; } +int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles) +{ + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + + return t->timer_next_event(vcpu, ncycles); +} + +static enum hrtimer_restart kvm_riscv_vcpu_vstimer_expired(struct hrtimer *h) +{ + u64 delta_ns; + struct kvm_vcpu_timer *t = container_of(h, struct kvm_vcpu_timer, hrt); + struct kvm_vcpu *vcpu = container_of(t, struct kvm_vcpu, arch.timer); + struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer; + + if (kvm_riscv_current_cycles(gt) < t->next_cycles) { + delta_ns = kvm_riscv_delta_cycles2ns(t->next_cycles, gt, t); + hrtimer_forward_now(&t->hrt, ktime_set(0, delta_ns)); + return HRTIMER_RESTART; + } + + t->next_set = false; + kvm_vcpu_kick(vcpu); + + return HRTIMER_NORESTART; +} + +bool kvm_riscv_vcpu_timer_pending(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer; + + if (!kvm_riscv_delta_cycles2ns(t->next_cycles, gt, t) || + kvm_riscv_vcpu_has_interrupts(vcpu, 1UL << IRQ_VS_TIMER)) + return true; + else + return false; +} + +static void kvm_riscv_vcpu_timer_blocking(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer; + u64 delta_ns; + + if (!t->init_done) + return; + + delta_ns = kvm_riscv_delta_cycles2ns(t->next_cycles, gt, t); + if (delta_ns) { + hrtimer_start(&t->hrt, ktime_set(0, delta_ns), HRTIMER_MODE_REL); + t->next_set = true; + } +} + +static void kvm_riscv_vcpu_timer_unblocking(struct kvm_vcpu *vcpu) +{ + kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer); +} + int kvm_riscv_vcpu_get_reg_timer(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) { @@ -180,10 +250,20 @@ int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu) return -EINVAL; hrtimer_init(&t->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL); - t->hrt.function = kvm_riscv_vcpu_hrtimer_expired; t->init_done = true; t->next_set = false; + /* Enable sstc for every vcpu if available in hardware */ + if (riscv_isa_extension_available(NULL, SSTC)) { + t->sstc_enabled = true; + t->hrt.function = kvm_riscv_vcpu_vstimer_expired; + t->timer_next_event = kvm_riscv_vcpu_update_vstimecmp; + } else { + t->sstc_enabled = false; + t->hrt.function = kvm_riscv_vcpu_hrtimer_expired; + t->timer_next_event = kvm_riscv_vcpu_update_hrtimer; + } + return 0; } @@ -199,21 +279,73 @@ int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu) int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu) { + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + + t->next_cycles = -1ULL; return kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer); } -void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu) +static void kvm_riscv_vcpu_update_timedelta(struct kvm_vcpu *vcpu) { struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer; -#ifdef CONFIG_64BIT - csr_write(CSR_HTIMEDELTA, gt->time_delta); -#else +#if defined(CONFIG_32BIT) csr_write(CSR_HTIMEDELTA, (u32)(gt->time_delta)); csr_write(CSR_HTIMEDELTAH, (u32)(gt->time_delta >> 32)); +#else + csr_write(CSR_HTIMEDELTA, gt->time_delta); #endif } +void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_csr *csr; + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + + kvm_riscv_vcpu_update_timedelta(vcpu); + + if (!t->sstc_enabled) + return; + + csr = &vcpu->arch.guest_csr; +#if defined(CONFIG_32BIT) + csr_write(CSR_VSTIMECMP, (u32)t->next_cycles); + csr_write(CSR_VSTIMECMPH, (u32)(t->next_cycles >> 32)); +#else + csr_write(CSR_VSTIMECMP, t->next_cycles); +#endif + + /* timer should be enabled for the remaining operations */ + if (unlikely(!t->init_done)) + return; + + kvm_riscv_vcpu_timer_unblocking(vcpu); +} + +void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_csr *csr; + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + + if (!t->sstc_enabled) + return; + + csr = &vcpu->arch.guest_csr; + t = &vcpu->arch.timer; +#if defined(CONFIG_32BIT) + t->next_cycles = csr_read(CSR_VSTIMECMP); + t->next_cycles |= (u64)csr_read(CSR_VSTIMECMPH) << 32; +#else + t->next_cycles = csr_read(CSR_VSTIMECMP); +#endif + /* timer should be enabled for the remaining operations */ + if (unlikely(!t->init_done)) + return; + + if (kvm_vcpu_is_blocking(vcpu)) + kvm_riscv_vcpu_timer_blocking(vcpu); +} + void kvm_riscv_guest_timer_init(struct kvm *kvm) { struct kvm_guest_timer *gt = &kvm->arch.timer; -- cgit v1.2.3 From 9019b4f6d9bd88524ecd95420cf9cd4aaed7a125 Mon Sep 17 00:00:00 2001 From: "Jason A. Donenfeld" Date: Tue, 9 Aug 2022 16:57:57 +0200 Subject: wireguard: selftests: set CONFIG_NONPORTABLE on riscv32 When the CONFIG_PORTABLE/CONFIG_NONPORTABLE switches were added, various configs were updated, but the wireguard config was forgotten about. This leads to unbootable test kernels, causing CI fails. Add CONFIG_NONPORTABLE=y to the wireguard test suite configuration for riscv32. Fixes: 44c1e84a38a0 ("RISC-V: Add CONFIG_{NON,}PORTABLE") Signed-off-by: Jason A. Donenfeld Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220809145757.83673-1-Jason@zx2c4.com Signed-off-by: Palmer Dabbelt --- tools/testing/selftests/wireguard/qemu/arch/riscv32.config | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/testing/selftests/wireguard/qemu/arch/riscv32.config b/tools/testing/selftests/wireguard/qemu/arch/riscv32.config index 0bd0e72d95d4..2fc36efb166d 100644 --- a/tools/testing/selftests/wireguard/qemu/arch/riscv32.config +++ b/tools/testing/selftests/wireguard/qemu/arch/riscv32.config @@ -1,3 +1,4 @@ +CONFIG_NONPORTABLE=y CONFIG_ARCH_RV32I=y CONFIG_MMU=y CONFIG_FPU=y -- cgit v1.2.3 From 419831617ed349992c84344dbd9e627f9e68f842 Mon Sep 17 00:00:00 2001 From: Przemyslaw Patynowski Date: Tue, 19 Jul 2022 11:16:52 +0200 Subject: iavf: Fix adminq error handling iavf_alloc_asq_bufs/iavf_alloc_arq_bufs allocates with dma_alloc_coherent memory for VF mailbox. Free DMA regions for both ASQ and ARQ in case error happens during configuration of ASQ/ARQ registers. Without this change it is possible to see when unloading interface: 74626.583369: dma_debug_device_change: device driver has pending DMA allocations while released from device [count=32] One of leaked entries details: [device address=0x0000000b27ff9000] [size=4096 bytes] [mapped with DMA_BIDIRECTIONAL] [mapped as coherent] Fixes: d358aa9a7a2d ("i40evf: init code and hardware support") Signed-off-by: Przemyslaw Patynowski Signed-off-by: Jedrzej Jagielski Tested-by: Marek Szlosek Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/iavf/iavf_adminq.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/iavf/iavf_adminq.c b/drivers/net/ethernet/intel/iavf/iavf_adminq.c index cd4e6a22d0f9..9ffbd24d83cb 100644 --- a/drivers/net/ethernet/intel/iavf/iavf_adminq.c +++ b/drivers/net/ethernet/intel/iavf/iavf_adminq.c @@ -324,6 +324,7 @@ static enum iavf_status iavf_config_arq_regs(struct iavf_hw *hw) static enum iavf_status iavf_init_asq(struct iavf_hw *hw) { enum iavf_status ret_code = 0; + int i; if (hw->aq.asq.count > 0) { /* queue already initialized */ @@ -354,12 +355,17 @@ static enum iavf_status iavf_init_asq(struct iavf_hw *hw) /* initialize base registers */ ret_code = iavf_config_asq_regs(hw); if (ret_code) - goto init_adminq_free_rings; + goto init_free_asq_bufs; /* success! */ hw->aq.asq.count = hw->aq.num_asq_entries; goto init_adminq_exit; +init_free_asq_bufs: + for (i = 0; i < hw->aq.num_asq_entries; i++) + iavf_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); + iavf_free_virt_mem(hw, &hw->aq.asq.dma_head); + init_adminq_free_rings: iavf_free_adminq_asq(hw); @@ -383,6 +389,7 @@ init_adminq_exit: static enum iavf_status iavf_init_arq(struct iavf_hw *hw) { enum iavf_status ret_code = 0; + int i; if (hw->aq.arq.count > 0) { /* queue already initialized */ @@ -413,12 +420,16 @@ static enum iavf_status iavf_init_arq(struct iavf_hw *hw) /* initialize base registers */ ret_code = iavf_config_arq_regs(hw); if (ret_code) - goto init_adminq_free_rings; + goto init_free_arq_bufs; /* success! */ hw->aq.arq.count = hw->aq.num_arq_entries; goto init_adminq_exit; +init_free_arq_bufs: + for (i = 0; i < hw->aq.num_arq_entries; i++) + iavf_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); + iavf_free_virt_mem(hw, &hw->aq.arq.dma_head); init_adminq_free_rings: iavf_free_adminq_arq(hw); -- cgit v1.2.3 From 541a1af451b0cb3779e915d48d08efb17915207b Mon Sep 17 00:00:00 2001 From: Przemyslaw Patynowski Date: Tue, 19 Jul 2022 11:16:53 +0200 Subject: iavf: Fix NULL pointer dereference in iavf_get_link_ksettings Fix possible NULL pointer dereference, due to freeing of adapter->vf_res in iavf_init_get_resources. Previous commit introduced a regression, where receiving IAVF_ERR_ADMIN_QUEUE_NO_WORK from iavf_get_vf_config would free adapter->vf_res. However, netdev is still registered, so ethtool_ops can be called. Calling iavf_get_link_ksettings with no vf_res, will result with: [ 9385.242676] BUG: kernel NULL pointer dereference, address: 0000000000000008 [ 9385.242683] #PF: supervisor read access in kernel mode [ 9385.242686] #PF: error_code(0x0000) - not-present page [ 9385.242690] PGD 0 P4D 0 [ 9385.242696] Oops: 0000 [#1] PREEMPT SMP DEBUG_PAGEALLOC PTI [ 9385.242701] CPU: 6 PID: 3217 Comm: pmdalinux Kdump: loaded Tainted: G S E 5.18.0-04958-ga54ce3703613-dirty #1 [ 9385.242708] Hardware name: Dell Inc. PowerEdge R730/0WCJNT, BIOS 2.11.0 11/02/2019 [ 9385.242710] RIP: 0010:iavf_get_link_ksettings+0x29/0xd0 [iavf] [ 9385.242745] Code: 00 0f 1f 44 00 00 b8 01 ef ff ff 48 c7 46 30 00 00 00 00 48 c7 46 38 00 00 00 00 c6 46 0b 00 66 89 46 08 48 8b 87 68 0e 00 00 40 08 80 75 50 8b 87 5c 0e 00 00 83 f8 08 74 7a 76 1d 83 f8 20 [ 9385.242749] RSP: 0018:ffffc0560ec7fbd0 EFLAGS: 00010246 [ 9385.242755] RAX: 0000000000000000 RBX: ffffc0560ec7fc08 RCX: 0000000000000000 [ 9385.242759] RDX: ffffffffc0ad4550 RSI: ffffc0560ec7fc08 RDI: ffffa0fc66674000 [ 9385.242762] RBP: 00007ffd1fb2bf50 R08: b6a2d54b892363ee R09: ffffa101dc14fb00 [ 9385.242765] R10: 0000000000000000 R11: 0000000000000004 R12: ffffa0fc66674000 [ 9385.242768] R13: 0000000000000000 R14: ffffa0fc66674000 R15: 00000000ffffffa1 [ 9385.242771] FS: 00007f93711a2980(0000) GS:ffffa0fad72c0000(0000) knlGS:0000000000000000 [ 9385.242775] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 9385.242778] CR2: 0000000000000008 CR3: 0000000a8e61c003 CR4: 00000000003706e0 [ 9385.242781] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 9385.242784] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 9385.242787] Call Trace: [ 9385.242791] [ 9385.242793] ethtool_get_settings+0x71/0x1a0 [ 9385.242814] __dev_ethtool+0x426/0x2f40 [ 9385.242823] ? slab_post_alloc_hook+0x4f/0x280 [ 9385.242836] ? kmem_cache_alloc_trace+0x15d/0x2f0 [ 9385.242841] ? dev_ethtool+0x59/0x170 [ 9385.242848] dev_ethtool+0xa7/0x170 [ 9385.242856] dev_ioctl+0xc3/0x520 [ 9385.242866] sock_do_ioctl+0xa0/0xe0 [ 9385.242877] sock_ioctl+0x22f/0x320 [ 9385.242885] __x64_sys_ioctl+0x84/0xc0 [ 9385.242896] do_syscall_64+0x3a/0x80 [ 9385.242904] entry_SYSCALL_64_after_hwframe+0x46/0xb0 [ 9385.242918] RIP: 0033:0x7f93702396db [ 9385.242923] Code: 73 01 c3 48 8b 0d ad 57 38 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 7d 57 38 00 f7 d8 64 89 01 48 [ 9385.242927] RSP: 002b:00007ffd1fb2bf18 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 [ 9385.242932] RAX: ffffffffffffffda RBX: 000055671b1d2fe0 RCX: 00007f93702396db [ 9385.242935] RDX: 00007ffd1fb2bf20 RSI: 0000000000008946 RDI: 0000000000000007 [ 9385.242937] RBP: 00007ffd1fb2bf20 R08: 0000000000000003 R09: 0030763066307330 [ 9385.242940] R10: 0000000000000000 R11: 0000000000000246 R12: 00007ffd1fb2bf80 [ 9385.242942] R13: 0000000000000007 R14: 0000556719f6de90 R15: 00007ffd1fb2c1b0 [ 9385.242948] [ 9385.242949] Modules linked in: iavf(E) xt_CHECKSUM xt_MASQUERADE xt_conntrack ipt_REJECT nft_compat nf_nat_tftp nft_objref nf_conntrack_tftp bridge stp llc nft_fib_inet nft_fib_ipv4 nft_fib_ipv6 nft_fib nft_reject_inet nf_reject_ipv4 nf_reject_ipv6 nft_reject nft_ct nft_chain_nat nf_nat nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 ip_set nf_tables rfkill nfnetlink vfat fat irdma ib_uverbs ib_core intel_rapl_msr intel_rapl_common sb_edac x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel kvm iTCO_wdt iTCO_vendor_support ice irqbypass crct10dif_pclmul crc32_pclmul ghash_clmulni_intel rapl i40e pcspkr intel_cstate joydev mei_me intel_uncore mxm_wmi mei ipmi_ssif lpc_ich ipmi_si acpi_power_meter xfs libcrc32c mgag200 i2c_algo_bit drm_shmem_helper drm_kms_helper sd_mod t10_pi crc64_rocksoft crc64 syscopyarea sg sysfillrect sysimgblt fb_sys_fops drm ixgbe ahci libahci libata crc32c_intel mdio dca wmi dm_mirror dm_region_hash dm_log dm_mod ipmi_devintf ipmi_msghandler fuse [ 9385.243065] [last unloaded: iavf] Dereference happens in if (ADV_LINK_SUPPORT(adapter)) statement Fixes: 209f2f9c7181 ("iavf: Add support for VIRTCHNL_VF_OFFLOAD_VLAN_V2 negotiation") Signed-off-by: Przemyslaw Patynowski Signed-off-by: Jedrzej Jagielski Tested-by: Marek Szlosek Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/iavf/iavf_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/iavf/iavf_main.c b/drivers/net/ethernet/intel/iavf/iavf_main.c index 45d097a164ad..6aa3eff0da2c 100644 --- a/drivers/net/ethernet/intel/iavf/iavf_main.c +++ b/drivers/net/ethernet/intel/iavf/iavf_main.c @@ -2367,7 +2367,7 @@ static void iavf_init_get_resources(struct iavf_adapter *adapter) err = iavf_get_vf_config(adapter); if (err == -EALREADY) { err = iavf_send_vf_config_msg(adapter); - goto err_alloc; + goto err; } else if (err == -EINVAL) { /* We only get -EINVAL if the device is in a very bad * state or if we've been disabled for previous bad -- cgit v1.2.3 From 31071173771e079f7bc08dacd61e0db913262fbf Mon Sep 17 00:00:00 2001 From: Przemyslaw Patynowski Date: Tue, 19 Jul 2022 11:16:54 +0200 Subject: iavf: Fix reset error handling Do not call iavf_close in iavf_reset_task error handling. Doing so can lead to double call of napi_disable, which can lead to deadlock there. Removing VF would lead to iavf_remove task being stuck, because it requires crit_lock, which is held by iavf_close. Call iavf_disable_vf if reset fail, so that driver will clean up remaining invalid resources. During rapid VF resets, HW can fail to setup VF mailbox. Wrong error handling can lead to iavf_remove being stuck with: [ 5218.999087] iavf 0000:82:01.0: Failed to init adminq: -53 ... [ 5267.189211] INFO: task repro.sh:11219 blocked for more than 30 seconds. [ 5267.189520] Tainted: G S E 5.18.0-04958-ga54ce3703613-dirty #1 [ 5267.189764] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [ 5267.190062] task:repro.sh state:D stack: 0 pid:11219 ppid: 8162 flags:0x00000000 [ 5267.190347] Call Trace: [ 5267.190647] [ 5267.190927] __schedule+0x460/0x9f0 [ 5267.191264] schedule+0x44/0xb0 [ 5267.191563] schedule_preempt_disabled+0x14/0x20 [ 5267.191890] __mutex_lock.isra.12+0x6e3/0xac0 [ 5267.192237] ? iavf_remove+0xf9/0x6c0 [iavf] [ 5267.192565] iavf_remove+0x12a/0x6c0 [iavf] [ 5267.192911] ? _raw_spin_unlock_irqrestore+0x1e/0x40 [ 5267.193285] pci_device_remove+0x36/0xb0 [ 5267.193619] device_release_driver_internal+0xc1/0x150 [ 5267.193974] pci_stop_bus_device+0x69/0x90 [ 5267.194361] pci_stop_and_remove_bus_device+0xe/0x20 [ 5267.194735] pci_iov_remove_virtfn+0xba/0x120 [ 5267.195130] sriov_disable+0x2f/0xe0 [ 5267.195506] ice_free_vfs+0x7d/0x2f0 [ice] [ 5267.196056] ? pci_get_device+0x4f/0x70 [ 5267.196496] ice_sriov_configure+0x78/0x1a0 [ice] [ 5267.196995] sriov_numvfs_store+0xfe/0x140 [ 5267.197466] kernfs_fop_write_iter+0x12e/0x1c0 [ 5267.197918] new_sync_write+0x10c/0x190 [ 5267.198404] vfs_write+0x24e/0x2d0 [ 5267.198886] ksys_write+0x5c/0xd0 [ 5267.199367] do_syscall_64+0x3a/0x80 [ 5267.199827] entry_SYSCALL_64_after_hwframe+0x46/0xb0 [ 5267.200317] RIP: 0033:0x7f5b381205c8 [ 5267.200814] RSP: 002b:00007fff8c7e8c78 EFLAGS: 00000246 ORIG_RAX: 0000000000000001 [ 5267.201981] RAX: ffffffffffffffda RBX: 0000000000000002 RCX: 00007f5b381205c8 [ 5267.202620] RDX: 0000000000000002 RSI: 00005569420ee900 RDI: 0000000000000001 [ 5267.203426] RBP: 00005569420ee900 R08: 000000000000000a R09: 00007f5b38180820 [ 5267.204327] R10: 000000000000000a R11: 0000000000000246 R12: 00007f5b383c06e0 [ 5267.205193] R13: 0000000000000002 R14: 00007f5b383bb880 R15: 0000000000000002 [ 5267.206041] [ 5267.206970] Kernel panic - not syncing: hung_task: blocked tasks [ 5267.207809] CPU: 48 PID: 551 Comm: khungtaskd Kdump: loaded Tainted: G S E 5.18.0-04958-ga54ce3703613-dirty #1 [ 5267.208726] Hardware name: Dell Inc. PowerEdge R730/0WCJNT, BIOS 2.11.0 11/02/2019 [ 5267.209623] Call Trace: [ 5267.210569] [ 5267.211480] dump_stack_lvl+0x33/0x42 [ 5267.212472] panic+0x107/0x294 [ 5267.213467] watchdog.cold.8+0xc/0xbb [ 5267.214413] ? proc_dohung_task_timeout_secs+0x30/0x30 [ 5267.215511] kthread+0xf4/0x120 [ 5267.216459] ? kthread_complete_and_exit+0x20/0x20 [ 5267.217505] ret_from_fork+0x22/0x30 [ 5267.218459] Fixes: f0db78928783 ("i40evf: use netdev variable in reset task") Signed-off-by: Przemyslaw Patynowski Signed-off-by: Jedrzej Jagielski Tested-by: Marek Szlosek Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/iavf/iavf_main.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/intel/iavf/iavf_main.c b/drivers/net/ethernet/intel/iavf/iavf_main.c index 6aa3eff0da2c..95d4348e7579 100644 --- a/drivers/net/ethernet/intel/iavf/iavf_main.c +++ b/drivers/net/ethernet/intel/iavf/iavf_main.c @@ -3086,12 +3086,15 @@ continue_reset: return; reset_err: + if (running) { + set_bit(__IAVF_VSI_DOWN, adapter->vsi.state); + iavf_free_traffic_irqs(adapter); + } + iavf_disable_vf(adapter); + mutex_unlock(&adapter->client_lock); mutex_unlock(&adapter->crit_lock); - if (running) - iavf_change_state(adapter, __IAVF_RUNNING); dev_err(&adapter->pdev->dev, "failed to allocate resources during reinit\n"); - iavf_close(netdev); } /** -- cgit v1.2.3 From cbe9e51126305832cf407ee6bb556ce831488ffe Mon Sep 17 00:00:00 2001 From: Ivan Vecera Date: Mon, 8 Aug 2022 19:58:45 +0200 Subject: iavf: Fix deadlock in initialization Fix deadlock that occurs when iavf interface is a part of failover configuration. 1. Mutex crit_lock is taken at the beginning of iavf_watchdog_task() 2. Function iavf_init_config_adapter() is called when adapter state is __IAVF_INIT_CONFIG_ADAPTER 3. iavf_init_config_adapter() calls register_netdevice() that emits NETDEV_REGISTER event 4. Notifier function failover_event() then calls net_failover_slave_register() that calls dev_open() 5. dev_open() calls iavf_open() that tries to take crit_lock in end-less loop Stack trace: ... [ 790.251876] usleep_range_state+0x5b/0x80 [ 790.252547] iavf_open+0x37/0x1d0 [iavf] [ 790.253139] __dev_open+0xcd/0x160 [ 790.253699] dev_open+0x47/0x90 [ 790.254323] net_failover_slave_register+0x122/0x220 [net_failover] [ 790.255213] failover_slave_register.part.7+0xd2/0x180 [failover] [ 790.256050] failover_event+0x122/0x1ab [failover] [ 790.256821] notifier_call_chain+0x47/0x70 [ 790.257510] register_netdevice+0x20f/0x550 [ 790.258263] iavf_watchdog_task+0x7c8/0xea0 [iavf] [ 790.259009] process_one_work+0x1a7/0x360 [ 790.259705] worker_thread+0x30/0x390 To fix the situation we should check the current adapter state after first unsuccessful mutex_trylock() and return with -EBUSY if it is __IAVF_INIT_CONFIG_ADAPTER. Fixes: 226d528512cf ("iavf: fix locking of critical sections") Signed-off-by: Ivan Vecera Tested-by: Konrad Jankowski Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/iavf/iavf_main.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/iavf/iavf_main.c b/drivers/net/ethernet/intel/iavf/iavf_main.c index 95d4348e7579..f39440ad5c50 100644 --- a/drivers/net/ethernet/intel/iavf/iavf_main.c +++ b/drivers/net/ethernet/intel/iavf/iavf_main.c @@ -4088,8 +4088,17 @@ static int iavf_open(struct net_device *netdev) return -EIO; } - while (!mutex_trylock(&adapter->crit_lock)) + while (!mutex_trylock(&adapter->crit_lock)) { + /* If we are in __IAVF_INIT_CONFIG_ADAPTER state the crit_lock + * is already taken and iavf_open is called from an upper + * device's notifier reacting on NETDEV_REGISTER event. + * We have to leave here to avoid dead lock. + */ + if (adapter->state == __IAVF_INIT_CONFIG_ADAPTER) + return -EBUSY; + usleep_range(500, 1000); + } if (adapter->state != __IAVF_DOWN) { err = -EBUSY; -- cgit v1.2.3 From 5cef38dd03f33ef206eb792df0fb3b200d762546 Mon Sep 17 00:00:00 2001 From: Atul Khare Date: Wed, 3 Aug 2022 16:55:40 +0100 Subject: dt-bindings: gpio: sifive: add gpio-line-names Fix device tree schema validation messages like 'gpio-line-names' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: ... sifive,gpio.yaml'. The bindings were missing the gpio-line-names element, which was causing the dt-schema checker to trip-up. Acked-by: Rob Herring Signed-off-by: Atul Khare Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20220803155539.800766-1-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- Documentation/devicetree/bindings/gpio/sifive,gpio.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml index 939e31c48081..fc095646adea 100644 --- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml @@ -46,6 +46,10 @@ properties: maximum: 32 default: 16 + gpio-line-names: + minItems: 1 + maxItems: 32 + gpio-controller: true required: -- cgit v1.2.3 From f75f5d58099ffe0a70ae96dfeb837b5c46399da3 Mon Sep 17 00:00:00 2001 From: Yury Norov Date: Thu, 11 Aug 2022 22:55:05 -0700 Subject: lib: remove lib/nodemask.c Commit 36d4b36b6959 ("lib/nodemask: inline next_node_in() and node_random()") removed the lib/nodemask.c file, but the remove didn't happen when the patch was applied. Reported-by: "Aneesh Kumar K.V" Signed-off-by: Yury Norov Signed-off-by: Linus Torvalds --- lib/nodemask.c | 23 ----------------------- 1 file changed, 23 deletions(-) delete mode 100644 lib/nodemask.c diff --git a/lib/nodemask.c b/lib/nodemask.c deleted file mode 100644 index b8a433d16b51..000000000000 --- a/lib/nodemask.c +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include - -EXPORT_SYMBOL(__next_node_in); - -#ifdef CONFIG_NUMA -/* - * Return the bit number of a random bit set in the nodemask. - * (returns NUMA_NO_NODE if nodemask is empty) - */ -int node_random(const nodemask_t *maskp) -{ - int w, bit = NUMA_NO_NODE; - - w = nodes_weight(*maskp); - if (w) - bit = bitmap_ord_to_pos(maskp->bits, - get_random_int() % w, MAX_NUMNODES); - return bit; -} -#endif -- cgit v1.2.3 From dc72768ebf84b87fd26ad97dd3422c3783157a4a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 9 Aug 2022 19:27:48 +0300 Subject: dt-bindings: iio: Drop Joachim Eastwood Emails to Joachim Eastwood bounce ("552 5.2.2 The email account that you tried to reach is over quota and inactive."). Signed-off-by: Krzysztof Kozlowski Acked-by: Jonathan Cameron Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20220809162752.10186-2-krzysztof.kozlowski@linaro.org --- Documentation/devicetree/bindings/iio/accel/fsl,mma7455.yaml | 1 - Documentation/devicetree/bindings/iio/adc/nxp,lpc1850-adc.yaml | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/accel/fsl,mma7455.yaml b/Documentation/devicetree/bindings/iio/accel/fsl,mma7455.yaml index 7c8f8bdc2333..9c7c66feeffc 100644 --- a/Documentation/devicetree/bindings/iio/accel/fsl,mma7455.yaml +++ b/Documentation/devicetree/bindings/iio/accel/fsl,mma7455.yaml @@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale MMA7455 and MMA7456 three axis accelerometers maintainers: - - Joachim Eastwood - Jonathan Cameron description: diff --git a/Documentation/devicetree/bindings/iio/adc/nxp,lpc1850-adc.yaml b/Documentation/devicetree/bindings/iio/adc/nxp,lpc1850-adc.yaml index 6404fb73f8ed..43abb300fa3d 100644 --- a/Documentation/devicetree/bindings/iio/adc/nxp,lpc1850-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/nxp,lpc1850-adc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: NXP LPC1850 ADC bindings maintainers: - - Joachim Eastwood + - Jonathan Cameron description: Supports the ADC found on the LPC1850 SoC. -- cgit v1.2.3 From 691b0d55199927d429d1d951eb90b0c4dd45a7f4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 9 Aug 2022 19:27:49 +0300 Subject: dt-bindings: iio: Drop Bogdan Pricop Emails to Bogdan Pricop bounce ("550 5.4.1 Recipient address rejected: Access denied. AS(201806281)"). Signed-off-by: Krzysztof Kozlowski Acked-by: Jonathan Cameron Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20220809162752.10186-3-krzysztof.kozlowski@linaro.org --- Documentation/devicetree/bindings/iio/adc/ti,adc108s102.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iio/adc/ti,adc108s102.yaml b/Documentation/devicetree/bindings/iio/adc/ti,adc108s102.yaml index 54955f03df93..ae5ce60987fe 100644 --- a/Documentation/devicetree/bindings/iio/adc/ti,adc108s102.yaml +++ b/Documentation/devicetree/bindings/iio/adc/ti,adc108s102.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Texas Instruments ADC108S102 and ADC128S102 maintainers: - - Bogdan Pricop + - Jonathan Cameron description: | Family of 8 channel, 10/12 bit, SPI, single ended ADCs. -- cgit v1.2.3 From 2e645db3bca713f964b1064177b4b9b4b06289cd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 9 Aug 2022 19:27:50 +0300 Subject: dt-bindings: Drop Beniamin Bia and Stefan Popa Emails to Beniamin Bia and Stefan Popa bounce ("550 5.1.10 RESOLVER.ADR.RecipientNotFound; Recipient not found by SMTP address lookup"). Signed-off-by: Krzysztof Kozlowski Acked-by: Jonathan Cameron Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20220809162752.10186-4-krzysztof.kozlowski@linaro.org --- Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml | 1 - Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml | 2 +- Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml | 3 +-- Documentation/devicetree/bindings/iio/amplifiers/adi,hmc425a.yaml | 1 - 4 files changed, 2 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml b/Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml index 154bee851139..d794deb08bb7 100644 --- a/Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml +++ b/Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml @@ -8,7 +8,6 @@ title: Analog Devices ADM1177 Hot Swap Controller and Digital Power Monitor maintainers: - Michael Hennerich - - Beniamin Bia description: | Analog Devices ADM1177 Hot Swap Controller and Digital Power Monitor diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml index 31ffa275f5fa..b97559f23b3a 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analog Devices AD7091R5 4-Channel 12-Bit ADC maintainers: - - Beniamin Bia + - Michael Hennerich description: | Analog Devices AD7091R5 4-Channel 12-Bit ADC diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml index 73775174cf57..516fc24d3346 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analog Devices AD7606 Simultaneous Sampling ADC maintainers: - - Beniamin Bia - - Stefan Popa + - Michael Hennerich description: | Analog Devices AD7606 Simultaneous Sampling ADC diff --git a/Documentation/devicetree/bindings/iio/amplifiers/adi,hmc425a.yaml b/Documentation/devicetree/bindings/iio/amplifiers/adi,hmc425a.yaml index a557761d8016..9fda56fa49c3 100644 --- a/Documentation/devicetree/bindings/iio/amplifiers/adi,hmc425a.yaml +++ b/Documentation/devicetree/bindings/iio/amplifiers/adi,hmc425a.yaml @@ -8,7 +8,6 @@ title: HMC425A 6-bit Digital Step Attenuator maintainers: - Michael Hennerich - - Beniamin Bia description: | Digital Step Attenuator IIO device with gpio interface. -- cgit v1.2.3 From 3156c50fdaab41ec4f6e03c1e603703b9985bf48 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 9 Aug 2022 19:27:51 +0300 Subject: dt-bindings: Drop Robert Jones Emails to Robert Jones bounce ("550 5.2.1 The email account that you tried to reach is disabled"). Signed-off-by: Krzysztof Kozlowski Acked-by: Jonathan Cameron Acked-by: Lee Jones Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20220809162752.10186-5-krzysztof.kozlowski@linaro.org --- Documentation/devicetree/bindings/iio/imu/nxp,fxos8700.yaml | 2 +- Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/imu/nxp,fxos8700.yaml b/Documentation/devicetree/bindings/iio/imu/nxp,fxos8700.yaml index 479e7065d4eb..0203b83b8587 100644 --- a/Documentation/devicetree/bindings/iio/imu/nxp,fxos8700.yaml +++ b/Documentation/devicetree/bindings/iio/imu/nxp,fxos8700.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale FXOS8700 Inertial Measurement Unit maintainers: - - Robert Jones + - Jonathan Cameron description: | Accelerometer and magnetometer combo device with an i2c and SPI interface. diff --git a/Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml b/Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml index 5a1e8d21f7a0..5e0fe3ebe1d2 100644 --- a/Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml +++ b/Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml @@ -19,7 +19,6 @@ description: | maintainers: - Tim Harvey - - Robert Jones properties: $nodename: -- cgit v1.2.3 From 07d1caa4c2ccd28ade90f16d1967015214db40b7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 9 Aug 2022 19:27:52 +0300 Subject: dt-bindings: Drop Dan Murphy and Ricardo Rivera-Matos Emails to Dan Murphy and Ricardo Rivera-Matos bounce ("550 Invalid recipient"). Andrew Davis agreed to take over the bindings. Signed-off-by: Krzysztof Kozlowski Acked-by: Mark Brown Acked-by: Andrew Davis Acked-by: Jonathan Cameron Acked-by: Sebastian Reichel Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20220809162752.10186-6-krzysztof.kozlowski@linaro.org --- Documentation/devicetree/bindings/iio/adc/ti,ads124s08.yaml | 2 +- Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml | 2 +- Documentation/devicetree/bindings/leds/leds-lp50xx.yaml | 2 +- Documentation/devicetree/bindings/net/ti,dp83822.yaml | 2 +- Documentation/devicetree/bindings/net/ti,dp83867.yaml | 2 +- Documentation/devicetree/bindings/net/ti,dp83869.yaml | 2 +- Documentation/devicetree/bindings/power/supply/bq2515x.yaml | 3 +-- Documentation/devicetree/bindings/power/supply/bq256xx.yaml | 2 +- Documentation/devicetree/bindings/power/supply/bq25980.yaml | 3 +-- Documentation/devicetree/bindings/sound/tas2562.yaml | 2 +- Documentation/devicetree/bindings/sound/tlv320adcx140.yaml | 2 +- 11 files changed, 11 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/ti,ads124s08.yaml b/Documentation/devicetree/bindings/iio/adc/ti,ads124s08.yaml index 9f5e96439c01..2e6abc9d746a 100644 --- a/Documentation/devicetree/bindings/iio/adc/ti,ads124s08.yaml +++ b/Documentation/devicetree/bindings/iio/adc/ti,ads124s08.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Texas Instruments' ads124s08 and ads124s06 ADC chip maintainers: - - Dan Murphy + - Andrew Davis properties: compatible: diff --git a/Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml b/Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml index 12693483231f..31840e33dcf5 100644 --- a/Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml +++ b/Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Common properties for the multicolor LED class. maintainers: - - Dan Murphy + - Andrew Davis description: | Bindings for multi color LEDs show how to describe current outputs of diff --git a/Documentation/devicetree/bindings/leds/leds-lp50xx.yaml b/Documentation/devicetree/bindings/leds/leds-lp50xx.yaml index e0b658f07973..63da380748bf 100644 --- a/Documentation/devicetree/bindings/leds/leds-lp50xx.yaml +++ b/Documentation/devicetree/bindings/leds/leds-lp50xx.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: LED driver for LP50XX RGB LED from Texas Instruments. maintainers: - - Dan Murphy + - Andrew Davis description: | The LP50XX is multi-channel, I2C RGB LED Drivers that can group RGB LEDs into diff --git a/Documentation/devicetree/bindings/net/ti,dp83822.yaml b/Documentation/devicetree/bindings/net/ti,dp83822.yaml index 75e8712e903a..f2489a9c852f 100644 --- a/Documentation/devicetree/bindings/net/ti,dp83822.yaml +++ b/Documentation/devicetree/bindings/net/ti,dp83822.yaml @@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: TI DP83822 ethernet PHY maintainers: - - Dan Murphy + - Andrew Davis description: | The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It diff --git a/Documentation/devicetree/bindings/net/ti,dp83867.yaml b/Documentation/devicetree/bindings/net/ti,dp83867.yaml index 76ff08a477ba..b8c0e4b5b494 100644 --- a/Documentation/devicetree/bindings/net/ti,dp83867.yaml +++ b/Documentation/devicetree/bindings/net/ti,dp83867.yaml @@ -11,7 +11,7 @@ allOf: - $ref: "ethernet-controller.yaml#" maintainers: - - Dan Murphy + - Andrew Davis description: | The DP83867 device is a robust, low power, fully featured Physical Layer diff --git a/Documentation/devicetree/bindings/net/ti,dp83869.yaml b/Documentation/devicetree/bindings/net/ti,dp83869.yaml index 1b780dce61ab..b04ff0014a59 100644 --- a/Documentation/devicetree/bindings/net/ti,dp83869.yaml +++ b/Documentation/devicetree/bindings/net/ti,dp83869.yaml @@ -11,7 +11,7 @@ allOf: - $ref: "ethernet-phy.yaml#" maintainers: - - Dan Murphy + - Andrew Davis description: | The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver diff --git a/Documentation/devicetree/bindings/power/supply/bq2515x.yaml b/Documentation/devicetree/bindings/power/supply/bq2515x.yaml index 27db38577822..1a1b240034ef 100644 --- a/Documentation/devicetree/bindings/power/supply/bq2515x.yaml +++ b/Documentation/devicetree/bindings/power/supply/bq2515x.yaml @@ -8,8 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: TI bq2515x 500-mA Linear charger family maintainers: - - Dan Murphy - - Ricardo Rivera-Matos + - Andrew Davis description: | The BQ2515x family is a highly integrated battery charge management IC that diff --git a/Documentation/devicetree/bindings/power/supply/bq256xx.yaml b/Documentation/devicetree/bindings/power/supply/bq256xx.yaml index 91abe5733c41..82f382a7ffb3 100644 --- a/Documentation/devicetree/bindings/power/supply/bq256xx.yaml +++ b/Documentation/devicetree/bindings/power/supply/bq256xx.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: TI bq256xx Switch Mode Buck Charger maintainers: - - Ricardo Rivera-Matos + - Andrew Davis description: | The bq256xx devices are a family of highly-integrated battery charge diff --git a/Documentation/devicetree/bindings/power/supply/bq25980.yaml b/Documentation/devicetree/bindings/power/supply/bq25980.yaml index 4883527ab5c7..b687b8bcd705 100644 --- a/Documentation/devicetree/bindings/power/supply/bq25980.yaml +++ b/Documentation/devicetree/bindings/power/supply/bq25980.yaml @@ -8,8 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: TI BQ25980 Flash Charger maintainers: - - Dan Murphy - - Ricardo Rivera-Matos + - Andrew Davis description: | The BQ25980, BQ25975, and BQ25960 are a series of flash chargers intended diff --git a/Documentation/devicetree/bindings/sound/tas2562.yaml b/Documentation/devicetree/bindings/sound/tas2562.yaml index 5f7dd5d6cbca..30f6b029ac08 100644 --- a/Documentation/devicetree/bindings/sound/tas2562.yaml +++ b/Documentation/devicetree/bindings/sound/tas2562.yaml @@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: Texas Instruments TAS2562 Smart PA maintainers: - - Dan Murphy + - Andrew Davis description: | The TAS2562 is a mono, digital input Class-D audio amplifier optimized for diff --git a/Documentation/devicetree/bindings/sound/tlv320adcx140.yaml b/Documentation/devicetree/bindings/sound/tlv320adcx140.yaml index bc2fb1a80ed7..ee698614862e 100644 --- a/Documentation/devicetree/bindings/sound/tlv320adcx140.yaml +++ b/Documentation/devicetree/bindings/sound/tlv320adcx140.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter maintainers: - - Dan Murphy + - Andrew Davis description: | The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital -- cgit v1.2.3 From 8f426582e0e0c9bbd58e170e1b209334eb5df79e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 11 Aug 2022 09:22:45 +0300 Subject: dt-bindings: chrome: google,cros-ec-typec: restrict allowed properties Describe exactly what properties are allowed in Google Chrome OS EC Type C port, so the schema can properly validate the DTS. Existing DTS defines always connectors with unit addresses, not a sole "connector" child. Signed-off-by: Krzysztof Kozlowski Acked-by: Prashant Malani Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20220811062245.4316-1-krzysztof.kozlowski@linaro.org --- .../devicetree/bindings/chrome/google,cros-ec-typec.yaml | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml b/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml index 2d98f7c4d3bc..50ebd8c57795 100644 --- a/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml +++ b/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml @@ -20,13 +20,24 @@ properties: compatible: const: google,cros-ec-typec - connector: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + '^connector@[0-9a-f]+$': $ref: /schemas/connector/usb-connector.yaml# + unevaluatedProperties: false + properties: + reg: + maxItems: 1 required: - compatible -additionalProperties: true #fixme +additionalProperties: false examples: - |+ -- cgit v1.2.3 From f3c96bec7c6344ab30d6f01b97e3eba0b2fe4fd9 Mon Sep 17 00:00:00 2001 From: shaomin Deng Date: Sun, 7 Aug 2022 03:47:53 -0400 Subject: perf test: Fix double word in comments Delete the redundant word "then" in comments. Signed-off-by: shaomin Deng Cc: Peter Zijlstra Link: http://lore.kernel.org/lkml/20220807074753.7857-1-dengshaomin@cdjrlc.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/perf-time-to-tsc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/tests/perf-time-to-tsc.c b/tools/perf/tests/perf-time-to-tsc.c index 26ce30a35191..c3aaa1ddff29 100644 --- a/tools/perf/tests/perf-time-to-tsc.c +++ b/tools/perf/tests/perf-time-to-tsc.c @@ -62,7 +62,7 @@ static int test__tsc_is_supported(struct test_suite *test __maybe_unused, * This function implements a test that checks that the conversion of perf time * to and from TSC is consistent with the order of events. If the test passes * %0 is returned, otherwise %-1 is returned. If TSC conversion is not - * supported then then the test passes but " (not supported)" is printed. + * supported then the test passes but " (not supported)" is printed. */ static int test__perf_time_to_tsc(struct test_suite *test __maybe_unused, int subtest __maybe_unused) { -- cgit v1.2.3 From ae4e4a0ba30aa3978ac17a919b2ff7b073faa2f3 Mon Sep 17 00:00:00 2001 From: shaomin Deng Date: Sun, 7 Aug 2022 04:06:42 -0400 Subject: perf script: Delete repeated word "from" Delete the repeated word "from" in code. Signed-off-by: shaomin Deng Cc: Peter Zijlstra Link: http://lore.kernel.org/lkml/20220807080642.13004-1-dengshaomin@cdjrlc.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-script.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index ac19fee62d8e..13580a9c50b8 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -3861,7 +3861,7 @@ int cmd_script(int argc, const char **argv) OPT_CALLBACK_OPTARG(0, "xed", NULL, NULL, NULL, "Run xed disassembler on output", parse_xed), OPT_CALLBACK_OPTARG(0, "call-trace", &itrace_synth_opts, NULL, NULL, - "Decode calls from from itrace", parse_call_trace), + "Decode calls from itrace", parse_call_trace), OPT_CALLBACK_OPTARG(0, "call-ret-trace", &itrace_synth_opts, NULL, NULL, "Decode calls and returns from itrace", parse_callret_trace), OPT_STRING(0, "graph-function", &symbol_conf.graph_function, "symbol[,symbol...]", -- cgit v1.2.3 From 632f5c224e95ce6846724a0720f7e7ef704fb858 Mon Sep 17 00:00:00 2001 From: shaomin Deng Date: Sun, 7 Aug 2022 04:46:29 -0400 Subject: perf trace: Fix double word in comments Delete repeated word "and" in comments. Signed-off-by: shaomin Deng Cc: Mark Rutland Cc: Peter Zijlstra Link: http://lore.kernel.org/lkml/20220807084629.23121-1-dengshaomin@cdjrlc.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-trace.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/builtin-trace.c b/tools/perf/builtin-trace.c index 1e1f10a1971d..0bd9d01c0df9 100644 --- a/tools/perf/builtin-trace.c +++ b/tools/perf/builtin-trace.c @@ -2749,7 +2749,7 @@ static size_t trace__fprintf_tp_fields(struct trace *trace, struct evsel *evsel, /* * Suppress this argument if its value is zero and - * and we don't have a string associated in an + * we don't have a string associated in an * strarray for it. */ if (val == 0 && -- cgit v1.2.3 From 987f5cbd2f3f3300c3f681130b5c67661efa53a5 Mon Sep 17 00:00:00 2001 From: shaomin Deng Date: Sun, 7 Aug 2022 11:55:49 -0400 Subject: perf tools: Fix double word in comments Delete the repeated word "to" in comments. Signed-off-by: shaomin Deng Cc: Mark Rutland Cc: Peter Zijlstra Link: http://lore.kernel.org/lkml/20220807155549.30953-1-dengshaomin@cdjrlc.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/events_stats.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/util/events_stats.h b/tools/perf/util/events_stats.h index 1b0006092265..040ab9d0a803 100644 --- a/tools/perf/util/events_stats.h +++ b/tools/perf/util/events_stats.h @@ -22,7 +22,7 @@ * * The total_period is needed because by default auto-freq is used, so * multiplying nr_events[PERF_EVENT_SAMPLE] by a frequency isn't possible to get - * the total number of low level events, it is necessary to to sum all struct + * the total number of low level events, it is necessary to sum all struct * perf_record_sample.period and stash the result in total_period. */ struct events_stats { -- cgit v1.2.3 From 0029e8ace159216d668f9ae6d3892cfebde848c6 Mon Sep 17 00:00:00 2001 From: shaomin Deng Date: Sun, 7 Aug 2022 12:02:39 -0400 Subject: perf scripting python: Delete repeated word in comments Delete the repeated word "into" in comments. Signed-off-by: shaomin Deng Cc: Alexander Shishkin Cc: Mark Rutland Cc: Peter Zijlstra Link: http://lore.kernel.org/lkml/20220807160239.474-1-dengshaomin@cdjrlc.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/scripting-engines/trace-event-python.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/util/scripting-engines/trace-event-python.c b/tools/perf/util/scripting-engines/trace-event-python.c index 5bbc1b16f368..9ef2406e0ede 100644 --- a/tools/perf/util/scripting-engines/trace-event-python.c +++ b/tools/perf/util/scripting-engines/trace-event-python.c @@ -131,7 +131,7 @@ static void handler_call_die(const char *handler_name) } /* - * Insert val into into the dictionary and decrement the reference counter. + * Insert val into the dictionary and decrement the reference counter. * This is necessary for dictionaries since PyDict_SetItemString() does not * steal a reference, as opposed to PyTuple_SetItem(). */ -- cgit v1.2.3 From 8d33834f9fb06b5349b145e6499aca976deed3d8 Mon Sep 17 00:00:00 2001 From: Yang Li Date: Thu, 4 Aug 2022 08:52:13 +0800 Subject: perf stat: Remove duplicated include in builtin-stat.c util/topdown.h is included twice in builtin-stat.c, remove one of them. Reported-by: Abaci Robot Signed-off-by: Yang Li Tested-by: Ian Rogers Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1818 Link: https://lore.kernel.org/r/20220804005213.71990-1-yang.lee@linux.alibaba.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-stat.c | 1 - 1 file changed, 1 deletion(-) diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index 0d9fec377071..7fb81a44672d 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -71,7 +71,6 @@ #include "util/bpf_counter.h" #include "util/iostat.h" #include "util/pmu-hybrid.h" - #include "util/topdown.h" #include "asm/bug.h" #include -- cgit v1.2.3 From e4fe2a2fc423cb51bfd36c14f95f3ca1d279ca92 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Fri, 12 Aug 2022 15:42:05 -0400 Subject: MAINTAINERS: add PCI Endpoint NTB drivers to NTB files The PCI Endpoint NTB drivers are under the NTB umbrella. Add an entry there to allow for notification of changes for it. Signed-off-by: Jon Mason Acked-by: Bjorn Helgaas --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 64379c699903..47e9f86bd712 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14254,6 +14254,7 @@ W: https://github.com/jonmason/ntb/wiki T: git git://github.com/jonmason/ntb.git F: drivers/net/ntb_netdev.c F: drivers/ntb/ +F: drivers/pci/endpoint/functions/pci-epf-*ntb.c F: include/linux/ntb.h F: include/linux/ntb_transport.h F: tools/testing/selftests/ntb/ -- cgit v1.2.3 From 7eb59a98701d3113671b513593bb489cc76f58d2 Mon Sep 17 00:00:00 2001 From: Ronnie Sahlberg Date: Thu, 11 Aug 2022 19:51:18 -0500 Subject: cifs: Do not access tcon->cfids->cfid directly from is_path_accessible cfids will soon keep a list of cached fids so we should not access this directly from outside of cached_dir.c Reviewed-by: Paulo Alcantara (SUSE) Signed-off-by: Ronnie Sahlberg Signed-off-by: Steve French --- fs/cifs/cached_dir.c | 10 ++++++---- fs/cifs/cached_dir.h | 2 +- fs/cifs/readdir.c | 4 ++-- fs/cifs/smb2inode.c | 2 +- fs/cifs/smb2ops.c | 19 +++++++++++++++---- 5 files changed, 25 insertions(+), 12 deletions(-) diff --git a/fs/cifs/cached_dir.c b/fs/cifs/cached_dir.c index 78e8deb82a0a..b401339f6e73 100644 --- a/fs/cifs/cached_dir.c +++ b/fs/cifs/cached_dir.c @@ -16,9 +16,9 @@ * If error then *cfid is not initialized. */ int open_cached_dir(unsigned int xid, struct cifs_tcon *tcon, - const char *path, - struct cifs_sb_info *cifs_sb, - struct cached_fid **ret_cfid) + const char *path, + struct cifs_sb_info *cifs_sb, + bool lookup_only, struct cached_fid **ret_cfid) { struct cifs_ses *ses; struct TCP_Server_Info *server; @@ -68,9 +68,11 @@ int open_cached_dir(unsigned int xid, struct cifs_tcon *tcon, * cifs_mark_open_files_invalid() which takes the lock again * thus causing a deadlock */ - mutex_unlock(&cfid->fid_mutex); + if (lookup_only) + return -ENOENT; + if (smb3_encryption_required(tcon)) flags |= CIFS_TRANSFORM_REQ; diff --git a/fs/cifs/cached_dir.h b/fs/cifs/cached_dir.h index 89c0343d7e26..bd262dc8b179 100644 --- a/fs/cifs/cached_dir.h +++ b/fs/cifs/cached_dir.h @@ -50,7 +50,7 @@ extern void free_cached_dir(struct cifs_tcon *tcon); extern int open_cached_dir(unsigned int xid, struct cifs_tcon *tcon, const char *path, struct cifs_sb_info *cifs_sb, - struct cached_fid **cfid); + bool lookup_only, struct cached_fid **cfid); extern int open_cached_dir_by_dentry(struct cifs_tcon *tcon, struct dentry *dentry, struct cached_fid **cfid); diff --git a/fs/cifs/readdir.c b/fs/cifs/readdir.c index a06072ae6c7e..2eece8a07c11 100644 --- a/fs/cifs/readdir.c +++ b/fs/cifs/readdir.c @@ -1072,7 +1072,7 @@ int cifs_readdir(struct file *file, struct dir_context *ctx) tcon = tlink_tcon(cifsFile->tlink); } - rc = open_cached_dir(xid, tcon, full_path, cifs_sb, &cfid); + rc = open_cached_dir(xid, tcon, full_path, cifs_sb, false, &cfid); cifs_put_tlink(tlink); if (rc) goto cache_not_found; @@ -1143,7 +1143,7 @@ int cifs_readdir(struct file *file, struct dir_context *ctx) tcon = tlink_tcon(cifsFile->tlink); rc = find_cifs_entry(xid, tcon, ctx->pos, file, full_path, ¤t_entry, &num_to_fill); - open_cached_dir(xid, tcon, full_path, cifs_sb, &cfid); + open_cached_dir(xid, tcon, full_path, cifs_sb, false, &cfid); if (rc) { cifs_dbg(FYI, "fce error %d\n", rc); goto rddir2_exit; diff --git a/fs/cifs/smb2inode.c b/fs/cifs/smb2inode.c index 9696184a09e3..b83f59051b26 100644 --- a/fs/cifs/smb2inode.c +++ b/fs/cifs/smb2inode.c @@ -516,7 +516,7 @@ smb2_query_path_info(const unsigned int xid, struct cifs_tcon *tcon, if (strcmp(full_path, "")) rc = -ENOENT; else - rc = open_cached_dir(xid, tcon, full_path, cifs_sb, &cfid); + rc = open_cached_dir(xid, tcon, full_path, cifs_sb, false, &cfid); /* If it is a root and its handle is cached then use it */ if (!rc) { if (cfid->file_all_info_is_valid) { diff --git a/fs/cifs/smb2ops.c b/fs/cifs/smb2ops.c index 6507761a8040..f406af596887 100644 --- a/fs/cifs/smb2ops.c +++ b/fs/cifs/smb2ops.c @@ -720,7 +720,7 @@ smb3_qfs_tcon(const unsigned int xid, struct cifs_tcon *tcon, oparms.fid = &fid; oparms.reconnect = false; - rc = open_cached_dir(xid, tcon, "", cifs_sb, &cfid); + rc = open_cached_dir(xid, tcon, "", cifs_sb, false, &cfid); if (rc == 0) memcpy(&fid, &cfid->fid, sizeof(struct cifs_fid)); else @@ -783,9 +783,16 @@ smb2_is_path_accessible(const unsigned int xid, struct cifs_tcon *tcon, __u8 oplock = SMB2_OPLOCK_LEVEL_NONE; struct cifs_open_parms oparms; struct cifs_fid fid; + struct cached_fid *cfid; - if ((*full_path == 0) && tcon->cfid->is_valid) - return 0; + rc = open_cached_dir(xid, tcon, full_path, cifs_sb, true, &cfid); + if (!rc) { + if (cfid->is_valid) { + close_cached_dir(cfid); + return 0; + } + close_cached_dir(cfid); + } utf16_path = cifs_convert_path_to_utf16(full_path, cifs_sb); if (!utf16_path) @@ -2430,8 +2437,12 @@ smb2_query_info_compound(const unsigned int xid, struct cifs_tcon *tcon, resp_buftype[0] = resp_buftype[1] = resp_buftype[2] = CIFS_NO_BUFFER; memset(rsp_iov, 0, sizeof(rsp_iov)); + /* + * We can only call this for things we know are directories. + */ if (!strcmp(path, "")) - open_cached_dir(xid, tcon, path, cifs_sb, &cfid); /* cfid null if open dir failed */ + open_cached_dir(xid, tcon, path, cifs_sb, false, + &cfid); /* cfid null if open dir failed */ memset(&open_iov, 0, sizeof(open_iov)); rqst[0].rq_iov = open_iov; -- cgit v1.2.3 From addebd9ac9ca0ef8b3764907bf8018e48caffc64 Mon Sep 17 00:00:00 2001 From: Keith Busch Date: Fri, 12 Aug 2022 15:56:33 -0700 Subject: fs: don't randomize struct kiocb fields This is a size sensitive structure and randomizing can introduce extra padding that breaks io_uring's fixed size expectations. There are few fields here as it is, half of which need a fixed order to optimally pack, so the randomization isn't providing much. Suggested-by: Linus Torvalds Signed-off-by: Keith Busch Link: https://lore.kernel.org/io-uring/b6f508ca-b1b2-5f40-7998-e4cff1cf7212@kernel.dk/ Signed-off-by: Jens Axboe --- include/linux/fs.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/include/linux/fs.h b/include/linux/fs.h index 9f131e559d05..daf69a6504b6 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -339,17 +339,12 @@ enum rw_hint { struct kiocb { struct file *ki_filp; - - /* The 'ki_filp' pointer is shared in a union for aio */ - randomized_struct_fields_start - loff_t ki_pos; void (*ki_complete)(struct kiocb *iocb, long ret); void *private; int ki_flags; u16 ki_ioprio; /* See linux/ioprio.h */ struct wait_page_queue *ki_waitq; /* for async buffered IO */ - randomized_struct_fields_end }; static inline bool is_sync_kiocb(struct kiocb *kiocb) -- cgit v1.2.3 From f2ccb5aed7bce1d8b3ed5b3385759a5509663028 Mon Sep 17 00:00:00 2001 From: Stefan Metzmacher Date: Thu, 11 Aug 2022 09:11:15 +0200 Subject: io_uring: make io_kiocb_to_cmd() typesafe We need to make sure (at build time) that struct io_cmd_data is not casted to a structure that's larger. Signed-off-by: Stefan Metzmacher Link: https://lore.kernel.org/r/c024cdf25ae19fc0319d4180e2298bade8ed17b8.1660201408.git.metze@samba.org Signed-off-by: Jens Axboe --- include/linux/io_uring_types.h | 9 ++++++++- io_uring/advise.c | 8 ++++---- io_uring/cancel.c | 4 ++-- io_uring/epoll.c | 4 ++-- io_uring/fs.c | 28 ++++++++++++++-------------- io_uring/kbuf.c | 8 ++++---- io_uring/msg_ring.c | 8 ++++---- io_uring/net.c | 42 +++++++++++++++++++++--------------------- io_uring/notif.c | 2 -- io_uring/notif.h | 2 +- io_uring/openclose.c | 16 ++++++++-------- io_uring/poll.c | 16 ++++++++-------- io_uring/rsrc.c | 10 +++++----- io_uring/rw.c | 28 ++++++++++++++-------------- io_uring/splice.c | 8 ++++---- io_uring/statx.c | 6 +++--- io_uring/sync.c | 12 ++++++------ io_uring/timeout.c | 26 +++++++++++++------------- io_uring/uring_cmd.c | 8 ++++---- io_uring/xattr.c | 18 +++++++++--------- 20 files changed, 134 insertions(+), 129 deletions(-) diff --git a/include/linux/io_uring_types.h b/include/linux/io_uring_types.h index f7fab3758cb9..677a25d44d7f 100644 --- a/include/linux/io_uring_types.h +++ b/include/linux/io_uring_types.h @@ -491,7 +491,14 @@ struct io_cmd_data { __u8 data[56]; }; -#define io_kiocb_to_cmd(req) ((void *) &(req)->cmd) +static inline void io_kiocb_cmd_sz_check(size_t cmd_sz) +{ + BUILD_BUG_ON(cmd_sz > sizeof(struct io_cmd_data)); +} +#define io_kiocb_to_cmd(req, cmd_type) ( \ + io_kiocb_cmd_sz_check(sizeof(cmd_type)) , \ + ((cmd_type *)&(req)->cmd) \ +) #define cmd_to_io_kiocb(ptr) ((struct io_kiocb *) ptr) struct io_kiocb { diff --git a/io_uring/advise.c b/io_uring/advise.c index 581956934c0b..449c6f14649f 100644 --- a/io_uring/advise.c +++ b/io_uring/advise.c @@ -31,7 +31,7 @@ struct io_madvise { int io_madvise_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { #if defined(CONFIG_ADVISE_SYSCALLS) && defined(CONFIG_MMU) - struct io_madvise *ma = io_kiocb_to_cmd(req); + struct io_madvise *ma = io_kiocb_to_cmd(req, struct io_madvise); if (sqe->buf_index || sqe->off || sqe->splice_fd_in) return -EINVAL; @@ -48,7 +48,7 @@ int io_madvise_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_madvise(struct io_kiocb *req, unsigned int issue_flags) { #if defined(CONFIG_ADVISE_SYSCALLS) && defined(CONFIG_MMU) - struct io_madvise *ma = io_kiocb_to_cmd(req); + struct io_madvise *ma = io_kiocb_to_cmd(req, struct io_madvise); int ret; if (issue_flags & IO_URING_F_NONBLOCK) @@ -64,7 +64,7 @@ int io_madvise(struct io_kiocb *req, unsigned int issue_flags) int io_fadvise_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_fadvise *fa = io_kiocb_to_cmd(req); + struct io_fadvise *fa = io_kiocb_to_cmd(req, struct io_fadvise); if (sqe->buf_index || sqe->addr || sqe->splice_fd_in) return -EINVAL; @@ -77,7 +77,7 @@ int io_fadvise_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_fadvise(struct io_kiocb *req, unsigned int issue_flags) { - struct io_fadvise *fa = io_kiocb_to_cmd(req); + struct io_fadvise *fa = io_kiocb_to_cmd(req, struct io_fadvise); int ret; if (issue_flags & IO_URING_F_NONBLOCK) { diff --git a/io_uring/cancel.c b/io_uring/cancel.c index 8435a1eba59a..e4e1dc0325f0 100644 --- a/io_uring/cancel.c +++ b/io_uring/cancel.c @@ -107,7 +107,7 @@ int io_try_cancel(struct io_uring_task *tctx, struct io_cancel_data *cd, int io_async_cancel_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_cancel *cancel = io_kiocb_to_cmd(req); + struct io_cancel *cancel = io_kiocb_to_cmd(req, struct io_cancel); if (unlikely(req->flags & REQ_F_BUFFER_SELECT)) return -EINVAL; @@ -164,7 +164,7 @@ static int __io_async_cancel(struct io_cancel_data *cd, int io_async_cancel(struct io_kiocb *req, unsigned int issue_flags) { - struct io_cancel *cancel = io_kiocb_to_cmd(req); + struct io_cancel *cancel = io_kiocb_to_cmd(req, struct io_cancel); struct io_cancel_data cd = { .ctx = req->ctx, .data = cancel->addr, diff --git a/io_uring/epoll.c b/io_uring/epoll.c index a8b794471d6b..9aa74d2c80bc 100644 --- a/io_uring/epoll.c +++ b/io_uring/epoll.c @@ -23,7 +23,7 @@ struct io_epoll { int io_epoll_ctl_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_epoll *epoll = io_kiocb_to_cmd(req); + struct io_epoll *epoll = io_kiocb_to_cmd(req, struct io_epoll); pr_warn_once("%s: epoll_ctl support in io_uring is deprecated and will " "be removed in a future Linux kernel version.\n", @@ -49,7 +49,7 @@ int io_epoll_ctl_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_epoll_ctl(struct io_kiocb *req, unsigned int issue_flags) { - struct io_epoll *ie = io_kiocb_to_cmd(req); + struct io_epoll *ie = io_kiocb_to_cmd(req, struct io_epoll); int ret; bool force_nonblock = issue_flags & IO_URING_F_NONBLOCK; diff --git a/io_uring/fs.c b/io_uring/fs.c index 0de4f549bb7d..7100c293c13a 100644 --- a/io_uring/fs.c +++ b/io_uring/fs.c @@ -49,7 +49,7 @@ struct io_link { int io_renameat_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_rename *ren = io_kiocb_to_cmd(req); + struct io_rename *ren = io_kiocb_to_cmd(req, struct io_rename); const char __user *oldf, *newf; if (sqe->buf_index || sqe->splice_fd_in) @@ -79,7 +79,7 @@ int io_renameat_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_renameat(struct io_kiocb *req, unsigned int issue_flags) { - struct io_rename *ren = io_kiocb_to_cmd(req); + struct io_rename *ren = io_kiocb_to_cmd(req, struct io_rename); int ret; if (issue_flags & IO_URING_F_NONBLOCK) @@ -95,7 +95,7 @@ int io_renameat(struct io_kiocb *req, unsigned int issue_flags) void io_renameat_cleanup(struct io_kiocb *req) { - struct io_rename *ren = io_kiocb_to_cmd(req); + struct io_rename *ren = io_kiocb_to_cmd(req, struct io_rename); putname(ren->oldpath); putname(ren->newpath); @@ -103,7 +103,7 @@ void io_renameat_cleanup(struct io_kiocb *req) int io_unlinkat_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_unlink *un = io_kiocb_to_cmd(req); + struct io_unlink *un = io_kiocb_to_cmd(req, struct io_unlink); const char __user *fname; if (sqe->off || sqe->len || sqe->buf_index || sqe->splice_fd_in) @@ -128,7 +128,7 @@ int io_unlinkat_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_unlinkat(struct io_kiocb *req, unsigned int issue_flags) { - struct io_unlink *un = io_kiocb_to_cmd(req); + struct io_unlink *un = io_kiocb_to_cmd(req, struct io_unlink); int ret; if (issue_flags & IO_URING_F_NONBLOCK) @@ -146,14 +146,14 @@ int io_unlinkat(struct io_kiocb *req, unsigned int issue_flags) void io_unlinkat_cleanup(struct io_kiocb *req) { - struct io_unlink *ul = io_kiocb_to_cmd(req); + struct io_unlink *ul = io_kiocb_to_cmd(req, struct io_unlink); putname(ul->filename); } int io_mkdirat_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_mkdir *mkd = io_kiocb_to_cmd(req); + struct io_mkdir *mkd = io_kiocb_to_cmd(req, struct io_mkdir); const char __user *fname; if (sqe->off || sqe->rw_flags || sqe->buf_index || sqe->splice_fd_in) @@ -175,7 +175,7 @@ int io_mkdirat_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_mkdirat(struct io_kiocb *req, unsigned int issue_flags) { - struct io_mkdir *mkd = io_kiocb_to_cmd(req); + struct io_mkdir *mkd = io_kiocb_to_cmd(req, struct io_mkdir); int ret; if (issue_flags & IO_URING_F_NONBLOCK) @@ -190,14 +190,14 @@ int io_mkdirat(struct io_kiocb *req, unsigned int issue_flags) void io_mkdirat_cleanup(struct io_kiocb *req) { - struct io_mkdir *md = io_kiocb_to_cmd(req); + struct io_mkdir *md = io_kiocb_to_cmd(req, struct io_mkdir); putname(md->filename); } int io_symlinkat_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_link *sl = io_kiocb_to_cmd(req); + struct io_link *sl = io_kiocb_to_cmd(req, struct io_link); const char __user *oldpath, *newpath; if (sqe->len || sqe->rw_flags || sqe->buf_index || sqe->splice_fd_in) @@ -225,7 +225,7 @@ int io_symlinkat_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_symlinkat(struct io_kiocb *req, unsigned int issue_flags) { - struct io_link *sl = io_kiocb_to_cmd(req); + struct io_link *sl = io_kiocb_to_cmd(req, struct io_link); int ret; if (issue_flags & IO_URING_F_NONBLOCK) @@ -240,7 +240,7 @@ int io_symlinkat(struct io_kiocb *req, unsigned int issue_flags) int io_linkat_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_link *lnk = io_kiocb_to_cmd(req); + struct io_link *lnk = io_kiocb_to_cmd(req, struct io_link); const char __user *oldf, *newf; if (sqe->rw_flags || sqe->buf_index || sqe->splice_fd_in) @@ -270,7 +270,7 @@ int io_linkat_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_linkat(struct io_kiocb *req, unsigned int issue_flags) { - struct io_link *lnk = io_kiocb_to_cmd(req); + struct io_link *lnk = io_kiocb_to_cmd(req, struct io_link); int ret; if (issue_flags & IO_URING_F_NONBLOCK) @@ -286,7 +286,7 @@ int io_linkat(struct io_kiocb *req, unsigned int issue_flags) void io_link_cleanup(struct io_kiocb *req) { - struct io_link *sl = io_kiocb_to_cmd(req); + struct io_link *sl = io_kiocb_to_cmd(req, struct io_link); putname(sl->oldpath); putname(sl->newpath); diff --git a/io_uring/kbuf.c b/io_uring/kbuf.c index a73f40a4cfe6..25cd724ade18 100644 --- a/io_uring/kbuf.c +++ b/io_uring/kbuf.c @@ -272,7 +272,7 @@ void io_destroy_buffers(struct io_ring_ctx *ctx) int io_remove_buffers_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_provide_buf *p = io_kiocb_to_cmd(req); + struct io_provide_buf *p = io_kiocb_to_cmd(req, struct io_provide_buf); u64 tmp; if (sqe->rw_flags || sqe->addr || sqe->len || sqe->off || @@ -291,7 +291,7 @@ int io_remove_buffers_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_remove_buffers(struct io_kiocb *req, unsigned int issue_flags) { - struct io_provide_buf *p = io_kiocb_to_cmd(req); + struct io_provide_buf *p = io_kiocb_to_cmd(req, struct io_provide_buf); struct io_ring_ctx *ctx = req->ctx; struct io_buffer_list *bl; int ret = 0; @@ -319,7 +319,7 @@ int io_remove_buffers(struct io_kiocb *req, unsigned int issue_flags) int io_provide_buffers_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { unsigned long size, tmp_check; - struct io_provide_buf *p = io_kiocb_to_cmd(req); + struct io_provide_buf *p = io_kiocb_to_cmd(req, struct io_provide_buf); u64 tmp; if (sqe->rw_flags || sqe->splice_fd_in) @@ -421,7 +421,7 @@ static int io_add_buffers(struct io_ring_ctx *ctx, struct io_provide_buf *pbuf, int io_provide_buffers(struct io_kiocb *req, unsigned int issue_flags) { - struct io_provide_buf *p = io_kiocb_to_cmd(req); + struct io_provide_buf *p = io_kiocb_to_cmd(req, struct io_provide_buf); struct io_ring_ctx *ctx = req->ctx; struct io_buffer_list *bl; int ret = 0; diff --git a/io_uring/msg_ring.c b/io_uring/msg_ring.c index 753d16734319..976c4ba68ee7 100644 --- a/io_uring/msg_ring.c +++ b/io_uring/msg_ring.c @@ -26,7 +26,7 @@ struct io_msg { static int io_msg_ring_data(struct io_kiocb *req) { struct io_ring_ctx *target_ctx = req->file->private_data; - struct io_msg *msg = io_kiocb_to_cmd(req); + struct io_msg *msg = io_kiocb_to_cmd(req, struct io_msg); if (msg->src_fd || msg->dst_fd || msg->flags) return -EINVAL; @@ -76,7 +76,7 @@ static int io_double_lock_ctx(struct io_ring_ctx *ctx, static int io_msg_send_fd(struct io_kiocb *req, unsigned int issue_flags) { struct io_ring_ctx *target_ctx = req->file->private_data; - struct io_msg *msg = io_kiocb_to_cmd(req); + struct io_msg *msg = io_kiocb_to_cmd(req, struct io_msg); struct io_ring_ctx *ctx = req->ctx; unsigned long file_ptr; struct file *src_file; @@ -122,7 +122,7 @@ out_unlock: int io_msg_ring_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_msg *msg = io_kiocb_to_cmd(req); + struct io_msg *msg = io_kiocb_to_cmd(req, struct io_msg); if (unlikely(sqe->buf_index || sqe->personality)) return -EINVAL; @@ -141,7 +141,7 @@ int io_msg_ring_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_msg_ring(struct io_kiocb *req, unsigned int issue_flags) { - struct io_msg *msg = io_kiocb_to_cmd(req); + struct io_msg *msg = io_kiocb_to_cmd(req, struct io_msg); int ret; ret = -EBADFD; diff --git a/io_uring/net.c b/io_uring/net.c index e6fc9748fbd2..6d71748e2c5a 100644 --- a/io_uring/net.c +++ b/io_uring/net.c @@ -77,7 +77,7 @@ struct io_sendzc { int io_shutdown_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_shutdown *shutdown = io_kiocb_to_cmd(req); + struct io_shutdown *shutdown = io_kiocb_to_cmd(req, struct io_shutdown); if (unlikely(sqe->off || sqe->addr || sqe->rw_flags || sqe->buf_index || sqe->splice_fd_in)) @@ -89,7 +89,7 @@ int io_shutdown_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_shutdown(struct io_kiocb *req, unsigned int issue_flags) { - struct io_shutdown *shutdown = io_kiocb_to_cmd(req); + struct io_shutdown *shutdown = io_kiocb_to_cmd(req, struct io_shutdown); struct socket *sock; int ret; @@ -174,7 +174,7 @@ static int io_setup_async_msg(struct io_kiocb *req, static int io_sendmsg_copy_hdr(struct io_kiocb *req, struct io_async_msghdr *iomsg) { - struct io_sr_msg *sr = io_kiocb_to_cmd(req); + struct io_sr_msg *sr = io_kiocb_to_cmd(req, struct io_sr_msg); iomsg->msg.msg_name = &iomsg->addr; iomsg->free_iov = iomsg->fast_iov; @@ -201,7 +201,7 @@ void io_sendmsg_recvmsg_cleanup(struct io_kiocb *req) int io_sendmsg_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_sr_msg *sr = io_kiocb_to_cmd(req); + struct io_sr_msg *sr = io_kiocb_to_cmd(req, struct io_sr_msg); if (unlikely(sqe->file_index || sqe->addr2)) return -EINVAL; @@ -225,7 +225,7 @@ int io_sendmsg_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_sendmsg(struct io_kiocb *req, unsigned int issue_flags) { - struct io_sr_msg *sr = io_kiocb_to_cmd(req); + struct io_sr_msg *sr = io_kiocb_to_cmd(req, struct io_sr_msg); struct io_async_msghdr iomsg, *kmsg; struct socket *sock; unsigned flags; @@ -284,7 +284,7 @@ int io_sendmsg(struct io_kiocb *req, unsigned int issue_flags) int io_send(struct io_kiocb *req, unsigned int issue_flags) { - struct io_sr_msg *sr = io_kiocb_to_cmd(req); + struct io_sr_msg *sr = io_kiocb_to_cmd(req, struct io_sr_msg); struct msghdr msg; struct iovec iov; struct socket *sock; @@ -358,7 +358,7 @@ static bool io_recvmsg_multishot_overflow(struct io_async_msghdr *iomsg) static int __io_recvmsg_copy_hdr(struct io_kiocb *req, struct io_async_msghdr *iomsg) { - struct io_sr_msg *sr = io_kiocb_to_cmd(req); + struct io_sr_msg *sr = io_kiocb_to_cmd(req, struct io_sr_msg); struct user_msghdr msg; int ret; @@ -405,7 +405,7 @@ static int __io_recvmsg_copy_hdr(struct io_kiocb *req, static int __io_compat_recvmsg_copy_hdr(struct io_kiocb *req, struct io_async_msghdr *iomsg) { - struct io_sr_msg *sr = io_kiocb_to_cmd(req); + struct io_sr_msg *sr = io_kiocb_to_cmd(req, struct io_sr_msg); struct compat_msghdr msg; struct compat_iovec __user *uiov; int ret; @@ -483,7 +483,7 @@ int io_recvmsg_prep_async(struct io_kiocb *req) int io_recvmsg_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_sr_msg *sr = io_kiocb_to_cmd(req); + struct io_sr_msg *sr = io_kiocb_to_cmd(req, struct io_sr_msg); if (unlikely(sqe->file_index || sqe->addr2)) return -EINVAL; @@ -518,7 +518,7 @@ int io_recvmsg_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) static inline void io_recv_prep_retry(struct io_kiocb *req) { - struct io_sr_msg *sr = io_kiocb_to_cmd(req); + struct io_sr_msg *sr = io_kiocb_to_cmd(req, struct io_sr_msg); sr->done_io = 0; sr->len = 0; /* get from the provided buffer */ @@ -647,7 +647,7 @@ static int io_recvmsg_multishot(struct socket *sock, struct io_sr_msg *io, int io_recvmsg(struct io_kiocb *req, unsigned int issue_flags) { - struct io_sr_msg *sr = io_kiocb_to_cmd(req); + struct io_sr_msg *sr = io_kiocb_to_cmd(req, struct io_sr_msg); struct io_async_msghdr iomsg, *kmsg; struct socket *sock; unsigned int cflags; @@ -759,7 +759,7 @@ retry_multishot: int io_recv(struct io_kiocb *req, unsigned int issue_flags) { - struct io_sr_msg *sr = io_kiocb_to_cmd(req); + struct io_sr_msg *sr = io_kiocb_to_cmd(req, struct io_sr_msg); struct msghdr msg; struct socket *sock; struct iovec iov; @@ -850,7 +850,7 @@ out_free: int io_sendzc_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_sendzc *zc = io_kiocb_to_cmd(req); + struct io_sendzc *zc = io_kiocb_to_cmd(req, struct io_sendzc); struct io_ring_ctx *ctx = req->ctx; if (READ_ONCE(sqe->__pad2[0]) || READ_ONCE(sqe->addr3)) @@ -946,7 +946,7 @@ int io_sendzc(struct io_kiocb *req, unsigned int issue_flags) { struct sockaddr_storage address; struct io_ring_ctx *ctx = req->ctx; - struct io_sendzc *zc = io_kiocb_to_cmd(req); + struct io_sendzc *zc = io_kiocb_to_cmd(req, struct io_sendzc); struct io_notif_slot *notif_slot; struct io_kiocb *notif; struct msghdr msg; @@ -1037,7 +1037,7 @@ int io_sendzc(struct io_kiocb *req, unsigned int issue_flags) int io_accept_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_accept *accept = io_kiocb_to_cmd(req); + struct io_accept *accept = io_kiocb_to_cmd(req, struct io_accept); unsigned flags; if (sqe->len || sqe->buf_index) @@ -1071,7 +1071,7 @@ int io_accept_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_accept(struct io_kiocb *req, unsigned int issue_flags) { struct io_ring_ctx *ctx = req->ctx; - struct io_accept *accept = io_kiocb_to_cmd(req); + struct io_accept *accept = io_kiocb_to_cmd(req, struct io_accept); bool force_nonblock = issue_flags & IO_URING_F_NONBLOCK; unsigned int file_flags = force_nonblock ? O_NONBLOCK : 0; bool fixed = !!accept->file_slot; @@ -1129,7 +1129,7 @@ retry: int io_socket_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_socket *sock = io_kiocb_to_cmd(req); + struct io_socket *sock = io_kiocb_to_cmd(req, struct io_socket); if (sqe->addr || sqe->rw_flags || sqe->buf_index) return -EINVAL; @@ -1150,7 +1150,7 @@ int io_socket_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_socket(struct io_kiocb *req, unsigned int issue_flags) { - struct io_socket *sock = io_kiocb_to_cmd(req); + struct io_socket *sock = io_kiocb_to_cmd(req, struct io_socket); bool fixed = !!sock->file_slot; struct file *file; int ret, fd; @@ -1184,14 +1184,14 @@ int io_socket(struct io_kiocb *req, unsigned int issue_flags) int io_connect_prep_async(struct io_kiocb *req) { struct io_async_connect *io = req->async_data; - struct io_connect *conn = io_kiocb_to_cmd(req); + struct io_connect *conn = io_kiocb_to_cmd(req, struct io_connect); return move_addr_to_kernel(conn->addr, conn->addr_len, &io->address); } int io_connect_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_connect *conn = io_kiocb_to_cmd(req); + struct io_connect *conn = io_kiocb_to_cmd(req, struct io_connect); if (sqe->len || sqe->buf_index || sqe->rw_flags || sqe->splice_fd_in) return -EINVAL; @@ -1203,7 +1203,7 @@ int io_connect_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_connect(struct io_kiocb *req, unsigned int issue_flags) { - struct io_connect *connect = io_kiocb_to_cmd(req); + struct io_connect *connect = io_kiocb_to_cmd(req, struct io_connect); struct io_async_connect __io, *io; unsigned file_flags; int ret; diff --git a/io_uring/notif.c b/io_uring/notif.c index 48d29dead62a..977736e82c1a 100644 --- a/io_uring/notif.c +++ b/io_uring/notif.c @@ -123,8 +123,6 @@ __cold int io_notif_register(struct io_ring_ctx *ctx, struct io_uring_notification_register reg; unsigned i; - BUILD_BUG_ON(sizeof(struct io_notif_data) > 64); - if (ctx->nr_notif_slots) return -EBUSY; if (size != sizeof(reg)) diff --git a/io_uring/notif.h b/io_uring/notif.h index 0819304d7e00..65f0b42f2555 100644 --- a/io_uring/notif.h +++ b/io_uring/notif.h @@ -46,7 +46,7 @@ struct io_kiocb *io_alloc_notif(struct io_ring_ctx *ctx, static inline struct io_notif_data *io_notif_to_data(struct io_kiocb *notif) { - return io_kiocb_to_cmd(notif); + return io_kiocb_to_cmd(notif, struct io_notif_data); } static inline struct io_kiocb *io_get_notif(struct io_ring_ctx *ctx, diff --git a/io_uring/openclose.c b/io_uring/openclose.c index d1818ec9169b..67178e4bb282 100644 --- a/io_uring/openclose.c +++ b/io_uring/openclose.c @@ -33,7 +33,7 @@ struct io_close { static int __io_openat_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_open *open = io_kiocb_to_cmd(req); + struct io_open *open = io_kiocb_to_cmd(req, struct io_open); const char __user *fname; int ret; @@ -66,7 +66,7 @@ static int __io_openat_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe int io_openat_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_open *open = io_kiocb_to_cmd(req); + struct io_open *open = io_kiocb_to_cmd(req, struct io_open); u64 mode = READ_ONCE(sqe->len); u64 flags = READ_ONCE(sqe->open_flags); @@ -76,7 +76,7 @@ int io_openat_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_openat2_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_open *open = io_kiocb_to_cmd(req); + struct io_open *open = io_kiocb_to_cmd(req, struct io_open); struct open_how __user *how; size_t len; int ret; @@ -95,7 +95,7 @@ int io_openat2_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_openat2(struct io_kiocb *req, unsigned int issue_flags) { - struct io_open *open = io_kiocb_to_cmd(req); + struct io_open *open = io_kiocb_to_cmd(req, struct io_open); struct open_flags op; struct file *file; bool resolve_nonblock, nonblock_set; @@ -167,7 +167,7 @@ int io_openat(struct io_kiocb *req, unsigned int issue_flags) void io_open_cleanup(struct io_kiocb *req) { - struct io_open *open = io_kiocb_to_cmd(req); + struct io_open *open = io_kiocb_to_cmd(req, struct io_open); if (open->filename) putname(open->filename); @@ -187,14 +187,14 @@ int __io_close_fixed(struct io_ring_ctx *ctx, unsigned int issue_flags, static inline int io_close_fixed(struct io_kiocb *req, unsigned int issue_flags) { - struct io_close *close = io_kiocb_to_cmd(req); + struct io_close *close = io_kiocb_to_cmd(req, struct io_close); return __io_close_fixed(req->ctx, issue_flags, close->file_slot - 1); } int io_close_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_close *close = io_kiocb_to_cmd(req); + struct io_close *close = io_kiocb_to_cmd(req, struct io_close); if (sqe->off || sqe->addr || sqe->len || sqe->rw_flags || sqe->buf_index) return -EINVAL; @@ -212,7 +212,7 @@ int io_close_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_close(struct io_kiocb *req, unsigned int issue_flags) { struct files_struct *files = current->files; - struct io_close *close = io_kiocb_to_cmd(req); + struct io_close *close = io_kiocb_to_cmd(req, struct io_close); struct fdtable *fdt; struct file *file; int ret = -EBADF; diff --git a/io_uring/poll.c b/io_uring/poll.c index dadd293749b0..d5bad0bea6e4 100644 --- a/io_uring/poll.c +++ b/io_uring/poll.c @@ -85,7 +85,7 @@ static struct io_poll *io_poll_get_double(struct io_kiocb *req) static struct io_poll *io_poll_get_single(struct io_kiocb *req) { if (req->opcode == IORING_OP_POLL_ADD) - return io_kiocb_to_cmd(req); + return io_kiocb_to_cmd(req, struct io_poll); return &req->apoll->poll; } @@ -274,7 +274,7 @@ static void io_poll_task_func(struct io_kiocb *req, bool *locked) return; if (ret == IOU_POLL_DONE) { - struct io_poll *poll = io_kiocb_to_cmd(req); + struct io_poll *poll = io_kiocb_to_cmd(req, struct io_poll); req->cqe.res = mangle_poll(req->cqe.res & poll->events); } else if (ret != IOU_POLL_REMOVE_POLL_USE_RES) { req->cqe.res = ret; @@ -475,7 +475,7 @@ static void io_poll_queue_proc(struct file *file, struct wait_queue_head *head, struct poll_table_struct *p) { struct io_poll_table *pt = container_of(p, struct io_poll_table, pt); - struct io_poll *poll = io_kiocb_to_cmd(pt->req); + struct io_poll *poll = io_kiocb_to_cmd(pt->req, struct io_poll); __io_queue_proc(poll, pt, head, (struct io_poll **) &pt->req->async_data); @@ -821,7 +821,7 @@ static __poll_t io_poll_parse_events(const struct io_uring_sqe *sqe, int io_poll_remove_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_poll_update *upd = io_kiocb_to_cmd(req); + struct io_poll_update *upd = io_kiocb_to_cmd(req, struct io_poll_update); u32 flags; if (sqe->buf_index || sqe->splice_fd_in) @@ -851,7 +851,7 @@ int io_poll_remove_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_poll_add_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_poll *poll = io_kiocb_to_cmd(req); + struct io_poll *poll = io_kiocb_to_cmd(req, struct io_poll); u32 flags; if (sqe->buf_index || sqe->off || sqe->addr) @@ -868,7 +868,7 @@ int io_poll_add_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_poll_add(struct io_kiocb *req, unsigned int issue_flags) { - struct io_poll *poll = io_kiocb_to_cmd(req); + struct io_poll *poll = io_kiocb_to_cmd(req, struct io_poll); struct io_poll_table ipt; int ret; @@ -891,7 +891,7 @@ int io_poll_add(struct io_kiocb *req, unsigned int issue_flags) int io_poll_remove(struct io_kiocb *req, unsigned int issue_flags) { - struct io_poll_update *poll_update = io_kiocb_to_cmd(req); + struct io_poll_update *poll_update = io_kiocb_to_cmd(req, struct io_poll_update); struct io_cancel_data cd = { .data = poll_update->old_user_data, }; struct io_ring_ctx *ctx = req->ctx; struct io_hash_bucket *bucket; @@ -930,7 +930,7 @@ found: if (poll_update->update_events || poll_update->update_user_data) { /* only mask one event flags, keep behavior flags */ if (poll_update->update_events) { - struct io_poll *poll = io_kiocb_to_cmd(preq); + struct io_poll *poll = io_kiocb_to_cmd(preq, struct io_poll); poll->events &= ~0xffff; poll->events |= poll_update->events & 0xffff; diff --git a/io_uring/rsrc.c b/io_uring/rsrc.c index 59704b9ac537..71359a4d0bd4 100644 --- a/io_uring/rsrc.c +++ b/io_uring/rsrc.c @@ -657,7 +657,7 @@ __cold int io_register_rsrc(struct io_ring_ctx *ctx, void __user *arg, int io_rsrc_update_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_rsrc_update *up = io_kiocb_to_cmd(req); + struct io_rsrc_update *up = io_kiocb_to_cmd(req, struct io_rsrc_update); if (unlikely(req->flags & (REQ_F_FIXED_FILE | REQ_F_BUFFER_SELECT))) return -EINVAL; @@ -676,7 +676,7 @@ int io_rsrc_update_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) static int io_files_update_with_index_alloc(struct io_kiocb *req, unsigned int issue_flags) { - struct io_rsrc_update *up = io_kiocb_to_cmd(req); + struct io_rsrc_update *up = io_kiocb_to_cmd(req, struct io_rsrc_update); __s32 __user *fds = u64_to_user_ptr(up->arg); unsigned int done; struct file *file; @@ -714,7 +714,7 @@ static int io_files_update_with_index_alloc(struct io_kiocb *req, static int io_files_update(struct io_kiocb *req, unsigned int issue_flags) { - struct io_rsrc_update *up = io_kiocb_to_cmd(req); + struct io_rsrc_update *up = io_kiocb_to_cmd(req, struct io_rsrc_update); struct io_ring_ctx *ctx = req->ctx; struct io_uring_rsrc_update2 up2; int ret; @@ -743,7 +743,7 @@ static int io_files_update(struct io_kiocb *req, unsigned int issue_flags) static int io_notif_update(struct io_kiocb *req, unsigned int issue_flags) { - struct io_rsrc_update *up = io_kiocb_to_cmd(req); + struct io_rsrc_update *up = io_kiocb_to_cmd(req, struct io_rsrc_update); struct io_ring_ctx *ctx = req->ctx; unsigned len = up->nr_args; unsigned idx_end, idx = up->offset; @@ -778,7 +778,7 @@ out: int io_rsrc_update(struct io_kiocb *req, unsigned int issue_flags) { - struct io_rsrc_update *up = io_kiocb_to_cmd(req); + struct io_rsrc_update *up = io_kiocb_to_cmd(req, struct io_rsrc_update); switch (up->type) { case IORING_RSRC_UPDATE_FILES: diff --git a/io_uring/rw.c b/io_uring/rw.c index 2b784795103c..3d732b19b760 100644 --- a/io_uring/rw.c +++ b/io_uring/rw.c @@ -35,7 +35,7 @@ static inline bool io_file_supports_nowait(struct io_kiocb *req) int io_prep_rw(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_rw *rw = io_kiocb_to_cmd(req); + struct io_rw *rw = io_kiocb_to_cmd(req, struct io_rw); unsigned ioprio; int ret; @@ -102,7 +102,7 @@ static inline void io_rw_done(struct kiocb *kiocb, ssize_t ret) static inline loff_t *io_kiocb_update_pos(struct io_kiocb *req) { - struct io_rw *rw = io_kiocb_to_cmd(req); + struct io_rw *rw = io_kiocb_to_cmd(req, struct io_rw); if (rw->kiocb.ki_pos != -1) return &rw->kiocb.ki_pos; @@ -186,7 +186,7 @@ static void kiocb_end_write(struct io_kiocb *req) static bool __io_complete_rw_common(struct io_kiocb *req, long res) { - struct io_rw *rw = io_kiocb_to_cmd(req); + struct io_rw *rw = io_kiocb_to_cmd(req, struct io_rw); if (rw->kiocb.ki_flags & IOCB_WRITE) { kiocb_end_write(req); @@ -241,7 +241,7 @@ static int kiocb_done(struct io_kiocb *req, ssize_t ret, unsigned int issue_flags) { struct io_async_rw *io = req->async_data; - struct io_rw *rw = io_kiocb_to_cmd(req); + struct io_rw *rw = io_kiocb_to_cmd(req, struct io_rw); /* add previously done IO, if any */ if (req_has_async_data(req) && io->bytes_done > 0) { @@ -277,7 +277,7 @@ static int kiocb_done(struct io_kiocb *req, ssize_t ret, static ssize_t io_compat_import(struct io_kiocb *req, struct iovec *iov, unsigned int issue_flags) { - struct io_rw *rw = io_kiocb_to_cmd(req); + struct io_rw *rw = io_kiocb_to_cmd(req, struct io_rw); struct compat_iovec __user *uiov; compat_ssize_t clen; void __user *buf; @@ -305,7 +305,7 @@ static ssize_t io_compat_import(struct io_kiocb *req, struct iovec *iov, static ssize_t __io_iov_buffer_select(struct io_kiocb *req, struct iovec *iov, unsigned int issue_flags) { - struct io_rw *rw = io_kiocb_to_cmd(req); + struct io_rw *rw = io_kiocb_to_cmd(req, struct io_rw); struct iovec __user *uiov = u64_to_user_ptr(rw->addr); void __user *buf; ssize_t len; @@ -328,7 +328,7 @@ static ssize_t __io_iov_buffer_select(struct io_kiocb *req, struct iovec *iov, static ssize_t io_iov_buffer_select(struct io_kiocb *req, struct iovec *iov, unsigned int issue_flags) { - struct io_rw *rw = io_kiocb_to_cmd(req); + struct io_rw *rw = io_kiocb_to_cmd(req, struct io_rw); if (req->flags & (REQ_F_BUFFER_SELECTED|REQ_F_BUFFER_RING)) { iov[0].iov_base = u64_to_user_ptr(rw->addr); @@ -350,7 +350,7 @@ static struct iovec *__io_import_iovec(int ddir, struct io_kiocb *req, struct io_rw_state *s, unsigned int issue_flags) { - struct io_rw *rw = io_kiocb_to_cmd(req); + struct io_rw *rw = io_kiocb_to_cmd(req, struct io_rw); struct iov_iter *iter = &s->iter; u8 opcode = req->opcode; struct iovec *iovec; @@ -571,7 +571,7 @@ static int io_async_buf_func(struct wait_queue_entry *wait, unsigned mode, { struct wait_page_queue *wpq; struct io_kiocb *req = wait->private; - struct io_rw *rw = io_kiocb_to_cmd(req); + struct io_rw *rw = io_kiocb_to_cmd(req, struct io_rw); struct wait_page_key *key = arg; wpq = container_of(wait, struct wait_page_queue, wait); @@ -601,7 +601,7 @@ static bool io_rw_should_retry(struct io_kiocb *req) { struct io_async_rw *io = req->async_data; struct wait_page_queue *wait = &io->wpq; - struct io_rw *rw = io_kiocb_to_cmd(req); + struct io_rw *rw = io_kiocb_to_cmd(req, struct io_rw); struct kiocb *kiocb = &rw->kiocb; /* never retry for NOWAIT, we just complete with -EAGAIN */ @@ -649,7 +649,7 @@ static bool need_complete_io(struct io_kiocb *req) static int io_rw_init_file(struct io_kiocb *req, fmode_t mode) { - struct io_rw *rw = io_kiocb_to_cmd(req); + struct io_rw *rw = io_kiocb_to_cmd(req, struct io_rw); struct kiocb *kiocb = &rw->kiocb; struct io_ring_ctx *ctx = req->ctx; struct file *file = req->file; @@ -694,7 +694,7 @@ static int io_rw_init_file(struct io_kiocb *req, fmode_t mode) int io_read(struct io_kiocb *req, unsigned int issue_flags) { - struct io_rw *rw = io_kiocb_to_cmd(req); + struct io_rw *rw = io_kiocb_to_cmd(req, struct io_rw); struct io_rw_state __s, *s = &__s; struct iovec *iovec; struct kiocb *kiocb = &rw->kiocb; @@ -839,7 +839,7 @@ done: int io_write(struct io_kiocb *req, unsigned int issue_flags) { - struct io_rw *rw = io_kiocb_to_cmd(req); + struct io_rw *rw = io_kiocb_to_cmd(req, struct io_rw); struct io_rw_state __s, *s = &__s; struct iovec *iovec; struct kiocb *kiocb = &rw->kiocb; @@ -994,7 +994,7 @@ int io_do_iopoll(struct io_ring_ctx *ctx, bool force_nonspin) wq_list_for_each(pos, start, &ctx->iopoll_list) { struct io_kiocb *req = container_of(pos, struct io_kiocb, comp_list); - struct io_rw *rw = io_kiocb_to_cmd(req); + struct io_rw *rw = io_kiocb_to_cmd(req, struct io_rw); int ret; /* diff --git a/io_uring/splice.c b/io_uring/splice.c index b013ba34bffa..53e4232d0866 100644 --- a/io_uring/splice.c +++ b/io_uring/splice.c @@ -26,7 +26,7 @@ struct io_splice { static int __io_splice_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_splice *sp = io_kiocb_to_cmd(req); + struct io_splice *sp = io_kiocb_to_cmd(req, struct io_splice); unsigned int valid_flags = SPLICE_F_FD_IN_FIXED | SPLICE_F_ALL; sp->len = READ_ONCE(sqe->len); @@ -46,7 +46,7 @@ int io_tee_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_tee(struct io_kiocb *req, unsigned int issue_flags) { - struct io_splice *sp = io_kiocb_to_cmd(req); + struct io_splice *sp = io_kiocb_to_cmd(req, struct io_splice); struct file *out = sp->file_out; unsigned int flags = sp->flags & ~SPLICE_F_FD_IN_FIXED; struct file *in; @@ -78,7 +78,7 @@ done: int io_splice_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_splice *sp = io_kiocb_to_cmd(req); + struct io_splice *sp = io_kiocb_to_cmd(req, struct io_splice); sp->off_in = READ_ONCE(sqe->splice_off_in); sp->off_out = READ_ONCE(sqe->off); @@ -87,7 +87,7 @@ int io_splice_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_splice(struct io_kiocb *req, unsigned int issue_flags) { - struct io_splice *sp = io_kiocb_to_cmd(req); + struct io_splice *sp = io_kiocb_to_cmd(req, struct io_splice); struct file *out = sp->file_out; unsigned int flags = sp->flags & ~SPLICE_F_FD_IN_FIXED; loff_t *poff_in, *poff_out; diff --git a/io_uring/statx.c b/io_uring/statx.c index 6056cd7f4876..d8fc933d3f59 100644 --- a/io_uring/statx.c +++ b/io_uring/statx.c @@ -22,7 +22,7 @@ struct io_statx { int io_statx_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_statx *sx = io_kiocb_to_cmd(req); + struct io_statx *sx = io_kiocb_to_cmd(req, struct io_statx); const char __user *path; if (sqe->buf_index || sqe->splice_fd_in) @@ -53,7 +53,7 @@ int io_statx_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_statx(struct io_kiocb *req, unsigned int issue_flags) { - struct io_statx *sx = io_kiocb_to_cmd(req); + struct io_statx *sx = io_kiocb_to_cmd(req, struct io_statx); int ret; if (issue_flags & IO_URING_F_NONBLOCK) @@ -66,7 +66,7 @@ int io_statx(struct io_kiocb *req, unsigned int issue_flags) void io_statx_cleanup(struct io_kiocb *req) { - struct io_statx *sx = io_kiocb_to_cmd(req); + struct io_statx *sx = io_kiocb_to_cmd(req, struct io_statx); if (sx->filename) putname(sx->filename); diff --git a/io_uring/sync.c b/io_uring/sync.c index f2102afa79ca..64e87ea2b8fb 100644 --- a/io_uring/sync.c +++ b/io_uring/sync.c @@ -24,7 +24,7 @@ struct io_sync { int io_sfr_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_sync *sync = io_kiocb_to_cmd(req); + struct io_sync *sync = io_kiocb_to_cmd(req, struct io_sync); if (unlikely(sqe->addr || sqe->buf_index || sqe->splice_fd_in)) return -EINVAL; @@ -37,7 +37,7 @@ int io_sfr_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_sync_file_range(struct io_kiocb *req, unsigned int issue_flags) { - struct io_sync *sync = io_kiocb_to_cmd(req); + struct io_sync *sync = io_kiocb_to_cmd(req, struct io_sync); int ret; /* sync_file_range always requires a blocking context */ @@ -51,7 +51,7 @@ int io_sync_file_range(struct io_kiocb *req, unsigned int issue_flags) int io_fsync_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_sync *sync = io_kiocb_to_cmd(req); + struct io_sync *sync = io_kiocb_to_cmd(req, struct io_sync); if (unlikely(sqe->addr || sqe->buf_index || sqe->splice_fd_in)) return -EINVAL; @@ -67,7 +67,7 @@ int io_fsync_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_fsync(struct io_kiocb *req, unsigned int issue_flags) { - struct io_sync *sync = io_kiocb_to_cmd(req); + struct io_sync *sync = io_kiocb_to_cmd(req, struct io_sync); loff_t end = sync->off + sync->len; int ret; @@ -83,7 +83,7 @@ int io_fsync(struct io_kiocb *req, unsigned int issue_flags) int io_fallocate_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_sync *sync = io_kiocb_to_cmd(req); + struct io_sync *sync = io_kiocb_to_cmd(req, struct io_sync); if (sqe->buf_index || sqe->rw_flags || sqe->splice_fd_in) return -EINVAL; @@ -96,7 +96,7 @@ int io_fallocate_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_fallocate(struct io_kiocb *req, unsigned int issue_flags) { - struct io_sync *sync = io_kiocb_to_cmd(req); + struct io_sync *sync = io_kiocb_to_cmd(req, struct io_sync); int ret; /* fallocate always requiring blocking context */ diff --git a/io_uring/timeout.c b/io_uring/timeout.c index 2f9e56935479..78ea2c64b70e 100644 --- a/io_uring/timeout.c +++ b/io_uring/timeout.c @@ -36,7 +36,7 @@ struct io_timeout_rem { static inline bool io_is_timeout_noseq(struct io_kiocb *req) { - struct io_timeout *timeout = io_kiocb_to_cmd(req); + struct io_timeout *timeout = io_kiocb_to_cmd(req, struct io_timeout); return !timeout->off; } @@ -56,7 +56,7 @@ static bool io_kill_timeout(struct io_kiocb *req, int status) struct io_timeout_data *io = req->async_data; if (hrtimer_try_to_cancel(&io->timer) != -1) { - struct io_timeout *timeout = io_kiocb_to_cmd(req); + struct io_timeout *timeout = io_kiocb_to_cmd(req, struct io_timeout); if (status) req_set_fail(req); @@ -188,7 +188,7 @@ struct io_kiocb *__io_disarm_linked_timeout(struct io_kiocb *req, __must_hold(&req->ctx->timeout_lock) { struct io_timeout_data *io = link->async_data; - struct io_timeout *timeout = io_kiocb_to_cmd(link); + struct io_timeout *timeout = io_kiocb_to_cmd(link, struct io_timeout); io_remove_next_linked(req); timeout->head = NULL; @@ -205,7 +205,7 @@ static enum hrtimer_restart io_timeout_fn(struct hrtimer *timer) struct io_timeout_data *data = container_of(timer, struct io_timeout_data, timer); struct io_kiocb *req = data->req; - struct io_timeout *timeout = io_kiocb_to_cmd(req); + struct io_timeout *timeout = io_kiocb_to_cmd(req, struct io_timeout); struct io_ring_ctx *ctx = req->ctx; unsigned long flags; @@ -252,7 +252,7 @@ static struct io_kiocb *io_timeout_extract(struct io_ring_ctx *ctx, io = req->async_data; if (hrtimer_try_to_cancel(&io->timer) == -1) return ERR_PTR(-EALREADY); - timeout = io_kiocb_to_cmd(req); + timeout = io_kiocb_to_cmd(req, struct io_timeout); list_del_init(&timeout->list); return req; } @@ -275,7 +275,7 @@ int io_timeout_cancel(struct io_ring_ctx *ctx, struct io_cancel_data *cd) static void io_req_task_link_timeout(struct io_kiocb *req, bool *locked) { unsigned issue_flags = *locked ? 0 : IO_URING_F_UNLOCKED; - struct io_timeout *timeout = io_kiocb_to_cmd(req); + struct io_timeout *timeout = io_kiocb_to_cmd(req, struct io_timeout); struct io_kiocb *prev = timeout->prev; int ret = -ENOENT; @@ -302,7 +302,7 @@ static enum hrtimer_restart io_link_timeout_fn(struct hrtimer *timer) struct io_timeout_data *data = container_of(timer, struct io_timeout_data, timer); struct io_kiocb *prev, *req = data->req; - struct io_timeout *timeout = io_kiocb_to_cmd(req); + struct io_timeout *timeout = io_kiocb_to_cmd(req, struct io_timeout); struct io_ring_ctx *ctx = req->ctx; unsigned long flags; @@ -378,7 +378,7 @@ static int io_timeout_update(struct io_ring_ctx *ctx, __u64 user_data, { struct io_cancel_data cd = { .data = user_data, }; struct io_kiocb *req = io_timeout_extract(ctx, &cd); - struct io_timeout *timeout = io_kiocb_to_cmd(req); + struct io_timeout *timeout = io_kiocb_to_cmd(req, struct io_timeout); struct io_timeout_data *data; if (IS_ERR(req)) @@ -395,7 +395,7 @@ static int io_timeout_update(struct io_ring_ctx *ctx, __u64 user_data, int io_timeout_remove_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_timeout_rem *tr = io_kiocb_to_cmd(req); + struct io_timeout_rem *tr = io_kiocb_to_cmd(req, struct io_timeout_rem); if (unlikely(req->flags & (REQ_F_FIXED_FILE | REQ_F_BUFFER_SELECT))) return -EINVAL; @@ -435,7 +435,7 @@ static inline enum hrtimer_mode io_translate_timeout_mode(unsigned int flags) */ int io_timeout_remove(struct io_kiocb *req, unsigned int issue_flags) { - struct io_timeout_rem *tr = io_kiocb_to_cmd(req); + struct io_timeout_rem *tr = io_kiocb_to_cmd(req, struct io_timeout_rem); struct io_ring_ctx *ctx = req->ctx; int ret; @@ -466,7 +466,7 @@ static int __io_timeout_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe, bool is_timeout_link) { - struct io_timeout *timeout = io_kiocb_to_cmd(req); + struct io_timeout *timeout = io_kiocb_to_cmd(req, struct io_timeout); struct io_timeout_data *data; unsigned flags; u32 off = READ_ONCE(sqe->off); @@ -532,7 +532,7 @@ int io_link_timeout_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_timeout(struct io_kiocb *req, unsigned int issue_flags) { - struct io_timeout *timeout = io_kiocb_to_cmd(req); + struct io_timeout *timeout = io_kiocb_to_cmd(req, struct io_timeout); struct io_ring_ctx *ctx = req->ctx; struct io_timeout_data *data = req->async_data; struct list_head *entry; @@ -583,7 +583,7 @@ add: void io_queue_linked_timeout(struct io_kiocb *req) { - struct io_timeout *timeout = io_kiocb_to_cmd(req); + struct io_timeout *timeout = io_kiocb_to_cmd(req, struct io_timeout); struct io_ring_ctx *ctx = req->ctx; spin_lock_irq(&ctx->timeout_lock); diff --git a/io_uring/uring_cmd.c b/io_uring/uring_cmd.c index ee7036f2241f..478e86a9dfaf 100644 --- a/io_uring/uring_cmd.c +++ b/io_uring/uring_cmd.c @@ -11,7 +11,7 @@ static void io_uring_cmd_work(struct io_kiocb *req, bool *locked) { - struct io_uring_cmd *ioucmd = io_kiocb_to_cmd(req); + struct io_uring_cmd *ioucmd = io_kiocb_to_cmd(req, struct io_uring_cmd); ioucmd->task_work_cb(ioucmd); } @@ -55,7 +55,7 @@ EXPORT_SYMBOL_GPL(io_uring_cmd_done); int io_uring_cmd_prep_async(struct io_kiocb *req) { - struct io_uring_cmd *ioucmd = io_kiocb_to_cmd(req); + struct io_uring_cmd *ioucmd = io_kiocb_to_cmd(req, struct io_uring_cmd); size_t cmd_size; cmd_size = uring_cmd_pdu_size(req->ctx->flags & IORING_SETUP_SQE128); @@ -66,7 +66,7 @@ int io_uring_cmd_prep_async(struct io_kiocb *req) int io_uring_cmd_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_uring_cmd *ioucmd = io_kiocb_to_cmd(req); + struct io_uring_cmd *ioucmd = io_kiocb_to_cmd(req, struct io_uring_cmd); if (sqe->rw_flags || sqe->__pad1) return -EINVAL; @@ -77,7 +77,7 @@ int io_uring_cmd_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_uring_cmd(struct io_kiocb *req, unsigned int issue_flags) { - struct io_uring_cmd *ioucmd = io_kiocb_to_cmd(req); + struct io_uring_cmd *ioucmd = io_kiocb_to_cmd(req, struct io_uring_cmd); struct io_ring_ctx *ctx = req->ctx; struct file *file = req->file; int ret; diff --git a/io_uring/xattr.c b/io_uring/xattr.c index b179f9acd5ac..84180afd090b 100644 --- a/io_uring/xattr.c +++ b/io_uring/xattr.c @@ -24,7 +24,7 @@ struct io_xattr { void io_xattr_cleanup(struct io_kiocb *req) { - struct io_xattr *ix = io_kiocb_to_cmd(req); + struct io_xattr *ix = io_kiocb_to_cmd(req, struct io_xattr); if (ix->filename) putname(ix->filename); @@ -44,7 +44,7 @@ static void io_xattr_finish(struct io_kiocb *req, int ret) static int __io_getxattr_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_xattr *ix = io_kiocb_to_cmd(req); + struct io_xattr *ix = io_kiocb_to_cmd(req, struct io_xattr); const char __user *name; int ret; @@ -85,7 +85,7 @@ int io_fgetxattr_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_getxattr_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_xattr *ix = io_kiocb_to_cmd(req); + struct io_xattr *ix = io_kiocb_to_cmd(req, struct io_xattr); const char __user *path; int ret; @@ -106,7 +106,7 @@ int io_getxattr_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) int io_fgetxattr(struct io_kiocb *req, unsigned int issue_flags) { - struct io_xattr *ix = io_kiocb_to_cmd(req); + struct io_xattr *ix = io_kiocb_to_cmd(req, struct io_xattr); int ret; if (issue_flags & IO_URING_F_NONBLOCK) @@ -122,7 +122,7 @@ int io_fgetxattr(struct io_kiocb *req, unsigned int issue_flags) int io_getxattr(struct io_kiocb *req, unsigned int issue_flags) { - struct io_xattr *ix = io_kiocb_to_cmd(req); + struct io_xattr *ix = io_kiocb_to_cmd(req, struct io_xattr); unsigned int lookup_flags = LOOKUP_FOLLOW; struct path path; int ret; @@ -151,7 +151,7 @@ retry: static int __io_setxattr_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_xattr *ix = io_kiocb_to_cmd(req); + struct io_xattr *ix = io_kiocb_to_cmd(req, struct io_xattr); const char __user *name; int ret; @@ -181,7 +181,7 @@ static int __io_setxattr_prep(struct io_kiocb *req, int io_setxattr_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) { - struct io_xattr *ix = io_kiocb_to_cmd(req); + struct io_xattr *ix = io_kiocb_to_cmd(req, struct io_xattr); const char __user *path; int ret; @@ -208,7 +208,7 @@ int io_fsetxattr_prep(struct io_kiocb *req, const struct io_uring_sqe *sqe) static int __io_setxattr(struct io_kiocb *req, unsigned int issue_flags, struct path *path) { - struct io_xattr *ix = io_kiocb_to_cmd(req); + struct io_xattr *ix = io_kiocb_to_cmd(req, struct io_xattr); int ret; ret = mnt_want_write(path->mnt); @@ -234,7 +234,7 @@ int io_fsetxattr(struct io_kiocb *req, unsigned int issue_flags) int io_setxattr(struct io_kiocb *req, unsigned int issue_flags) { - struct io_xattr *ix = io_kiocb_to_cmd(req); + struct io_xattr *ix = io_kiocb_to_cmd(req, struct io_xattr); unsigned int lookup_flags = LOOKUP_FOLLOW; struct path path; int ret; -- cgit v1.2.3 From 9c71d39aa0f40d4e6bfe14958045a42c722bd327 Mon Sep 17 00:00:00 2001 From: Stefan Metzmacher Date: Thu, 11 Aug 2022 09:11:16 +0200 Subject: io_uring: add missing BUILD_BUG_ON() checks for new io_uring_sqe fields Signed-off-by: Stefan Metzmacher Link: https://lore.kernel.org/r/ffcaf8dc4778db4af673822df60dbda6efdd3065.1660201408.git.metze@samba.org Signed-off-by: Jens Axboe --- io_uring/io_uring.c | 19 ++++++++++++++++--- io_uring/uring_cmd.c | 3 +++ 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/io_uring/io_uring.c b/io_uring/io_uring.c index b54218da075c..ebfdb2212ec2 100644 --- a/io_uring/io_uring.c +++ b/io_uring/io_uring.c @@ -3885,13 +3885,15 @@ out_fput: static int __init io_uring_init(void) { -#define __BUILD_BUG_VERIFY_ELEMENT(stype, eoffset, etype, ename) do { \ +#define __BUILD_BUG_VERIFY_OFFSET_SIZE(stype, eoffset, esize, ename) do { \ BUILD_BUG_ON(offsetof(stype, ename) != eoffset); \ - BUILD_BUG_ON(sizeof(etype) != sizeof_field(stype, ename)); \ + BUILD_BUG_ON(sizeof_field(stype, ename) != esize); \ } while (0) #define BUILD_BUG_SQE_ELEM(eoffset, etype, ename) \ - __BUILD_BUG_VERIFY_ELEMENT(struct io_uring_sqe, eoffset, etype, ename) + __BUILD_BUG_VERIFY_OFFSET_SIZE(struct io_uring_sqe, eoffset, sizeof(etype), ename) +#define BUILD_BUG_SQE_ELEM_SIZE(eoffset, esize, ename) \ + __BUILD_BUG_VERIFY_OFFSET_SIZE(struct io_uring_sqe, eoffset, esize, ename) BUILD_BUG_ON(sizeof(struct io_uring_sqe) != 64); BUILD_BUG_SQE_ELEM(0, __u8, opcode); BUILD_BUG_SQE_ELEM(1, __u8, flags); @@ -3899,6 +3901,8 @@ static int __init io_uring_init(void) BUILD_BUG_SQE_ELEM(4, __s32, fd); BUILD_BUG_SQE_ELEM(8, __u64, off); BUILD_BUG_SQE_ELEM(8, __u64, addr2); + BUILD_BUG_SQE_ELEM(8, __u32, cmd_op); + BUILD_BUG_SQE_ELEM(12, __u32, __pad1); BUILD_BUG_SQE_ELEM(16, __u64, addr); BUILD_BUG_SQE_ELEM(16, __u64, splice_off_in); BUILD_BUG_SQE_ELEM(24, __u32, len); @@ -3917,13 +3921,22 @@ static int __init io_uring_init(void) BUILD_BUG_SQE_ELEM(28, __u32, statx_flags); BUILD_BUG_SQE_ELEM(28, __u32, fadvise_advice); BUILD_BUG_SQE_ELEM(28, __u32, splice_flags); + BUILD_BUG_SQE_ELEM(28, __u32, rename_flags); + BUILD_BUG_SQE_ELEM(28, __u32, unlink_flags); + BUILD_BUG_SQE_ELEM(28, __u32, hardlink_flags); + BUILD_BUG_SQE_ELEM(28, __u32, xattr_flags); + BUILD_BUG_SQE_ELEM(28, __u32, msg_ring_flags); BUILD_BUG_SQE_ELEM(32, __u64, user_data); BUILD_BUG_SQE_ELEM(40, __u16, buf_index); BUILD_BUG_SQE_ELEM(40, __u16, buf_group); BUILD_BUG_SQE_ELEM(42, __u16, personality); BUILD_BUG_SQE_ELEM(44, __s32, splice_fd_in); BUILD_BUG_SQE_ELEM(44, __u32, file_index); + BUILD_BUG_SQE_ELEM(44, __u16, notification_idx); + BUILD_BUG_SQE_ELEM(46, __u16, addr_len); BUILD_BUG_SQE_ELEM(48, __u64, addr3); + BUILD_BUG_SQE_ELEM_SIZE(48, 0, cmd); + BUILD_BUG_SQE_ELEM(56, __u64, __pad2); BUILD_BUG_ON(sizeof(struct io_uring_files_update) != sizeof(struct io_uring_rsrc_update)); diff --git a/io_uring/uring_cmd.c b/io_uring/uring_cmd.c index 478e86a9dfaf..8e0cc2d9205e 100644 --- a/io_uring/uring_cmd.c +++ b/io_uring/uring_cmd.c @@ -58,6 +58,9 @@ int io_uring_cmd_prep_async(struct io_kiocb *req) struct io_uring_cmd *ioucmd = io_kiocb_to_cmd(req, struct io_uring_cmd); size_t cmd_size; + BUILD_BUG_ON(uring_cmd_pdu_size(0) != 16); + BUILD_BUG_ON(uring_cmd_pdu_size(1) != 80); + cmd_size = uring_cmd_pdu_size(req->ctx->flags & IORING_SETUP_SQE128); memcpy(req->async_data, ioucmd->cmd, cmd_size); -- cgit v1.2.3 From 61d5e2a251fb20c2c5e998c3f1d52ed6d5360319 Mon Sep 17 00:00:00 2001 From: Csókás Bence Date: Thu, 11 Aug 2022 12:13:49 +0200 Subject: fec: Fix timer capture timing in `fec_ptp_enable_pps()` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Code reimplements functionality already in `fec_ptp_read()`, but misses check for FEC_QUIRK_BUG_CAPTURE. Replace with function call. Fixes: 28b5f058cf1d ("net: fec: ptp: fix convergence issue to support LinuxPTP stack") Signed-off-by: Csókás Bence Link: https://lore.kernel.org/r/20220811101348.13755-1-csokas.bence@prolan.hu Signed-off-by: Jakub Kicinski --- drivers/net/ethernet/freescale/fec_ptp.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/net/ethernet/freescale/fec_ptp.c b/drivers/net/ethernet/freescale/fec_ptp.c index 7d49c28215f3..3dc3c0b626c2 100644 --- a/drivers/net/ethernet/freescale/fec_ptp.c +++ b/drivers/net/ethernet/freescale/fec_ptp.c @@ -135,11 +135,7 @@ static int fec_ptp_enable_pps(struct fec_enet_private *fep, uint enable) * NSEC_PER_SEC - ts.tv_nsec. Add the remaining nanoseconds * to current timer would be next second. */ - tempval = readl(fep->hwp + FEC_ATIME_CTRL); - tempval |= FEC_T_CTRL_CAPTURE; - writel(tempval, fep->hwp + FEC_ATIME_CTRL); - - tempval = readl(fep->hwp + FEC_ATIME); + tempval = fep->cc.read(&fep->cc); /* Convert the ptp local counter to 1588 timestamp */ ns = timecounter_cyc2time(&fep->tc, tempval); ts = ns_to_timespec64(ns); -- cgit v1.2.3 From 246bbf2f977ea36aaf41f5d24370fef433250728 Mon Sep 17 00:00:00 2001 From: Sergei Antonov Date: Thu, 11 Aug 2022 10:09:39 +0300 Subject: net: dsa: mv88e6060: prevent crash on an unused port If the port isn't a CPU port nor a user port, 'cpu_dp' is a null pointer and a crash happened on dereferencing it in mv88e6060_setup_port(): [ 9.575872] Unable to handle kernel NULL pointer dereference at virtual address 00000014 ... [ 9.942216] mv88e6060_setup from dsa_register_switch+0x814/0xe84 [ 9.948616] dsa_register_switch from mdio_probe+0x2c/0x54 [ 9.954433] mdio_probe from really_probe.part.0+0x98/0x2a0 [ 9.960375] really_probe.part.0 from driver_probe_device+0x30/0x10c [ 9.967029] driver_probe_device from __device_attach_driver+0xb8/0x13c [ 9.973946] __device_attach_driver from bus_for_each_drv+0x90/0xe0 [ 9.980509] bus_for_each_drv from __device_attach+0x110/0x184 [ 9.986632] __device_attach from bus_probe_device+0x8c/0x94 [ 9.992577] bus_probe_device from deferred_probe_work_func+0x78/0xa8 [ 9.999311] deferred_probe_work_func from process_one_work+0x290/0x73c [ 10.006292] process_one_work from worker_thread+0x30/0x4b8 [ 10.012155] worker_thread from kthread+0xd4/0x10c [ 10.017238] kthread from ret_from_fork+0x14/0x3c Fixes: 0abfd494deef ("net: dsa: use dedicated CPU port") CC: Vivien Didelot CC: Florian Fainelli Signed-off-by: Sergei Antonov Signed-off-by: Vladimir Oltean Link: https://lore.kernel.org/r/20220811070939.1717146-1-saproj@gmail.com Signed-off-by: Jakub Kicinski --- drivers/net/dsa/mv88e6060.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/dsa/mv88e6060.c b/drivers/net/dsa/mv88e6060.c index a4c6eb9a52d0..83dca9179aa0 100644 --- a/drivers/net/dsa/mv88e6060.c +++ b/drivers/net/dsa/mv88e6060.c @@ -118,6 +118,9 @@ static int mv88e6060_setup_port(struct mv88e6060_priv *priv, int p) int addr = REG_PORT(p); int ret; + if (dsa_is_unused_port(priv->ds, p)) + return 0; + /* Do not force flow control, disable Ingress and Egress * Header tagging, disable VLAN tunneling, and set the port * state to Forwarding. Additionally, if this is the CPU -- cgit v1.2.3 From 777885673122b78b2abd2f1e428730961a786ff2 Mon Sep 17 00:00:00 2001 From: Hongbin Wang Date: Thu, 11 Aug 2022 23:38:33 -0400 Subject: ip6_tunnel: Fix the type of functions Functions ip6_tnl_change, ip6_tnl_update and ip6_tnl0_update do always return 0, change the type of functions to void. Signed-off-by: Hongbin Wang Signed-off-by: David S. Miller --- net/ipv6/ip6_tunnel.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/net/ipv6/ip6_tunnel.c b/net/ipv6/ip6_tunnel.c index 3fda5634578c..79c6a827dea9 100644 --- a/net/ipv6/ip6_tunnel.c +++ b/net/ipv6/ip6_tunnel.c @@ -1517,7 +1517,7 @@ static void ip6_tnl_link_config(struct ip6_tnl *t) * ip6_tnl_change() updates the tunnel parameters **/ -static int +static void ip6_tnl_change(struct ip6_tnl *t, const struct __ip6_tnl_parm *p) { t->parms.laddr = p->laddr; @@ -1531,29 +1531,25 @@ ip6_tnl_change(struct ip6_tnl *t, const struct __ip6_tnl_parm *p) t->parms.fwmark = p->fwmark; dst_cache_reset(&t->dst_cache); ip6_tnl_link_config(t); - return 0; } -static int ip6_tnl_update(struct ip6_tnl *t, struct __ip6_tnl_parm *p) +static void ip6_tnl_update(struct ip6_tnl *t, struct __ip6_tnl_parm *p) { struct net *net = t->net; struct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id); - int err; ip6_tnl_unlink(ip6n, t); synchronize_net(); - err = ip6_tnl_change(t, p); + ip6_tnl_change(t, p); ip6_tnl_link(ip6n, t); netdev_state_change(t->dev); - return err; } -static int ip6_tnl0_update(struct ip6_tnl *t, struct __ip6_tnl_parm *p) +static void ip6_tnl0_update(struct ip6_tnl *t, struct __ip6_tnl_parm *p) { /* for default tnl0 device allow to change only the proto */ t->parms.proto = p->proto; netdev_state_change(t->dev); - return 0; } static void @@ -1667,9 +1663,9 @@ ip6_tnl_siocdevprivate(struct net_device *dev, struct ifreq *ifr, } else t = netdev_priv(dev); if (dev == ip6n->fb_tnl_dev) - err = ip6_tnl0_update(t, &p1); + ip6_tnl0_update(t, &p1); else - err = ip6_tnl_update(t, &p1); + ip6_tnl_update(t, &p1); } if (!IS_ERR(t)) { err = 0; @@ -2091,7 +2087,8 @@ static int ip6_tnl_changelink(struct net_device *dev, struct nlattr *tb[], } else t = netdev_priv(dev); - return ip6_tnl_update(t, &p); + ip6_tnl_update(t, &p); + return 0; } static void ip6_tnl_dellink(struct net_device *dev, struct list_head *head) -- cgit v1.2.3 From 099b157c08e8e8faa622d4bb70826ae179248fd4 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 12 Aug 2022 16:09:36 -0700 Subject: perf jevent: Add an 'all' architecture argument When 'all' is passed as the architecture generate a mapping table for all architectures. This simplifies testing. To identify the table for an architecture add an arch variable to the pmu_events_map. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Stephane Eranian Cc: Will Deacon Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220812230949.683239-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/empty-pmu-events.c | 2 + tools/perf/pmu-events/jevents.py | 70 ++++++++++++++++++++------------ tools/perf/pmu-events/pmu-events.h | 1 + tools/perf/tests/pmu-events.c | 3 +- 4 files changed, 47 insertions(+), 29 deletions(-) diff --git a/tools/perf/pmu-events/empty-pmu-events.c b/tools/perf/pmu-events/empty-pmu-events.c index 77e655c6f116..d8cf9283e486 100644 --- a/tools/perf/pmu-events/empty-pmu-events.c +++ b/tools/perf/pmu-events/empty-pmu-events.c @@ -110,12 +110,14 @@ static const struct pmu_event pme_test_soc_cpu[] = { const struct pmu_events_map pmu_events_map[] = { { + .arch = "testarch", .cpuid = "testcpu", .version = "v1", .type = "core", .table = pme_test_soc_cpu, }, { + .arch = 0, .cpuid = 0, .version = 0, .type = 0, diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index c5c9bb186abd..b49a0dd946b7 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -305,38 +305,45 @@ def process_one_file(parents: Sequence[str], item: os.DirEntry) -> None: print_events_table_entries(item, get_topic(item.name)) -def print_mapping_table() -> None: +def print_mapping_table(archs: Sequence[str]) -> None: """Read the mapfile and generate the struct from cpuid string to event table.""" - with open(f'{_args.starting_dir}/{_args.arch}/mapfile.csv') as csvfile: - table = csv.reader(csvfile) - _args.output_file.write( - 'const struct pmu_events_map pmu_events_map[] = {\n') - first = True - for row in table: - # Skip the first row or any row beginning with #. - if not first and len(row) > 0 and not row[0].startswith('#'): - tblname = file_name_to_table_name([], row[2].replace('/', '_')) - _args.output_file.write("""{ -\t.cpuid = \"%s\", -\t.version = \"%s\", -\t.type = \"%s\", -\t.table = %s -}, -""" % (row[0].replace('\\', '\\\\'), row[1], row[3], tblname)) - first = False - - _args.output_file.write("""{ + _args.output_file.write('const struct pmu_events_map pmu_events_map[] = {\n') + for arch in archs: + if arch == 'test': + _args.output_file.write("""{ +\t.arch = "testarch", \t.cpuid = "testcpu", \t.version = "v1", \t.type = "core", \t.table = pme_test_soc_cpu, }, -{ +""") + else: + with open(f'{_args.starting_dir}/{arch}/mapfile.csv') as csvfile: + table = csv.reader(csvfile) + first = True + for row in table: + # Skip the first row or any row beginning with #. + if not first and len(row) > 0 and not row[0].startswith('#'): + tblname = file_name_to_table_name([], row[2].replace('/', '_')) + cpuid = row[0].replace('\\', '\\\\') + _args.output_file.write(f"""{{ +\t.arch = "{arch}", +\t.cpuid = "{cpuid}", +\t.version = "{row[1]}", +\t.type = "{row[3]}", +\t.table = {tblname} +}}, +""") + first = False + + _args.output_file.write("""{ +\t.arch = 0, \t.cpuid = 0, \t.version = 0, \t.type = 0, \t.table = 0, -}, +} }; """) @@ -387,15 +394,24 @@ def main() -> None: _args = ap.parse_args() _args.output_file.write("#include \"pmu-events/pmu-events.h\"\n") - for path in [_args.arch, 'test']: - arch_path = f'{_args.starting_dir}/{path}' - if not os.path.isdir(arch_path): - raise IOError(f'Missing architecture directory in \'{arch_path}\'') + archs = [] + for item in os.scandir(_args.starting_dir): + if not item.is_dir(): + continue + if item.name == _args.arch or _args.arch == 'all' or item.name == 'test': + archs.append(item.name) + + if len(archs) < 2: + raise IOError(f'Missing architecture directory \'{_args.arch}\'') + + archs.sort() + for arch in archs: + arch_path = f'{_args.starting_dir}/{arch}' preprocess_arch_std_files(arch_path) ftw(arch_path, [], process_one_file) print_events_table_suffix() - print_mapping_table() + print_mapping_table(archs) print_system_mapping_table() diff --git a/tools/perf/pmu-events/pmu-events.h b/tools/perf/pmu-events/pmu-events.h index 6efe73976440..7a360792635f 100644 --- a/tools/perf/pmu-events/pmu-events.h +++ b/tools/perf/pmu-events/pmu-events.h @@ -38,6 +38,7 @@ struct pmu_event { * The cpuid can contain any character other than the comma. */ struct pmu_events_map { + const char *arch; const char *cpuid; const char *version; const char *type; /* core, uncore etc */ diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index 263cbb67c861..82192f1a7bf7 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -864,8 +864,7 @@ static void expr_failure(const char *msg, const struct pmu_events_map *map, const struct pmu_event *pe) { - pr_debug("%s for map %s %s %s\n", - msg, map->cpuid, map->version, map->type); + pr_debug("%s for map %s %s\n", msg, map->arch, map->cpuid); pr_debug("On metric %s\n", pe->metric_name); pr_debug("On expression %s\n", pe->metric_expr); } -- cgit v1.2.3 From f793ae185e27645ad83942ef6fffd901b8169941 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 12 Aug 2022 16:09:37 -0700 Subject: perf jevents: Remove the type/version variables pmu_events_map has a type variable that is always initialized to "core" and a version variable that is never read. Remove these from the API as it is straightforward to add them back when necessary. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Stephane Eranian Cc: Will Deacon Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220812230949.683239-3-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/empty-pmu-events.c | 4 ---- tools/perf/pmu-events/jevents.py | 6 ------ tools/perf/pmu-events/pmu-events.h | 2 -- tools/perf/tests/expand-cgroup.c | 2 -- tools/perf/tests/parse-metric.c | 2 -- 5 files changed, 16 deletions(-) diff --git a/tools/perf/pmu-events/empty-pmu-events.c b/tools/perf/pmu-events/empty-pmu-events.c index d8cf9283e486..4182a986f505 100644 --- a/tools/perf/pmu-events/empty-pmu-events.c +++ b/tools/perf/pmu-events/empty-pmu-events.c @@ -112,15 +112,11 @@ const struct pmu_events_map pmu_events_map[] = { { .arch = "testarch", .cpuid = "testcpu", - .version = "v1", - .type = "core", .table = pme_test_soc_cpu, }, { .arch = 0, .cpuid = 0, - .version = 0, - .type = 0, .table = 0, }, }; diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index b49a0dd946b7..8e8462cb359b 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -313,8 +313,6 @@ def print_mapping_table(archs: Sequence[str]) -> None: _args.output_file.write("""{ \t.arch = "testarch", \t.cpuid = "testcpu", -\t.version = "v1", -\t.type = "core", \t.table = pme_test_soc_cpu, }, """) @@ -330,8 +328,6 @@ def print_mapping_table(archs: Sequence[str]) -> None: _args.output_file.write(f"""{{ \t.arch = "{arch}", \t.cpuid = "{cpuid}", -\t.version = "{row[1]}", -\t.type = "{row[3]}", \t.table = {tblname} }}, """) @@ -340,8 +336,6 @@ def print_mapping_table(archs: Sequence[str]) -> None: _args.output_file.write("""{ \t.arch = 0, \t.cpuid = 0, -\t.version = 0, -\t.type = 0, \t.table = 0, } }; diff --git a/tools/perf/pmu-events/pmu-events.h b/tools/perf/pmu-events/pmu-events.h index 7a360792635f..a491b117c8ac 100644 --- a/tools/perf/pmu-events/pmu-events.h +++ b/tools/perf/pmu-events/pmu-events.h @@ -40,8 +40,6 @@ struct pmu_event { struct pmu_events_map { const char *arch; const char *cpuid; - const char *version; - const char *type; /* core, uncore etc */ const struct pmu_event *table; }; diff --git a/tools/perf/tests/expand-cgroup.c b/tools/perf/tests/expand-cgroup.c index dfefe5b60eb2..dc4038f997d7 100644 --- a/tools/perf/tests/expand-cgroup.c +++ b/tools/perf/tests/expand-cgroup.c @@ -197,8 +197,6 @@ static int expand_metric_events(void) }; const struct pmu_events_map ev_map = { .cpuid = "test", - .version = "1", - .type = "core", .table = pme_test, }; diff --git a/tools/perf/tests/parse-metric.c b/tools/perf/tests/parse-metric.c index 07b6f4ec024f..1b811a26f4ee 100644 --- a/tools/perf/tests/parse-metric.c +++ b/tools/perf/tests/parse-metric.c @@ -81,8 +81,6 @@ static struct pmu_event pme_test[] = { static const struct pmu_events_map map = { .cpuid = "test", - .version = "1", - .type = "core", .table = pme_test, }; -- cgit v1.2.3 From ee2ce6fdc8021979346f71056938c60335a7570c Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 12 Aug 2022 16:09:38 -0700 Subject: perf jevents: Provide path to JSON file on error If a JSONDecoderError or similar is raised then it is useful to know the path. Print this and then raise the exception agan. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Stephane Eranian Cc: Will Deacon Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220812230949.683239-4-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/jevents.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index 8e8462cb359b..31936eafa9ff 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -225,7 +225,12 @@ class JsonEvent: def read_json_events(path: str) -> Sequence[JsonEvent]: """Read json events from the specified file.""" - return json.load(open(path), object_hook=lambda d: JsonEvent(d)) + + try: + return json.load(open(path), object_hook=lambda d: JsonEvent(d)) + except BaseException as err: + print(f"Exception processing {path}") + raise def preprocess_arch_std_files(archpath: str) -> None: -- cgit v1.2.3 From 7b2f844c43cef59740095dfa1f6366f3dfb318dc Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 12 Aug 2022 16:09:39 -0700 Subject: perf jevents: Sort JSON files entries Sort the JSON files entries on conversion to C. The sort order tries to replicated cmp_sevent from pmu.c so that the input there is already sorted except for sysfs events. Specifically, the sort order is given by the tuple: (not j.desc is None, fix_none(j.topic), fix_none(j.name), fix_none(j.pmu), fix_none(j.metric_name)) which is putting events with descriptions and topics before those without, then sorting by name, then pmu and finally metric_name Add the topic to JsonEvent on reading to simplify. Remove an unnecessary lambda in the JSON reading. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Stephane Eranian Cc: Will Deacon Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220812230949.683239-5-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/jevents.py | 48 +++++++++++++++++++++++++++++----------- 1 file changed, 35 insertions(+), 13 deletions(-) diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index 31936eafa9ff..84fbb0f384cc 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -18,6 +18,8 @@ _sys_event_tables = [] _arch_std_events = {} # Track whether an events table is currently being defined and needs closing. _close_table = False +# Events to write out when the table is closed +_pending_events = [] def removesuffix(s: str, suffix: str) -> str: @@ -128,6 +130,7 @@ class JsonEvent: eventcode |= int(jd['ExtSel']) << 8 configcode = int(jd['ConfigCode'], 0) if 'ConfigCode' in jd else None self.name = jd['EventName'].lower() if 'EventName' in jd else None + self.topic = '' self.compat = jd.get('Compat') self.desc = fixdesc(jd.get('BriefDescription')) self.long_desc = fixdesc(jd.get('PublicDescription')) @@ -200,7 +203,7 @@ class JsonEvent: s += f'\t{attr} = {value},\n' return s + '}' - def to_c_string(self, topic_local: str) -> str: + def to_c_string(self) -> str: """Representation of the event as a C struct initializer.""" def attr_string(attr: str, value: str) -> str: @@ -212,25 +215,27 @@ class JsonEvent: return attr_string(attr, getattr(self, attr)) s = '{\n' - s += f'\t.topic = "{topic_local}",\n' for attr in [ 'aggr_mode', 'compat', 'deprecated', 'desc', 'event', 'long_desc', 'metric_constraint', 'metric_expr', 'metric_group', 'metric_name', - 'name', 'perpkg', 'pmu', 'unit' + 'name', 'perpkg', 'pmu', 'topic', 'unit' ]: s += str_if_present(self, attr) s += '},\n' return s -def read_json_events(path: str) -> Sequence[JsonEvent]: +def read_json_events(path: str, topic: str) -> Sequence[JsonEvent]: """Read json events from the specified file.""" try: - return json.load(open(path), object_hook=lambda d: JsonEvent(d)) + result = json.load(open(path), object_hook=JsonEvent) except BaseException as err: print(f"Exception processing {path}") raise + for event in result: + event.topic = topic + return result def preprocess_arch_std_files(archpath: str) -> None: @@ -238,7 +243,7 @@ def preprocess_arch_std_files(archpath: str) -> None: global _arch_std_events for item in os.scandir(archpath): if item.is_file() and item.name.endswith('.json'): - for event in read_json_events(item.path): + for event in read_json_events(item.path, topic=''): if event.name: _arch_std_events[event.name.lower()] = event @@ -252,19 +257,36 @@ def print_events_table_prefix(tblname: str) -> None: _close_table = True -def print_events_table_entries(item: os.DirEntry, topic: str) -> None: - """Create contents of an events table.""" +def add_events_table_entries(item: os.DirEntry, topic: str) -> None: + """Add contents of file to _pending_events table.""" if not _close_table: raise IOError('Table entries missing prefix') - for event in read_json_events(item.path): - _args.output_file.write(event.to_c_string(topic)) + for e in read_json_events(item.path, topic): + _pending_events.append(e) def print_events_table_suffix() -> None: """Optionally close events table.""" + + def event_cmp_key(j: JsonEvent): + def fix_none(s: str): + if s is None: + return '' + return s + + return (not j.desc is None, fix_none(j.topic), fix_none(j.name), fix_none(j.pmu), + fix_none(j.metric_name)) + global _close_table - if _close_table: - _args.output_file.write("""{ + if not _close_table: + return + + global _pending_events + for event in sorted(_pending_events, key=event_cmp_key): + _args.output_file.write(event.to_c_string()) + _pending_events = [] + + _args.output_file.write("""{ \t.name = 0, \t.event = 0, \t.desc = 0, @@ -307,7 +329,7 @@ def process_one_file(parents: Sequence[str], item: os.DirEntry) -> None: if not item.is_file() or not item.name.endswith('.json'): return - print_events_table_entries(item, get_topic(item.name)) + add_events_table_entries(item, get_topic(item.name)) def print_mapping_table(archs: Sequence[str]) -> None: -- cgit v1.2.3 From 2519db2a9dc4f7ca5c1ad8309c51262e5b8ef89f Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 12 Aug 2022 16:09:40 -0700 Subject: perf pmu-events: Hide pmu_sys_event_tables Move usage of the table to pmu-events.c so it may be hidden. By abstracting the table the implementation can later be changed. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Stephane Eranian Cc: Will Deacon Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220812230949.683239-6-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/empty-pmu-events.c | 37 +++++++++++++++++++++++++- tools/perf/pmu-events/jevents.py | 45 +++++++++++++++++++++++++++++--- tools/perf/pmu-events/pmu-events.h | 11 ++++---- tools/perf/tests/pmu-events.c | 14 +--------- tools/perf/util/pmu.c | 27 ------------------- tools/perf/util/pmu.h | 2 -- 6 files changed, 84 insertions(+), 52 deletions(-) diff --git a/tools/perf/pmu-events/empty-pmu-events.c b/tools/perf/pmu-events/empty-pmu-events.c index 4182a986f505..216ea0482c37 100644 --- a/tools/perf/pmu-events/empty-pmu-events.c +++ b/tools/perf/pmu-events/empty-pmu-events.c @@ -6,6 +6,8 @@ * The test cpu/soc is provided for testing. */ #include "pmu-events/pmu-events.h" +#include +#include static const struct pmu_event pme_test_soc_cpu[] = { { @@ -145,7 +147,12 @@ static const struct pmu_event pme_test_soc_sys[] = { }, }; -const struct pmu_sys_events pmu_sys_event_tables[] = { +struct pmu_sys_events { + const char *name; + const struct pmu_event *table; +}; + +static const struct pmu_sys_events pmu_sys_event_tables[] = { { .table = pme_test_soc_sys, .name = "pme_test_soc_sys", @@ -154,3 +161,31 @@ const struct pmu_sys_events pmu_sys_event_tables[] = { .table = 0 }, }; + +const struct pmu_event *find_sys_events_table(const char *name) +{ + for (const struct pmu_sys_events *tables = &pmu_sys_event_tables[0]; + tables->name; + tables++) { + if (!strcmp(tables->name, name)) + return tables->table; + } + return NULL; +} + +int pmu_for_each_sys_event(pmu_event_iter_fn fn, void *data) +{ + for (const struct pmu_sys_events *tables = &pmu_sys_event_tables[0]; + tables->name; + tables++) { + for (const struct pmu_event *pe = &tables->table[0]; + pe->name || pe->metric_group || pe->metric_name; + pe++) { + int ret = fn(pe, data); + + if (ret) + return ret; + } + } + return 0; +} diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index 84fbb0f384cc..8f929dd3e065 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -371,8 +371,14 @@ def print_mapping_table(archs: Sequence[str]) -> None: def print_system_mapping_table() -> None: """C struct mapping table array for tables from /sys directories.""" - _args.output_file.write( - '\nconst struct pmu_sys_events pmu_sys_event_tables[] = {\n') + _args.output_file.write(""" +struct pmu_sys_events { +\tconst char *name; +\tconst struct pmu_event *table; +}; + +static const struct pmu_sys_events pmu_sys_event_tables[] = { +""") for tblname in _sys_event_tables: _args.output_file.write(f"""\t{{ \t\t.table = {tblname}, @@ -383,6 +389,34 @@ def print_system_mapping_table() -> None: \t\t.table = 0 \t}, }; + +const struct pmu_event *find_sys_events_table(const char *name) +{ + for (const struct pmu_sys_events *tables = &pmu_sys_event_tables[0]; + tables->name; + tables++) { + if (!strcmp(tables->name, name)) + return tables->table; + } + return NULL; +} + +int pmu_for_each_sys_event(pmu_event_iter_fn fn, void *data) +{ + for (const struct pmu_sys_events *tables = &pmu_sys_event_tables[0]; + tables->name; + tables++) { + for (const struct pmu_event *pe = &tables->table[0]; + pe->name || pe->metric_group || pe->metric_name; + pe++) { + int ret = fn(pe, data); + + if (ret) + return ret; + } + } + return 0; +} """) @@ -414,7 +448,12 @@ def main() -> None: 'output_file', type=argparse.FileType('w'), nargs='?', default=sys.stdout) _args = ap.parse_args() - _args.output_file.write("#include \"pmu-events/pmu-events.h\"\n") + _args.output_file.write(""" +#include "pmu-events/pmu-events.h" +#include +#include + +""") archs = [] for item in os.scandir(_args.starting_dir): if not item.is_dir(): diff --git a/tools/perf/pmu-events/pmu-events.h b/tools/perf/pmu-events/pmu-events.h index a491b117c8ac..2386212b1df0 100644 --- a/tools/perf/pmu-events/pmu-events.h +++ b/tools/perf/pmu-events/pmu-events.h @@ -43,16 +43,15 @@ struct pmu_events_map { const struct pmu_event *table; }; -struct pmu_sys_events { - const char *name; - const struct pmu_event *table; -}; - /* * Global table mapping each known CPU for the architecture to its * table of PMU events. */ extern const struct pmu_events_map pmu_events_map[]; -extern const struct pmu_sys_events pmu_sys_event_tables[]; + +const struct pmu_event *find_sys_events_table(const char *name); + +typedef int (*pmu_event_iter_fn)(const struct pmu_event *pe, void *data); +int pmu_for_each_sys_event(pmu_event_iter_fn fn, void *data); #endif diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index 82192f1a7bf7..a39a2c99ede6 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -286,18 +286,6 @@ static const struct pmu_events_map *__test_pmu_get_events_map(void) return NULL; } -static const struct pmu_event *__test_pmu_get_sys_events_table(void) -{ - const struct pmu_sys_events *tables = &pmu_sys_event_tables[0]; - - for ( ; tables->name; tables++) { - if (!strcmp("pme_test_soc_sys", tables->name)) - return tables->table; - } - - return NULL; -} - static int compare_pmu_events(const struct pmu_event *e1, const struct pmu_event *e2) { if (!is_same(e1->name, e2->name)) { @@ -451,7 +439,7 @@ static int compare_alias_to_test_event(struct perf_pmu_alias *alias, static int test__pmu_event_table(struct test_suite *test __maybe_unused, int subtest __maybe_unused) { - const struct pmu_event *sys_event_tables = __test_pmu_get_sys_events_table(); + const struct pmu_event *sys_event_tables = find_sys_events_table("pme_test_soc_sys"); const struct pmu_events_map *map = __test_pmu_get_events_map(); const struct pmu_event *table; int map_events = 0, expected_events; diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 0112e1c36418..d8717c4548a4 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -868,33 +868,6 @@ static void pmu_add_cpu_aliases(struct list_head *head, struct perf_pmu *pmu) pmu_add_cpu_aliases_map(head, pmu, map); } -void pmu_for_each_sys_event(pmu_sys_event_iter_fn fn, void *data) -{ - int i = 0; - - while (1) { - const struct pmu_sys_events *event_table; - int j = 0; - - event_table = &pmu_sys_event_tables[i++]; - - if (!event_table->table) - break; - - while (1) { - const struct pmu_event *pe = &event_table->table[j++]; - int ret; - - if (!pe->name && !pe->metric_group && !pe->metric_name) - break; - - ret = fn(pe, data); - if (ret) - break; - } - } -} - struct pmu_sys_event_iter_data { struct list_head *head; struct perf_pmu *pmu; diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h index 4b45fd8da5a3..7e667eec2a01 100644 --- a/tools/perf/util/pmu.h +++ b/tools/perf/util/pmu.h @@ -133,8 +133,6 @@ const struct pmu_events_map *pmu_events_map__find(void); bool pmu_uncore_alias_match(const char *pmu_name, const char *name); void perf_pmu_free_alias(struct perf_pmu_alias *alias); -typedef int (*pmu_sys_event_iter_fn)(const struct pmu_event *pe, void *data); -void pmu_for_each_sys_event(pmu_sys_event_iter_fn fn, void *data); int perf_pmu__convert_scale(const char *scale, char **end, double *sval); int perf_pmu__caps_parse(struct perf_pmu *pmu); -- cgit v1.2.3 From eeac7730418563152b0e3172bce9bac4ff6d6bc4 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 12 Aug 2022 16:09:41 -0700 Subject: perf pmu-events: Avoid passing pmu_events_map Preparation for hiding pmu_events_map as an implementation detail. While the map is passed, the table of events is all that is normally wanted. While modifying the function's types, rename pmu_events_map__find to pmu_events_table__find to match later encapsulation. Similarly rename pmu_add_cpu_aliases_map to pmu_add_cpu_aliases_table. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Stephane Eranian Cc: Will Deacon Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220812230949.683239-7-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/arm64/util/pmu.c | 4 +- tools/perf/tests/expand-cgroup.c | 6 +-- tools/perf/tests/parse-metric.c | 7 +--- tools/perf/tests/pmu-events.c | 63 +++++++++++++----------------- tools/perf/util/metricgroup.c | 82 +++++++++++++++++++-------------------- tools/perf/util/metricgroup.h | 4 +- tools/perf/util/pmu.c | 35 +++++++++-------- tools/perf/util/pmu.h | 8 ++-- tools/perf/util/s390-sample-raw.c | 12 +++--- 9 files changed, 101 insertions(+), 120 deletions(-) diff --git a/tools/perf/arch/arm64/util/pmu.c b/tools/perf/arch/arm64/util/pmu.c index 79124bba713e..92d774647f6e 100644 --- a/tools/perf/arch/arm64/util/pmu.c +++ b/tools/perf/arch/arm64/util/pmu.c @@ -3,7 +3,7 @@ #include "../../../util/cpumap.h" #include "../../../util/pmu.h" -const struct pmu_events_map *pmu_events_map__find(void) +const struct pmu_event *pmu_events_table__find(void) { struct perf_pmu *pmu = NULL; @@ -18,7 +18,7 @@ const struct pmu_events_map *pmu_events_map__find(void) if (pmu->cpus->nr != cpu__max_cpu().cpu) return NULL; - return perf_pmu__find_map(pmu); + return perf_pmu__find_table(pmu); } return NULL; diff --git a/tools/perf/tests/expand-cgroup.c b/tools/perf/tests/expand-cgroup.c index dc4038f997d7..411fc578e5a4 100644 --- a/tools/perf/tests/expand-cgroup.c +++ b/tools/perf/tests/expand-cgroup.c @@ -195,16 +195,12 @@ static int expand_metric_events(void) .metric_name = NULL, }, }; - const struct pmu_events_map ev_map = { - .cpuid = "test", - .table = pme_test, - }; evlist = evlist__new(); TEST_ASSERT_VAL("failed to get evlist", evlist); rblist__init(&metric_events); - ret = metricgroup__parse_groups_test(evlist, &ev_map, metric_str, + ret = metricgroup__parse_groups_test(evlist, pme_test, metric_str, false, false, &metric_events); if (ret < 0) { pr_debug("failed to parse '%s' metric\n", metric_str); diff --git a/tools/perf/tests/parse-metric.c b/tools/perf/tests/parse-metric.c index 1b811a26f4ee..7aebde7c37ec 100644 --- a/tools/perf/tests/parse-metric.c +++ b/tools/perf/tests/parse-metric.c @@ -79,11 +79,6 @@ static struct pmu_event pme_test[] = { } }; -static const struct pmu_events_map map = { - .cpuid = "test", - .table = pme_test, -}; - struct value { const char *event; u64 val; @@ -166,7 +161,7 @@ static int __compute_metric(const char *name, struct value *vals, runtime_stat__init(&st); /* Parse the metric into metric_events list. */ - err = metricgroup__parse_groups_test(evlist, &map, name, + err = metricgroup__parse_groups_test(evlist, pme_test, name, false, false, &metric_events); if (err) diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index a39a2c99ede6..5bba15350cdc 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -272,13 +272,11 @@ static bool is_same(const char *reference, const char *test) return !strcmp(reference, test); } -static const struct pmu_events_map *__test_pmu_get_events_map(void) +static const struct pmu_event *__test_pmu_get_events_table(void) { - const struct pmu_events_map *map; - - for (map = &pmu_events_map[0]; map->cpuid; map++) { + for (const struct pmu_events_map *map = &pmu_events_map[0]; map->cpuid; map++) { if (!strcmp(map->cpuid, "testcpu")) - return map; + return map->table; } pr_err("could not find test events map\n"); @@ -440,8 +438,7 @@ static int test__pmu_event_table(struct test_suite *test __maybe_unused, int subtest __maybe_unused) { const struct pmu_event *sys_event_tables = find_sys_events_table("pme_test_soc_sys"); - const struct pmu_events_map *map = __test_pmu_get_events_map(); - const struct pmu_event *table; + const struct pmu_event *table = __test_pmu_get_events_table(); int map_events = 0, expected_events; /* ignore 3x sentinels */ @@ -449,10 +446,10 @@ static int test__pmu_event_table(struct test_suite *test __maybe_unused, ARRAY_SIZE(uncore_events) + ARRAY_SIZE(sys_events) - 3; - if (!map || !sys_event_tables) + if (!table || !sys_event_tables) return -1; - for (table = map->table; table->name; table++) { + for (; table->name; table++) { struct perf_pmu_test_event const **test_event_table; bool found = false; @@ -537,10 +534,10 @@ static int __test_core_pmu_event_aliases(char *pmu_name, int *count) struct perf_pmu *pmu; LIST_HEAD(aliases); int res = 0; - const struct pmu_events_map *map = __test_pmu_get_events_map(); + const struct pmu_event *table = __test_pmu_get_events_table(); struct perf_pmu_alias *a, *tmp; - if (!map) + if (!table) return -1; test_event_table = &core_events[0]; @@ -551,7 +548,7 @@ static int __test_core_pmu_event_aliases(char *pmu_name, int *count) pmu->name = pmu_name; - pmu_add_cpu_aliases_map(&aliases, pmu, map); + pmu_add_cpu_aliases_table(&aliases, pmu, table); for (; *test_event_table; test_event_table++) { struct perf_pmu_test_event const *test_event = *test_event_table; @@ -590,14 +587,14 @@ static int __test_uncore_pmu_event_aliases(struct perf_pmu_test_pmu *test_pmu) struct perf_pmu *pmu = &test_pmu->pmu; const char *pmu_name = pmu->name; struct perf_pmu_alias *a, *tmp, *alias; - const struct pmu_events_map *map; + const struct pmu_event *events_table; LIST_HEAD(aliases); int res = 0; - map = __test_pmu_get_events_map(); - if (!map) + events_table = __test_pmu_get_events_table(); + if (!events_table) return -1; - pmu_add_cpu_aliases_map(&aliases, pmu, map); + pmu_add_cpu_aliases_table(&aliases, pmu, events_table); pmu_add_sys_aliases(&aliases, pmu); /* Count how many aliases we generated */ @@ -848,13 +845,9 @@ static int check_parse_fake(const char *id) return ret; } -static void expr_failure(const char *msg, - const struct pmu_events_map *map, - const struct pmu_event *pe) +static void expr_failure(const char *msg, const struct pmu_event *pe) { - pr_debug("%s for map %s %s\n", msg, map->arch, map->cpuid); - pr_debug("On metric %s\n", pe->metric_name); - pr_debug("On expression %s\n", pe->metric_expr); + pr_debug("%s\nOn metric %s\nOn expression %s\n", msg, pe->metric_name, pe->metric_expr); } struct metric { @@ -864,7 +857,7 @@ struct metric { static int resolve_metric_simple(struct expr_parse_ctx *pctx, struct list_head *compound_list, - const struct pmu_events_map *map, + const struct pmu_event *map, const char *metric_name) { struct hashmap_entry *cur, *cur_tmp; @@ -925,8 +918,7 @@ out_err: static int test__parsing(struct test_suite *test __maybe_unused, int subtest __maybe_unused) { - const struct pmu_events_map *cpus_map = pmu_events_map__find(); - const struct pmu_events_map *map; + const struct pmu_event *cpus_table = pmu_events_table__find(); const struct pmu_event *pe; int i, j, k; int ret = 0; @@ -940,7 +932,8 @@ static int test__parsing(struct test_suite *test __maybe_unused, } i = 0; for (;;) { - map = &pmu_events_map[i++]; + const struct pmu_events_map *map = &pmu_events_map[i++]; + if (!map->table) break; j = 0; @@ -957,14 +950,14 @@ static int test__parsing(struct test_suite *test __maybe_unused, continue; expr__ctx_clear(ctx); if (expr__find_ids(pe->metric_expr, NULL, ctx) < 0) { - expr_failure("Parse find ids failed", map, pe); + expr_failure("Parse find ids failed", pe); ret++; continue; } - if (resolve_metric_simple(ctx, &compound_list, map, + if (resolve_metric_simple(ctx, &compound_list, map->table, pe->metric_name)) { - expr_failure("Could not resolve metrics", map, pe); + expr_failure("Could not resolve metrics", pe); ret++; goto exit; /* Don't tolerate errors due to severity */ } @@ -979,7 +972,7 @@ static int test__parsing(struct test_suite *test __maybe_unused, expr__add_id_val(ctx, strdup(cur->key), k++); hashmap__for_each_entry(ctx->ids, cur, bkt) { - if (check_parse_cpu(cur->key, map == cpus_map, + if (check_parse_cpu(cur->key, map->table == cpus_table, pe)) ret++; } @@ -999,7 +992,7 @@ static int test__parsing(struct test_suite *test __maybe_unused, hashmap__for_each_entry(ctx->ids, cur, bkt) expr__add_id_val(ctx, strdup(cur->key), k--); if (expr__parse(&result, ctx, pe->metric_expr)) { - expr_failure("Parse failed", map, pe); + expr_failure("Parse failed", pe); ret++; } } @@ -1088,8 +1081,6 @@ out: static int test__parsing_fake(struct test_suite *test __maybe_unused, int subtest __maybe_unused) { - const struct pmu_events_map *map; - const struct pmu_event *pe; unsigned int i, j; int err = 0; @@ -1101,12 +1092,14 @@ static int test__parsing_fake(struct test_suite *test __maybe_unused, i = 0; for (;;) { - map = &pmu_events_map[i++]; + const struct pmu_events_map *map = &pmu_events_map[i++]; + if (!map->table) break; j = 0; for (;;) { - pe = &map->table[j++]; + const struct pmu_event *pe = &map->table[j++]; + if (!pe->name && !pe->metric_group && !pe->metric_name) break; if (!pe->metric_expr) diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index 8f7baeabc5cf..3c3510744dab 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -539,9 +539,6 @@ static int metricgroup__print_sys_event_iter(const struct pmu_event *pe, void *d void metricgroup__print(bool metrics, bool metricgroups, char *filter, bool raw, bool details, const char *pmu_name) { - const struct pmu_events_map *map = pmu_events_map__find(); - const struct pmu_event *pe; - int i; struct rblist groups; struct rb_node *node, *next; struct strlist *metriclist = NULL; @@ -556,8 +553,7 @@ void metricgroup__print(bool metrics, bool metricgroups, char *filter, groups.node_new = mep_new; groups.node_cmp = mep_cmp; groups.node_delete = mep_delete; - for (i = 0; map; i++) { - pe = &map->table[i]; + for (const struct pmu_event *pe = pmu_events_table__find(); pe; pe++) { if (!pe->name && !pe->metric_group && !pe->metric_name) break; @@ -850,7 +846,7 @@ struct metricgroup_add_iter_data { bool metric_no_group; struct metric *root_metric; const struct visited_metric *visited; - const struct pmu_events_map *map; + const struct pmu_event *table; }; static int add_metric(struct list_head *metric_list, @@ -859,7 +855,7 @@ static int add_metric(struct list_head *metric_list, bool metric_no_group, struct metric *root_metric, const struct visited_metric *visited, - const struct pmu_events_map *map); + const struct pmu_event *table); /** * resolve_metric - Locate metrics within the root metric and recursively add @@ -874,7 +870,7 @@ static int add_metric(struct list_head *metric_list, * metrics. When adding a root this argument is NULL. * @visited: A singly linked list of metric names being added that is used to * detect recursion. - * @map: The map that is searched for metrics, most commonly the table for the + * @table: The table that is searched for metrics, most commonly the table for the * architecture perf is running upon. */ static int resolve_metric(struct list_head *metric_list, @@ -882,7 +878,7 @@ static int resolve_metric(struct list_head *metric_list, bool metric_no_group, struct metric *root_metric, const struct visited_metric *visited, - const struct pmu_events_map *map) + const struct pmu_event *table) { struct hashmap_entry *cur; size_t bkt; @@ -904,7 +900,7 @@ static int resolve_metric(struct list_head *metric_list, hashmap__for_each_entry(root_metric->pctx->ids, cur, bkt) { const struct pmu_event *pe; - pe = metricgroup__find_metric(cur->key, map); + pe = metricgroup__find_metric(cur->key, table); if (pe) { pending = realloc(pending, (pending_cnt + 1) * sizeof(struct to_resolve)); @@ -927,7 +923,7 @@ static int resolve_metric(struct list_head *metric_list, */ for (i = 0; i < pending_cnt; i++) { ret = add_metric(metric_list, pending[i].pe, modifier, metric_no_group, - root_metric, visited, map); + root_metric, visited, table); if (ret) break; } @@ -950,7 +946,7 @@ static int resolve_metric(struct list_head *metric_list, * metrics. When adding a root this argument is NULL. * @visited: A singly linked list of metric names being added that is used to * detect recursion. - * @map: The map that is searched for metrics, most commonly the table for the + * @table: The table that is searched for metrics, most commonly the table for the * architecture perf is running upon. */ static int __add_metric(struct list_head *metric_list, @@ -960,7 +956,7 @@ static int __add_metric(struct list_head *metric_list, int runtime, struct metric *root_metric, const struct visited_metric *visited, - const struct pmu_events_map *map) + const struct pmu_event *table) { const struct visited_metric *vm; int ret; @@ -1032,7 +1028,7 @@ static int __add_metric(struct list_head *metric_list, } else { /* Resolve referenced metrics. */ ret = resolve_metric(metric_list, modifier, metric_no_group, root_metric, - &visited_node, map); + &visited_node, table); } if (ret) { @@ -1045,25 +1041,25 @@ static int __add_metric(struct list_head *metric_list, return ret; } -#define map_for_each_event(__pe, __idx, __map) \ - if (__map) \ - for (__idx = 0, __pe = &__map->table[__idx]; \ +#define table_for_each_event(__pe, __idx, __table) \ + if (__table) \ + for (__idx = 0, __pe = &__table[__idx]; \ __pe->name || __pe->metric_group || __pe->metric_name; \ - __pe = &__map->table[++__idx]) + __pe = &__table[++__idx]) -#define map_for_each_metric(__pe, __idx, __map, __metric) \ - map_for_each_event(__pe, __idx, __map) \ +#define table_for_each_metric(__pe, __idx, __table, __metric) \ + table_for_each_event(__pe, __idx, __table) \ if (__pe->metric_expr && \ (match_metric(__pe->metric_group, __metric) || \ match_metric(__pe->metric_name, __metric))) const struct pmu_event *metricgroup__find_metric(const char *metric, - const struct pmu_events_map *map) + const struct pmu_event *table) { const struct pmu_event *pe; int i; - map_for_each_event(pe, i, map) { + table_for_each_event(pe, i, table) { if (match_metric(pe->metric_name, metric)) return pe; } @@ -1077,7 +1073,7 @@ static int add_metric(struct list_head *metric_list, bool metric_no_group, struct metric *root_metric, const struct visited_metric *visited, - const struct pmu_events_map *map) + const struct pmu_event *table) { int ret = 0; @@ -1085,7 +1081,7 @@ static int add_metric(struct list_head *metric_list, if (!strstr(pe->metric_expr, "?")) { ret = __add_metric(metric_list, pe, modifier, metric_no_group, 0, - root_metric, visited, map); + root_metric, visited, table); } else { int j, count; @@ -1098,7 +1094,7 @@ static int add_metric(struct list_head *metric_list, for (j = 0; j < count && !ret; j++) ret = __add_metric(metric_list, pe, modifier, metric_no_group, j, - root_metric, visited, map); + root_metric, visited, table); } return ret; @@ -1114,7 +1110,7 @@ static int metricgroup__add_metric_sys_event_iter(const struct pmu_event *pe, return 0; ret = add_metric(d->metric_list, pe, d->modifier, d->metric_no_group, - d->root_metric, d->visited, d->map); + d->root_metric, d->visited, d->table); if (ret) goto out; @@ -1162,13 +1158,13 @@ static int metric_list_cmp(void *priv __maybe_unused, const struct list_head *l, * global. Grouping is the default but due to multiplexing the * user may override. * @metric_list: The list that the metric or metric group are added to. - * @map: The map that is searched for metrics, most commonly the table for the + * @table: The table that is searched for metrics, most commonly the table for the * architecture perf is running upon. */ static int metricgroup__add_metric(const char *metric_name, const char *modifier, bool metric_no_group, struct list_head *metric_list, - const struct pmu_events_map *map) + const struct pmu_event *table) { const struct pmu_event *pe; LIST_HEAD(list); @@ -1179,11 +1175,11 @@ static int metricgroup__add_metric(const char *metric_name, const char *modifier * Iterate over all metrics seeing if metric matches either the name or * group. When it does add the metric to the list. */ - map_for_each_metric(pe, i, map, metric_name) { + table_for_each_metric(pe, i, table, metric_name) { has_match = true; ret = add_metric(&list, pe, modifier, metric_no_group, /*root_metric=*/NULL, - /*visited_metrics=*/NULL, map); + /*visited_metrics=*/NULL, table); if (ret) goto out; } @@ -1198,7 +1194,7 @@ static int metricgroup__add_metric(const char *metric_name, const char *modifier .metric_no_group = metric_no_group, .has_match = &has_match, .ret = &ret, - .map = map, + .table = table, }, }; @@ -1227,12 +1223,12 @@ out: * global. Grouping is the default but due to multiplexing the * user may override. * @metric_list: The list that metrics are added to. - * @map: The map that is searched for metrics, most commonly the table for the + * @table: The table that is searched for metrics, most commonly the table for the * architecture perf is running upon. */ static int metricgroup__add_metric_list(const char *list, bool metric_no_group, struct list_head *metric_list, - const struct pmu_events_map *map) + const struct pmu_event *table) { char *list_itr, *list_copy, *metric_name, *modifier; int ret, count = 0; @@ -1249,7 +1245,7 @@ static int metricgroup__add_metric_list(const char *list, bool metric_no_group, ret = metricgroup__add_metric(metric_name, modifier, metric_no_group, metric_list, - map); + table); if (ret == -EINVAL) pr_err("Cannot find metric or group `%s'\n", metric_name); @@ -1440,7 +1436,7 @@ static int parse_groups(struct evlist *perf_evlist, const char *str, bool metric_no_merge, struct perf_pmu *fake_pmu, struct rblist *metric_events_list, - const struct pmu_events_map *map) + const struct pmu_event *table) { struct evlist *combined_evlist = NULL; LIST_HEAD(metric_list); @@ -1451,7 +1447,7 @@ static int parse_groups(struct evlist *perf_evlist, const char *str, if (metric_events_list->nr_entries == 0) metricgroup__rblist_init(metric_events_list); ret = metricgroup__add_metric_list(str, metric_no_group, - &metric_list, map); + &metric_list, table); if (ret) goto out; @@ -1586,34 +1582,34 @@ int metricgroup__parse_groups(const struct option *opt, struct rblist *metric_events) { struct evlist *perf_evlist = *(struct evlist **)opt->value; - const struct pmu_events_map *map = pmu_events_map__find(); + const struct pmu_event *table = pmu_events_table__find(); return parse_groups(perf_evlist, str, metric_no_group, - metric_no_merge, NULL, metric_events, map); + metric_no_merge, NULL, metric_events, table); } int metricgroup__parse_groups_test(struct evlist *evlist, - const struct pmu_events_map *map, + const struct pmu_event *table, const char *str, bool metric_no_group, bool metric_no_merge, struct rblist *metric_events) { return parse_groups(evlist, str, metric_no_group, - metric_no_merge, &perf_pmu__fake, metric_events, map); + metric_no_merge, &perf_pmu__fake, metric_events, table); } bool metricgroup__has_metric(const char *metric) { - const struct pmu_events_map *map = pmu_events_map__find(); + const struct pmu_event *table = pmu_events_table__find(); const struct pmu_event *pe; int i; - if (!map) + if (!table) return false; for (i = 0; ; i++) { - pe = &map->table[i]; + pe = &table[i]; if (!pe->name && !pe->metric_group && !pe->metric_name) break; diff --git a/tools/perf/util/metricgroup.h b/tools/perf/util/metricgroup.h index 2b42b778d1bf..5a1390e73d25 100644 --- a/tools/perf/util/metricgroup.h +++ b/tools/perf/util/metricgroup.h @@ -71,9 +71,9 @@ int metricgroup__parse_groups(const struct option *opt, bool metric_no_merge, struct rblist *metric_events); const struct pmu_event *metricgroup__find_metric(const char *metric, - const struct pmu_events_map *map); + const struct pmu_event *table); int metricgroup__parse_groups_test(struct evlist *evlist, - const struct pmu_events_map *map, + const struct pmu_event *table, const char *str, bool metric_no_group, bool metric_no_merge, diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index d8717c4548a4..7874d67485ac 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -710,9 +710,9 @@ static char *perf_pmu__getcpuid(struct perf_pmu *pmu) return cpuid; } -const struct pmu_events_map *perf_pmu__find_map(struct perf_pmu *pmu) +const struct pmu_event *perf_pmu__find_table(struct perf_pmu *pmu) { - const struct pmu_events_map *map; + const struct pmu_event *table = NULL; char *cpuid = perf_pmu__getcpuid(pmu); int i; @@ -724,22 +724,23 @@ const struct pmu_events_map *perf_pmu__find_map(struct perf_pmu *pmu) i = 0; for (;;) { - map = &pmu_events_map[i++]; - if (!map->table) { - map = NULL; + const struct pmu_events_map *map = &pmu_events_map[i++]; + + if (!map->table) break; - } - if (!strcmp_cpuid_str(map->cpuid, cpuid)) + if (!strcmp_cpuid_str(map->cpuid, cpuid)) { + table = map->table; break; + } } free(cpuid); - return map; + return table; } -const struct pmu_events_map *__weak pmu_events_map__find(void) +__weak const struct pmu_event *pmu_events_table__find(void) { - return perf_pmu__find_map(NULL); + return perf_pmu__find_table(NULL); } /* @@ -823,8 +824,8 @@ out: * to the current running CPU. Then, add all PMU events from that table * as aliases. */ -void pmu_add_cpu_aliases_map(struct list_head *head, struct perf_pmu *pmu, - const struct pmu_events_map *map) +void pmu_add_cpu_aliases_table(struct list_head *head, struct perf_pmu *pmu, + const struct pmu_event *table) { int i; const char *name = pmu->name; @@ -834,7 +835,7 @@ void pmu_add_cpu_aliases_map(struct list_head *head, struct perf_pmu *pmu, i = 0; while (1) { const char *cpu_name = is_arm_pmu_core(name) ? name : "cpu"; - const struct pmu_event *pe = &map->table[i++]; + const struct pmu_event *pe = &table[i++]; const char *pname = pe->pmu ? pe->pmu : cpu_name; if (!pe->name) { @@ -859,13 +860,13 @@ new_alias: static void pmu_add_cpu_aliases(struct list_head *head, struct perf_pmu *pmu) { - const struct pmu_events_map *map; + const struct pmu_event *table; - map = perf_pmu__find_map(pmu); - if (!map) + table = perf_pmu__find_table(pmu); + if (!table) return; - pmu_add_cpu_aliases_map(head, pmu, map); + pmu_add_cpu_aliases_table(head, pmu, table); } struct pmu_sys_event_iter_data { diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h index 7e667eec2a01..d535a98c5998 100644 --- a/tools/perf/util/pmu.h +++ b/tools/perf/util/pmu.h @@ -125,11 +125,11 @@ int perf_pmu__scan_file(struct perf_pmu *pmu, const char *name, const char *fmt, int perf_pmu__test(void); struct perf_event_attr *perf_pmu__get_default_config(struct perf_pmu *pmu); -void pmu_add_cpu_aliases_map(struct list_head *head, struct perf_pmu *pmu, - const struct pmu_events_map *map); +void pmu_add_cpu_aliases_table(struct list_head *head, struct perf_pmu *pmu, + const struct pmu_event *table); -const struct pmu_events_map *perf_pmu__find_map(struct perf_pmu *pmu); -const struct pmu_events_map *pmu_events_map__find(void); +const struct pmu_event *perf_pmu__find_table(struct perf_pmu *pmu); +const struct pmu_event *pmu_events_table__find(void); bool pmu_uncore_alias_match(const char *pmu_name, const char *name); void perf_pmu_free_alias(struct perf_pmu_alias *alias); diff --git a/tools/perf/util/s390-sample-raw.c b/tools/perf/util/s390-sample-raw.c index cd3a34840389..dddd2be59827 100644 --- a/tools/perf/util/s390-sample-raw.c +++ b/tools/perf/util/s390-sample-raw.c @@ -135,12 +135,12 @@ static int get_counterset_start(int setnr) * the name of this counter. * If no match is found a NULL pointer is returned. */ -static const char *get_counter_name(int set, int nr, const struct pmu_events_map *map) +static const char *get_counter_name(int set, int nr, const struct pmu_event *table) { int rc, event_nr, wanted = get_counterset_start(set) + nr; - if (map) { - const struct pmu_event *evp = map->table; + if (table) { + const struct pmu_event *evp = table; for (; evp->name || evp->event || evp->desc; ++evp) { if (evp->name == NULL || evp->event == NULL) @@ -159,10 +159,10 @@ static void s390_cpumcfdg_dump(struct perf_sample *sample) unsigned char *buf = sample->raw_data; const char *color = PERF_COLOR_BLUE; struct cf_ctrset_entry *cep, ce; - const struct pmu_events_map *map; + const struct pmu_event *table; u64 *p; - map = pmu_events_map__find(); + table = pmu_events_table__find(); while (offset < len) { cep = (struct cf_ctrset_entry *)(buf + offset); @@ -180,7 +180,7 @@ static void s390_cpumcfdg_dump(struct perf_sample *sample) color_fprintf(stdout, color, " [%#08zx] Counterset:%d" " Counters:%d\n", offset, ce.set, ce.ctr); for (i = 0, p = (u64 *)(cep + 1); i < ce.ctr; ++i, ++p) { - const char *ev_name = get_counter_name(ce.set, i, map); + const char *ev_name = get_counter_name(ce.set, i, table); color_fprintf(stdout, color, "\tCounter:%03d %s Value:%#018lx\n", i, -- cgit v1.2.3 From 29be2fe0c157ee5c8c5d9571f42dc1f0f5d8f67b Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 12 Aug 2022 16:09:42 -0700 Subject: perf pmu-events: Hide pmu_events_map Move usage of the table to pmu-events.c so it may be hidden. By abstracting the table the implementation can later be changed. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Stephane Eranian Cc: Will Deacon Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220812230949.683239-8-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/empty-pmu-events.c | 81 +++++++++++- tools/perf/pmu-events/jevents.py | 81 +++++++++++- tools/perf/pmu-events/pmu-events.h | 29 ++-- tools/perf/tests/pmu-events.c | 218 ++++++++++++++----------------- tools/perf/util/metricgroup.c | 15 ++- tools/perf/util/pmu.c | 34 +---- tools/perf/util/pmu.h | 2 +- 7 files changed, 280 insertions(+), 180 deletions(-) diff --git a/tools/perf/pmu-events/empty-pmu-events.c b/tools/perf/pmu-events/empty-pmu-events.c index 216ea0482c37..8ef75aff996c 100644 --- a/tools/perf/pmu-events/empty-pmu-events.c +++ b/tools/perf/pmu-events/empty-pmu-events.c @@ -6,6 +6,8 @@ * The test cpu/soc is provided for testing. */ #include "pmu-events/pmu-events.h" +#include "util/header.h" +#include "util/pmu.h" #include #include @@ -110,7 +112,26 @@ static const struct pmu_event pme_test_soc_cpu[] = { }, }; -const struct pmu_events_map pmu_events_map[] = { + +/* + * Map a CPU to its table of PMU events. The CPU is identified by the + * cpuid field, which is an arch-specific identifier for the CPU. + * The identifier specified in tools/perf/pmu-events/arch/xxx/mapfile + * must match the get_cpuid_str() in tools/perf/arch/xxx/util/header.c) + * + * The cpuid can contain any character other than the comma. + */ +struct pmu_events_map { + const char *arch; + const char *cpuid; + const struct pmu_event *table; +}; + +/* + * Global table mapping each known CPU for the architecture to its + * table of PMU events. + */ +static const struct pmu_events_map pmu_events_map[] = { { .arch = "testarch", .cpuid = "testcpu", @@ -162,6 +183,62 @@ static const struct pmu_sys_events pmu_sys_event_tables[] = { }, }; +const struct pmu_event *perf_pmu__find_table(struct perf_pmu *pmu) +{ + const struct pmu_event *table = NULL; + char *cpuid = perf_pmu__getcpuid(pmu); + int i; + + /* on some platforms which uses cpus map, cpuid can be NULL for + * PMUs other than CORE PMUs. + */ + if (!cpuid) + return NULL; + + i = 0; + for (;;) { + const struct pmu_events_map *map = &pmu_events_map[i++]; + + if (!map->table) + break; + + if (!strcmp_cpuid_str(map->cpuid, cpuid)) { + table = map->table; + break; + } + } + free(cpuid); + return table; +} + +const struct pmu_event *find_core_events_table(const char *arch, const char *cpuid) +{ + for (const struct pmu_events_map *tables = &pmu_events_map[0]; + tables->table; + tables++) { + if (!strcmp(tables->arch, arch) && !strcmp_cpuid_str(tables->cpuid, cpuid)) + return tables->table; + } + return NULL; +} + +int pmu_for_each_core_event(pmu_event_iter_fn fn, void *data) +{ + for (const struct pmu_events_map *tables = &pmu_events_map[0]; + tables->table; + tables++) { + for (const struct pmu_event *pe = &tables->table[0]; + pe->name || pe->metric_group || pe->metric_name; + pe++) { + int ret = fn(pe, &tables->table[0], data); + + if (ret) + return ret; + } + } + return 0; +} + const struct pmu_event *find_sys_events_table(const char *name) { for (const struct pmu_sys_events *tables = &pmu_sys_event_tables[0]; @@ -181,7 +258,7 @@ int pmu_for_each_sys_event(pmu_event_iter_fn fn, void *data) for (const struct pmu_event *pe = &tables->table[0]; pe->name || pe->metric_group || pe->metric_name; pe++) { - int ret = fn(pe, data); + int ret = fn(pe, &tables->table[0], data); if (ret) return ret; diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index 8f929dd3e065..1a04b848d736 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -334,7 +334,27 @@ def process_one_file(parents: Sequence[str], item: os.DirEntry) -> None: def print_mapping_table(archs: Sequence[str]) -> None: """Read the mapfile and generate the struct from cpuid string to event table.""" - _args.output_file.write('const struct pmu_events_map pmu_events_map[] = {\n') + _args.output_file.write(""" +/* + * Map a CPU to its table of PMU events. The CPU is identified by the + * cpuid field, which is an arch-specific identifier for the CPU. + * The identifier specified in tools/perf/pmu-events/arch/xxx/mapfile + * must match the get_cpuid_str() in tools/perf/arch/xxx/util/header.c) + * + * The cpuid can contain any character other than the comma. + */ +struct pmu_events_map { + const char *arch; + const char *cpuid; + const struct pmu_event *table; +}; + +/* + * Global table mapping each known CPU for the architecture to its + * table of PMU events. + */ +const struct pmu_events_map pmu_events_map[] = { +""") for arch in archs: if arch == 'test': _args.output_file.write("""{ @@ -390,6 +410,61 @@ static const struct pmu_sys_events pmu_sys_event_tables[] = { \t}, }; +const struct pmu_event *perf_pmu__find_table(struct perf_pmu *pmu) +{ + const struct pmu_event *table = NULL; + char *cpuid = perf_pmu__getcpuid(pmu); + int i; + + /* on some platforms which uses cpus map, cpuid can be NULL for + * PMUs other than CORE PMUs. + */ + if (!cpuid) + return NULL; + + i = 0; + for (;;) { + const struct pmu_events_map *map = &pmu_events_map[i++]; + if (!map->table) + break; + + if (!strcmp_cpuid_str(map->cpuid, cpuid)) { + table = map->table; + break; + } + } + free(cpuid); + return table; +} + +const struct pmu_event *find_core_events_table(const char *arch, const char *cpuid) +{ + for (const struct pmu_events_map *tables = &pmu_events_map[0]; + tables->table; + tables++) { + if (!strcmp(tables->arch, arch) && !strcmp_cpuid_str(tables->cpuid, cpuid)) + return tables->table; + } + return NULL; +} + +int pmu_for_each_core_event(pmu_event_iter_fn fn, void *data) +{ + for (const struct pmu_events_map *tables = &pmu_events_map[0]; + tables->table; + tables++) { + for (const struct pmu_event *pe = &tables->table[0]; + pe->name || pe->metric_group || pe->metric_name; + pe++) { + int ret = fn(pe, &tables->table[0], data); + + if (ret) + return ret; + } + } + return 0; +} + const struct pmu_event *find_sys_events_table(const char *name) { for (const struct pmu_sys_events *tables = &pmu_sys_event_tables[0]; @@ -409,7 +484,7 @@ int pmu_for_each_sys_event(pmu_event_iter_fn fn, void *data) for (const struct pmu_event *pe = &tables->table[0]; pe->name || pe->metric_group || pe->metric_name; pe++) { - int ret = fn(pe, data); + int ret = fn(pe, &tables->table[0], data); if (ret) return ret; @@ -450,6 +525,8 @@ def main() -> None: _args.output_file.write(""" #include "pmu-events/pmu-events.h" +#include "util/header.h" +#include "util/pmu.h" #include #include diff --git a/tools/perf/pmu-events/pmu-events.h b/tools/perf/pmu-events/pmu-events.h index 2386212b1df0..485e730f9922 100644 --- a/tools/perf/pmu-events/pmu-events.h +++ b/tools/perf/pmu-events/pmu-events.h @@ -2,6 +2,8 @@ #ifndef PMU_EVENTS_H #define PMU_EVENTS_H +struct perf_pmu; + enum aggr_mode_class { PerChip = 1, PerCore @@ -28,30 +30,15 @@ struct pmu_event { const char *metric_constraint; }; -/* - * - * Map a CPU to its table of PMU events. The CPU is identified by the - * cpuid field, which is an arch-specific identifier for the CPU. - * The identifier specified in tools/perf/pmu-events/arch/xxx/mapfile - * must match the get_cpuid_str() in tools/perf/arch/xxx/util/header.c) - * - * The cpuid can contain any character other than the comma. - */ -struct pmu_events_map { - const char *arch; - const char *cpuid; - const struct pmu_event *table; -}; +typedef int (*pmu_event_iter_fn)(const struct pmu_event *pe, + const struct pmu_event *table, + void *data); -/* - * Global table mapping each known CPU for the architecture to its - * table of PMU events. - */ -extern const struct pmu_events_map pmu_events_map[]; +const struct pmu_event *perf_pmu__find_table(struct perf_pmu *pmu); +const struct pmu_event *find_core_events_table(const char *arch, const char *cpuid); +int pmu_for_each_core_event(pmu_event_iter_fn fn, void *data); const struct pmu_event *find_sys_events_table(const char *name); - -typedef int (*pmu_event_iter_fn)(const struct pmu_event *pe, void *data); int pmu_for_each_sys_event(pmu_event_iter_fn fn, void *data); #endif diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index 5bba15350cdc..3ebea8f589c4 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -272,18 +272,6 @@ static bool is_same(const char *reference, const char *test) return !strcmp(reference, test); } -static const struct pmu_event *__test_pmu_get_events_table(void) -{ - for (const struct pmu_events_map *map = &pmu_events_map[0]; map->cpuid; map++) { - if (!strcmp(map->cpuid, "testcpu")) - return map->table; - } - - pr_err("could not find test events map\n"); - - return NULL; -} - static int compare_pmu_events(const struct pmu_event *e1, const struct pmu_event *e2) { if (!is_same(e1->name, e2->name)) { @@ -438,7 +426,7 @@ static int test__pmu_event_table(struct test_suite *test __maybe_unused, int subtest __maybe_unused) { const struct pmu_event *sys_event_tables = find_sys_events_table("pme_test_soc_sys"); - const struct pmu_event *table = __test_pmu_get_events_table(); + const struct pmu_event *table = find_core_events_table("testarch", "testcpu"); int map_events = 0, expected_events; /* ignore 3x sentinels */ @@ -534,7 +522,7 @@ static int __test_core_pmu_event_aliases(char *pmu_name, int *count) struct perf_pmu *pmu; LIST_HEAD(aliases); int res = 0; - const struct pmu_event *table = __test_pmu_get_events_table(); + const struct pmu_event *table = find_core_events_table("testarch", "testcpu"); struct perf_pmu_alias *a, *tmp; if (!table) @@ -591,7 +579,7 @@ static int __test_uncore_pmu_event_aliases(struct perf_pmu_test_pmu *test_pmu) LIST_HEAD(aliases); int res = 0; - events_table = __test_pmu_get_events_table(); + events_table = find_core_events_table("testarch", "testcpu"); if (!events_table) return -1; pmu_add_cpu_aliases_table(&aliases, pmu, events_table); @@ -845,11 +833,6 @@ static int check_parse_fake(const char *id) return ret; } -static void expr_failure(const char *msg, const struct pmu_event *pe) -{ - pr_debug("%s\nOn metric %s\nOn expression %s\n", msg, pe->metric_name, pe->metric_expr); -} - struct metric { struct list_head list; struct metric_ref metric_ref; @@ -915,93 +898,100 @@ out_err: } -static int test__parsing(struct test_suite *test __maybe_unused, - int subtest __maybe_unused) +static void expr_failure(const char *msg, const struct pmu_event *pe) { - const struct pmu_event *cpus_table = pmu_events_table__find(); - const struct pmu_event *pe; - int i, j, k; - int ret = 0; + pr_debug("%s\nOn metric %s\nOn expression %s\n", msg, pe->metric_name, pe->metric_expr); +} + + +struct test__parsing_data { + const struct pmu_event *cpus_table; struct expr_parse_ctx *ctx; + int failures; +}; + +static int test__parsing_callback(const struct pmu_event *pe, const struct pmu_event *table, + void *vdata) +{ + struct test__parsing_data *data = vdata; + struct metric *metric, *tmp; + struct hashmap_entry *cur; + LIST_HEAD(compound_list); + size_t bkt; + int k; double result; - ctx = expr__ctx_new(); - if (!ctx) { - pr_debug("expr__ctx_new failed"); - return TEST_FAIL; + if (!pe->metric_expr) + return 0; + + pr_debug("Found metric '%s'\n", pe->metric_name); + + expr__ctx_clear(data->ctx); + if (expr__find_ids(pe->metric_expr, NULL, data->ctx) < 0) { + expr_failure("Parse find ids failed", pe); + data->failures++; + return 0; } - i = 0; - for (;;) { - const struct pmu_events_map *map = &pmu_events_map[i++]; - if (!map->table) - break; - j = 0; - for (;;) { - struct metric *metric, *tmp; - struct hashmap_entry *cur; - LIST_HEAD(compound_list); - size_t bkt; - - pe = &map->table[j++]; - if (!pe->name && !pe->metric_group && !pe->metric_name) - break; - if (!pe->metric_expr) - continue; - expr__ctx_clear(ctx); - if (expr__find_ids(pe->metric_expr, NULL, ctx) < 0) { - expr_failure("Parse find ids failed", pe); - ret++; - continue; - } + if (resolve_metric_simple(data->ctx, &compound_list, table, + pe->metric_name)) { + expr_failure("Could not resolve metrics", pe); + data->failures++; + return TEST_FAIL; /* Don't tolerate errors due to severity */ + } - if (resolve_metric_simple(ctx, &compound_list, map->table, - pe->metric_name)) { - expr_failure("Could not resolve metrics", pe); - ret++; - goto exit; /* Don't tolerate errors due to severity */ - } + /* + * Add all ids with a made up value. The value may trigger divide by + * zero when subtracted and so try to make them unique. + */ + k = 1; + hashmap__for_each_entry(data->ctx->ids, cur, bkt) + expr__add_id_val(data->ctx, strdup(cur->key), k++); - /* - * Add all ids with a made up value. The value may - * trigger divide by zero when subtracted and so try to - * make them unique. - */ - k = 1; - hashmap__for_each_entry(ctx->ids, cur, bkt) - expr__add_id_val(ctx, strdup(cur->key), k++); - - hashmap__for_each_entry(ctx->ids, cur, bkt) { - if (check_parse_cpu(cur->key, map->table == cpus_table, - pe)) - ret++; - } + hashmap__for_each_entry(data->ctx->ids, cur, bkt) { + if (check_parse_cpu(cur->key, table == data->cpus_table, pe)) + data->failures++; + } - list_for_each_entry_safe(metric, tmp, &compound_list, list) { - expr__add_ref(ctx, &metric->metric_ref); - free(metric); - } + list_for_each_entry_safe(metric, tmp, &compound_list, list) { + expr__add_ref(data->ctx, &metric->metric_ref); + free(metric); + } - if (expr__parse(&result, ctx, pe->metric_expr)) { - /* - * Parsing failed, make numbers go from large to - * small which can resolve divide by zero - * issues. - */ - k = 1024; - hashmap__for_each_entry(ctx->ids, cur, bkt) - expr__add_id_val(ctx, strdup(cur->key), k--); - if (expr__parse(&result, ctx, pe->metric_expr)) { - expr_failure("Parse failed", pe); - ret++; - } - } + if (expr__parse(&result, data->ctx, pe->metric_expr)) { + /* + * Parsing failed, make numbers go from large to small which can + * resolve divide by zero issues. + */ + k = 1024; + hashmap__for_each_entry(data->ctx->ids, cur, bkt) + expr__add_id_val(data->ctx, strdup(cur->key), k--); + if (expr__parse(&result, data->ctx, pe->metric_expr)) { + expr_failure("Parse failed", pe); + data->failures++; } } - expr__ctx_free(ctx); - /* TODO: fail when not ok */ -exit: - return ret == 0 ? TEST_OK : TEST_SKIP; + return 0; +} + +static int test__parsing(struct test_suite *test __maybe_unused, + int subtest __maybe_unused) +{ + struct test__parsing_data data = { + .cpus_table = pmu_events_table__find(), + .ctx = expr__ctx_new(), + .failures = 0, + }; + + if (!data.ctx) { + pr_debug("expr__ctx_new failed"); + return TEST_FAIL; + } + pmu_for_each_core_event(test__parsing_callback, &data); + pmu_for_each_sys_event(test__parsing_callback, &data); + + expr__ctx_free(data.ctx); + return data.failures == 0 ? TEST_OK : TEST_FAIL; } struct test_metric { @@ -1073,6 +1063,16 @@ out: return ret; } +static int test__parsing_fake_callback(const struct pmu_event *pe, + const struct pmu_event *table __maybe_unused, + void *data __maybe_unused) +{ + if (!pe->metric_expr) + return 0; + + return metric_parse_fake(pe->metric_expr); +} + /* * Parse all the metrics for current architecture, * or all defined cpus via the 'fake_pmu' @@ -1081,37 +1081,19 @@ out: static int test__parsing_fake(struct test_suite *test __maybe_unused, int subtest __maybe_unused) { - unsigned int i, j; int err = 0; - for (i = 0; i < ARRAY_SIZE(metrics); i++) { + for (size_t i = 0; i < ARRAY_SIZE(metrics); i++) { err = metric_parse_fake(metrics[i].str); if (err) return err; } - i = 0; - for (;;) { - const struct pmu_events_map *map = &pmu_events_map[i++]; + err = pmu_for_each_core_event(test__parsing_fake_callback, NULL); + if (err) + return err; - if (!map->table) - break; - j = 0; - for (;;) { - const struct pmu_event *pe = &map->table[j++]; - - if (!pe->name && !pe->metric_group && !pe->metric_name) - break; - if (!pe->metric_expr) - continue; - pr_debug("Found metric '%s' for '%s'\n", pe->metric_name, map->cpuid); - err = metric_parse_fake(pe->metric_expr); - if (err) - return err; - } - } - - return 0; + return pmu_for_each_sys_event(test__parsing_fake_callback, NULL); } static struct test_case pmu_events_tests[] = { diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index 3c3510744dab..8d994539d6ea 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -502,14 +502,14 @@ struct metricgroup_print_sys_idata { bool details; }; -typedef int (*metricgroup_sys_event_iter_fn)(const struct pmu_event *pe, void *); - struct metricgroup_iter_data { - metricgroup_sys_event_iter_fn fn; + pmu_event_iter_fn fn; void *data; }; -static int metricgroup__sys_event_iter(const struct pmu_event *pe, void *data) +static int metricgroup__sys_event_iter(const struct pmu_event *pe, + const struct pmu_event *table __maybe_unused, + void *data) { struct metricgroup_iter_data *d = data; struct perf_pmu *pmu = NULL; @@ -522,13 +522,15 @@ static int metricgroup__sys_event_iter(const struct pmu_event *pe, void *data) if (!pmu->id || strcmp(pmu->id, pe->compat)) continue; - return d->fn(pe, d->data); + return d->fn(pe, table, d->data); } return 0; } -static int metricgroup__print_sys_event_iter(const struct pmu_event *pe, void *data) +static int metricgroup__print_sys_event_iter(const struct pmu_event *pe, + const struct pmu_event *table __maybe_unused, + void *data) { struct metricgroup_print_sys_idata *d = data; @@ -1101,6 +1103,7 @@ static int add_metric(struct list_head *metric_list, } static int metricgroup__add_metric_sys_event_iter(const struct pmu_event *pe, + const struct pmu_event *table __maybe_unused, void *data) { struct metricgroup_add_iter_data *d = data; diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 7874d67485ac..f117324eb5f0 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -690,7 +690,7 @@ static int is_arm_pmu_core(const char *name) return file_available(path); } -static char *perf_pmu__getcpuid(struct perf_pmu *pmu) +char *perf_pmu__getcpuid(struct perf_pmu *pmu) { char *cpuid; static bool printed; @@ -710,34 +710,6 @@ static char *perf_pmu__getcpuid(struct perf_pmu *pmu) return cpuid; } -const struct pmu_event *perf_pmu__find_table(struct perf_pmu *pmu) -{ - const struct pmu_event *table = NULL; - char *cpuid = perf_pmu__getcpuid(pmu); - int i; - - /* on some platforms which uses cpus map, cpuid can be NULL for - * PMUs other than CORE PMUs. - */ - if (!cpuid) - return NULL; - - i = 0; - for (;;) { - const struct pmu_events_map *map = &pmu_events_map[i++]; - - if (!map->table) - break; - - if (!strcmp_cpuid_str(map->cpuid, cpuid)) { - table = map->table; - break; - } - } - free(cpuid); - return table; -} - __weak const struct pmu_event *pmu_events_table__find(void) { return perf_pmu__find_table(NULL); @@ -874,7 +846,9 @@ struct pmu_sys_event_iter_data { struct perf_pmu *pmu; }; -static int pmu_add_sys_aliases_iter_fn(const struct pmu_event *pe, void *data) +static int pmu_add_sys_aliases_iter_fn(const struct pmu_event *pe, + const struct pmu_event *table __maybe_unused, + void *data) { struct pmu_sys_event_iter_data *idata = data; struct perf_pmu *pmu = idata->pmu; diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h index d535a98c5998..f0aba1e462fa 100644 --- a/tools/perf/util/pmu.h +++ b/tools/perf/util/pmu.h @@ -128,7 +128,7 @@ struct perf_event_attr *perf_pmu__get_default_config(struct perf_pmu *pmu); void pmu_add_cpu_aliases_table(struct list_head *head, struct perf_pmu *pmu, const struct pmu_event *table); -const struct pmu_event *perf_pmu__find_table(struct perf_pmu *pmu); +char *perf_pmu__getcpuid(struct perf_pmu *pmu); const struct pmu_event *pmu_events_table__find(void); bool pmu_uncore_alias_match(const char *pmu_name, const char *name); void perf_pmu_free_alias(struct perf_pmu_alias *alias); -- cgit v1.2.3 From 64234c141bc8fb76c3166d39143f2bf66ffe9a22 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 12 Aug 2022 16:09:43 -0700 Subject: perf test: Use full metric resolution The simple metric resolution doesn't handle recursion properly, switch to use the full resolution as with the parse-metric tests which also increases coverage. Don't set the values for the metric backward as failures to generate a result are ignored. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Stephane Eranian Cc: Will Deacon Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220812230949.683239-9-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/pmu-events.c | 222 +++++++++++++++--------------------------- 1 file changed, 77 insertions(+), 145 deletions(-) diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index 3ebea8f589c4..a64497cb9fb2 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -9,10 +9,12 @@ #include #include "debug.h" #include "../pmu-events/pmu-events.h" +#include #include "util/evlist.h" #include "util/expr.h" #include "util/parse-events.h" #include "metricgroup.h" +#include "stat.h" struct perf_pmu_test_event { /* used for matching against events from generated pmu-events.c */ @@ -801,27 +803,6 @@ static int check_parse_id(const char *id, struct parse_events_error *error, return ret; } -static int check_parse_cpu(const char *id, bool same_cpu, const struct pmu_event *pe) -{ - struct parse_events_error error; - int ret; - - parse_events_error__init(&error); - ret = check_parse_id(id, &error, NULL); - if (ret && same_cpu) { - pr_warning("Parse event failed metric '%s' id '%s' expr '%s'\n", - pe->metric_name, id, pe->metric_expr); - pr_warning("Error string '%s' help '%s'\n", error.str, - error.help); - } else if (ret) { - pr_debug3("Parse event failed, but for an event that may not be supported by this CPU.\nid '%s' metric '%s' expr '%s'\n", - id, pe->metric_name, pe->metric_expr); - ret = 0; - } - parse_events_error__exit(&error); - return ret; -} - static int check_parse_fake(const char *id) { struct parse_events_error error; @@ -838,160 +819,111 @@ struct metric { struct metric_ref metric_ref; }; -static int resolve_metric_simple(struct expr_parse_ctx *pctx, - struct list_head *compound_list, - const struct pmu_event *map, - const char *metric_name) -{ - struct hashmap_entry *cur, *cur_tmp; - struct metric *metric, *tmp; - size_t bkt; - bool all; - int rc; - - do { - all = true; - hashmap__for_each_entry_safe(pctx->ids, cur, cur_tmp, bkt) { - struct metric_ref *ref; - const struct pmu_event *pe; - - pe = metricgroup__find_metric(cur->key, map); - if (!pe) - continue; - - if (!strcmp(metric_name, (char *)cur->key)) { - pr_warning("Recursion detected for metric %s\n", metric_name); - rc = -1; - goto out_err; - } - - all = false; - - /* The metric key itself needs to go out.. */ - expr__del_id(pctx, cur->key); - - metric = malloc(sizeof(*metric)); - if (!metric) { - rc = -ENOMEM; - goto out_err; - } - - ref = &metric->metric_ref; - ref->metric_name = pe->metric_name; - ref->metric_expr = pe->metric_expr; - list_add_tail(&metric->list, compound_list); - - rc = expr__find_ids(pe->metric_expr, NULL, pctx); - if (rc) - goto out_err; - break; /* The hashmap has been modified, so restart */ - } - } while (!all); - - return 0; - -out_err: - list_for_each_entry_safe(metric, tmp, compound_list, list) - free(metric); - - return rc; - -} - -static void expr_failure(const char *msg, const struct pmu_event *pe) -{ - pr_debug("%s\nOn metric %s\nOn expression %s\n", msg, pe->metric_name, pe->metric_expr); -} - - -struct test__parsing_data { - const struct pmu_event *cpus_table; - struct expr_parse_ctx *ctx; - int failures; -}; - static int test__parsing_callback(const struct pmu_event *pe, const struct pmu_event *table, - void *vdata) + void *data) { - struct test__parsing_data *data = vdata; - struct metric *metric, *tmp; - struct hashmap_entry *cur; - LIST_HEAD(compound_list); - size_t bkt; + int *failures = data; int k; - double result; + struct evlist *evlist; + struct perf_cpu_map *cpus; + struct runtime_stat st; + struct evsel *evsel; + struct rblist metric_events = { + .nr_entries = 0, + }; + int err = 0; if (!pe->metric_expr) return 0; pr_debug("Found metric '%s'\n", pe->metric_name); + (*failures)++; - expr__ctx_clear(data->ctx); - if (expr__find_ids(pe->metric_expr, NULL, data->ctx) < 0) { - expr_failure("Parse find ids failed", pe); - data->failures++; - return 0; + /* + * We need to prepare evlist for stat mode running on CPU 0 + * because that's where all the stats are going to be created. + */ + evlist = evlist__new(); + if (!evlist) + return -ENOMEM; + + cpus = perf_cpu_map__new("0"); + if (!cpus) { + evlist__delete(evlist); + return -ENOMEM; } - if (resolve_metric_simple(data->ctx, &compound_list, table, - pe->metric_name)) { - expr_failure("Could not resolve metrics", pe); - data->failures++; - return TEST_FAIL; /* Don't tolerate errors due to severity */ + perf_evlist__set_maps(&evlist->core, cpus, NULL); + runtime_stat__init(&st); + + err = metricgroup__parse_groups_test(evlist, table, pe->metric_name, + false, false, + &metric_events); + if (err) { + if (!strcmp(pe->metric_name, "M1") || !strcmp(pe->metric_name, "M2") || + !strcmp(pe->metric_name, "M3")) { + (*failures)--; + pr_debug("Expected broken metric %s skipping\n", pe->metric_name); + err = 0; + } + goto out_err; } + err = evlist__alloc_stats(evlist, false); + if (err) + goto out_err; /* * Add all ids with a made up value. The value may trigger divide by * zero when subtracted and so try to make them unique. */ k = 1; - hashmap__for_each_entry(data->ctx->ids, cur, bkt) - expr__add_id_val(data->ctx, strdup(cur->key), k++); - - hashmap__for_each_entry(data->ctx->ids, cur, bkt) { - if (check_parse_cpu(cur->key, table == data->cpus_table, pe)) - data->failures++; + perf_stat__reset_shadow_stats(); + evlist__for_each_entry(evlist, evsel) { + perf_stat__update_shadow_stats(evsel, k, 0, &st); + if (!strcmp(evsel->name, "duration_time")) + update_stats(&walltime_nsecs_stats, k); + k++; } + evlist__for_each_entry(evlist, evsel) { + struct metric_event *me = metricgroup__lookup(&metric_events, evsel, false); - list_for_each_entry_safe(metric, tmp, &compound_list, list) { - expr__add_ref(data->ctx, &metric->metric_ref); - free(metric); - } + if (me != NULL) { + struct metric_expr *mexp; - if (expr__parse(&result, data->ctx, pe->metric_expr)) { - /* - * Parsing failed, make numbers go from large to small which can - * resolve divide by zero issues. - */ - k = 1024; - hashmap__for_each_entry(data->ctx->ids, cur, bkt) - expr__add_id_val(data->ctx, strdup(cur->key), k--); - if (expr__parse(&result, data->ctx, pe->metric_expr)) { - expr_failure("Parse failed", pe); - data->failures++; + list_for_each_entry (mexp, &me->head, nd) { + if (strcmp(mexp->metric_name, pe->metric_name)) + continue; + pr_debug("Result %f\n", test_generic_metric(mexp, 0, &st)); + err = 0; + (*failures)--; + goto out_err; + } } } - return 0; + pr_debug("Didn't find parsed metric %s", pe->metric_name); + err = 1; +out_err: + if (err) + pr_debug("Broken metric %s\n", pe->metric_name); + + /* ... cleanup. */ + metricgroup__rblist_exit(&metric_events); + runtime_stat__exit(&st); + evlist__free_stats(evlist); + perf_cpu_map__put(cpus); + evlist__delete(evlist); + return err; } static int test__parsing(struct test_suite *test __maybe_unused, int subtest __maybe_unused) { - struct test__parsing_data data = { - .cpus_table = pmu_events_table__find(), - .ctx = expr__ctx_new(), - .failures = 0, - }; + int failures = 0; - if (!data.ctx) { - pr_debug("expr__ctx_new failed"); - return TEST_FAIL; - } - pmu_for_each_core_event(test__parsing_callback, &data); - pmu_for_each_sys_event(test__parsing_callback, &data); + pmu_for_each_core_event(test__parsing_callback, &failures); + pmu_for_each_sys_event(test__parsing_callback, &failures); - expr__ctx_free(data.ctx); - return data.failures == 0 ? TEST_OK : TEST_FAIL; + return failures == 0 ? TEST_OK : TEST_FAIL; } struct test_metric { -- cgit v1.2.3 From 7ae5c03a27934bee9daaeede1b0b1d4bada61ffd Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 12 Aug 2022 16:09:44 -0700 Subject: perf pmu-events: Move test events/metrics to JSON Move arrays of pmu_events into the JSON code so that it may be regenerated and modified by the jevents.py script. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Stephane Eranian Cc: Will Deacon Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220812230949.683239-10-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/test/test_soc/cpu/metrics.json | 64 ++++++++++++++++++++ tools/perf/pmu-events/empty-pmu-events.c | 64 ++++++++++++++++++++ tools/perf/tests/expand-cgroup.c | 17 +----- tools/perf/tests/parse-metric.c | 68 +--------------------- 4 files changed, 132 insertions(+), 81 deletions(-) create mode 100644 tools/perf/pmu-events/arch/test/test_soc/cpu/metrics.json diff --git a/tools/perf/pmu-events/arch/test/test_soc/cpu/metrics.json b/tools/perf/pmu-events/arch/test/test_soc/cpu/metrics.json new file mode 100644 index 000000000000..42d9b5242fd7 --- /dev/null +++ b/tools/perf/pmu-events/arch/test/test_soc/cpu/metrics.json @@ -0,0 +1,64 @@ +[ + { + "MetricExpr": "1 / IPC", + "MetricName": "CPI" + }, + { + "MetricExpr": "inst_retired.any / cpu_clk_unhalted.thread", + "MetricName": "IPC", + "MetricGroup": "group1" + }, + { + "MetricExpr": "idq_uops_not_delivered.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))", + "MetricName": "Frontend_Bound_SMT" + }, + { + "MetricExpr": "l1d\\-loads\\-misses / inst_retired.any", + "MetricName": "dcache_miss_cpi" + }, + { + "MetricExpr": "l1i\\-loads\\-misses / inst_retired.any", + "MetricName": "icache_miss_cycles" + }, + { + "MetricExpr": "(dcache_miss_cpi + icache_miss_cycles)", + "MetricName": "cache_miss_cycles", + "MetricGroup": "group1" + }, + { + "MetricExpr": "l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit", + "MetricName": "DCache_L2_All_Hits" + }, + { + "MetricExpr": "max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss", + "MetricName": "DCache_L2_All_Miss" + }, + { + "MetricExpr": "dcache_l2_all_hits + dcache_l2_all_miss", + "MetricName": "DCache_L2_All" + }, + { + "MetricExpr": "d_ratio(dcache_l2_all_hits, dcache_l2_all)", + "MetricName": "DCache_L2_Hits" + }, + { + "MetricExpr": "d_ratio(dcache_l2_all_miss, dcache_l2_all)", + "MetricName": "DCache_L2_Misses" + }, + { + "MetricExpr": "ipc + M2", + "MetricName": "M1" + }, + { + "MetricExpr": "ipc + M1", + "MetricName": "M2" + }, + { + "MetricExpr": "1/M3", + "MetricName": "M3" + }, + { + "MetricExpr": "64 * l1d.replacement / 1000000000 / duration_time", + "MetricName": "L1D_Cache_Fill_BW" + } +] diff --git a/tools/perf/pmu-events/empty-pmu-events.c b/tools/perf/pmu-events/empty-pmu-events.c index 8ef75aff996c..028f44efe48d 100644 --- a/tools/perf/pmu-events/empty-pmu-events.c +++ b/tools/perf/pmu-events/empty-pmu-events.c @@ -105,6 +105,70 @@ static const struct pmu_event pme_test_soc_cpu[] = { .desc = "L2 BTB Correction", .topic = "branch", }, + { + .metric_expr = "1 / IPC", + .metric_name = "CPI", + }, + { + .metric_expr = "inst_retired.any / cpu_clk_unhalted.thread", + .metric_name = "IPC", + .metric_group = "group1", + }, + { + .metric_expr = "idq_uops_not_delivered.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * " + "( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))", + .metric_name = "Frontend_Bound_SMT", + }, + { + .metric_expr = "l1d\\-loads\\-misses / inst_retired.any", + .metric_name = "dcache_miss_cpi", + }, + { + .metric_expr = "l1i\\-loads\\-misses / inst_retired.any", + .metric_name = "icache_miss_cycles", + }, + { + .metric_expr = "(dcache_miss_cpi + icache_miss_cycles)", + .metric_name = "cache_miss_cycles", + .metric_group = "group1", + }, + { + .metric_expr = "l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit", + .metric_name = "DCache_L2_All_Hits", + }, + { + .metric_expr = "max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + " + "l2_rqsts.pf_miss + l2_rqsts.rfo_miss", + .metric_name = "DCache_L2_All_Miss", + }, + { + .metric_expr = "dcache_l2_all_hits + dcache_l2_all_miss", + .metric_name = "DCache_L2_All", + }, + { + .metric_expr = "d_ratio(dcache_l2_all_hits, dcache_l2_all)", + .metric_name = "DCache_L2_Hits", + }, + { + .metric_expr = "d_ratio(dcache_l2_all_miss, dcache_l2_all)", + .metric_name = "DCache_L2_Misses", + }, + { + .metric_expr = "ipc + M2", + .metric_name = "M1", + }, + { + .metric_expr = "ipc + M1", + .metric_name = "M2", + }, + { + .metric_expr = "1/M3", + .metric_name = "M3", + }, + { + .metric_expr = "64 * l1d.replacement / 1000000000 / duration_time", + .metric_name = "L1D_Cache_Fill_BW", + }, { .name = 0, .event = 0, diff --git a/tools/perf/tests/expand-cgroup.c b/tools/perf/tests/expand-cgroup.c index 411fc578e5a4..e79ee8621a90 100644 --- a/tools/perf/tests/expand-cgroup.c +++ b/tools/perf/tests/expand-cgroup.c @@ -180,26 +180,13 @@ static int expand_metric_events(void) struct evlist *evlist; struct rblist metric_events; const char metric_str[] = "CPI"; - - struct pmu_event pme_test[] = { - { - .metric_expr = "instructions / cycles", - .metric_name = "IPC", - }, - { - .metric_expr = "1 / IPC", - .metric_name = "CPI", - }, - { - .metric_expr = NULL, - .metric_name = NULL, - }, - }; + const struct pmu_event *pme_test; evlist = evlist__new(); TEST_ASSERT_VAL("failed to get evlist", evlist); rblist__init(&metric_events); + pme_test = find_core_events_table("testarch", "testcpu"); ret = metricgroup__parse_groups_test(evlist, pme_test, metric_str, false, false, &metric_events); if (ret < 0) { diff --git a/tools/perf/tests/parse-metric.c b/tools/perf/tests/parse-metric.c index 7aebde7c37ec..30c7091857b8 100644 --- a/tools/perf/tests/parse-metric.c +++ b/tools/perf/tests/parse-metric.c @@ -13,72 +13,6 @@ #include "stat.h" #include "pmu.h" -static struct pmu_event pme_test[] = { -{ - .metric_expr = "inst_retired.any / cpu_clk_unhalted.thread", - .metric_name = "IPC", - .metric_group = "group1", -}, -{ - .metric_expr = "idq_uops_not_delivered.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * " - "( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))", - .metric_name = "Frontend_Bound_SMT", -}, -{ - .metric_expr = "l1d\\-loads\\-misses / inst_retired.any", - .metric_name = "dcache_miss_cpi", -}, -{ - .metric_expr = "l1i\\-loads\\-misses / inst_retired.any", - .metric_name = "icache_miss_cycles", -}, -{ - .metric_expr = "(dcache_miss_cpi + icache_miss_cycles)", - .metric_name = "cache_miss_cycles", - .metric_group = "group1", -}, -{ - .metric_expr = "l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit", - .metric_name = "DCache_L2_All_Hits", -}, -{ - .metric_expr = "max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + " - "l2_rqsts.pf_miss + l2_rqsts.rfo_miss", - .metric_name = "DCache_L2_All_Miss", -}, -{ - .metric_expr = "dcache_l2_all_hits + dcache_l2_all_miss", - .metric_name = "DCache_L2_All", -}, -{ - .metric_expr = "d_ratio(dcache_l2_all_hits, dcache_l2_all)", - .metric_name = "DCache_L2_Hits", -}, -{ - .metric_expr = "d_ratio(dcache_l2_all_miss, dcache_l2_all)", - .metric_name = "DCache_L2_Misses", -}, -{ - .metric_expr = "ipc + m2", - .metric_name = "M1", -}, -{ - .metric_expr = "ipc + m1", - .metric_name = "M2", -}, -{ - .metric_expr = "1/m3", - .metric_name = "M3", -}, -{ - .metric_expr = "64 * l1d.replacement / 1000000000 / duration_time", - .metric_name = "L1D_Cache_Fill_BW", -}, -{ - .name = NULL, -} -}; - struct value { const char *event; u64 val; @@ -138,6 +72,7 @@ static int __compute_metric(const char *name, struct value *vals, struct rblist metric_events = { .nr_entries = 0, }; + const struct pmu_event *pme_test; struct perf_cpu_map *cpus; struct runtime_stat st; struct evlist *evlist; @@ -161,6 +96,7 @@ static int __compute_metric(const char *name, struct value *vals, runtime_stat__init(&st); /* Parse the metric into metric_events list. */ + pme_test = find_core_events_table("testarch", "testcpu"); err = metricgroup__parse_groups_test(evlist, pme_test, name, false, false, &metric_events); -- cgit v1.2.3 From 660842e468dcefb5d1d4fb40ed3abe4d1388dff7 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 12 Aug 2022 16:09:45 -0700 Subject: perf pmu-events: Don't assume pmu_event is an array The current code assumes that a struct pmu_event can be iterated over forward until a NULL pmu_event is encountered. This makes it difficult to refactor pmu_event. Add a loop function taking a callback function that's passed the struct pmu_event. This way the pmu_event is only needed for one element and not an entire array. Switch existing code iterating over the pmu_event arrays to use the new loop function pmu_events_table_for_each_event. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Stephane Eranian Cc: Will Deacon Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220812230949.683239-11-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/empty-pmu-events.c | 34 +++--- tools/perf/pmu-events/jevents.py | 34 +++--- tools/perf/pmu-events/pmu-events.h | 3 + tools/perf/tests/pmu-events.c | 136 +++++++++++++---------- tools/perf/util/metricgroup.c | 181 +++++++++++++++++++++---------- tools/perf/util/pmu.c | 65 ++++++----- tools/perf/util/s390-sample-raw.c | 42 +++++-- 7 files changed, 313 insertions(+), 182 deletions(-) diff --git a/tools/perf/pmu-events/empty-pmu-events.c b/tools/perf/pmu-events/empty-pmu-events.c index 028f44efe48d..bee1967baa2b 100644 --- a/tools/perf/pmu-events/empty-pmu-events.c +++ b/tools/perf/pmu-events/empty-pmu-events.c @@ -247,6 +247,20 @@ static const struct pmu_sys_events pmu_sys_event_tables[] = { }, }; +int pmu_events_table_for_each_event(const struct pmu_event *table, pmu_event_iter_fn fn, + void *data) +{ + for (const struct pmu_event *pe = &table[0]; + pe->name || pe->metric_group || pe->metric_name; + pe++) { + int ret = fn(pe, table, data); + + if (ret) + return ret; + } + return 0; +} + const struct pmu_event *perf_pmu__find_table(struct perf_pmu *pmu) { const struct pmu_event *table = NULL; @@ -291,14 +305,10 @@ int pmu_for_each_core_event(pmu_event_iter_fn fn, void *data) for (const struct pmu_events_map *tables = &pmu_events_map[0]; tables->table; tables++) { - for (const struct pmu_event *pe = &tables->table[0]; - pe->name || pe->metric_group || pe->metric_name; - pe++) { - int ret = fn(pe, &tables->table[0], data); + int ret = pmu_events_table_for_each_event(tables->table, fn, data); - if (ret) - return ret; - } + if (ret) + return ret; } return 0; } @@ -319,14 +329,10 @@ int pmu_for_each_sys_event(pmu_event_iter_fn fn, void *data) for (const struct pmu_sys_events *tables = &pmu_sys_event_tables[0]; tables->name; tables++) { - for (const struct pmu_event *pe = &tables->table[0]; - pe->name || pe->metric_group || pe->metric_name; - pe++) { - int ret = fn(pe, &tables->table[0], data); + int ret = pmu_events_table_for_each_event(tables->table, fn, data); - if (ret) - return ret; - } + if (ret) + return ret; } return 0; } diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index 1a04b848d736..977f2061a990 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -410,6 +410,20 @@ static const struct pmu_sys_events pmu_sys_event_tables[] = { \t}, }; +int pmu_events_table_for_each_event(const struct pmu_event *table, pmu_event_iter_fn fn, + void *data) +{ + for (const struct pmu_event *pe = &table[0]; + pe->name || pe->metric_group || pe->metric_name; + pe++) { + int ret = fn(pe, table, data); + + if (ret) + return ret; + } + return 0; +} + const struct pmu_event *perf_pmu__find_table(struct perf_pmu *pmu) { const struct pmu_event *table = NULL; @@ -453,14 +467,10 @@ int pmu_for_each_core_event(pmu_event_iter_fn fn, void *data) for (const struct pmu_events_map *tables = &pmu_events_map[0]; tables->table; tables++) { - for (const struct pmu_event *pe = &tables->table[0]; - pe->name || pe->metric_group || pe->metric_name; - pe++) { - int ret = fn(pe, &tables->table[0], data); + int ret = pmu_events_table_for_each_event(tables->table, fn, data); - if (ret) - return ret; - } + if (ret) + return ret; } return 0; } @@ -481,14 +491,10 @@ int pmu_for_each_sys_event(pmu_event_iter_fn fn, void *data) for (const struct pmu_sys_events *tables = &pmu_sys_event_tables[0]; tables->name; tables++) { - for (const struct pmu_event *pe = &tables->table[0]; - pe->name || pe->metric_group || pe->metric_name; - pe++) { - int ret = fn(pe, &tables->table[0], data); + int ret = pmu_events_table_for_each_event(tables->table, fn, data); - if (ret) - return ret; - } + if (ret) + return ret; } return 0; } diff --git a/tools/perf/pmu-events/pmu-events.h b/tools/perf/pmu-events/pmu-events.h index 485e730f9922..70672842f77f 100644 --- a/tools/perf/pmu-events/pmu-events.h +++ b/tools/perf/pmu-events/pmu-events.h @@ -34,6 +34,9 @@ typedef int (*pmu_event_iter_fn)(const struct pmu_event *pe, const struct pmu_event *table, void *data); +int pmu_events_table_for_each_event(const struct pmu_event *table, pmu_event_iter_fn fn, + void *data); + const struct pmu_event *perf_pmu__find_table(struct perf_pmu *pmu); const struct pmu_event *find_core_events_table(const char *arch, const char *cpuid); int pmu_for_each_core_event(pmu_event_iter_fn fn, void *data); diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index a64497cb9fb2..e308d480f0fb 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -423,84 +423,104 @@ static int compare_alias_to_test_event(struct perf_pmu_alias *alias, return 0; } -/* Verify generated events from pmu-events.c are as expected */ -static int test__pmu_event_table(struct test_suite *test __maybe_unused, - int subtest __maybe_unused) +static int test__pmu_event_table_core_callback(const struct pmu_event *pe, + const struct pmu_event *table __maybe_unused, + void *data) { - const struct pmu_event *sys_event_tables = find_sys_events_table("pme_test_soc_sys"); - const struct pmu_event *table = find_core_events_table("testarch", "testcpu"); - int map_events = 0, expected_events; + int *map_events = data; + struct perf_pmu_test_event const **test_event_table; + bool found = false; - /* ignore 3x sentinels */ - expected_events = ARRAY_SIZE(core_events) + - ARRAY_SIZE(uncore_events) + - ARRAY_SIZE(sys_events) - 3; + if (!pe->name) + return 0; - if (!table || !sys_event_tables) - return -1; + if (pe->pmu) + test_event_table = &uncore_events[0]; + else + test_event_table = &core_events[0]; - for (; table->name; table++) { - struct perf_pmu_test_event const **test_event_table; - bool found = false; + for (; *test_event_table; test_event_table++) { + struct perf_pmu_test_event const *test_event = *test_event_table; + struct pmu_event const *event = &test_event->event; - if (table->pmu) - test_event_table = &uncore_events[0]; - else - test_event_table = &core_events[0]; + if (strcmp(pe->name, event->name)) + continue; + found = true; + (*map_events)++; - for (; *test_event_table; test_event_table++) { - struct perf_pmu_test_event const *test_event = *test_event_table; - struct pmu_event const *event = &test_event->event; + if (compare_pmu_events(pe, event)) + return -1; - if (strcmp(table->name, event->name)) - continue; - found = true; - map_events++; + pr_debug("testing event table %s: pass\n", pe->name); + } + if (!found) { + pr_err("testing event table: could not find event %s\n", pe->name); + return -1; + } + return 0; +} - if (compare_pmu_events(table, event)) - return -1; +static int test__pmu_event_table_sys_callback(const struct pmu_event *pe, + const struct pmu_event *table __maybe_unused, + void *data) +{ + int *map_events = data; + struct perf_pmu_test_event const **test_event_table; + bool found = false; - pr_debug("testing event table %s: pass\n", table->name); - } + test_event_table = &sys_events[0]; - if (!found) { - pr_err("testing event table: could not find event %s\n", - table->name); - return -1; - } - } + for (; *test_event_table; test_event_table++) { + struct perf_pmu_test_event const *test_event = *test_event_table; + struct pmu_event const *event = &test_event->event; - for (table = sys_event_tables; table->name; table++) { - struct perf_pmu_test_event const **test_event_table; - bool found = false; + if (strcmp(pe->name, event->name)) + continue; + found = true; + (*map_events)++; - test_event_table = &sys_events[0]; + if (compare_pmu_events(pe, event)) + return TEST_FAIL; - for (; *test_event_table; test_event_table++) { - struct perf_pmu_test_event const *test_event = *test_event_table; - struct pmu_event const *event = &test_event->event; + pr_debug("testing sys event table %s: pass\n", pe->name); + } + if (!found) { + pr_debug("testing sys event table: could not find event %s\n", pe->name); + return TEST_FAIL; + } + return TEST_OK; +} - if (strcmp(table->name, event->name)) - continue; - found = true; - map_events++; +/* Verify generated events from pmu-events.c are as expected */ +static int test__pmu_event_table(struct test_suite *test __maybe_unused, + int subtest __maybe_unused) +{ + const struct pmu_event *sys_event_table = find_sys_events_table("pme_test_soc_sys"); + const struct pmu_event *table = find_core_events_table("testarch", "testcpu"); + int map_events = 0, expected_events, err; - if (compare_pmu_events(table, event)) - return -1; + /* ignore 3x sentinels */ + expected_events = ARRAY_SIZE(core_events) + + ARRAY_SIZE(uncore_events) + + ARRAY_SIZE(sys_events) - 3; - pr_debug("testing sys event table %s: pass\n", table->name); - } - if (!found) { - pr_debug("testing event table: could not find event %s\n", - table->name); - return -1; - } - } + if (!table || !sys_event_table) + return -1; + + err = pmu_events_table_for_each_event(table, test__pmu_event_table_core_callback, + &map_events); + if (err) + return err; + + err = pmu_events_table_for_each_event(sys_event_table, test__pmu_event_table_sys_callback, + &map_events); + if (err) + return err; if (map_events != expected_events) { pr_err("testing event table: found %d, but expected %d\n", map_events, expected_events); - return -1; + return TEST_FAIL; } return 0; diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index 8d994539d6ea..cae97b6dc5bc 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -538,12 +538,40 @@ static int metricgroup__print_sys_event_iter(const struct pmu_event *pe, d->details, d->groups, d->metriclist); } +struct metricgroup_print_data { + const char *pmu_name; + struct strlist *metriclist; + char *filter; + struct rblist *groups; + bool metricgroups; + bool raw; + bool details; +}; + +static int metricgroup__print_callback(const struct pmu_event *pe, + const struct pmu_event *table __maybe_unused, + void *vdata) +{ + struct metricgroup_print_data *data = vdata; + + if (!pe->metric_expr) + return 0; + + if (data->pmu_name && perf_pmu__is_hybrid(pe->pmu) && strcmp(data->pmu_name, pe->pmu)) + return 0; + + return metricgroup__print_pmu_event(pe, data->metricgroups, data->filter, + data->raw, data->details, data->groups, + data->metriclist); +} + void metricgroup__print(bool metrics, bool metricgroups, char *filter, bool raw, bool details, const char *pmu_name) { struct rblist groups; struct rb_node *node, *next; struct strlist *metriclist = NULL; + const struct pmu_event *table; if (!metricgroups) { metriclist = strlist__new(NULL, NULL); @@ -555,22 +583,22 @@ void metricgroup__print(bool metrics, bool metricgroups, char *filter, groups.node_new = mep_new; groups.node_cmp = mep_cmp; groups.node_delete = mep_delete; - for (const struct pmu_event *pe = pmu_events_table__find(); pe; pe++) { + table = pmu_events_table__find(); + if (table) { + struct metricgroup_print_data data = { + .pmu_name = pmu_name, + .metriclist = metriclist, + .metricgroups = metricgroups, + .filter = filter, + .raw = raw, + .details = details, + .groups = &groups, + }; - if (!pe->name && !pe->metric_group && !pe->metric_name) - break; - if (!pe->metric_expr) - continue; - if (pmu_name && perf_pmu__is_hybrid(pe->pmu) && - strcmp(pmu_name, pe->pmu)) { - continue; - } - if (metricgroup__print_pmu_event(pe, metricgroups, filter, - raw, details, &groups, - metriclist) < 0) - return; + pmu_events_table_for_each_event(table, + metricgroup__print_callback, + &data); } - { struct metricgroup_iter_data data = { .fn = metricgroup__print_sys_event_iter, @@ -1043,30 +1071,35 @@ static int __add_metric(struct list_head *metric_list, return ret; } -#define table_for_each_event(__pe, __idx, __table) \ - if (__table) \ - for (__idx = 0, __pe = &__table[__idx]; \ - __pe->name || __pe->metric_group || __pe->metric_name; \ - __pe = &__table[++__idx]) +struct metricgroup__find_metric_data { + const char *metric; + const struct pmu_event *pe; +}; + +static int metricgroup__find_metric_callback(const struct pmu_event *pe, + const struct pmu_event *table __maybe_unused, + void *vdata) +{ + struct metricgroup__find_metric_data *data = vdata; + + if (!match_metric(pe->metric_name, data->metric)) + return 0; -#define table_for_each_metric(__pe, __idx, __table, __metric) \ - table_for_each_event(__pe, __idx, __table) \ - if (__pe->metric_expr && \ - (match_metric(__pe->metric_group, __metric) || \ - match_metric(__pe->metric_name, __metric))) + data->pe = pe; + return -1; +} const struct pmu_event *metricgroup__find_metric(const char *metric, const struct pmu_event *table) { - const struct pmu_event *pe; - int i; + struct metricgroup__find_metric_data data = { + .metric = metric, + .pe = NULL, + }; - table_for_each_event(pe, i, table) { - if (match_metric(pe->metric_name, metric)) - return pe; - } + pmu_events_table_for_each_event(table, metricgroup__find_metric_callback, &data); - return NULL; + return data.pe; } static int add_metric(struct list_head *metric_list, @@ -1151,6 +1184,33 @@ static int metric_list_cmp(void *priv __maybe_unused, const struct list_head *l, return right_count - left_count; } +struct metricgroup__add_metric_data { + struct list_head *list; + const char *metric_name; + const char *modifier; + bool metric_no_group; + bool has_match; +}; + +static int metricgroup__add_metric_callback(const struct pmu_event *pe, + const struct pmu_event *table, + void *vdata) +{ + struct metricgroup__add_metric_data *data = vdata; + int ret = 0; + + if (pe->metric_expr && + (match_metric(pe->metric_group, data->metric_name) || + match_metric(pe->metric_name, data->metric_name))) { + + data->has_match = true; + ret = add_metric(data->list, pe, data->modifier, data->metric_no_group, + /*root_metric=*/NULL, + /*visited_metrics=*/NULL, table); + } + return ret; +} + /** * metricgroup__add_metric - Find and add a metric, or a metric group. * @metric_name: The name of the metric or metric group. For example, "IPC" @@ -1169,24 +1229,29 @@ static int metricgroup__add_metric(const char *metric_name, const char *modifier struct list_head *metric_list, const struct pmu_event *table) { - const struct pmu_event *pe; LIST_HEAD(list); - int i, ret; + int ret; bool has_match = false; - /* - * Iterate over all metrics seeing if metric matches either the name or - * group. When it does add the metric to the list. - */ - table_for_each_metric(pe, i, table, metric_name) { - has_match = true; - ret = add_metric(&list, pe, modifier, metric_no_group, - /*root_metric=*/NULL, - /*visited_metrics=*/NULL, table); + { + struct metricgroup__add_metric_data data = { + .list = &list, + .metric_name = metric_name, + .modifier = modifier, + .metric_no_group = metric_no_group, + .has_match = false, + }; + /* + * Iterate over all metrics seeing if metric matches either the + * name or group. When it does add the metric to the list. + */ + ret = pmu_events_table_for_each_event(table, metricgroup__add_metric_callback, + &data); if (ret) goto out; - } + has_match = data.has_match; + } { struct metricgroup_iter_data data = { .fn = metricgroup__add_metric_sys_event_iter, @@ -1602,26 +1667,30 @@ int metricgroup__parse_groups_test(struct evlist *evlist, metric_no_merge, &perf_pmu__fake, metric_events, table); } +static int metricgroup__has_metric_callback(const struct pmu_event *pe, + const struct pmu_event *table __maybe_unused, + void *vdata) +{ + const char *metric = vdata; + + if (!pe->metric_expr) + return 0; + + if (match_metric(pe->metric_name, metric)) + return 1; + + return 0; +} + bool metricgroup__has_metric(const char *metric) { const struct pmu_event *table = pmu_events_table__find(); - const struct pmu_event *pe; - int i; if (!table) return false; - for (i = 0; ; i++) { - pe = &table[i]; - - if (!pe->name && !pe->metric_group && !pe->metric_name) - break; - if (!pe->metric_expr) - continue; - if (match_metric(pe->metric_name, metric)) - return true; - } - return false; + return pmu_events_table_for_each_event(table, metricgroup__has_metric_callback, + (void *)metric) ? true : false; } int metricgroup__copy_metric_events(struct evlist *evlist, struct cgroup *cgrp, diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index f117324eb5f0..dd1e171d7480 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -791,6 +791,36 @@ out: return res; } +struct pmu_add_cpu_aliases_map_data { + struct list_head *head; + const char *name; + const char *cpu_name; + struct perf_pmu *pmu; +}; + +static int pmu_add_cpu_aliases_map_callback(const struct pmu_event *pe, + const struct pmu_event *table __maybe_unused, + void *vdata) +{ + struct pmu_add_cpu_aliases_map_data *data = vdata; + const char *pname = pe->pmu ? pe->pmu : data->cpu_name; + + if (!pe->name) + return 0; + + if (data->pmu->is_uncore && pmu_uncore_alias_match(pname, data->name)) + goto new_alias; + + if (strcmp(pname, data->name)) + return 0; + +new_alias: + /* need type casts to override 'const' */ + __perf_pmu__new_alias(data->head, NULL, (char *)pe->name, (char *)pe->desc, + (char *)pe->event, pe); + return 0; +} + /* * From the pmu_events_map, find the table of PMU events that corresponds * to the current running CPU. Then, add all PMU events from that table @@ -799,35 +829,14 @@ out: void pmu_add_cpu_aliases_table(struct list_head *head, struct perf_pmu *pmu, const struct pmu_event *table) { - int i; - const char *name = pmu->name; - /* - * Found a matching PMU events table. Create aliases - */ - i = 0; - while (1) { - const char *cpu_name = is_arm_pmu_core(name) ? name : "cpu"; - const struct pmu_event *pe = &table[i++]; - const char *pname = pe->pmu ? pe->pmu : cpu_name; - - if (!pe->name) { - if (pe->metric_group || pe->metric_name) - continue; - break; - } - - if (pmu->is_uncore && pmu_uncore_alias_match(pname, name)) - goto new_alias; - - if (strcmp(pname, name)) - continue; + struct pmu_add_cpu_aliases_map_data data = { + .head = head, + .name = pmu->name, + .cpu_name = is_arm_pmu_core(pmu->name) ? pmu->name : "cpu", + .pmu = pmu, + }; -new_alias: - /* need type casts to override 'const' */ - __perf_pmu__new_alias(head, NULL, (char *)pe->name, - (char *)pe->desc, (char *)pe->event, - pe); - } + pmu_events_table_for_each_event(table, pmu_add_cpu_aliases_map_callback, &data); } static void pmu_add_cpu_aliases(struct list_head *head, struct perf_pmu *pmu) diff --git a/tools/perf/util/s390-sample-raw.c b/tools/perf/util/s390-sample-raw.c index dddd2be59827..235319d45d02 100644 --- a/tools/perf/util/s390-sample-raw.c +++ b/tools/perf/util/s390-sample-raw.c @@ -129,6 +129,28 @@ static int get_counterset_start(int setnr) } } +struct get_counter_name_data { + int wanted; + const char *result; +}; + +static int get_counter_name_callback(const struct pmu_event *evp, + const struct pmu_event *table __maybe_unused, + void *vdata) +{ + struct get_counter_name_data *data = vdata; + int rc, event_nr; + + if (evp->name == NULL || evp->event == NULL) + return 0; + rc = sscanf(evp->event, "event=%x", &event_nr); + if (rc == 1 && event_nr == data->wanted) { + data->result = evp->name; + return 1; /* Terminate the search. */ + } + return 0; +} + /* Scan the PMU table and extract the logical name of a counter from the * PMU events table. Input is the counter set and counter number with in the * set. Construct the event number and use this as key. If they match return @@ -137,20 +159,16 @@ static int get_counterset_start(int setnr) */ static const char *get_counter_name(int set, int nr, const struct pmu_event *table) { - int rc, event_nr, wanted = get_counterset_start(set) + nr; + struct get_counter_name_data data = { + .wanted = get_counterset_start(set) + nr, + .result = NULL, + }; - if (table) { - const struct pmu_event *evp = table; + if (!table) + return NULL; - for (; evp->name || evp->event || evp->desc; ++evp) { - if (evp->name == NULL || evp->event == NULL) - continue; - rc = sscanf(evp->event, "event=%x", &event_nr); - if (rc == 1 && event_nr == wanted) - return evp->name; - } - } - return NULL; + pmu_events_table_for_each_event(table, get_counter_name_callback, &data); + return data.result; } static void s390_cpumcfdg_dump(struct perf_sample *sample) -- cgit v1.2.3 From 1ba3752aec30c04bfb7c82b44332ff98294ec0b8 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 12 Aug 2022 16:09:46 -0700 Subject: perf pmu-events: Hide the pmu_events Hide that the pmu_event structs are an array with a new wrapper struct. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Stephane Eranian Cc: Will Deacon Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220812230949.683239-12-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/arm64/util/pmu.c | 2 +- tools/perf/pmu-events/empty-pmu-events.c | 44 ++++++++++++++++-------------- tools/perf/pmu-events/jevents.py | 47 ++++++++++++++++++-------------- tools/perf/pmu-events/pmu-events.h | 12 ++++---- tools/perf/tests/expand-cgroup.c | 2 +- tools/perf/tests/parse-metric.c | 2 +- tools/perf/tests/pmu-events.c | 16 +++++------ tools/perf/util/metricgroup.c | 42 ++++++++++++++-------------- tools/perf/util/metricgroup.h | 5 ++-- tools/perf/util/pmu.c | 10 +++---- tools/perf/util/pmu.h | 4 +-- tools/perf/util/s390-sample-raw.c | 6 ++-- 12 files changed, 101 insertions(+), 91 deletions(-) diff --git a/tools/perf/arch/arm64/util/pmu.c b/tools/perf/arch/arm64/util/pmu.c index 92d774647f6e..f849b1e88d43 100644 --- a/tools/perf/arch/arm64/util/pmu.c +++ b/tools/perf/arch/arm64/util/pmu.c @@ -3,7 +3,7 @@ #include "../../../util/cpumap.h" #include "../../../util/pmu.h" -const struct pmu_event *pmu_events_table__find(void) +const struct pmu_events_table *pmu_events_table__find(void) { struct perf_pmu *pmu = NULL; diff --git a/tools/perf/pmu-events/empty-pmu-events.c b/tools/perf/pmu-events/empty-pmu-events.c index bee1967baa2b..5ed8c0aa4817 100644 --- a/tools/perf/pmu-events/empty-pmu-events.c +++ b/tools/perf/pmu-events/empty-pmu-events.c @@ -176,6 +176,10 @@ static const struct pmu_event pme_test_soc_cpu[] = { }, }; +/* Struct used to make the PMU event table implementation opaque to callers. */ +struct pmu_events_table { + const struct pmu_event *entries; +}; /* * Map a CPU to its table of PMU events. The CPU is identified by the @@ -188,7 +192,7 @@ static const struct pmu_event pme_test_soc_cpu[] = { struct pmu_events_map { const char *arch; const char *cpuid; - const struct pmu_event *table; + const struct pmu_events_table table; }; /* @@ -199,12 +203,12 @@ static const struct pmu_events_map pmu_events_map[] = { { .arch = "testarch", .cpuid = "testcpu", - .table = pme_test_soc_cpu, + .table = { pme_test_soc_cpu }, }, { .arch = 0, .cpuid = 0, - .table = 0, + .table = { 0 }, }, }; @@ -234,23 +238,23 @@ static const struct pmu_event pme_test_soc_sys[] = { struct pmu_sys_events { const char *name; - const struct pmu_event *table; + const struct pmu_events_table table; }; static const struct pmu_sys_events pmu_sys_event_tables[] = { { - .table = pme_test_soc_sys, + .table = { pme_test_soc_sys }, .name = "pme_test_soc_sys", }, { - .table = 0 + .table = { 0 } }, }; -int pmu_events_table_for_each_event(const struct pmu_event *table, pmu_event_iter_fn fn, +int pmu_events_table_for_each_event(const struct pmu_events_table *table, pmu_event_iter_fn fn, void *data) { - for (const struct pmu_event *pe = &table[0]; + for (const struct pmu_event *pe = &table->entries[0]; pe->name || pe->metric_group || pe->metric_name; pe++) { int ret = fn(pe, table, data); @@ -261,9 +265,9 @@ int pmu_events_table_for_each_event(const struct pmu_event *table, pmu_event_ite return 0; } -const struct pmu_event *perf_pmu__find_table(struct perf_pmu *pmu) +const struct pmu_events_table *perf_pmu__find_table(struct perf_pmu *pmu) { - const struct pmu_event *table = NULL; + const struct pmu_events_table *table = NULL; char *cpuid = perf_pmu__getcpuid(pmu); int i; @@ -277,11 +281,11 @@ const struct pmu_event *perf_pmu__find_table(struct perf_pmu *pmu) for (;;) { const struct pmu_events_map *map = &pmu_events_map[i++]; - if (!map->table) + if (!map->cpuid) break; if (!strcmp_cpuid_str(map->cpuid, cpuid)) { - table = map->table; + table = &map->table; break; } } @@ -289,13 +293,13 @@ const struct pmu_event *perf_pmu__find_table(struct perf_pmu *pmu) return table; } -const struct pmu_event *find_core_events_table(const char *arch, const char *cpuid) +const struct pmu_events_table *find_core_events_table(const char *arch, const char *cpuid) { for (const struct pmu_events_map *tables = &pmu_events_map[0]; - tables->table; + tables->arch; tables++) { if (!strcmp(tables->arch, arch) && !strcmp_cpuid_str(tables->cpuid, cpuid)) - return tables->table; + return &tables->table; } return NULL; } @@ -303,9 +307,9 @@ const struct pmu_event *find_core_events_table(const char *arch, const char *cpu int pmu_for_each_core_event(pmu_event_iter_fn fn, void *data) { for (const struct pmu_events_map *tables = &pmu_events_map[0]; - tables->table; + tables->arch; tables++) { - int ret = pmu_events_table_for_each_event(tables->table, fn, data); + int ret = pmu_events_table_for_each_event(&tables->table, fn, data); if (ret) return ret; @@ -313,13 +317,13 @@ int pmu_for_each_core_event(pmu_event_iter_fn fn, void *data) return 0; } -const struct pmu_event *find_sys_events_table(const char *name) +const struct pmu_events_table *find_sys_events_table(const char *name) { for (const struct pmu_sys_events *tables = &pmu_sys_event_tables[0]; tables->name; tables++) { if (!strcmp(tables->name, name)) - return tables->table; + return &tables->table; } return NULL; } @@ -329,7 +333,7 @@ int pmu_for_each_sys_event(pmu_event_iter_fn fn, void *data) for (const struct pmu_sys_events *tables = &pmu_sys_event_tables[0]; tables->name; tables++) { - int ret = pmu_events_table_for_each_event(tables->table, fn, data); + int ret = pmu_events_table_for_each_event(&tables->table, fn, data); if (ret) return ret; diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index 977f2061a990..4b7948ba57d6 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -335,6 +335,11 @@ def process_one_file(parents: Sequence[str], item: os.DirEntry) -> None: def print_mapping_table(archs: Sequence[str]) -> None: """Read the mapfile and generate the struct from cpuid string to event table.""" _args.output_file.write(""" +/* Struct used to make the PMU event table implementation opaque to callers. */ +struct pmu_events_table { + const struct pmu_event *entries; +}; + /* * Map a CPU to its table of PMU events. The CPU is identified by the * cpuid field, which is an arch-specific identifier for the CPU. @@ -346,7 +351,7 @@ def print_mapping_table(archs: Sequence[str]) -> None: struct pmu_events_map { const char *arch; const char *cpuid; - const struct pmu_event *table; + struct pmu_events_table table; }; /* @@ -360,7 +365,7 @@ const struct pmu_events_map pmu_events_map[] = { _args.output_file.write("""{ \t.arch = "testarch", \t.cpuid = "testcpu", -\t.table = pme_test_soc_cpu, +\t.table = { pme_test_soc_cpu }, }, """) else: @@ -375,7 +380,7 @@ const struct pmu_events_map pmu_events_map[] = { _args.output_file.write(f"""{{ \t.arch = "{arch}", \t.cpuid = "{cpuid}", -\t.table = {tblname} +\t.table = {{ {tblname} }} }}, """) first = False @@ -383,7 +388,7 @@ const struct pmu_events_map pmu_events_map[] = { _args.output_file.write("""{ \t.arch = 0, \t.cpuid = 0, -\t.table = 0, +\t.table = { 0 }, } }; """) @@ -394,26 +399,26 @@ def print_system_mapping_table() -> None: _args.output_file.write(""" struct pmu_sys_events { \tconst char *name; -\tconst struct pmu_event *table; +\tstruct pmu_events_table table; }; static const struct pmu_sys_events pmu_sys_event_tables[] = { """) for tblname in _sys_event_tables: _args.output_file.write(f"""\t{{ -\t\t.table = {tblname}, +\t\t.table = {{ {tblname} }}, \t\t.name = \"{tblname}\", \t}}, """) _args.output_file.write("""\t{ -\t\t.table = 0 +\t\t.table = { 0 } \t}, }; -int pmu_events_table_for_each_event(const struct pmu_event *table, pmu_event_iter_fn fn, +int pmu_events_table_for_each_event(const struct pmu_events_table *table, pmu_event_iter_fn fn, void *data) { - for (const struct pmu_event *pe = &table[0]; + for (const struct pmu_event *pe = &table->entries[0]; pe->name || pe->metric_group || pe->metric_name; pe++) { int ret = fn(pe, table, data); @@ -424,9 +429,9 @@ int pmu_events_table_for_each_event(const struct pmu_event *table, pmu_event_ite return 0; } -const struct pmu_event *perf_pmu__find_table(struct perf_pmu *pmu) +const struct pmu_events_table *perf_pmu__find_table(struct perf_pmu *pmu) { - const struct pmu_event *table = NULL; + const struct pmu_events_table *table = NULL; char *cpuid = perf_pmu__getcpuid(pmu); int i; @@ -439,11 +444,11 @@ const struct pmu_event *perf_pmu__find_table(struct perf_pmu *pmu) i = 0; for (;;) { const struct pmu_events_map *map = &pmu_events_map[i++]; - if (!map->table) + if (!map->arch) break; if (!strcmp_cpuid_str(map->cpuid, cpuid)) { - table = map->table; + table = &map->table; break; } } @@ -451,13 +456,13 @@ const struct pmu_event *perf_pmu__find_table(struct perf_pmu *pmu) return table; } -const struct pmu_event *find_core_events_table(const char *arch, const char *cpuid) +const struct pmu_events_table *find_core_events_table(const char *arch, const char *cpuid) { for (const struct pmu_events_map *tables = &pmu_events_map[0]; - tables->table; + tables->arch; tables++) { if (!strcmp(tables->arch, arch) && !strcmp_cpuid_str(tables->cpuid, cpuid)) - return tables->table; + return &tables->table; } return NULL; } @@ -465,9 +470,9 @@ const struct pmu_event *find_core_events_table(const char *arch, const char *cpu int pmu_for_each_core_event(pmu_event_iter_fn fn, void *data) { for (const struct pmu_events_map *tables = &pmu_events_map[0]; - tables->table; + tables->arch; tables++) { - int ret = pmu_events_table_for_each_event(tables->table, fn, data); + int ret = pmu_events_table_for_each_event(&tables->table, fn, data); if (ret) return ret; @@ -475,13 +480,13 @@ int pmu_for_each_core_event(pmu_event_iter_fn fn, void *data) return 0; } -const struct pmu_event *find_sys_events_table(const char *name) +const struct pmu_events_table *find_sys_events_table(const char *name) { for (const struct pmu_sys_events *tables = &pmu_sys_event_tables[0]; tables->name; tables++) { if (!strcmp(tables->name, name)) - return tables->table; + return &tables->table; } return NULL; } @@ -491,7 +496,7 @@ int pmu_for_each_sys_event(pmu_event_iter_fn fn, void *data) for (const struct pmu_sys_events *tables = &pmu_sys_event_tables[0]; tables->name; tables++) { - int ret = pmu_events_table_for_each_event(tables->table, fn, data); + int ret = pmu_events_table_for_each_event(&tables->table, fn, data); if (ret) return ret; diff --git a/tools/perf/pmu-events/pmu-events.h b/tools/perf/pmu-events/pmu-events.h index 70672842f77f..fe343c4d8016 100644 --- a/tools/perf/pmu-events/pmu-events.h +++ b/tools/perf/pmu-events/pmu-events.h @@ -30,18 +30,20 @@ struct pmu_event { const char *metric_constraint; }; +struct pmu_events_table; + typedef int (*pmu_event_iter_fn)(const struct pmu_event *pe, - const struct pmu_event *table, + const struct pmu_events_table *table, void *data); -int pmu_events_table_for_each_event(const struct pmu_event *table, pmu_event_iter_fn fn, +int pmu_events_table_for_each_event(const struct pmu_events_table *table, pmu_event_iter_fn fn, void *data); -const struct pmu_event *perf_pmu__find_table(struct perf_pmu *pmu); -const struct pmu_event *find_core_events_table(const char *arch, const char *cpuid); +const struct pmu_events_table *perf_pmu__find_table(struct perf_pmu *pmu); +const struct pmu_events_table *find_core_events_table(const char *arch, const char *cpuid); int pmu_for_each_core_event(pmu_event_iter_fn fn, void *data); -const struct pmu_event *find_sys_events_table(const char *name); +const struct pmu_events_table *find_sys_events_table(const char *name); int pmu_for_each_sys_event(pmu_event_iter_fn fn, void *data); #endif diff --git a/tools/perf/tests/expand-cgroup.c b/tools/perf/tests/expand-cgroup.c index e79ee8621a90..51fb5f34c1dd 100644 --- a/tools/perf/tests/expand-cgroup.c +++ b/tools/perf/tests/expand-cgroup.c @@ -180,7 +180,7 @@ static int expand_metric_events(void) struct evlist *evlist; struct rblist metric_events; const char metric_str[] = "CPI"; - const struct pmu_event *pme_test; + const struct pmu_events_table *pme_test; evlist = evlist__new(); TEST_ASSERT_VAL("failed to get evlist", evlist); diff --git a/tools/perf/tests/parse-metric.c b/tools/perf/tests/parse-metric.c index 30c7091857b8..68f5a2a03242 100644 --- a/tools/perf/tests/parse-metric.c +++ b/tools/perf/tests/parse-metric.c @@ -72,7 +72,7 @@ static int __compute_metric(const char *name, struct value *vals, struct rblist metric_events = { .nr_entries = 0, }; - const struct pmu_event *pme_test; + const struct pmu_events_table *pme_test; struct perf_cpu_map *cpus; struct runtime_stat st; struct evlist *evlist; diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index e308d480f0fb..097e05c796ab 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -424,7 +424,7 @@ static int compare_alias_to_test_event(struct perf_pmu_alias *alias, } static int test__pmu_event_table_core_callback(const struct pmu_event *pe, - const struct pmu_event *table __maybe_unused, + const struct pmu_events_table *table __maybe_unused, void *data) { int *map_events = data; @@ -461,7 +461,7 @@ static int test__pmu_event_table_core_callback(const struct pmu_event *pe, } static int test__pmu_event_table_sys_callback(const struct pmu_event *pe, - const struct pmu_event *table __maybe_unused, + const struct pmu_events_table *table __maybe_unused, void *data) { int *map_events = data; @@ -495,8 +495,8 @@ static int test__pmu_event_table_sys_callback(const struct pmu_event *pe, static int test__pmu_event_table(struct test_suite *test __maybe_unused, int subtest __maybe_unused) { - const struct pmu_event *sys_event_table = find_sys_events_table("pme_test_soc_sys"); - const struct pmu_event *table = find_core_events_table("testarch", "testcpu"); + const struct pmu_events_table *sys_event_table = find_sys_events_table("pme_test_soc_sys"); + const struct pmu_events_table *table = find_core_events_table("testarch", "testcpu"); int map_events = 0, expected_events, err; /* ignore 3x sentinels */ @@ -544,7 +544,7 @@ static int __test_core_pmu_event_aliases(char *pmu_name, int *count) struct perf_pmu *pmu; LIST_HEAD(aliases); int res = 0; - const struct pmu_event *table = find_core_events_table("testarch", "testcpu"); + const struct pmu_events_table *table = find_core_events_table("testarch", "testcpu"); struct perf_pmu_alias *a, *tmp; if (!table) @@ -597,7 +597,7 @@ static int __test_uncore_pmu_event_aliases(struct perf_pmu_test_pmu *test_pmu) struct perf_pmu *pmu = &test_pmu->pmu; const char *pmu_name = pmu->name; struct perf_pmu_alias *a, *tmp, *alias; - const struct pmu_event *events_table; + const struct pmu_events_table *events_table; LIST_HEAD(aliases); int res = 0; @@ -839,7 +839,7 @@ struct metric { struct metric_ref metric_ref; }; -static int test__parsing_callback(const struct pmu_event *pe, const struct pmu_event *table, +static int test__parsing_callback(const struct pmu_event *pe, const struct pmu_events_table *table, void *data) { int *failures = data; @@ -1016,7 +1016,7 @@ out: } static int test__parsing_fake_callback(const struct pmu_event *pe, - const struct pmu_event *table __maybe_unused, + const struct pmu_events_table *table __maybe_unused, void *data __maybe_unused) { if (!pe->metric_expr) diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index cae97b6dc5bc..42a5c8ae915e 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -508,7 +508,7 @@ struct metricgroup_iter_data { }; static int metricgroup__sys_event_iter(const struct pmu_event *pe, - const struct pmu_event *table __maybe_unused, + const struct pmu_events_table *table, void *data) { struct metricgroup_iter_data *d = data; @@ -529,7 +529,7 @@ static int metricgroup__sys_event_iter(const struct pmu_event *pe, } static int metricgroup__print_sys_event_iter(const struct pmu_event *pe, - const struct pmu_event *table __maybe_unused, + const struct pmu_events_table *table __maybe_unused, void *data) { struct metricgroup_print_sys_idata *d = data; @@ -549,7 +549,7 @@ struct metricgroup_print_data { }; static int metricgroup__print_callback(const struct pmu_event *pe, - const struct pmu_event *table __maybe_unused, + const struct pmu_events_table *table __maybe_unused, void *vdata) { struct metricgroup_print_data *data = vdata; @@ -571,7 +571,7 @@ void metricgroup__print(bool metrics, bool metricgroups, char *filter, struct rblist groups; struct rb_node *node, *next; struct strlist *metriclist = NULL; - const struct pmu_event *table; + const struct pmu_events_table *table; if (!metricgroups) { metriclist = strlist__new(NULL, NULL); @@ -876,7 +876,7 @@ struct metricgroup_add_iter_data { bool metric_no_group; struct metric *root_metric; const struct visited_metric *visited; - const struct pmu_event *table; + const struct pmu_events_table *table; }; static int add_metric(struct list_head *metric_list, @@ -885,7 +885,7 @@ static int add_metric(struct list_head *metric_list, bool metric_no_group, struct metric *root_metric, const struct visited_metric *visited, - const struct pmu_event *table); + const struct pmu_events_table *table); /** * resolve_metric - Locate metrics within the root metric and recursively add @@ -908,7 +908,7 @@ static int resolve_metric(struct list_head *metric_list, bool metric_no_group, struct metric *root_metric, const struct visited_metric *visited, - const struct pmu_event *table) + const struct pmu_events_table *table) { struct hashmap_entry *cur; size_t bkt; @@ -986,7 +986,7 @@ static int __add_metric(struct list_head *metric_list, int runtime, struct metric *root_metric, const struct visited_metric *visited, - const struct pmu_event *table) + const struct pmu_events_table *table) { const struct visited_metric *vm; int ret; @@ -1077,7 +1077,7 @@ struct metricgroup__find_metric_data { }; static int metricgroup__find_metric_callback(const struct pmu_event *pe, - const struct pmu_event *table __maybe_unused, + const struct pmu_events_table *table __maybe_unused, void *vdata) { struct metricgroup__find_metric_data *data = vdata; @@ -1090,7 +1090,7 @@ static int metricgroup__find_metric_callback(const struct pmu_event *pe, } const struct pmu_event *metricgroup__find_metric(const char *metric, - const struct pmu_event *table) + const struct pmu_events_table *table) { struct metricgroup__find_metric_data data = { .metric = metric, @@ -1108,7 +1108,7 @@ static int add_metric(struct list_head *metric_list, bool metric_no_group, struct metric *root_metric, const struct visited_metric *visited, - const struct pmu_event *table) + const struct pmu_events_table *table) { int ret = 0; @@ -1136,8 +1136,8 @@ static int add_metric(struct list_head *metric_list, } static int metricgroup__add_metric_sys_event_iter(const struct pmu_event *pe, - const struct pmu_event *table __maybe_unused, - void *data) + const struct pmu_events_table *table __maybe_unused, + void *data) { struct metricgroup_add_iter_data *d = data; int ret; @@ -1193,7 +1193,7 @@ struct metricgroup__add_metric_data { }; static int metricgroup__add_metric_callback(const struct pmu_event *pe, - const struct pmu_event *table, + const struct pmu_events_table *table, void *vdata) { struct metricgroup__add_metric_data *data = vdata; @@ -1227,7 +1227,7 @@ static int metricgroup__add_metric_callback(const struct pmu_event *pe, static int metricgroup__add_metric(const char *metric_name, const char *modifier, bool metric_no_group, struct list_head *metric_list, - const struct pmu_event *table) + const struct pmu_events_table *table) { LIST_HEAD(list); int ret; @@ -1296,7 +1296,7 @@ out: */ static int metricgroup__add_metric_list(const char *list, bool metric_no_group, struct list_head *metric_list, - const struct pmu_event *table) + const struct pmu_events_table *table) { char *list_itr, *list_copy, *metric_name, *modifier; int ret, count = 0; @@ -1504,7 +1504,7 @@ static int parse_groups(struct evlist *perf_evlist, const char *str, bool metric_no_merge, struct perf_pmu *fake_pmu, struct rblist *metric_events_list, - const struct pmu_event *table) + const struct pmu_events_table *table) { struct evlist *combined_evlist = NULL; LIST_HEAD(metric_list); @@ -1650,14 +1650,14 @@ int metricgroup__parse_groups(const struct option *opt, struct rblist *metric_events) { struct evlist *perf_evlist = *(struct evlist **)opt->value; - const struct pmu_event *table = pmu_events_table__find(); + const struct pmu_events_table *table = pmu_events_table__find(); return parse_groups(perf_evlist, str, metric_no_group, metric_no_merge, NULL, metric_events, table); } int metricgroup__parse_groups_test(struct evlist *evlist, - const struct pmu_event *table, + const struct pmu_events_table *table, const char *str, bool metric_no_group, bool metric_no_merge, @@ -1668,7 +1668,7 @@ int metricgroup__parse_groups_test(struct evlist *evlist, } static int metricgroup__has_metric_callback(const struct pmu_event *pe, - const struct pmu_event *table __maybe_unused, + const struct pmu_events_table *table __maybe_unused, void *vdata) { const char *metric = vdata; @@ -1684,7 +1684,7 @@ static int metricgroup__has_metric_callback(const struct pmu_event *pe, bool metricgroup__has_metric(const char *metric) { - const struct pmu_event *table = pmu_events_table__find(); + const struct pmu_events_table *table = pmu_events_table__find(); if (!table) return false; diff --git a/tools/perf/util/metricgroup.h b/tools/perf/util/metricgroup.h index 5a1390e73d25..f54d170043e9 100644 --- a/tools/perf/util/metricgroup.h +++ b/tools/perf/util/metricgroup.h @@ -11,7 +11,6 @@ struct evlist; struct evsel; struct option; struct rblist; -struct pmu_events_map; struct cgroup; /** @@ -71,9 +70,9 @@ int metricgroup__parse_groups(const struct option *opt, bool metric_no_merge, struct rblist *metric_events); const struct pmu_event *metricgroup__find_metric(const char *metric, - const struct pmu_event *table); + const struct pmu_events_table *table); int metricgroup__parse_groups_test(struct evlist *evlist, - const struct pmu_event *table, + const struct pmu_events_table *table, const char *str, bool metric_no_group, bool metric_no_merge, diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index dd1e171d7480..89655d53117a 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -710,7 +710,7 @@ char *perf_pmu__getcpuid(struct perf_pmu *pmu) return cpuid; } -__weak const struct pmu_event *pmu_events_table__find(void) +__weak const struct pmu_events_table *pmu_events_table__find(void) { return perf_pmu__find_table(NULL); } @@ -799,7 +799,7 @@ struct pmu_add_cpu_aliases_map_data { }; static int pmu_add_cpu_aliases_map_callback(const struct pmu_event *pe, - const struct pmu_event *table __maybe_unused, + const struct pmu_events_table *table __maybe_unused, void *vdata) { struct pmu_add_cpu_aliases_map_data *data = vdata; @@ -827,7 +827,7 @@ new_alias: * as aliases. */ void pmu_add_cpu_aliases_table(struct list_head *head, struct perf_pmu *pmu, - const struct pmu_event *table) + const struct pmu_events_table *table) { struct pmu_add_cpu_aliases_map_data data = { .head = head, @@ -841,7 +841,7 @@ void pmu_add_cpu_aliases_table(struct list_head *head, struct perf_pmu *pmu, static void pmu_add_cpu_aliases(struct list_head *head, struct perf_pmu *pmu) { - const struct pmu_event *table; + const struct pmu_events_table *table; table = perf_pmu__find_table(pmu); if (!table) @@ -856,7 +856,7 @@ struct pmu_sys_event_iter_data { }; static int pmu_add_sys_aliases_iter_fn(const struct pmu_event *pe, - const struct pmu_event *table __maybe_unused, + const struct pmu_events_table *table __maybe_unused, void *data) { struct pmu_sys_event_iter_data *idata = data; diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h index f0aba1e462fa..a7b0f9507510 100644 --- a/tools/perf/util/pmu.h +++ b/tools/perf/util/pmu.h @@ -126,10 +126,10 @@ int perf_pmu__test(void); struct perf_event_attr *perf_pmu__get_default_config(struct perf_pmu *pmu); void pmu_add_cpu_aliases_table(struct list_head *head, struct perf_pmu *pmu, - const struct pmu_event *table); + const struct pmu_events_table *table); char *perf_pmu__getcpuid(struct perf_pmu *pmu); -const struct pmu_event *pmu_events_table__find(void); +const struct pmu_events_table *pmu_events_table__find(void); bool pmu_uncore_alias_match(const char *pmu_name, const char *name); void perf_pmu_free_alias(struct perf_pmu_alias *alias); diff --git a/tools/perf/util/s390-sample-raw.c b/tools/perf/util/s390-sample-raw.c index 235319d45d02..9a631d97471c 100644 --- a/tools/perf/util/s390-sample-raw.c +++ b/tools/perf/util/s390-sample-raw.c @@ -135,7 +135,7 @@ struct get_counter_name_data { }; static int get_counter_name_callback(const struct pmu_event *evp, - const struct pmu_event *table __maybe_unused, + const struct pmu_events_table *table __maybe_unused, void *vdata) { struct get_counter_name_data *data = vdata; @@ -157,7 +157,7 @@ static int get_counter_name_callback(const struct pmu_event *evp, * the name of this counter. * If no match is found a NULL pointer is returned. */ -static const char *get_counter_name(int set, int nr, const struct pmu_event *table) +static const char *get_counter_name(int set, int nr, const struct pmu_events_table *table) { struct get_counter_name_data data = { .wanted = get_counterset_start(set) + nr, @@ -177,7 +177,7 @@ static void s390_cpumcfdg_dump(struct perf_sample *sample) unsigned char *buf = sample->raw_data; const char *color = PERF_COLOR_BLUE; struct cf_ctrset_entry *cep, ce; - const struct pmu_event *table; + const struct pmu_events_table *table; u64 *p; table = pmu_events_table__find(); -- cgit v1.2.3 From d3abd7b8bd8af16703e81410de3e35bf4de3a9ce Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 12 Aug 2022 16:09:47 -0700 Subject: perf metrics: Copy entire pmu_event in find metric The pmu_event passed to the pmu_events_table_for_each_event is invalid after the loop. Copy the entire struct in metricgroup__find_metric. Reduce the scope of this function to static. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Stephane Eranian Cc: Will Deacon Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220812230949.683239-13-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/metricgroup.c | 33 ++++++++++++++++++--------------- tools/perf/util/metricgroup.h | 2 -- 2 files changed, 18 insertions(+), 17 deletions(-) diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index 42a5c8ae915e..464475fd6b9a 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -879,6 +879,10 @@ struct metricgroup_add_iter_data { const struct pmu_events_table *table; }; +static bool metricgroup__find_metric(const char *metric, + const struct pmu_events_table *table, + struct pmu_event *pe); + static int add_metric(struct list_head *metric_list, const struct pmu_event *pe, const char *modifier, @@ -914,7 +918,7 @@ static int resolve_metric(struct list_head *metric_list, size_t bkt; struct to_resolve { /* The metric to resolve. */ - const struct pmu_event *pe; + struct pmu_event pe; /* * The key in the IDs map, this may differ from in case, * etc. from pe->metric_name. @@ -928,16 +932,15 @@ static int resolve_metric(struct list_head *metric_list, * the pending array. */ hashmap__for_each_entry(root_metric->pctx->ids, cur, bkt) { - const struct pmu_event *pe; + struct pmu_event pe; - pe = metricgroup__find_metric(cur->key, table); - if (pe) { + if (metricgroup__find_metric(cur->key, table, &pe)) { pending = realloc(pending, (pending_cnt + 1) * sizeof(struct to_resolve)); if (!pending) return -ENOMEM; - pending[pending_cnt].pe = pe; + memcpy(&pending[pending_cnt].pe, &pe, sizeof(pe)); pending[pending_cnt].key = cur->key; pending_cnt++; } @@ -952,7 +955,7 @@ static int resolve_metric(struct list_head *metric_list, * context. */ for (i = 0; i < pending_cnt; i++) { - ret = add_metric(metric_list, pending[i].pe, modifier, metric_no_group, + ret = add_metric(metric_list, &pending[i].pe, modifier, metric_no_group, root_metric, visited, table); if (ret) break; @@ -1073,7 +1076,7 @@ static int __add_metric(struct list_head *metric_list, struct metricgroup__find_metric_data { const char *metric; - const struct pmu_event *pe; + struct pmu_event *pe; }; static int metricgroup__find_metric_callback(const struct pmu_event *pe, @@ -1085,21 +1088,21 @@ static int metricgroup__find_metric_callback(const struct pmu_event *pe, if (!match_metric(pe->metric_name, data->metric)) return 0; - data->pe = pe; - return -1; + memcpy(data->pe, pe, sizeof(*pe)); + return 1; } -const struct pmu_event *metricgroup__find_metric(const char *metric, - const struct pmu_events_table *table) +static bool metricgroup__find_metric(const char *metric, + const struct pmu_events_table *table, + struct pmu_event *pe) { struct metricgroup__find_metric_data data = { .metric = metric, - .pe = NULL, + .pe = pe, }; - pmu_events_table_for_each_event(table, metricgroup__find_metric_callback, &data); - - return data.pe; + return pmu_events_table_for_each_event(table, metricgroup__find_metric_callback, &data) + ? true : false; } static int add_metric(struct list_head *metric_list, diff --git a/tools/perf/util/metricgroup.h b/tools/perf/util/metricgroup.h index f54d170043e9..016b3b1a289a 100644 --- a/tools/perf/util/metricgroup.h +++ b/tools/perf/util/metricgroup.h @@ -69,8 +69,6 @@ int metricgroup__parse_groups(const struct option *opt, bool metric_no_group, bool metric_no_merge, struct rblist *metric_events); -const struct pmu_event *metricgroup__find_metric(const char *metric, - const struct pmu_events_table *table); int metricgroup__parse_groups_test(struct evlist *evlist, const struct pmu_events_table *table, const char *str, -- cgit v1.2.3 From 9118259c1dc275e0f7b90da0d3cbaadc4e1ca3fe Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 12 Aug 2022 16:09:48 -0700 Subject: perf jevents: Compress the pmu_events_table The pmu_events array requires 15 pointers per entry which in position independent code need relocating. Change the array to be an array of offsets within a big C string. Only the offset of the first variable is required, subsequent variables are stored in order after the \0 terminator (requiring a byte per variable rather than 4 bytes per offset). The file size savings are: no jevents - the same 19,788,464bytes x86 jevents - ~16.7% file size saving 23,744,288bytes vs 28,502,632bytes all jevents - ~19.5% file size saving 24,469,056bytes vs 30,379,920bytes default build options plus NO_LIBBFD=1. For example, the x86 build savings come from .rela.dyn and .data.rel.ro becoming smaller by 3,157,032bytes and 3,042,016bytes respectively. .rodata increases by 1,432,448bytes, giving an overall 4,766,600bytes saving. To make metric strings more shareable, the topic is changed from say 'skx metrics' to just 'metrics'. To try to help with the memory layout the pmu_events are ordered as used by perf qsort comparator functions. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Stephane Eranian Cc: Will Deacon Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220812230949.683239-14-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/jevents.py | 207 ++++++++++++++++++++++++++++++--------- 1 file changed, 162 insertions(+), 45 deletions(-) diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index 4b7948ba57d6..d722fcba2d9f 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -6,7 +6,8 @@ import csv import json import os import sys -from typing import (Callable, Optional, Sequence) +from typing import (Callable, Dict, Optional, Sequence, Set, Tuple) +import collections # Global command line arguments. _args = None @@ -20,6 +21,19 @@ _arch_std_events = {} _close_table = False # Events to write out when the table is closed _pending_events = [] +# Global BigCString shared by all structures. +_bcs = None +# Order specific JsonEvent attributes will be visited. +_json_event_attributes = [ + # cmp_sevent related attributes. + 'name', 'pmu', 'topic', 'desc', 'metric_name', 'metric_group', + # Seems useful, put it early. + 'event', + # Short things in alphabetical order. + 'aggr_mode', 'compat', 'deprecated', 'perpkg', 'unit', + # Longer things (the last won't be iterated over during decompress). + 'metric_constraint', 'metric_expr', 'long_desc' +] def removesuffix(s: str, suffix: str) -> str: @@ -39,6 +53,66 @@ def file_name_to_table_name(parents: Sequence[str], dirname: str) -> str: tblname += '_' + dirname return tblname.replace('-', '_') +def c_len(s: str) -> int: + """Return the length of s a C string + + This doesn't handle all escape characters properly. It first assumes + all \ are for escaping, it then adjusts as it will have over counted + \\. The code uses \000 rather than \0 as a terminator as an adjacent + number would be folded into a string of \0 (ie. "\0" + "5" doesn't + equal a terminator followed by the number 5 but the escape of + \05). The code adjusts for \000 but not properly for all octal, hex + or unicode values. + """ + try: + utf = s.encode(encoding='utf-8',errors='strict') + except: + print(f'broken string {s}') + raise + return len(utf) - utf.count(b'\\') + utf.count(b'\\\\') - (utf.count(b'\\000') * 2) + +class BigCString: + """A class to hold many strings concatenated together. + + Generating a large number of stand-alone C strings creates a large + number of relocations in position independent code. The BigCString + is a helper for this case. It builds a single string which within it + are all the other C strings (to avoid memory issues the string + itself is held as a list of strings). The offsets within the big + string are recorded and when stored to disk these don't need + relocation. + """ + strings: Set[str] + big_string: Sequence[str] + offsets: Dict[str, int] + + def __init__(self): + self.strings = set() + + def add(self, s: str) -> None: + """Called to add to the big string.""" + self.strings.add(s) + + def compute(self) -> None: + """Called once all strings are added to compute the string and offsets.""" + + # big_string_offset is the current location within the C string + # being appended to - comments, etc. don't count. big_string is + # the string contents represented as a list. Strings are immutable + # in Python and so appending to one causes memory issues, while + # lists are mutable. + big_string_offset = 0 + self.big_string = [] + self.offsets = {} + # Emit all strings in a sorted manner. + for s in sorted(self.strings): + self.offsets[s] = big_string_offset + self.big_string.append(f'/* offset={big_string_offset} */ "') + self.big_string.append(s) + self.big_string.append('"\n') + big_string_offset += c_len(s) + +_bcs = BigCString() class JsonEvent: """Representation of an event loaded from a json file dictionary.""" @@ -203,26 +277,18 @@ class JsonEvent: s += f'\t{attr} = {value},\n' return s + '}' + def build_c_string(self) -> str: + s = '' + for attr in _json_event_attributes: + x = getattr(self, attr) + s += f'{x}\\000' if x else '\\000' + return s + def to_c_string(self) -> str: """Representation of the event as a C struct initializer.""" - def attr_string(attr: str, value: str) -> str: - return f'\t.{attr} = \"{value}\",\n' - - def str_if_present(self, attr: str) -> str: - if not getattr(self, attr): - return '' - return attr_string(attr, getattr(self, attr)) - - s = '{\n' - for attr in [ - 'aggr_mode', 'compat', 'deprecated', 'desc', 'event', 'long_desc', - 'metric_constraint', 'metric_expr', 'metric_group', 'metric_name', - 'name', 'perpkg', 'pmu', 'topic', 'unit' - ]: - s += str_if_present(self, attr) - s += '},\n' - return s + s = self.build_c_string() + return f'{{ { _bcs.offsets[s] } }}, /* {s} */\n' def read_json_events(path: str, topic: str) -> Sequence[JsonEvent]: @@ -237,7 +303,6 @@ def read_json_events(path: str, topic: str) -> Sequence[JsonEvent]: event.topic = topic return result - def preprocess_arch_std_files(archpath: str) -> None: """Read in all architecture standard events.""" global _arch_std_events @@ -253,7 +318,7 @@ def print_events_table_prefix(tblname: str) -> None: global _close_table if _close_table: raise IOError('Printing table prefix but last table has no suffix') - _args.output_file.write(f'static const struct pmu_event {tblname}[] = {{\n') + _args.output_file.write(f'static const struct compact_pmu_event {tblname}[] = {{\n') _close_table = True @@ -268,13 +333,13 @@ def add_events_table_entries(item: os.DirEntry, topic: str) -> None: def print_events_table_suffix() -> None: """Optionally close events table.""" - def event_cmp_key(j: JsonEvent): - def fix_none(s: str): + def event_cmp_key(j: JsonEvent) -> Tuple[bool, str, str, str, str]: + def fix_none(s: Optional[str]) -> str: if s is None: return '' return s - return (not j.desc is None, fix_none(j.topic), fix_none(j.name), fix_none(j.pmu), + return (j.desc is not None, fix_none(j.topic), fix_none(j.name), fix_none(j.pmu), fix_none(j.metric_name)) global _close_table @@ -286,23 +351,37 @@ def print_events_table_suffix() -> None: _args.output_file.write(event.to_c_string()) _pending_events = [] - _args.output_file.write("""{ -\t.name = 0, -\t.event = 0, -\t.desc = 0, -}, -}; -""") + _args.output_file.write('};\n\n') _close_table = False +def get_topic(topic: str) -> str: + if topic.endswith('metrics.json'): + return 'metrics' + return removesuffix(topic, '.json').replace('-', ' ') + +def preprocess_one_file(parents: Sequence[str], item: os.DirEntry) -> None: + + if item.is_dir(): + return + + # base dir or too deep + level = len(parents) + if level == 0 or level > 4: + return + + # Ignore other directories. If the file name does not have a .json + # extension, ignore it. It could be a readme.txt for instance. + if not item.is_file() or not item.name.endswith('.json'): + return + + topic = get_topic(item.name) + for event in read_json_events(item.path, topic): + _bcs.add(event.build_c_string()) def process_one_file(parents: Sequence[str], item: os.DirEntry) -> None: """Process a JSON file during the main walk.""" global _sys_event_tables - def get_topic(topic: str) -> str: - return removesuffix(topic, '.json').replace('-', ' ') - def is_leaf_dir(path: str) -> bool: for item in os.scandir(path): if item.is_dir(): @@ -337,7 +416,8 @@ def print_mapping_table(archs: Sequence[str]) -> None: _args.output_file.write(""" /* Struct used to make the PMU event table implementation opaque to callers. */ struct pmu_events_table { - const struct pmu_event *entries; + const struct compact_pmu_event *entries; + size_t length; }; /* @@ -365,7 +445,10 @@ const struct pmu_events_map pmu_events_map[] = { _args.output_file.write("""{ \t.arch = "testarch", \t.cpuid = "testcpu", -\t.table = { pme_test_soc_cpu }, +\t.table = { +\t.entries = pme_test_soc_cpu, +\t.length = ARRAY_SIZE(pme_test_soc_cpu), +\t} }, """) else: @@ -380,7 +463,10 @@ const struct pmu_events_map pmu_events_map[] = { _args.output_file.write(f"""{{ \t.arch = "{arch}", \t.cpuid = "{cpuid}", -\t.table = {{ {tblname} }} +\t.table = {{ +\t\t.entries = {tblname}, +\t\t.length = ARRAY_SIZE({tblname}) +\t}} }}, """) first = False @@ -388,7 +474,7 @@ const struct pmu_events_map pmu_events_map[] = { _args.output_file.write("""{ \t.arch = 0, \t.cpuid = 0, -\t.table = { 0 }, +\t.table = { 0, 0 }, } }; """) @@ -406,23 +492,41 @@ static const struct pmu_sys_events pmu_sys_event_tables[] = { """) for tblname in _sys_event_tables: _args.output_file.write(f"""\t{{ -\t\t.table = {{ {tblname} }}, +\t\t.table = {{ +\t\t\t.entries = {tblname}, +\t\t\t.length = ARRAY_SIZE({tblname}) +\t\t}}, \t\t.name = \"{tblname}\", \t}}, """) _args.output_file.write("""\t{ -\t\t.table = { 0 } +\t\t.table = { 0, 0 } \t}, }; -int pmu_events_table_for_each_event(const struct pmu_events_table *table, pmu_event_iter_fn fn, +static void decompress(int offset, struct pmu_event *pe) +{ +\tconst char *p = &big_c_string[offset]; +""") + for attr in _json_event_attributes: + _args.output_file.write(f""" +\tpe->{attr} = (*p == '\\0' ? NULL : p); +""") + if attr == _json_event_attributes[-1]: + continue + _args.output_file.write('\twhile (*p++);') + _args.output_file.write("""} + +int pmu_events_table_for_each_event(const struct pmu_events_table *table, + pmu_event_iter_fn fn, void *data) { - for (const struct pmu_event *pe = &table->entries[0]; - pe->name || pe->metric_group || pe->metric_name; - pe++) { - int ret = fn(pe, table, data); + for (size_t i = 0; i < table->length; i++) { + struct pmu_event pe; + int ret; + decompress(table->entries[i].offset, &pe); + ret = fn(&pe, table, data); if (ret) return ret; } @@ -531,7 +635,7 @@ def main() -> None: help='Root of tree containing architecture directories containing json files' ) ap.add_argument( - 'output_file', type=argparse.FileType('w'), nargs='?', default=sys.stdout) + 'output_file', type=argparse.FileType('w', encoding='utf-8'), nargs='?', default=sys.stdout) _args = ap.parse_args() _args.output_file.write(""" @@ -541,6 +645,10 @@ def main() -> None: #include #include +struct compact_pmu_event { + int offset; +}; + """) archs = [] for item in os.scandir(_args.starting_dir): @@ -556,6 +664,15 @@ def main() -> None: for arch in archs: arch_path = f'{_args.starting_dir}/{arch}' preprocess_arch_std_files(arch_path) + ftw(arch_path, [], preprocess_one_file) + + _bcs.compute() + _args.output_file.write('static const char *const big_c_string =\n') + for s in _bcs.big_string: + _args.output_file.write(s) + _args.output_file.write(';\n\n') + for arch in archs: + arch_path = f'{_args.starting_dir}/{arch}' ftw(arch_path, [], process_one_file) print_events_table_suffix() -- cgit v1.2.3 From d0313e629f2690edfd269896b398048275227db0 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 12 Aug 2022 16:09:49 -0700 Subject: perf jevents: Fold strings optimization If a shorter string ends a longer string then the shorter string may reuse the longer string at an offset. For example, on x86 the event arith.cycles_div_busy and cycles_div_busy can be folded, even though they have difference names the strings are identical after 6 characters. cycles_div_busy can reuse the arith.cycles_div_busy string at an offset of 6. In pmu-events.c this looks like the following where the 'also:' lists folded strings: /* offset=177541 */ "arith.cycles_div_busy\000\000pipeline\000Cycles the divider is busy\000\000\000event=0x14,period=2000000,umask=0x1\000\000\000\000\000\000\000\000\000" /* also: cycles_div_busy\000\000pipeline\000Cycles the divider is busy\000\000\000event=0x14,period=2000000,umask=0x1\000\000\000\000\000\000\000\000\000 */ As jevents.py combines multiple strings for an event into a larger string, the amount of folding is minimal as all parts of the event must align. Other organizations can benefit more from folding, but lose space by say recording more offsets. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Stephane Eranian Cc: Will Deacon Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220812230949.683239-15-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/jevents.py | 55 +++++++++++++++++++++++++++++++++++----- 1 file changed, 48 insertions(+), 7 deletions(-) diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index d722fcba2d9f..0daa3e007528 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -80,7 +80,9 @@ class BigCString: are all the other C strings (to avoid memory issues the string itself is held as a list of strings). The offsets within the big string are recorded and when stored to disk these don't need - relocation. + relocation. To reduce the size of the string further, identical + strings are merged. If a longer string ends-with the same value as a + shorter string, these entries are also merged. """ strings: Set[str] big_string: Sequence[str] @@ -96,6 +98,33 @@ class BigCString: def compute(self) -> None: """Called once all strings are added to compute the string and offsets.""" + folded_strings = {} + # Determine if two strings can be folded, ie. let 1 string use the + # end of another. First reverse all strings and sort them. + sorted_reversed_strings = sorted([x[::-1] for x in self.strings]) + + # Strings 'xyz' and 'yz' will now be [ 'zy', 'zyx' ]. Scan forward + # for each string to see if there is a better candidate to fold it + # into, in the example rather than using 'yz' we can use'xyz' at + # an offset of 1. We record which string can be folded into which + # in folded_strings, we don't need to record the offset as it is + # trivially computed from the string lengths. + for pos,s in enumerate(sorted_reversed_strings): + best_pos = pos + for check_pos in range(pos + 1, len(sorted_reversed_strings)): + if sorted_reversed_strings[check_pos].startswith(s): + best_pos = check_pos + else: + break + if pos != best_pos: + folded_strings[s[::-1]] = sorted_reversed_strings[best_pos][::-1] + + # Compute reverse mappings for debugging. + fold_into_strings = collections.defaultdict(set) + for key, val in folded_strings.items(): + if key != val: + fold_into_strings[val].add(key) + # big_string_offset is the current location within the C string # being appended to - comments, etc. don't count. big_string is # the string contents represented as a list. Strings are immutable @@ -104,13 +133,25 @@ class BigCString: big_string_offset = 0 self.big_string = [] self.offsets = {} - # Emit all strings in a sorted manner. + + # Emit all strings that aren't folded in a sorted manner. for s in sorted(self.strings): - self.offsets[s] = big_string_offset - self.big_string.append(f'/* offset={big_string_offset} */ "') - self.big_string.append(s) - self.big_string.append('"\n') - big_string_offset += c_len(s) + if s not in folded_strings: + self.offsets[s] = big_string_offset + self.big_string.append(f'/* offset={big_string_offset} */ "') + self.big_string.append(s) + self.big_string.append('"') + if s in fold_into_strings: + self.big_string.append(' /* also: ' + ', '.join(fold_into_strings[s]) + ' */') + self.big_string.append('\n') + big_string_offset += c_len(s) + continue + + # Compute the offsets of the folded strings. + for s in folded_strings.keys(): + assert s not in self.offsets + folded_s = folded_strings[s] + self.offsets[s] = self.offsets[folded_s] + c_len(folded_s) - c_len(s) _bcs = BigCString() -- cgit v1.2.3 From bf79e18fdf65b451acf00457910879115cc51b1c Mon Sep 17 00:00:00 2001 From: Zhengjun Xing Date: Fri, 12 Aug 2022 16:52:29 +0800 Subject: perf vendor events: Update metrics for broadwellde MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The metrics are based on TMA 4.4 full, add new metrics “UNCORE_FREQ” for broadwellde. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py to download and generate the latest events and metrics. Manually copy the broadwellde files into perf. Signed-off-by: Xing Zhengjun Tested-by: Ian Rogers Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20220812085239.3089231-2-zhengjun.xing@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json b/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json index 6789285555f0..b6fdf5ba2c9a 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json @@ -450,6 +450,12 @@ "MetricGroup": "SoC", "MetricName": "Socket_CLKS" }, + { + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "cbox_0@event\\=0x0@ / #num_dies / duration_time / 1000000000", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" + }, { "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", -- cgit v1.2.3 From e349fa6cc824450f1aa0c4acbfefaa3c9a0cae9b Mon Sep 17 00:00:00 2001 From: Zhengjun Xing Date: Fri, 12 Aug 2022 16:52:30 +0800 Subject: perf vendor events: Update events and metrics for broadwellx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update to v19, the metrics are based on TMA 4.4 full, update events and add new metrics “UNCORE_FREQ” for broadwellx. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py to download and generate the latest events and metrics. Manually copy the broadwellx files into perf. Signed-off-by: Xing Zhengjun Tested-by: Ian Rogers Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20220812085239.3089231-3-zhengjun.xing@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/broadwellx/bdx-metrics.json | 6 + .../arch/x86/broadwellx/uncore-cache.json | 163 +-------------------- 2 files changed, 10 insertions(+), 159 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json b/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json index 720ee7c9332d..a3a15ee52841 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json @@ -444,6 +444,12 @@ "MetricGroup": "SoC", "MetricName": "Socket_CLKS" }, + { + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "cbox_0@event\\=0x0@ / #num_dies / duration_time / 1000000000", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" + }, { "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json index 1b9c1570aa47..abee6f773c1f 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json @@ -846,20 +846,19 @@ "Unit": "CBO" }, { - "BriefDescription": "PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode", + "BriefDescription": "TOR Inserts; Opcode Match", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE", - "Filter": "filter_opc=0x180,filter_tid=0x3e", + "EventName": "UNC_C_TOR_INSERTS.OPCODE", "PerPkg": "1", "UMask": "0x1", "Unit": "CBO" }, { - "BriefDescription": "PCIe writes (partial cache line)", + "BriefDescription": "PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.OPCODE", + "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE", "Filter": "filter_opc=0x180,filter_tid=0x3e", "PerPkg": "1", "UMask": "0x1", @@ -876,17 +875,6 @@ "UMask": "0x1", "Unit": "CBO" }, - { - "BriefDescription": "L2 demand and L2 prefetch code references to LLC", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.OPCODE", - "Filter": "filter_opc=0x181", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", - "Unit": "CBO" - }, { "BriefDescription": "Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode", "Counter": "0,1,2,3", @@ -898,17 +886,6 @@ "UMask": "0x1", "Unit": "CBO" }, - { - "BriefDescription": "Streaming stores (full cache line)", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.OPCODE", - "Filter": "filter_opc=0x18c", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", - "Unit": "CBO" - }, { "BriefDescription": "Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode", "Counter": "0,1,2,3", @@ -920,17 +897,6 @@ "UMask": "0x1", "Unit": "CBO" }, - { - "BriefDescription": "Streaming stores (partial cache line)", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.OPCODE", - "Filter": "filter_opc=0x18d", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", - "Unit": "CBO" - }, { "BriefDescription": "PCIe read current. Derived from unc_c_tor_inserts.opcode", "Counter": "0,1,2,3", @@ -942,17 +908,6 @@ "UMask": "0x1", "Unit": "CBO" }, - { - "BriefDescription": "PCIe read current", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.OPCODE", - "Filter": "filter_opc=0x19e", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", - "Unit": "CBO" - }, { "BriefDescription": "PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode", "Counter": "0,1,2,3", @@ -964,17 +919,6 @@ "UMask": "0x1", "Unit": "CBO" }, - { - "BriefDescription": "PCIe write references (full cache line)", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.OPCODE", - "Filter": "filter_opc=0x1c8,filter_tid=0x3e", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", - "Unit": "CBO" - }, { "BriefDescription": "TOR Inserts; Evictions", "Counter": "0,1,2,3", @@ -1035,17 +979,6 @@ "UMask": "0x3", "Unit": "CBO" }, - { - "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", - "Filter": "filter_opc=0x187", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", - "Unit": "CBO" - }, { "BriefDescription": "MMIO reads. Derived from unc_c_tor_inserts.miss_opcode", "Counter": "0,1,2,3", @@ -1057,17 +990,6 @@ "UMask": "0x3", "Unit": "CBO" }, - { - "BriefDescription": "MMIO reads", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", - "Filter": "filter_opc=0x187,filter_nc=1", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", - "Unit": "CBO" - }, { "BriefDescription": "MMIO writes. Derived from unc_c_tor_inserts.miss_opcode", "Counter": "0,1,2,3", @@ -1079,17 +1001,6 @@ "UMask": "0x3", "Unit": "CBO" }, - { - "BriefDescription": "MMIO writes", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", - "Filter": "filter_opc=0x18f,filter_nc=1", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", - "Unit": "CBO" - }, { "BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode", "Counter": "0,1,2,3", @@ -1101,17 +1012,6 @@ "UMask": "0x3", "Unit": "CBO" }, - { - "BriefDescription": "LLC prefetch misses for RFO", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", - "Filter": "filter_opc=0x190", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", - "Unit": "CBO" - }, { "BriefDescription": "LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode", "Counter": "0,1,2,3", @@ -1123,17 +1023,6 @@ "UMask": "0x3", "Unit": "CBO" }, - { - "BriefDescription": "LLC prefetch misses for code reads", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", - "Filter": "filter_opc=0x191", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", - "Unit": "CBO" - }, { "BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode", "Counter": "0,1,2,3", @@ -1145,17 +1034,6 @@ "UMask": "0x3", "Unit": "CBO" }, - { - "BriefDescription": "LLC prefetch misses for data reads", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", - "Filter": "filter_opc=0x192", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", - "Unit": "CBO" - }, { "BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode", "Counter": "0,1,2,3", @@ -1167,17 +1045,6 @@ "UMask": "0x3", "Unit": "CBO" }, - { - "BriefDescription": "LLC misses for PCIe read current", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", - "Filter": "filter_opc=0x19e", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", - "Unit": "CBO" - }, { "BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode", "Counter": "0,1,2,3", @@ -1189,17 +1056,6 @@ "UMask": "0x3", "Unit": "CBO" }, - { - "BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", - "Filter": "filter_opc=0x1c8", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", - "Unit": "CBO" - }, { "BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode", "Counter": "0,1,2,3", @@ -1211,17 +1067,6 @@ "UMask": "0x3", "Unit": "CBO" }, - { - "BriefDescription": "PCIe write misses (full cache line)", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", - "Filter": "filter_opc=0x1c8,filter_tid=0x3e", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", - "Unit": "CBO" - }, { "BriefDescription": "TOR Inserts; NID and Opcode Matched", "Counter": "0,1,2,3", -- cgit v1.2.3 From c6e9c0441801c3093d5e86c04db1880a3e273152 Mon Sep 17 00:00:00 2001 From: Zhengjun Xing Date: Fri, 12 Aug 2022 16:52:31 +0800 Subject: perf vendor events: Update events and metrics for cascadelakex MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update to v16, the metrics are based on TMA 4.4 full, update events and add new metrics “UNCORE_FREQ” for cascadelakex. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py to download and generate the latest events and metrics. Manually copy the cascadelakex files into perf. Signed-off-by: Xing Zhengjun Tested-by: Ian Rogers Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20220812085239.3089231-4-zhengjun.xing@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/cascadelakex/clx-metrics.json | 6 + .../arch/x86/cascadelakex/uncore-memory.json | 4424 +++- .../arch/x86/cascadelakex/uncore-other.json | 23162 +++++++++++++++++-- .../arch/x86/cascadelakex/uncore-power.json | 201 + 4 files changed, 26200 insertions(+), 1593 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json b/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json index ba5863a80d43..46613504b816 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json @@ -715,6 +715,12 @@ "MetricGroup": "SoC", "MetricName": "Socket_CLKS" }, + { + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "cha_0@event\\=0x0@ / #num_dies / duration_time / 1000000000", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" + }, { "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json index e82c6fa053a1..6facfb244cd3 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json @@ -1,4 +1,31 @@ [ + { + "BriefDescription": "DRAM Page Activate commands sent due to a write request", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_M_ACT_COUNT.WR", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "All DRAM Read CAS Commands issued (does not include underfills)", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_REG", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Underfill Read CAS Commands issued", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, { "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd", "Counter": "0,1,2,3", @@ -19,6 +46,15 @@ "UMask": "0x3", "Unit": "iMC" }, + { + "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.WR_WMM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, { "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr", "Counter": "0,1,2,3", @@ -39,6 +75,15 @@ "UMask": "0xC", "Unit": "iMC" }, + { + "BriefDescription": "All DRAM CAS Commands issued", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.ALL", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, { "BriefDescription": "Memory controller clock ticks", "Counter": "0,1,2,3", @@ -85,82 +130,107 @@ "Unit": "iMC" }, { - "BriefDescription": "Pre-charge for writes", + "BriefDescription": "Read Pending Queue Allocations", "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_M_PRE_COUNT.WR", + "EventCode": "0x10", + "EventName": "UNC_M_RPQ_INSERTS", "PerPkg": "1", - "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory", + "BriefDescription": "Read Pending Queue Occupancy", "Counter": "0,1,2,3", - "EventCode": "0xE3", - "EventName": "UNC_M_PMM_RPQ_INSERTS", + "EventCode": "0x80", + "EventName": "UNC_M_RPQ_OCCUPANCY", "PerPkg": "1", "Unit": "iMC" }, { - "BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory", + "BriefDescription": "All hits to Near Memory(DRAM cache) in Memory Mode", "Counter": "0,1,2,3", - "EventCode": "0xE7", - "EventName": "UNC_M_PMM_WPQ_INSERTS", + "EventCode": "0xD3", + "EventName": "UNC_M_TAGCHK.HIT", "PerPkg": "1", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "Intel Optane DC persistent memory bandwidth read (MB/sec). Derived from unc_m_pmm_rpq_inserts", + "BriefDescription": "All Clean line misses to Near Memory(DRAM cache) in Memory Mode", "Counter": "0,1,2,3", - "EventCode": "0xE3", - "EventName": "UNC_M_PMM_BANDWIDTH.READ", + "EventCode": "0xD3", + "EventName": "UNC_M_TAGCHK.MISS_CLEAN", "PerPkg": "1", - "ScaleUnit": "6.103515625E-5MB/sec", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "Intel Optane DC persistent memory bandwidth read (MB/sec)", + "BriefDescription": "All dirty line misses to Near Memory(DRAM cache) in Memory Mode", "Counter": "0,1,2,3", - "EventCode": "0xE3", - "EventName": "UNC_M_PMM_RPQ_INSERTS", + "EventCode": "0xD3", + "EventName": "UNC_M_TAGCHK.MISS_DIRTY", "PerPkg": "1", - "ScaleUnit": "6.103515625E-5MB/sec", + "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "Intel Optane DC persistent memory bandwidth write (MB/sec). Derived from unc_m_pmm_wpq_inserts", + "BriefDescription": "Write Pending Queue Allocations", "Counter": "0,1,2,3", - "EventCode": "0xE7", - "EventName": "UNC_M_PMM_BANDWIDTH.WRITE", + "EventCode": "0x20", + "EventName": "UNC_M_WPQ_INSERTS", "PerPkg": "1", - "ScaleUnit": "6.103515625E-5MB/sec", "Unit": "iMC" }, { - "BriefDescription": "Intel Optane DC persistent memory bandwidth write (MB/sec)", + "BriefDescription": "Write Pending Queue Occupancy", "Counter": "0,1,2,3", - "EventCode": "0xE7", - "EventName": "UNC_M_PMM_WPQ_INSERTS", + "EventCode": "0x81", + "EventName": "UNC_M_WPQ_OCCUPANCY", "PerPkg": "1", - "ScaleUnit": "6.103515625E-5MB/sec", "Unit": "iMC" }, { - "BriefDescription": "Intel Optane DC persistent memory bandwidth total (MB/sec). Derived from unc_m_pmm_rpq_inserts", + "BriefDescription": "Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory", + "Counter": "0,1,2,3", + "EventCode": "0xE0", + "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Intel Optane DC persistent memory read latency (ns). Derived from unc_m_pmm_rpq_occupancy.all", + "Counter": "0,1,2,3", + "EventCode": "0xE0", + "EventName": "UNC_M_PMM_READ_LATENCY", + "MetricExpr": "UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS / UNC_M_CLOCKTICKS", + "MetricName": "UNC_M_PMM_READ_LATENCY", + "PerPkg": "1", + "ScaleUnit": "6000000000ns", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory", "Counter": "0,1,2,3", "EventCode": "0xE3", - "EventName": "UNC_M_PMM_BANDWIDTH.TOTAL", - "MetricExpr": "UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS", - "MetricName": "UNC_M_PMM_BANDWIDTH.TOTAL", + "EventName": "UNC_M_PMM_RPQ_INSERTS", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Intel Optane DC persistent memory bandwidth read (MB/sec). Derived from unc_m_pmm_rpq_inserts", + "Counter": "0,1,2,3", + "EventCode": "0xE3", + "EventName": "UNC_M_PMM_BANDWIDTH.READ", "PerPkg": "1", "ScaleUnit": "6.103515625E-5MB/sec", "Unit": "iMC" }, { - "BriefDescription": "Intel Optane DC persistent memory bandwidth total (MB/sec)", + "BriefDescription": "Intel Optane DC persistent memory bandwidth total (MB/sec). Derived from unc_m_pmm_rpq_inserts", "Counter": "0,1,2,3", "EventCode": "0xE3", - "EventName": "UNC_M_PMM_RPQ_INSERTS", + "EventName": "UNC_M_PMM_BANDWIDTH.TOTAL", "MetricExpr": "UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS", "MetricName": "UNC_M_PMM_BANDWIDTH.TOTAL", "PerPkg": "1", @@ -168,202 +238,4312 @@ "Unit": "iMC" }, { - "BriefDescription": "Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory", + "BriefDescription": "All commands for Intel Optane DC persistent memory", "Counter": "0,1,2,3", - "EventCode": "0xE0", - "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL", + "EventCode": "0xEA", + "EventName": "UNC_M_PMM_CMD1.ALL", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "Intel Optane DC persistent memory read latency (ns). Derived from unc_m_pmm_rpq_occupancy.all", + "BriefDescription": "Regular reads(RPQ) commands for Intel Optane DC persistent memory", "Counter": "0,1,2,3", - "EventCode": "0xE0", - "EventName": "UNC_M_PMM_READ_LATENCY", - "MetricExpr": "UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS / UNC_M_CLOCKTICKS", - "MetricName": "UNC_M_PMM_READ_LATENCY", + "EventCode": "0xEA", + "EventName": "UNC_M_PMM_CMD1.RD", "PerPkg": "1", - "ScaleUnit": "6000000000ns", - "UMask": "0x1", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "Intel Optane DC persistent memory read latency (ns)", + "BriefDescription": "Write commands for Intel Optane DC persistent memory", "Counter": "0,1,2,3", - "EventCode": "0xE0", - "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL", - "MetricExpr": "UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS / UNC_M_CLOCKTICKS", - "MetricName": "UNC_M_PMM_READ_LATENCY", + "EventCode": "0xEA", + "EventName": "UNC_M_PMM_CMD1.WR", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Underfill read commands for Intel Optane DC persistent memory", + "Counter": "0,1,2,3", + "EventCode": "0xEA", + "EventName": "UNC_M_PMM_CMD1.UFILL_RD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory", + "Counter": "0,1,2,3", + "EventCode": "0xE7", + "EventName": "UNC_M_PMM_WPQ_INSERTS", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Intel Optane DC persistent memory bandwidth write (MB/sec). Derived from unc_m_pmm_wpq_inserts", + "Counter": "0,1,2,3", + "EventCode": "0xE7", + "EventName": "UNC_M_PMM_BANDWIDTH.WRITE", + "PerPkg": "1", + "ScaleUnit": "6.103515625E-5MB/sec", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory", + "Counter": "0,1,2,3", + "EventCode": "0xE4", + "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL", "PerPkg": "1", - "ScaleUnit": "6000000000ns", "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "DRAM Page Activate commands sent due to a write request", + "BriefDescription": "DRAM Activate Count; Activate due to Read", "Counter": "0,1,2,3", "EventCode": "0x1", - "EventName": "UNC_M_ACT_COUNT.WR", + "EventName": "UNC_M_ACT_COUNT.RD", "PerPkg": "1", - "PublicDescription": "Counts DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Controller). Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS (Column Access Select) command.", - "UMask": "0x2", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "All DRAM CAS Commands issued", + "BriefDescription": "DRAM Activate Count; Activate due to Bypass", "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_M_CAS_COUNT.ALL", + "EventCode": "0x1", + "EventName": "UNC_M_ACT_COUNT.BYP", "PerPkg": "1", - "PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM, so this event increments for every read and write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.", - "UMask": "0xF", + "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "All DRAM Read CAS Commands issued (does not include underfills)", + "BriefDescription": "ACT command issued by 2 cycle bypass", "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_M_CAS_COUNT.RD_REG", + "EventCode": "0xA1", + "EventName": "UNC_M_BYP_CMDS.ACT", "PerPkg": "1", - "PublicDescription": "Counts CAS (Column Access Select) regular read commands issued to DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every regular read. This event only counts regular reads and does not includes underfill reads due to partial write requests. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.", "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "DRAM Underfill Read CAS Commands issued", + "BriefDescription": "CAS command issued by 2 cycle bypass", "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", + "EventCode": "0xA1", + "EventName": "UNC_M_BYP_CMDS.CAS", "PerPkg": "1", - "PublicDescription": "Counts CAS (Column Access Select) underfill read commands issued to DRAM due to a partial write, on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this command counts underfill reads. Partial writes must be completed by first reading in the underfill from DRAM and then merging in the partial write data before writing the full line back to DRAM. This event will generally count about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ (due to a previous write request).", "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode", + "BriefDescription": "PRE command issued by 2 cycle bypass", "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_M_CAS_COUNT.WR_WMM", + "EventCode": "0xA1", + "EventName": "UNC_M_BYP_CMDS.PRE", "PerPkg": "1", - "PublicDescription": "Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode.", "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "All commands for Intel Optane DC persistent memory", + "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode", "Counter": "0,1,2,3", - "EventCode": "0xEA", - "EventName": "UNC_M_PMM_CMD1.ALL", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.WR_RMM", "PerPkg": "1", - "PublicDescription": "All commands for Intel Optane DC persistent memory", - "UMask": "0x1", + "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "Regular reads(RPQ) commands for Intel Optane DC persistent memory", + "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in WMM", "Counter": "0,1,2,3", - "EventCode": "0xEA", - "EventName": "UNC_M_PMM_CMD1.RD", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_WMM", "PerPkg": "1", - "PublicDescription": "All Reads - RPQ or Ufill", - "UMask": "0x2", + "UMask": "0x10", "Unit": "iMC" }, { - "BriefDescription": "Underfill read commands for Intel Optane DC persistent memory", + "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in RMM", "Counter": "0,1,2,3", - "EventCode": "0xEA", - "EventName": "UNC_M_PMM_CMD1.UFILL_RD", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_RMM", "PerPkg": "1", - "PublicDescription": "Underfill reads", - "UMask": "0x8", + "UMask": "0x20", "Unit": "iMC" }, { - "BriefDescription": "Write commands for Intel Optane DC persistent memory", + "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Read ISOCH Mode", "Counter": "0,1,2,3", - "EventCode": "0xEA", - "EventName": "UNC_M_PMM_CMD1.WR", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_ISOCH", "PerPkg": "1", - "PublicDescription": "Writes", - "UMask": "0x4", + "UMask": "0x40", "Unit": "iMC" }, { - "BriefDescription": "Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory", + "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Write ISOCH Mode", "Counter": "0,1,2,3", - "EventCode": "0xE4", - "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.WR_ISOCH", "PerPkg": "1", - "PublicDescription": "Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory", - "UMask": "0x1", + "UMask": "0x80", "Unit": "iMC" }, { - "BriefDescription": "Read Pending Queue Allocations", + "BriefDescription": "DRAM Precharge All Commands", "Counter": "0,1,2,3", - "EventCode": "0x10", - "EventName": "UNC_M_RPQ_INSERTS", + "EventCode": "0x6", + "EventName": "UNC_M_DRAM_PRE_ALL", "PerPkg": "1", - "PublicDescription": "Counts the number of read requests allocated into the Read Pending Queue (RPQ). This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. The requests deallocate after the read CAS command has been issued to DRAM. This event counts both Isochronous and non-Isochronous requests which were issued to the RPQ.", "Unit": "iMC" }, { - "BriefDescription": "Read Pending Queue Occupancy", + "BriefDescription": "ECC Correctable Errors", "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_M_RPQ_OCCUPANCY", + "EventCode": "0x9", + "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", "PerPkg": "1", - "PublicDescription": "Counts the number of entries in the Read Pending Queue (RPQ) at each cycle. This can then be used to calculate both the average occupancy of the queue (in conjunction with the number of cycles not empty) and the average latency in the queue (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate from the RPQ after the CAS command has been issued to memory.", "Unit": "iMC" }, { - "BriefDescription": "All hits to Near Memory(DRAM cache) in Memory Mode", + "BriefDescription": "Cycles in a Major Mode; Read Major Mode", "Counter": "0,1,2,3", - "EventCode": "0xD3", - "EventName": "UNC_M_TAGCHK.HIT", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.READ", "PerPkg": "1", - "PublicDescription": "Tag Check; Hit", "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "All Clean line misses to Near Memory(DRAM cache) in Memory Mode", + "BriefDescription": "Cycles in a Major Mode; Write Major Mode", "Counter": "0,1,2,3", - "EventCode": "0xD3", - "EventName": "UNC_M_TAGCHK.MISS_CLEAN", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.WRITE", "PerPkg": "1", - "PublicDescription": "Tag Check; Clean", "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "All dirty line misses to Near Memory(DRAM cache) in Memory Mode", + "BriefDescription": "Cycles in a Major Mode; Partial Major Mode", "Counter": "0,1,2,3", - "EventCode": "0xD3", - "EventName": "UNC_M_TAGCHK.MISS_DIRTY", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.PARTIAL", "PerPkg": "1", - "PublicDescription": "Tag Check; Dirty", "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "Write Pending Queue Allocations", + "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode", "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_M_WPQ_INSERTS", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.ISOCH", "PerPkg": "1", - "PublicDescription": "Counts the number of writes requests allocated into the Write Pending Queue (WPQ). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (Memory Controller). The write requests deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.", + "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "Write Pending Queue Occupancy", + "BriefDescription": "Channel DLLOFF Cycles", "Counter": "0,1,2,3", - "EventCode": "0x81", - "EventName": "UNC_M_WPQ_OCCUPANCY", + "EventCode": "0x84", + "EventName": "UNC_M_POWER_CHANNEL_DLLOFF", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Critical Throttle Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_POWER_PCU_THROTTLING", + "Counter": "0,1,2,3", + "EventCode": "0x42", + "EventName": "UNC_M_POWER_PCU_THROTTLING", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Preemption Count; Read over Read Preemption", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Preemption Count; Read over Write Preemption", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Pre-charge for writes", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_M_PRE_COUNT.WR", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_M_PRE_COUNT.BYP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS issued with LOW priority", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M_RD_CAS_PRIO.LOW", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS issued with MEDIUM priority", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M_RD_CAS_PRIO.MED", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS issued with HIGH priority", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M_RD_CAS_PRIO.HIGH", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M_RD_CAS_PRIO.PANIC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Full Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_M_RPQ_CYCLES_FULL", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_M_RPQ_CYCLES_NE", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses; Read Accepts", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_M_SB_ACCESSES.RD_ACCEPTS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses; Read Rejects", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_M_SB_ACCESSES.RD_REJECTS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses; NM read completions", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_M_SB_ACCESSES.WR_ACCEPTS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses; NM write completions", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_M_SB_ACCESSES.WR_REJECTS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses; FM read completions", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_M_SB_ACCESSES.NM_RD_CMPS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses; FM write completions", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_M_SB_ACCESSES.NM_WR_CMPS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses; Write Accepts", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_M_SB_ACCESSES.FM_RD_CMPS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses; Write Rejects", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_M_SB_ACCESSES.FM_WR_CMPS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Alloc", + "Counter": "0,1,2,3", + "EventCode": "0xD9", + "EventName": "UNC_M_SB_CANARY.ALLOC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Dealloc", + "Counter": "0,1,2,3", + "EventCode": "0xD9", + "EventName": "UNC_M_SB_CANARY.DEALLOC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Reject", + "Counter": "0,1,2,3", + "EventCode": "0xD9", + "EventName": "UNC_M_SB_CANARY.REJ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Valid", + "Counter": "0,1,2,3", + "EventCode": "0xD9", + "EventName": "UNC_M_SB_CANARY.VLD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "Near Mem Read Starved", + "Counter": "0,1,2,3", + "EventCode": "0xD9", + "EventName": "UNC_M_SB_CANARY.NMRD_STARVED", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "Near Mem Write Starved", + "Counter": "0,1,2,3", + "EventCode": "0xD9", + "EventName": "UNC_M_SB_CANARY.NMWR_STARVED", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "Far Mem Read Starved", + "Counter": "0,1,2,3", + "EventCode": "0xD9", + "EventName": "UNC_M_SB_CANARY.FMRD_STARVED", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "Far Mem Write Starved", + "Counter": "0,1,2,3", + "EventCode": "0xD9", + "EventName": "UNC_M_SB_CANARY.FMWR_STARVED", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Cycles Full", + "Counter": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "UNC_M_SB_CYCLES_FULL", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Cycles Not-Empty", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_M_SB_CYCLES_NE", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Inserts; Reads", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_M_SB_INSERTS.RDS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Inserts; Writes", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_M_SB_INSERTS.WRS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Inserts; Block region reads", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_M_SB_INSERTS.BLOCK_RDS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Inserts; Block region writes", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_M_SB_INSERTS.BLOCK_WRS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Inserts; Dealloc all commands (for error flows)", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_M_SB_INSERTS.DEALLOC", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Inserts; Patrol inserts", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_M_SB_INSERTS.PATROL", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Occupancy; Reads", + "Counter": "0,1,2,3", + "EventCode": "0xD5", + "EventName": "UNC_M_SB_OCCUPANCY.RDS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Occupancy; Writes", + "Counter": "0,1,2,3", + "EventCode": "0xD5", + "EventName": "UNC_M_SB_OCCUPANCY.WRS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Occupancy; Block region reads", + "Counter": "0,1,2,3", + "EventCode": "0xD5", + "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_RDS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Occupancy; Block region writes", + "Counter": "0,1,2,3", + "EventCode": "0xD5", + "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_WRS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Occupancy; Patrol", + "Counter": "0,1,2,3", + "EventCode": "0xD5", + "EventName": "UNC_M_SB_OCCUPANCY.PATROL", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of Scoreboard Requests Rejected; NM requests rejected due to set conflict", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_M_SB_REJECT.NM_SET_CNFLT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of Scoreboard Requests Rejected; FM requests rejected due to full address conflict", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_M_SB_REJECT.FM_ADDR_CNFLT", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of Scoreboard Requests Rejected; Patrol requests rejected due to set conflict", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_M_SB_REJECT.PATROL_SET_CNFLT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Near Mem Read - Set", + "Counter": "0,1,2,3", + "EventCode": "0xD7", + "EventName": "UNC_M_SB_STRV_ALLOC.NMRD_SET", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Far Mem Read - Set", + "Counter": "0,1,2,3", + "EventCode": "0xD7", + "EventName": "UNC_M_SB_STRV_ALLOC.FMRD_SET", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Near Mem Write - Set", + "Counter": "0,1,2,3", + "EventCode": "0xD7", + "EventName": "UNC_M_SB_STRV_ALLOC.NMWR_SET", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Far Mem Write - Set", + "Counter": "0,1,2,3", + "EventCode": "0xD7", + "EventName": "UNC_M_SB_STRV_ALLOC.FMWR_SET", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "Near Mem Read - Clear", + "Counter": "0,1,2,3", + "EventCode": "0xD7", + "EventName": "UNC_M_SB_STRV_ALLOC.NMRD_CLR", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "Far Mem Read - Clear", + "Counter": "0,1,2,3", + "EventCode": "0xD7", + "EventName": "UNC_M_SB_STRV_ALLOC.FMRD_CLR", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "Near Mem Write - Clear", + "Counter": "0,1,2,3", + "EventCode": "0xD7", + "EventName": "UNC_M_SB_STRV_ALLOC.NMWR_CLR", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "Far Mem Write - Clear", + "Counter": "0,1,2,3", + "EventCode": "0xD7", + "EventName": "UNC_M_SB_STRV_ALLOC.FMWR_CLR", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Near Mem Read", + "Counter": "0,1,2,3", + "EventCode": "0xD8", + "EventName": "UNC_M_SB_STRV_OCC.NMRD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Far Mem Read", + "Counter": "0,1,2,3", + "EventCode": "0xD8", + "EventName": "UNC_M_SB_STRV_OCC.FMRD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Near Mem Write", + "Counter": "0,1,2,3", + "EventCode": "0xD8", + "EventName": "UNC_M_SB_STRV_OCC.NMWR", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Far Mem Write", + "Counter": "0,1,2,3", + "EventCode": "0xD8", + "EventName": "UNC_M_SB_STRV_OCC.FMWR", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_SB_TAGGED.NEW", + "Counter": "0,1,2,3", + "EventCode": "0xDD", + "EventName": "UNC_M_SB_TAGGED.NEW", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_SB_TAGGED.RD_HIT", + "Counter": "0,1,2,3", + "EventCode": "0xDD", + "EventName": "UNC_M_SB_TAGGED.RD_HIT", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_SB_TAGGED.RD_MISS", + "Counter": "0,1,2,3", + "EventCode": "0xDD", + "EventName": "UNC_M_SB_TAGGED.RD_MISS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_SB_TAGGED.DDR4_CMP", + "Counter": "0,1,2,3", + "EventCode": "0xDD", + "EventName": "UNC_M_SB_TAGGED.DDR4_CMP", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_SB_TAGGED.OCC", + "Counter": "0,1,2,3", + "EventCode": "0xDD", + "EventName": "UNC_M_SB_TAGGED.OCC", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter", + "Counter": "0,1,2,3", + "EventCode": "0xC0", + "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Transition from WMM to RMM because of low threshold", + "Counter": "0,1,2,3", + "EventCode": "0xC0", + "EventName": "UNC_M_WMM_TO_RMM.STARVE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Transition from WMM to RMM because of low threshold", + "Counter": "0,1,2,3", + "EventCode": "0xC0", + "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Full Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_M_WPQ_CYCLES_FULL", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_M_WPQ_CYCLES_NE", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_M_WPQ_READ_HIT", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_M_WPQ_WRITE_HIT", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Not getting the requested Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_M_WRONG_MM", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter", + "Counter": "FIXED", + "EventCode": "0xff", + "EventName": "UNC_M_CLOCKTICKS_F", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0xE0", + "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Read Queue Cycles Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0xE1", + "EventName": "UNC_M_PMM_RPQ_CYCLES_NE", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Read Queue Cycles Full", + "Counter": "0,1,2,3", + "EventCode": "0xE2", + "EventName": "UNC_M_PMM_RPQ_CYCLES_FULL", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RPQ GNTs", + "Counter": "0,1,2,3", + "EventCode": "0xEA", + "EventName": "UNC_M_PMM_CMD1.RPQ_GNTS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "Underfill GNTs", + "Counter": "0,1,2,3", + "EventCode": "0xEA", + "EventName": "UNC_M_PMM_CMD1.WPQ_GNTS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "Misc GNTs", + "Counter": "0,1,2,3", + "EventCode": "0xEA", + "EventName": "UNC_M_PMM_CMD1.MISC_GNT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "Misc Commands (error, flow ACKs)", + "Counter": "0,1,2,3", + "EventCode": "0xEA", + "EventName": "UNC_M_PMM_CMD1.MISC", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Opportunistic Reads", + "Counter": "0,1,2,3", + "EventCode": "0xEB", + "EventName": "UNC_M_PMM_CMD2.OPP_RD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Expected No data packet (ERID matched NDP encoding)", + "Counter": "0,1,2,3", + "EventCode": "0xEB", + "EventName": "UNC_M_PMM_CMD2.NODATA_EXP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Unexpected No data packet (ERID matched a Read, but data was a NDP)", + "Counter": "0,1,2,3", + "EventCode": "0xEB", + "EventName": "UNC_M_PMM_CMD2.NODATA_UNEXP", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Requests - Slot 0", + "Counter": "0,1,2,3", + "EventCode": "0xEB", + "EventName": "UNC_M_PMM_CMD2.REQS_SLOT0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Requests - Slot 1", + "Counter": "0,1,2,3", + "EventCode": "0xEB", + "EventName": "UNC_M_PMM_CMD2.REQS_SLOT1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM ECC Errors", + "Counter": "0,1,2,3", + "EventCode": "0xEB", + "EventName": "UNC_M_PMM_CMD2.PMM_ECC_ERROR", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM ERID detectable parity error", + "Counter": "0,1,2,3", + "EventCode": "0xEB", + "EventName": "UNC_M_PMM_CMD2.PMM_ERID_ERROR", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Major Mode; Cycles PMM is in Read Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0xEC", + "EventName": "UNC_M_PMM_MAJMODE1.RD_CYC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Major Mode; Cycles PMM is in Partial Write Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0xEC", + "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_CYC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0xEC", + "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_ENTER", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0xEC", + "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_EXIT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_MAJMODE2.DRAM_CYC", + "Counter": "0,1,2,3", + "EventCode": "0xED", + "EventName": "UNC_M_MAJMODE2.DRAM_CYC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_MAJMODE2.DRAM_ENTER", + "Counter": "0,1,2,3", + "EventCode": "0xED", + "EventName": "UNC_M_MAJMODE2.DRAM_ENTER", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_MAJMODE2.PMM_ENTER", + "Counter": "0,1,2,3", + "EventCode": "0xED", + "EventName": "UNC_M_MAJMODE2.PMM_ENTER", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Write Queue Cycles Full", + "Counter": "0,1,2,3", + "EventCode": "0xE6", + "EventName": "UNC_M_PMM_WPQ_CYCLES_FULL", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Write Queue Cycles Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0xE5", + "EventName": "UNC_M_PMM_WPQ_CYCLES_NE", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0xE4", + "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.CAS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0xE4", + "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.PWR", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_PMM_WPQ_PCOMMIT", + "Counter": "0,1,2,3", + "EventCode": "0xE8", + "EventName": "UNC_M_PMM_WPQ_PCOMMIT", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_PMM_WPQ_PCOMMIT_CYC", + "Counter": "0,1,2,3", + "EventCode": "0xE9", + "EventName": "UNC_M_PMM_WPQ_PCOMMIT_CYC", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Major Mode; Cycles PMM is in Write Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0xEC", + "EventName": "UNC_M_PMM_MAJMODE1.WR_CYC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_MAJMODE2.PMM_CYC", + "Counter": "0,1,2,3", + "EventCode": "0xED", + "EventName": "UNC_M_MAJMODE2.PMM_CYC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_SB_TAGGED.PMM0_CMP", + "Counter": "0,1,2,3", + "EventCode": "0xDD", + "EventName": "UNC_M_SB_TAGGED.PMM0_CMP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_SB_TAGGED.PMM1_CMP", + "Counter": "0,1,2,3", + "EventCode": "0xDD", + "EventName": "UNC_M_SB_TAGGED.PMM1_CMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_SB_TAGGED.PMM2_CMP", + "Counter": "0,1,2,3", + "EventCode": "0xDD", + "EventName": "UNC_M_SB_TAGGED.PMM2_CMP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Inserts; Persistent Mem writes", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_M_SB_INSERTS.PMM_WRS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Occupancy; Persistent Mem writes", + "Counter": "0,1,2,3", + "EventCode": "0xD5", + "EventName": "UNC_M_SB_OCCUPANCY.PMM_WRS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Occupancy; Persistent Mem reads", + "Counter": "0,1,2,3", + "EventCode": "0xD5", + "EventName": "UNC_M_SB_OCCUPANCY.PMM_RDS", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Inserts; Persistent Mem reads", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_M_SB_INSERTS.PMM_RDS", "PerPkg": "1", - "PublicDescription": "Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller). They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. Is there a filter of sorts???", + "UMask": "0x04", "Unit": "iMC" } ] diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json index f301385845a4..a29bba230f49 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json @@ -1,344 +1,347 @@ [ { - "BriefDescription": "Uncore cache clock ticks", + "BriefDescription": "Traffic in which the M2M to iMC Bypass was not taken", "Counter": "0,1,2,3", - "EventName": "UNC_CHA_CLOCKTICKS", + "EventCode": "0x22", + "EventName": "UNC_M2M_BYPASS_M2M_Egress.NOT_TAKEN", "PerPkg": "1", - "Unit": "CHA" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss", + "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_MISSES.UNCACHEABLE", - "Filter": "config1=0x40e33", + "EventCode": "0x24", + "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" + "Unit": "M2M" }, { - "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ", + "BriefDescription": "Messages sent direct to core (bypassing the CHA)", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", - "Filter": "config1=0x40e33", + "EventCode": "0x23", + "EventName": "UNC_M2M_DIRECT2CORE_TAKEN", "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" + "Unit": "M2M" }, { - "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss", + "BriefDescription": "Number of reads in which direct to core transaction were overridden", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_MISSES.MMIO_READ", - "Filter": "config1=0x40040e33", + "EventCode": "0x25", + "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" + "Unit": "M2M" }, { - "BriefDescription": "MMIO reads", + "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", - "Filter": "config1=0x40040e33", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss", + "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_MISSES.MMIO_WRITE", - "Filter": "config1=0x40041e33", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "MMIO writes", + "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", - "Filter": "config1=0x40041e33", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss", + "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.STREAMING_FULL", - "Filter": "config1=0x41833", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x21", - "Unit": "CHA" + "UMask": "0x8", + "Unit": "M2M" }, { - "BriefDescription": "Streaming stores (full cache line)", + "BriefDescription": "Multi-socket cacheline Directory update from/to Any state", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", - "Filter": "config1=0x41833", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x21", - "Unit": "CHA" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss", + "BriefDescription": "Multi-socket cacheline Directory update from I to S", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", - "Filter": "config1=0x41a33", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x21", - "Unit": "CHA" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "Streaming stores (partial cache line)", + "BriefDescription": "Multi-socket cacheline Directory update from I to A", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", - "Filter": "config1=0x41a33", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x21", - "Unit": "CHA" + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "read requests from home agent", + "BriefDescription": "Multi-socket cacheline Directory update from S to I", "Counter": "0,1,2,3", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I", "PerPkg": "1", - "UMask": "0x03", - "Unit": "CHA" + "UMask": "0x8", + "Unit": "M2M" }, { - "BriefDescription": "read requests from local home agent", + "BriefDescription": "Multi-socket cacheline Directory update from S to A", "Counter": "0,1,2,3", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A", "PerPkg": "1", - "UMask": "0x01", - "Unit": "CHA" + "UMask": "0x10", + "Unit": "M2M" }, { - "BriefDescription": "read requests from remote home agent", + "BriefDescription": "Multi-socket cacheline Directory update from A to I", "Counter": "0,1,2,3", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I", "PerPkg": "1", - "UMask": "0x02", - "Unit": "CHA" + "UMask": "0x20", + "Unit": "M2M" }, { - "BriefDescription": "write requests from home agent", + "BriefDescription": "Multi-socket cacheline Directory update from A to S", "Counter": "0,1,2,3", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.WRITES", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S", "PerPkg": "1", - "UMask": "0x0C", - "Unit": "CHA" + "UMask": "0x40", + "Unit": "M2M" }, { - "BriefDescription": "write requests from local home agent", + "BriefDescription": "Reads to iMC issued at Normal Priority (Non-Isochronous)", "Counter": "0,1,2,3", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.NORMAL", "PerPkg": "1", - "UMask": "0x04", - "Unit": "CHA" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "write requests from remote home agent", + "BriefDescription": "Reads to iMC issued", "Counter": "0,1,2,3", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.ALL", "PerPkg": "1", - "UMask": "0x08", - "Unit": "CHA" + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data", + "BriefDescription": "Partial Non-Isochronous writes to the iMC", "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UPI_DATA_BANDWIDTH_TX", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", "PerPkg": "1", - "ScaleUnit": "7.11E-06Bytes", - "UMask": "0xf", - "Unit": "UPI LL" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "UPI interconnect send bandwidth for payload", + "BriefDescription": "Writes to iMC issued", "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.ALL", "PerPkg": "1", - "ScaleUnit": "7.11E-06Bytes", - "UMask": "0xf", - "Unit": "UPI LL" + "UMask": "0x10", + "Unit": "M2M" }, { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 0", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", + "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.NI", "PerPkg": "1", - "PortMask": "0x01", - "ScaleUnit": "4Bytes", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x80", + "Unit": "M2M" }, { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 1", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", + "BriefDescription": "Prefecth requests that got turn into a demand request", + "Counter": "0,1,2,3", + "EventCode": "0x56", + "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS", "PerPkg": "1", - "PortMask": "0x02", - "ScaleUnit": "4Bytes", - "UMask": "0x01", - "Unit": "IIO" + "Unit": "M2M" }, { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 2", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", + "BriefDescription": "Inserts into the Memory Controller Prefetch Queue", + "Counter": "0,1,2,3", + "EventCode": "0x57", + "EventName": "UNC_M2M_PREFCAM_INSERTS", "PerPkg": "1", - "PortMask": "0x04", - "ScaleUnit": "4Bytes", - "UMask": "0x01", - "Unit": "IIO" + "Unit": "M2M" }, { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 3", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", + "BriefDescription": "AD Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_M2M_RxC_AD_INSERTS", "PerPkg": "1", - "PortMask": "0x08", - "ScaleUnit": "4Bytes", - "UMask": "0x01", - "Unit": "IIO" + "Unit": "M2M" }, { - "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "LLC_MISSES.PCIE_WRITE", - "FCMask": "0x07", - "Filter": "ch_mask=0x1f", - "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "MetricName": "LLC_MISSES.PCIE_WRITE", + "BriefDescription": "AD Ingress (from CMS) Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", "PerPkg": "1", - "PortMask": "0x01", - "ScaleUnit": "4Bytes", - "UMask": "0x01", - "Unit": "IIO" + "Unit": "M2M" }, { - "BriefDescription": "PCI Express bandwidth writing at IIO", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "Filter": "ch_mask=0x1f", - "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "MetricName": "LLC_MISSES.PCIE_WRITE", + "BriefDescription": "BL Ingress (from CMS) Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_M2M_RxC_BL_INSERTS", "PerPkg": "1", - "PortMask": "0x01", - "ScaleUnit": "4Bytes", - "UMask": "0x01", - "Unit": "IIO" + "Unit": "M2M" }, { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 0", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", - "FCMask": "0x07", + "BriefDescription": "BL Ingress (from CMS) Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", "PerPkg": "1", - "PortMask": "0x01", - "ScaleUnit": "4Bytes", - "UMask": "0x04", - "Unit": "IIO" + "Unit": "M2M" }, { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 1", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", - "FCMask": "0x07", + "BriefDescription": "AD Egress (to CMS) Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_M2M_TxC_AD_INSERTS", "PerPkg": "1", - "PortMask": "0x02", - "ScaleUnit": "4Bytes", - "UMask": "0x04", - "Unit": "IIO" + "Unit": "M2M" }, { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 2", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", - "FCMask": "0x07", + "BriefDescription": "AD Egress (to CMS) Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", "PerPkg": "1", - "PortMask": "0x04", - "ScaleUnit": "4Bytes", - "UMask": "0x04", - "Unit": "IIO" + "Unit": "M2M" }, { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 3", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "FCMask": "0x07", + "BriefDescription": "BL Egress (to CMS) Allocations; All", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", "PerPkg": "1", - "PortMask": "0x08", - "ScaleUnit": "4Bytes", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x03", + "Unit": "M2M" }, { - "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "LLC_MISSES.PCIE_READ", - "FCMask": "0x07", - "Filter": "ch_mask=0x1f", - "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "MetricName": "LLC_MISSES.PCIE_READ", + "BriefDescription": "BL Egress (to CMS) Occupancy; All", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.ALL", "PerPkg": "1", - "PortMask": "0x01", - "ScaleUnit": "4Bytes", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x03", + "Unit": "M2M" }, { - "BriefDescription": "PCI Express bandwidth reading at IIO", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "Filter": "ch_mask=0x1f", - "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "MetricName": "LLC_MISSES.PCIE_READ", + "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles when direct to Intel UPI was disabled", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages sent direct to the Intel UPI", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_M2M_DIRECT2UPI_TAKEN", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Dirty line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Clean line underfill read hits to Near Memory(DRAM cache) in Memory Mode", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN", "PerPkg": "1", - "PortMask": "0x01", - "ScaleUnit": "4Bytes", "UMask": "0x04", - "Unit": "IIO" + "Unit": "M2M" + }, + { + "BriefDescription": "Dirty line underfill read hits to Near Memory(DRAM cache) in Memory Mode", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Read requests to Intel Optane DC persistent memory issued to the iMC from M2M", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.TO_PMM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Write requests to Intel Optane DC persistent memory issued to the iMC from M2M", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.TO_PMM", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CLOCKTICKS", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventName": "UNC_C_CLOCKTICKS", + "PerPkg": "1", + "Unit": "CHA" }, { "BriefDescription": "Core Cross Snoops Issued; Multiple Core Requests", @@ -346,7 +349,6 @@ "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", "UMask": "0x42", "Unit": "CHA" }, @@ -356,28 +358,25 @@ "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", "UMask": "0x82", "Unit": "CHA" }, { - "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed", + "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed", "Counter": "0,1,2,3", "EventCode": "0x53", - "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP", + "EventName": "UNC_CHA_DIR_LOOKUP.SNP", "PerPkg": "1", - "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed", - "UMask": "0x02", + "UMask": "0x01", "Unit": "CHA" }, { - "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed", + "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed", "Counter": "0,1,2,3", "EventCode": "0x53", - "EventName": "UNC_CHA_DIR_LOOKUP.SNP", + "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP", "PerPkg": "1", - "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed", - "UMask": "0x01", + "UMask": "0x02", "Unit": "CHA" }, { @@ -386,7 +385,6 @@ "EventCode": "0x54", "EventName": "UNC_CHA_DIR_UPDATE.HA", "PerPkg": "1", - "PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", "UMask": "0x01", "Unit": "CHA" }, @@ -396,17 +394,6 @@ "EventCode": "0x54", "EventName": "UNC_CHA_DIR_UPDATE.TOR", "PerPkg": "1", - "PublicDescription": "Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", - "UMask": "0x02", - "Unit": "CHA" - }, - { - "BriefDescription": "FaST wire asserted; Horizontal", - "Counter": "0,1,2,3", - "EventCode": "0xA5", - "EventName": "UNC_CHA_FAST_ASSERTED.HORZ", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", "UMask": "0x02", "Unit": "CHA" }, @@ -416,545 +403,516 @@ "EventCode": "0x5F", "EventName": "UNC_CHA_HITME_HIT.EX_RDS", "PerPkg": "1", - "PublicDescription": "Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state. This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*)", "UMask": "0x01", "Unit": "CHA" }, { - "BriefDescription": "Normal priority reads issued to the memory controller from the CHA", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ", "Counter": "0,1,2,3", - "EventCode": "0x59", - "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.DATA_READ", "PerPkg": "1", - "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.", - "UMask": "0x01", + "UMask": "0x3", "Unit": "CHA" }, { - "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP", "Counter": "0,1,2,3", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP", "PerPkg": "1", - "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels.", - "UMask": "0x01", + "UMask": "0x9", "Unit": "CHA" }, { - "BriefDescription": "Lines Victimized; Lines in E state", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M", "Counter": "0,1,2,3", + "Deprecated": "1", "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E", + "EventName": "UNC_C_LLC_VICTIMS.M_STATE", "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x02", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Lines Victimized; Lines in F State", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E", "Counter": "0,1,2,3", + "Deprecated": "1", "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_F", + "EventName": "UNC_C_LLC_VICTIMS.E_STATE", "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x08", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Lines Victimized; Lines in M state", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S", "Counter": "0,1,2,3", + "Deprecated": "1", "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M", + "EventName": "UNC_C_LLC_VICTIMS.S_STATE", "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x01", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Lines Victimized; Lines in S State", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F", "Counter": "0,1,2,3", + "Deprecated": "1", "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S", + "EventName": "UNC_C_LLC_VICTIMS.F_STATE", "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x04", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Number of times that an RFO hit in S state.", + "BriefDescription": "Number of times that an RFO hit in S state", "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.RFO_HIT_S", "PerPkg": "1", - "PublicDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.", "UMask": "0x08", "Unit": "CHA" }, { - "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data", + "BriefDescription": "read requests from home agent", "Counter": "0,1,2,3", "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", + "EventName": "UNC_CHA_REQUESTS.READS", "PerPkg": "1", - "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", - "UMask": "0x10", + "UMask": "0x03", "Unit": "CHA" }, { - "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data", + "BriefDescription": "write requests from home agent", "Counter": "0,1,2,3", "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", + "EventName": "UNC_CHA_REQUESTS.WRITES", "PerPkg": "1", - "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", - "UMask": "0x20", + "UMask": "0x0C", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Allocations; IRQ", + "BriefDescription": "read requests from local home agent", "Counter": "0,1,2,3", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.IRQ", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", "PerPkg": "1", - "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x01", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", + "BriefDescription": "write requests from local home agent", "Counter": "0,1,2,3", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", - "UMask": "0x80", + "UMask": "0x04", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Occupancy; IRQ", - "EventCode": "0x11", - "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ", + "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data", + "Counter": "0,1,2,3", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", "PerPkg": "1", - "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", - "UMask": "0x01", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Snoop filter capacity evictions for E-state entries.", + "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data", "Counter": "0,1,2,3", - "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.E_STATE", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", "PerPkg": "1", - "PublicDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.", - "UMask": "0x02", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Snoop filter capacity evictions for M-state entries.", + "BriefDescription": "RspIFwd Snoop Responses Received", "Counter": "0,1,2,3", - "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.M_STATE", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD", "PerPkg": "1", - "PublicDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.", - "UMask": "0x01", + "UMask": "0x04", "Unit": "CHA" }, { - "BriefDescription": "Snoop filter capacity evictions for S-state entries.", + "BriefDescription": "RspSFwd Snoop Responses Received", "Counter": "0,1,2,3", - "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.S_STATE", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD", "PerPkg": "1", - "PublicDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.", - "UMask": "0x04", + "UMask": "0x08", "Unit": "CHA" }, { - "BriefDescription": "RspCnflct* Snoop Responses Received", + "BriefDescription": "Rsp*Fwd*WB Snoop Responses Received", "Counter": "0,1,2,3", "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCTS", + "EventName": "UNC_CHA_SNOOP_RESP.RSP_FWD_WB", "PerPkg": "1", - "PublicDescription": "Counts when a a transaction with the opcode type RspCnflct* Snoop Response was received. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent. This triggers conflict resolution hardware. This covers both the opcode RspCnflct and RspCnflctWbI.", - "UMask": "0x40", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "RspI Snoop Responses Received", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPCNFLCTS", "Counter": "0,1,2,3", + "Deprecated": "1", "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPI", + "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", "PerPkg": "1", - "PublicDescription": "Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data).", - "UMask": "0x01", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "RspIFwd Snoop Responses Received", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA", "Counter": "0,1,2,3", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IRQ", "PerPkg": "1", - "PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.", - "UMask": "0x04", + "UMask": "0x31", "Unit": "CHA" }, { - "BriefDescription": "RspSFwd Snoop Responses Received", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IRQ", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", "Counter": "0,1,2,3", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.REM_ALL", "PerPkg": "1", - "PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.", - "UMask": "0x08", + "UMask": "0x30", "Unit": "CHA" }, { - "BriefDescription": "Rsp*Fwd*WB Snoop Responses Received", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_FAST_ASSERTED.HORZ", "Counter": "0,1,2,3", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSP_FWD_WB", + "Deprecated": "1", + "EventCode": "0xA5", + "EventName": "UNC_C_FAST_ASSERTED", "PerPkg": "1", - "PublicDescription": "Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to its home socket, and the cacheline was forwarded to the requestor socket. This snoop response is only used in >= 4 socket systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to its home socket to be written back to memory.", - "UMask": "0x20", + "UMask": "0x02", "Unit": "CHA" }, { - "BriefDescription": "Rsp*WB Snoop Responses Received", + "BriefDescription": "Ingress (from CMS) Allocations; IRQ", "Counter": "0,1,2,3", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IRQ", "PerPkg": "1", - "PublicDescription": "Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to its home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership.", - "UMask": "0x10", + "UMask": "0x01", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", - "Filter": "config1=0x40233", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", "PerPkg": "1", - "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x11", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC", + "BriefDescription": "Ingress (from CMS) Occupancy; IRQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT", "Counter": "0,1,2,3", + "Deprecated": "1", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", - "Filter": "config1=0x40433", + "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT", "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS", "Counter": "0,1,2,3", + "Deprecated": "1", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", - "Filter": "config1=0x4b233", + "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", - "UMask": "0x11", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_HIT", "Counter": "0,1,2,3", + "Deprecated": "1", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", - "Filter": "config1=0x4b433", + "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", - "UMask": "0x11", + "UMask": "0x14", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_MISS", "Counter": "0,1,2,3", + "Deprecated": "1", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefRFO", - "Filter": "config1=0x4b033", + "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_HIT", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_HIT", "PerPkg": "1", - "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_MISS", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Hits from Local IO", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", - "Filter": "config1=0x40033", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x11", + "UMask": "0x14", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC", + "BriefDescription": "TOR Inserts; Misses from Local IO", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", - "Filter": "config1=0x40233", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", "PerPkg": "1", - "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", + "UMask": "0x24", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC", + "BriefDescription": "TOR Inserts; All from Local iA", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", - "Filter": "config1=0x40433", + "EventName": "UNC_CHA_TOR_INSERTS.IA", "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", + "UMask": "0x31", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", + "BriefDescription": "TOR Inserts; Hits from Local iA", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", - "Filter": "config1=0x4b233", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", - "UMask": "0x21", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", + "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", - "Filter": "config1=0x4b433", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC", + "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO", - "Filter": "config1=0x4b033", + "EventName": "LLC_MISSES.UNCACHEABLE", + "Filter": "config1=0x40e33", "PerPkg": "1", - "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC", + "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", - "Filter": "config1=0x40033", + "EventName": "LLC_MISSES.MMIO_READ", + "Filter": "config1=0x40040e33", "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", + "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss", "Counter": "0,1,2,3", - "Deprecated": "1", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL", - "Filter": "CHAfilter1", + "EventName": "LLC_MISSES.MMIO_WRITE", + "Filter": "config1=0x40041e33", "PerPkg": "1", - "PublicDescription": "This event is deprecated. ", - "UMask": "0x30", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", - "Filter": "config1=0x40233", + "BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "LLC_REFERENCES.STREAMING_FULL", + "Filter": "config1=0x41833", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", - "UMask": "0x11", + "ScaleUnit": "64Bytes", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", - "Filter": "config1=0x40433", + "BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", + "Filter": "config1=0x41a33", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", - "UMask": "0x11", + "ScaleUnit": "64Bytes", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", + "BriefDescription": "TOR Occupancy; All from Local iA", "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", - "Filter": "config1=0x4b233", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", - "UMask": "0x11", + "UMask": "0x31", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", + "BriefDescription": "TOR Occupancy; Hits from Local iA", "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", - "Filter": "config1=0x4b433", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", + "BriefDescription": "TOR Occupancy; Misses from Local iA", "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", - "Filter": "config1=0x4b033", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", - "UMask": "0x11", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", - "Filter": "config1=0x40033", + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCS VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCS", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", - "UMask": "0x11", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", - "Filter": "config1=0x40233", + "BriefDescription": "FaST wire asserted; Horizontal", + "Counter": "0,1,2,3", + "EventCode": "0xA5", + "EventName": "UNC_CHA_FAST_ASSERTED.HORZ", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", - "UMask": "0x21", + "UMask": "0x02", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", - "Filter": "config1=0x40433", + "BriefDescription": "Uncore cache clock ticks", + "Counter": "0,1,2,3", + "EventName": "UNC_CHA_CLOCKTICKS", "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", - "Filter": "config1=0x4b233", - "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", - "Filter": "config1=0x4b433", + "BriefDescription": "Normal priority reads issued to the memory controller from the CHA", + "Counter": "0,1,2,3", + "EventCode": "0x59", + "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", - "UMask": "0x21", + "UMask": "0x01", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", - "Filter": "config1=0x4b033", + "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH", + "Counter": "0,1,2,3", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", - "UMask": "0x21", + "UMask": "0x01", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", - "Filter": "config1=0x40033", + "BriefDescription": "Read requests from a remote socket", + "Counter": "0,1,2,3", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", - "UMask": "0x21", + "UMask": "0x02", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CLOCKTICKS", + "BriefDescription": "RspI Snoop Responses Received", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventName": "UNC_C_CLOCKTICKS", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPI", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_CLOCKTICKS", + "UMask": "0x01", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_FAST_ASSERTED.HORZ", + "BriefDescription": "Rsp*WB Snoop Responses Received", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0xA5", - "EventName": "UNC_C_FAST_ASSERTED", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_FAST_ASSERTED.HORZ", - "UMask": "0x02", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E", + "BriefDescription": "RspCnflct* Snoop Responses Received", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.E_STATE", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCTS", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E", - "UMask": "0x2", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F", + "BriefDescription": "Snoop filter capacity evictions for M-state entries", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.F_STATE", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.M_STATE", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F", - "UMask": "0x8", + "UMask": "0x01", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M", + "BriefDescription": "Snoop filter capacity evictions for E-state entries", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.M_STATE", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.E_STATE", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M", - "UMask": "0x1", + "UMask": "0x02", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S", + "BriefDescription": "Snoop filter capacity evictions for S-state entries", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.S_STATE", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.S_STATE", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S", - "UMask": "0x4", + "UMask": "0x04", "Unit": "CHA" }, { @@ -962,413 +920,377 @@ "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.REM_ALL", - "Filter": "CHAfilter1", + "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL", "PerPkg": "1", - "PublicDescription": "This event is deprecated. ", "UMask": "0x30", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE", + "BriefDescription": "Lines Victimized; Lines in M state", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.CORE_GTONE", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE", - "UMask": "0x42", + "UMask": "0x01", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE", + "BriefDescription": "Lines Victimized; Lines in E state", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.EVICT_GTONE", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE", - "UMask": "0x82", + "UMask": "0x02", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP", + "BriefDescription": "Lines Victimized; Lines in S State", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x53", - "EventName": "UNC_H_DIR_LOOKUP.NO_SNP", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP", - "UMask": "0x2", + "UMask": "0x04", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP", + "BriefDescription": "Lines Victimized; Lines in F State", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x53", - "EventName": "UNC_H_DIR_LOOKUP.SNP", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_F", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP", - "UMask": "0x1", + "UMask": "0x08", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x54", - "EventName": "UNC_H_DIR_UPDATE.HA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", + "Filter": "config1=0x40433", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA", - "UMask": "0x1", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR", + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x54", - "EventName": "UNC_H_DIR_UPDATE.TOR", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", + "Filter": "config1=0x40233", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR", - "UMask": "0x2", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS", + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5F", - "EventName": "UNC_H_HITME_HIT.EX_RDS", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", + "Filter": "config1=0x40033", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS", - "UMask": "0x1", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S", + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x39", - "EventName": "UNC_H_MISC.RFO_HIT_S", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", + "Filter": "config1=0x4b433", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S", - "UMask": "0x8", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL", + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", + "Filter": "config1=0x4b233", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL", - "UMask": "0x10", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE", + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefRFO", + "Filter": "config1=0x4b033", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE", - "UMask": "0x20", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.READS", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Filter": "config1=0x40433", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS", - "UMask": "0x3", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS_LOCAL", + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.READS_LOCAL", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "Filter": "config1=0x40233", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS_LOCAL", - "UMask": "0x1", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES", + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.WRITES", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", + "Filter": "config1=0x40033", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES", - "UMask": "0xC", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES_LOCAL", + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", + "Filter": "config1=0x4b433", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES_LOCAL", - "UMask": "0x4", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ", + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x13", - "EventName": "UNC_H_RxC_INSERTS.IRQ", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", + "Filter": "config1=0x4b233", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ", - "UMask": "0x1", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x19", - "EventName": "UNC_H_RxC_IRQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", - "UMask": "0x80", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO", + "Filter": "config1=0x4b033", + "PerPkg": "1", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ", - "Deprecated": "1", - "EventCode": "0x11", - "EventName": "UNC_H_RxC_OCCUPANCY.IRQ", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "Filter": "config1=0x40433", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ", - "UMask": "0x1", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPCNFLCTS", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "Filter": "config1=0x40233", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPCNFLCTS", - "UMask": "0x40", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSPIFWD", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "Filter": "config1=0x40033", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD", - "UMask": "0x4", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", + "Filter": "config1=0x4b433", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD", - "UMask": "0x8", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", + "Filter": "config1=0x4b233", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB", - "UMask": "0x20", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "Clockticks of the IIO Traffic Controller", - "Counter": "0,1,2,3", - "EventCode": "0x1", - "EventName": "UNC_IIO_CLOCKTICKS", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", + "Filter": "config1=0x4b033", "PerPkg": "1", - "PublicDescription": "Counts clockticks of the 1GHz traffic controller clock in the IIO unit.", - "Unit": "IIO" + "UMask": "0x11", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3", - "Counter": "0,1,2,3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", - "FCMask": "0x4", + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Filter": "config1=0x40433", "PerPkg": "1", - "PortMask": "0x0f", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3", - "UMask": "0x03", - "Unit": "IIO" + "UMask": "0x21", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", - "Counter": "0,1,2,3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", - "FCMask": "0x4", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "Filter": "config1=0x40233", "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", - "UMask": "0x03", - "Unit": "IIO" + "UMask": "0x21", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", - "Counter": "0,1,2,3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", - "FCMask": "0x4", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "Filter": "config1=0x40033", "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", - "UMask": "0x03", - "Unit": "IIO" + "UMask": "0x21", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", - "Counter": "0,1,2,3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", - "FCMask": "0x4", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", + "Filter": "config1=0x4b433", "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", - "UMask": "0x03", - "Unit": "IIO" + "UMask": "0x21", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", - "Counter": "0,1,2,3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", - "FCMask": "0x4", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", + "Filter": "config1=0x4b233", "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", - "UMask": "0x03", - "Unit": "IIO" + "UMask": "0x21", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3", - "Counter": "2,3", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", - "FCMask": "0x04", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", + "Filter": "config1=0x4b033", "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3", - "UMask": "0x0f", - "Unit": "IIO" + "UMask": "0x21", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0", - "Counter": "2,3", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", - "FCMask": "0x04", + "BriefDescription": "Clockticks of the IIO Traffic Controller", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_IIO_CLOCKTICKS", "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0", - "UMask": "0x01", "Unit": "IIO" }, { - "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1", - "Counter": "2,3", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", - "FCMask": "0x04", + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0", + "FCMask": "0x7", "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1", - "UMask": "0x02", + "PortMask": "0x1", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2", - "Counter": "2,3", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", - "FCMask": "0x04", + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1", + "FCMask": "0x7", "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2", - "UMask": "0x04", + "PortMask": "0x2", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3", - "Counter": "2,3", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", - "FCMask": "0x04", + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2", + "FCMask": "0x7", "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3", - "UMask": "0x08", + "PortMask": "0x4", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", - "FCMask": "0x07", + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3", + "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x04", + "PortMask": "0x8", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", - "FCMask": "0x07", + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0", + "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x04", + "PortMask": "0x1", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part2", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", - "FCMask": "0x07", + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1", + "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x04", + "PortMask": "0x2", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part3", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", - "FCMask": "0x07", + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2", + "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x04", + "PortMask": "0x4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x4", "Unit": "IIO" }, { @@ -1379,7 +1301,6 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", "UMask": "0x01", "Unit": "IIO" }, @@ -1391,7 +1312,6 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", - "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", "UMask": "0x01", "Unit": "IIO" }, @@ -1403,7 +1323,6 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", - "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", "UMask": "0x01", "Unit": "IIO" }, @@ -1415,152 +1334,202 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", - "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", "UMask": "0x01", "Unit": "IIO" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0", + "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit", "Counter": "2,3", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x08", + "UMask": "0x02", "Unit": "IIO" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1", + "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit", "Counter": "2,3", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", - "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x08", + "UMask": "0x02", "Unit": "IIO" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2", + "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit", "Counter": "2,3", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", - "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x08", + "UMask": "0x02", "Unit": "IIO" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3", + "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit", "Counter": "2,3", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", - "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x08", + "UMask": "0x02", "Unit": "IIO" }, { - "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit", + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0", "Counter": "2,3", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x02", + "UMask": "0x04", "Unit": "IIO" }, { - "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit", + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1", "Counter": "2,3", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x02", + "UMask": "0x04", "Unit": "IIO" }, { - "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit", + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part2", "Counter": "2,3", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x02", + "UMask": "0x04", "Unit": "IIO" }, { - "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit", + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part3", "Counter": "2,3", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x02", + "UMask": "0x04", "Unit": "IIO" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target", + "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO, part 0", "Counter": "0,1", "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x08", + "ScaleUnit": "4Bytes", + "UMask": "0x01", "Unit": "IIO" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target", + "BriefDescription": "PCI Express bandwidth writing at IIO, part 1", "Counter": "0,1", "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x08", + "ScaleUnit": "4Bytes", + "UMask": "0x01", "Unit": "IIO" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target", + "BriefDescription": "PCI Express bandwidth writing at IIO, part 2", "Counter": "0,1", "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x08", + "ScaleUnit": "4Bytes", + "UMask": "0x01", "Unit": "IIO" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target", + "BriefDescription": "PCI Express bandwidth writing at IIO, part 3", "Counter": "0,1", "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x08", + "ScaleUnit": "4Bytes", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "LLC_MISSES.PCIE_WRITE", + "FCMask": "0x07", + "Filter": "ch_mask=0x1f", + "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "MetricName": "LLC_MISSES.PCIE_WRITE", + "PerPkg": "1", + "PortMask": "0x01", + "ScaleUnit": "4Bytes", + "UMask": "0x01", "Unit": "IIO" }, { @@ -1571,7 +1540,6 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", "UMask": "0x02", "Unit": "IIO" }, @@ -1583,7 +1551,6 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", "UMask": "0x02", "Unit": "IIO" }, @@ -1595,7 +1562,6 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", "UMask": "0x02", "Unit": "IIO" }, @@ -1607,208 +1573,246 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", "UMask": "0x02", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "BriefDescription": "PCI Express bandwidth reading at IIO, part 0", "Counter": "0,1", - "Deprecated": "1", "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0", - "FCMask": "0x7", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", - "UMask": "0x4", + "PortMask": "0x01", + "ScaleUnit": "4Bytes", + "UMask": "0x04", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "BriefDescription": "PCI Express bandwidth reading at IIO, part 1", "Counter": "0,1", - "Deprecated": "1", "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1", - "FCMask": "0x7", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x2", - "PublicDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", - "UMask": "0x4", + "PortMask": "0x02", + "ScaleUnit": "4Bytes", + "UMask": "0x04", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "BriefDescription": "PCI Express bandwidth reading at IIO, part 2", "Counter": "0,1", - "Deprecated": "1", "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2", - "FCMask": "0x7", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x4", - "PublicDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", - "UMask": "0x4", + "PortMask": "0x04", + "ScaleUnit": "4Bytes", + "UMask": "0x04", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "BriefDescription": "PCI Express bandwidth reading at IIO, part 3", "Counter": "0,1", - "Deprecated": "1", "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3", - "FCMask": "0x7", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x8", - "PublicDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "UMask": "0x4", + "PortMask": "0x08", + "ScaleUnit": "4Bytes", + "UMask": "0x04", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0", "Counter": "0,1", - "Deprecated": "1", "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0", - "FCMask": "0x7", + "EventName": "LLC_MISSES.PCIE_READ", + "FCMask": "0x07", + "Filter": "ch_mask=0x1f", + "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "MetricName": "LLC_MISSES.PCIE_READ", "PerPkg": "1", - "PortMask": "0x1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", - "UMask": "0x1", + "PortMask": "0x01", + "ScaleUnit": "4Bytes", + "UMask": "0x04", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target", "Counter": "0,1", - "Deprecated": "1", "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1", - "FCMask": "0x7", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", + "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x2", - "PublicDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", - "UMask": "0x1", + "PortMask": "0x01", + "UMask": "0x08", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target", "Counter": "0,1", - "Deprecated": "1", "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2", - "FCMask": "0x7", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", + "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x4", - "PublicDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", - "UMask": "0x1", + "PortMask": "0x02", + "UMask": "0x08", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target", "Counter": "0,1", - "Deprecated": "1", "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3", - "FCMask": "0x7", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", + "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x8", - "PublicDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "UMask": "0x1", - "Unit": "IIO" + "PortMask": "0x04", + "UMask": "0x08", + "Unit": "IIO" }, { - "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0", + "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU", "Counter": "0,1,2,3", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x04", + "UMask": "0x01", "Unit": "IIO" }, { - "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1", + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU", "Counter": "0,1,2,3", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x04", + "UMask": "0x01", "Unit": "IIO" }, { - "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2", + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU", "Counter": "0,1,2,3", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x04", + "UMask": "0x01", "Unit": "IIO" }, { - "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3", + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU", "Counter": "0,1,2,3", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x04", + "UMask": "0x01", "Unit": "IIO" }, { - "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU", + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit", "Counter": "0,1,2,3", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x01", + "UMask": "0x02", "Unit": "IIO" }, { - "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU", + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit", "Counter": "0,1,2,3", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x01", + "UMask": "0x02", "Unit": "IIO" }, { - "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU", + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit", "Counter": "0,1,2,3", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x01", + "UMask": "0x02", "Unit": "IIO" }, { - "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU", + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit", "Counter": "0,1,2,3", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x01", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x04", "Unit": "IIO" }, { @@ -1819,7 +1823,6 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", "UMask": "0x08", "Unit": "IIO" }, @@ -1831,7 +1834,6 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", "UMask": "0x08", "Unit": "IIO" }, @@ -1843,7 +1845,6 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", "UMask": "0x08", "Unit": "IIO" }, @@ -1855,55 +1856,94 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", "UMask": "0x08", "Unit": "IIO" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit", + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory", "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", "UMask": "0x02", "Unit": "IIO" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit", + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target", "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", "UMask": "0x02", "Unit": "IIO" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit", + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target", "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", "UMask": "0x02", "Unit": "IIO" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit", + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target", "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", "UMask": "0x02", "Unit": "IIO" }, @@ -1915,7 +1955,6 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", "UMask": "0x04", "Unit": "IIO" }, @@ -1927,816 +1966,20997 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", "UMask": "0x04", "Unit": "IIO" }, { - "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", - "FCMask": "0x07", + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x0f", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x0f", + "Unit": "IIO" + }, + { + "BriefDescription": "Total IRP occupancy of inbound read and write requests", + "Counter": "0,1", + "EventCode": "0xF", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.RFO", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.PCITOM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue", + "Counter": "0,1", + "EventCode": "0x18", + "EventName": "UNC_I_FAF_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Occupancy of the IRP FAF queue", + "Counter": "0,1", + "EventCode": "0x19", + "EventName": "UNC_I_FAF_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound write (fast path) requests received by the IRP", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Clocks of the Intel Ultra Path Interconnect (UPI)", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_UPI_CLOCKTICKS", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Data Response packets that go direct to core", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_DIRECT_ATTEMPTS.D2U", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Cycles Intel UPI is in L1 power mode (shutdown)", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_UPI_L1_POWER_CYCLES", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Cycles the Rx of the Intel UPI is in L0p power mode", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_UPI_RxL0P_POWER_CYCLES", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI LL" + }, + { + "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.ALL_NULL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.NULL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Cycles in which the Tx of the Intel Ultra Path Interconnect (UPI) is in L0p power mode", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "FLITs that bypassed the TxL Buffer", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_UPI_TxL_BYPASSED", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent; Data", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.DATA", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_NULL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.NULL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Protocol header and credit FLITs received from any slot", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", + "PerPkg": "1", + "UMask": "0x97", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Protocol header and credit FLITs transmitted across any slot", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", + "PerPkg": "1", + "UMask": "0x97", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Idle FLITs transmitted", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.IDLE", + "PerPkg": "1", + "UMask": "0x47", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Null FLITs transmitted from any slot", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", + "PerPkg": "1", + "UMask": "0x27", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Null FLITs received from any slot", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", + "PerPkg": "1", + "UMask": "0x27", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid data FLITs received from any slot", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", + "PerPkg": "1", + "UMask": "0x0F", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UPI_DATA_BANDWIDTH_TX", + "PerPkg": "1", + "ScaleUnit": "7.11E-06Bytes", + "UMask": "0xf", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UPI interconnect send bandwidth for payload", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", + "PerPkg": "1", + "ScaleUnit": "7.11E-06Bytes", + "UMask": "0xf", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Data Response packets that go direct to Intel UPI", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Prefetches generated by the flow control queue of the M3UPI unit", + "Counter": "0,1,2", + "EventCode": "0x29", + "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2M to iMC Bypass; Taken", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_M2M_BYPASS_M2M_Egress.TAKEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles - at UCLK", + "Counter": "0,1,2,3", + "EventName": "UNC_M2M_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On Dirty Line in I State", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On Dirty Line in S State", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On Dirty Line in L State", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On Dirty Line in A State", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On NonDirty Line in I State", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On NonDirty Line in S State", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On NonDirty Line in L State", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On NonDirty Line in A State", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On Dirty Line in I State", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On Dirty Line in S State", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On Dirty Line in L State", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On Dirty Line in A State", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On NonDirty Line in I State", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On NonDirty Line in S State", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On NonDirty Line in L State", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On NonDirty Line in A State", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC; Critical Priority", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.ISOCH", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC; All, regardless of priority", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.FROM_TRANSGRESS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC; Full Line Non-ISOCH", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FULL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC; ISOCH Full Line", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC; ISOCH Partial", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FROM_TRANSGRESS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Number Packet Header Matches; Mesh Match", + "Counter": "0,1,2,3", + "EventCode": "0x4C", + "EventName": "UNC_M2M_PKT_MATCH.MESH", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number Packet Header Matches; MC Match", + "Counter": "0,1,2,3", + "EventCode": "0x4C", + "EventName": "UNC_M2M_PKT_MATCH.MC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Full", + "Counter": "0,1,2,3", + "EventCode": "0x53", + "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "UNC_M2M_PREFCAM_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x55", + "EventName": "UNC_M2M_PREFCAM_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Number AD Ingress Credits", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M2M_TGR_AD_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number BL Ingress Credits", + "Counter": "0,1,2,3", + "EventCode": "0x42", + "EventName": "UNC_M2M_TGR_BL_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Full; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Full; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Full; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Not Empty; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Not Empty; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Not Empty; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Occupancy; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Occupancy; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Occupancy; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Pending Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x48", + "EventName": "UNC_M2M_TRACKER_PENDING_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x61", + "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x61", + "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x61", + "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Down", + "Counter": "0,1,2,3", + "EventCode": "0xAE", + "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Up", + "Counter": "0,1,2,3", + "EventCode": "0xAE", + "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA7", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA7", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA7", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA7", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA9", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA9", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA9", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA9", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Even", + "Counter": "0,1,2,3", + "EventCode": "0xAB", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xAB", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Even", + "Counter": "0,1,2,3", + "EventCode": "0xAB", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xAB", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Left", + "Counter": "0,1,2,3", + "EventCode": "0xAD", + "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Right", + "Counter": "0,1,2,3", + "EventCode": "0xAD", + "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; AD", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AD", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AK", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; BL", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; IV", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; AD", + "Counter": "0,1,2,3", + "EventCode": "0xA2", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core", + "Counter": "0,1,2,3", + "EventCode": "0xA2", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core", + "Counter": "0,1,2,3", + "EventCode": "0xA2", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache", + "Counter": "0,1,2,3", + "EventCode": "0xA2", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Source Throttle", + "Counter": "0,1,2,3", + "EventCode": "0xA4", + "EventName": "UNC_M2M_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Full", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_M2M_RxC_AD_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Full", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_M2M_RxC_BL_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; IFV - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Credits Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0xE", + "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Credit Acquired", + "Counter": "0,1,2,3", + "EventCode": "0xD", + "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Full", + "Counter": "0,1,2,3", + "EventCode": "0xC", + "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0xB", + "EventName": "UNC_M2M_TxC_AD_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No AD Egress (to CMS) Credits", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound Ring Transactions on AK; CRD Transactions to Cbo", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_M2M_TxC_AK.CRD_CBO", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound Ring Transactions on AK; NDR Transactions", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_M2M_TxC_AK.NDR", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x1F", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x1F", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_CACHE", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_CORE", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x1A", + "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x1A", + "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Full; All", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Not Empty; All", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; IV", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; IV", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; IV", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Down and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA6", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Down and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA6", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Up and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA6", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Up and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA6", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Down and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA8", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Down and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA8", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Up and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA8", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Up and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA8", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Down and Even", + "Counter": "0,1,2,3", + "EventCode": "0xAA", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Down and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xAA", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Up and Even", + "Counter": "0,1,2,3", + "EventCode": "0xAA", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Up and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xAA", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical IV Ring in Use; Down", + "Counter": "0,1,2,3", + "EventCode": "0xAC", + "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical IV Ring in Use; Up", + "Counter": "0,1,2,3", + "EventCode": "0xAC", + "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_TxC_BL.DRS_UPI", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x40", + "EventName": "UNC_NoUnit_TxC_BL.DRS_UPI", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_UPI", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; IV", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC Bypass; Taken", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC Bypass; Not Taken", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "EventCode": "0xC0", + "EventName": "UNC_M2M_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "FaST wire asserted; Vertical", + "Counter": "0,1,2,3", + "EventCode": "0xA5", + "EventName": "UNC_M2M_FAST_ASSERTED.VERT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "FaST wire asserted; Horizontal", + "Counter": "0,1,2,3", + "EventCode": "0xA5", + "EventName": "UNC_M2M_FAST_ASSERTED.HORZ", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Clean line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode and regular reads to DRAM in 1LM", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1", + "PerPkg": "1", + "UMask": "0x88", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1", + "PerPkg": "1", + "UMask": "0xA0", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; All", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; Read Credit Request", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; Write Credit Request", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; Write Compare Request", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; All", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Read Credit Request", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Write Credit Request", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Write Compare Request", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Prefetch Read Cam Hit", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; All", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; Read Credit Request", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; Write Credit Request", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; Write Compare Request", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; All", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Sideband", + "Counter": "0,1,2,3", + "EventCode": "0x6B", + "EventName": "UNC_M2M_TxC_AK_SIDEBAND.RD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Sideband", + "Counter": "0,1,2,3", + "EventCode": "0x6B", + "EventName": "UNC_M2M_TxC_AK_SIDEBAND.WR", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x4F", + "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x4F", + "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x4F", + "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CHA to iMC Bypass; Taken", + "Counter": "0,1,2,3", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Bypass; Intermediate bypass Taken", + "Counter": "0,1,2,3", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Bypass; Not Taken", + "Counter": "0,1,2,3", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Single External Snoops", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Single Core Requests", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", + "PerPkg": "1", + "UMask": "0x41", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Single Eviction", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", + "PerPkg": "1", + "UMask": "0x81", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Any Single Snoop", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", + "PerPkg": "1", + "UMask": "0xE1", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Multiple External Snoops", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", + "PerPkg": "1", + "UMask": "0x22", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Any Cycle with Multiple Snoops", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", + "PerPkg": "1", + "UMask": "0xE2", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; External Snoop to Remote Node", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_REMOTE", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Core Request to Remote Node", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_REMOTE", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Eviction to Remote Node", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_REMOTE", + "PerPkg": "1", + "UMask": "0x84", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Any Snoop to Remote Node", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_REMOTE", + "PerPkg": "1", + "UMask": "0xE4", + "Unit": "CHA" + }, + { + "BriefDescription": "Counter 0 Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x1F", + "EventName": "UNC_CHA_COUNTER0_OCCUPANCY", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; Shared hit and op is RdInvOwn, RdInv, Inv*", + "Counter": "0,1,2,3", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE", + "Counter": "0,1,2,3", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.WBMTOE", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", + "Counter": "0,1,2,3", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*", + "Counter": "0,1,2,3", + "EventCode": "0x5E", + "EventName": "UNC_CHA_HITME_LOOKUP.READ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", + "Counter": "0,1,2,3", + "EventCode": "0x5E", + "EventName": "UNC_CHA_HITME_LOOKUP.WRITE", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Misses in HitMe Cache; SF/LLC HitS/F and op is RdInvOwn", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Misses in HitMe Cache; No SF/LLC HitS/F and op is RdInvOwn", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Misses in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache to SHARed", + "Counter": "0,1,2,3", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.SHARED", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache on RdInvOwn even if not RspFwdI*", + "Counter": "0,1,2,3", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Deallocate HtiME$ on Reads without RspFwdI*", + "Counter": "0,1,2,3", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "HA to iMC Reads Issued; ISOCH", + "Counter": "0,1,2,3", + "EventCode": "0x59", + "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Writes Issued to the iMC by the HA; Partial Non-ISOCH", + "Counter": "0,1,2,3", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Full Line", + "Counter": "0,1,2,3", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Partial", + "Counter": "0,1,2,3", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Writes Issued to the iMC by the HA; Full Line MIG", + "Counter": "0,1,2,3", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_MIG", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Writes Issued to the iMC by the HA; Partial MIG", + "Counter": "0,1,2,3", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations", + "Counter": "0,1,2,3", + "EventCode": "0x62", + "EventName": "UNC_CHA_IODC_ALLOC.INVITOM", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations dropped due to IODC Full", + "Counter": "0,1,2,3", + "EventCode": "0x62", + "EventName": "UNC_CHA_IODC_ALLOC.IODCFULL", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IDOC allocation dropped due to OSB gate", + "Counter": "0,1,2,3", + "EventCode": "0x62", + "EventName": "UNC_CHA_IODC_ALLOC.OSBGATED", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoE", + "Counter": "0,1,2,3", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOE", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoI", + "Counter": "0,1,2,3", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOI", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbPushMtoI", + "Counter": "0,1,2,3", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.WBPUSHMTOI", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to conflicting transaction", + "Counter": "0,1,2,3", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.SNPOUT", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to any reason", + "Counter": "0,1,2,3", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.ALL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITE", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.WRITE", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.ANY", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.ANY", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOCAL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.LOCAL", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.REMOTE", + "PerPkg": "1", + "UMask": "0x91", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.LOCAL", + "PerPkg": "1", + "UMask": "0x2f", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.REMOTE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc; Silent Snoop Eviction", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc; Write Combining Aliasing", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.WC_ALIASING", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc; CV0 Prefetch Victim", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc; CV0 Prefetch Miss", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast", + "Counter": "0,1,2,3", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC0_SMI0", + "Counter": "0,1,2,3", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC0_SMI0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC1_SMI1", + "Counter": "0,1,2,3", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC1_SMI1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC0_SMI2", + "Counter": "0,1,2,3", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.EDC0_SMI2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC1_SMI3", + "Counter": "0,1,2,3", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.EDC1_SMI3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC2_SMI4", + "Counter": "0,1,2,3", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.EDC2_SMI4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC3_SMI5", + "Counter": "0,1,2,3", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.EDC3_SMI5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "write requests from remote home agent", + "Counter": "0,1,2,3", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.ALL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Local Requests", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Remote Requests", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.BCST_LOC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_REMOTE", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.BCST_REM", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.DIRECT_LOC", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.DIRECT_REM", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : RspS", + "Counter": "0,1,2,3", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_WBWB", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSP_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received; RspFwd", + "Counter": "0,1,2,3", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPI", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPIFWD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPSFWD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_FWD_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPCNFLCT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPFWD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.EVICT", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.EVICT", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.PRQ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.PRQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IPQ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IPQ", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.HIT", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.HIT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.MISS", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.EVICT", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.EVICT", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.PRQ", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.PRQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IPQ", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IPQ", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.HIT", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.HIT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.MISS", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "WbPushMtoI; Pushed to LLC", + "Counter": "0,1,2,3", + "EventCode": "0x56", + "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "WbPushMtoI; Pushed to Memory", + "Counter": "0,1,2,3", + "EventCode": "0x56", + "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC0_SMI0", + "Counter": "0,1,2,3", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC1_SMI1", + "Counter": "0,1,2,3", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC0_SMI2", + "Counter": "0,1,2,3", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC1_SMI3", + "Counter": "0,1,2,3", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC2_SMI4", + "Counter": "0,1,2,3", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC3_SMI5", + "Counter": "0,1,2,3", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOC_IO", + "PerPkg": "1", + "UMask": "0x34", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOC_IA", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOC_ALL", + "PerPkg": "1", + "UMask": "0x37", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IO", + "PerPkg": "1", + "UMask": "0x34", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IA", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.LOC_ALL", + "PerPkg": "1", + "UMask": "0x37", + "Unit": "CHA" + }, + { + "BriefDescription": "Core PMA Events; C1 State", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.C1_STATE", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Core PMA Events; C1 Transition", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.C1_TRANSITION", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Core PMA Events; C6 State", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.C6_STATE", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Core PMA Events; C6 Transition", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.C6_TRANSITION", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Core PMA Events; GV", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.GV", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CMS_CLOCKTICKS", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_H_CLOCK", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Up", + "Counter": "0,1,2,3", + "EventCode": "0xAE", + "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Down", + "Counter": "0,1,2,3", + "EventCode": "0xAE", + "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA7", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA7", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA7", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA7", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA9", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA9", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA9", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA9", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Even", + "Counter": "0,1,2,3", + "EventCode": "0xAB", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xAB", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Even", + "Counter": "0,1,2,3", + "EventCode": "0xAB", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xAB", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Left", + "Counter": "0,1,2,3", + "EventCode": "0xAD", + "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Right", + "Counter": "0,1,2,3", + "EventCode": "0xAD", + "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; AD", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AD", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AK", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; BL", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; IV", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; AD", + "Counter": "0,1,2,3", + "EventCode": "0xA2", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core", + "Counter": "0,1,2,3", + "EventCode": "0xA2", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core", + "Counter": "0,1,2,3", + "EventCode": "0xA2", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache", + "Counter": "0,1,2,3", + "EventCode": "0xA2", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SRC_THRTL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xA4", + "EventName": "UNC_C_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; IRQ Rejected", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; IPQ", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IPQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; PRQ", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.PRQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; PRQ", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; RRQ", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.RRQ", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; WBQ", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.WBQ", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; AD REQ on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; AD RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; BL RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; BL WB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; BL NCB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; BL NCS on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ANY0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.ANY_IPQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; HA", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; LLC Victim", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; SF Victim", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; Victim", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; Merging these two together to make room for ANY_REJECT_*0", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; Allow Snoop", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; PhyAddr Match", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.ANY_REJECT_IRQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Merging these two together to make room for ANY_REJECT_*0", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; AD REQ on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; AD RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; BL RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; BL WB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; BL NCB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; BL NCS on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; AD REQ on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; AD RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; BL RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; BL WB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; BL NCB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; BL NCS on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x25", + "EventName": "UNC_H_RxC_ISMQ1_REJECT.ANY_ISMQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; HA", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x2D", + "EventName": "UNC_H_RxC_ISMQ1_RETRY.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; HA", + "Counter": "0,1,2,3", + "EventCode": "0x2D", + "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy; IPQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy; RRQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy; WBQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; AD REQ on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; AD RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; BL RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; BL WB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; BL NCB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; BL NCS on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; HA", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; LLC Victim", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; SF Victim", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; Victim", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; Merging these two together to make room for ANY_REJECT_*0", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; Allow Snoop", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; PhyAddr Match", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.ANY_PRQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC OR SF Way", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; AD REQ on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; AD RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; BL RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; BL WB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; BL NCB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; BL NCS on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; HA", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; LLC Victim", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; SF Victim", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; Victim", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; Merging these two together to make room for ANY_REJECT_*0", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; Allow Snoop", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; PhyAddr Match", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; AD REQ on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; AD RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; BL RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; BL WB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; BL NCB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; BL NCS on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ANY0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.ANY_RRQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; HA", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; LLC Victim", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; SF Victim", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; Victim", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; Merging these two together to make room for ANY_REJECT_*0", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; Allow Snoop", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; PhyAddr Match", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; AD REQ on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; AD RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; BL RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; BL WB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; BL NCB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; BL NCS on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ANY0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.ANY_WBQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; HA", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; LLC Victim", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; SF Victim", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; Victim", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; Merging these two together to make room for ANY_REJECT_*0", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; Allow Snoop", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; PhyAddr Match", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; IFV - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.IV", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.IV_AG1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.IV", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.IV", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.IV", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; IV", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.IV", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Up and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA6", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Up and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA6", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Down and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA6", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Down and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA6", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Up and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA8", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Up and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA8", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Down and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA8", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Down and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA8", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Up and Even", + "Counter": "0,1,2,3", + "EventCode": "0xAA", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Up and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xAA", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Down and Even", + "Counter": "0,1,2,3", + "EventCode": "0xAA", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Down and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xAA", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical IV Ring in Use; Up", + "Counter": "0,1,2,3", + "EventCode": "0xAC", + "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical IV Ring in Use; Down", + "Counter": "0,1,2,3", + "EventCode": "0xAC", + "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; External RspHitFSE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Core RspHitFSE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE", + "PerPkg": "1", + "UMask": "0x41", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Evict RspHitFSE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE", + "PerPkg": "1", + "UMask": "0x81", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Any RspHitFSE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE", + "PerPkg": "1", + "UMask": "0xE1", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; External RspSFwdFE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE", + "PerPkg": "1", + "UMask": "0x22", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdFE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE", + "PerPkg": "1", + "UMask": "0x42", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdFE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE", + "PerPkg": "1", + "UMask": "0x82", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdFE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE", + "PerPkg": "1", + "UMask": "0xE2", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; External RspIFwdFE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdFE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdFE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE", + "PerPkg": "1", + "UMask": "0x84", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Any RspIFwdFE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE", + "PerPkg": "1", + "UMask": "0xE4", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; External RspSFwdM", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdM", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM", + "PerPkg": "1", + "UMask": "0x48", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdM", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM", + "PerPkg": "1", + "UMask": "0x88", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdM", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM", + "PerPkg": "1", + "UMask": "0xE8", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; External RspIFwdM", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM", + "PerPkg": "1", + "UMask": "0x30", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdM", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM", + "PerPkg": "1", + "UMask": "0x50", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdM", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM", + "PerPkg": "1", + "UMask": "0xF0", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT", + "PerPkg": "1", + "UMask": "0x18", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.RRQ_HIT", + "PerPkg": "1", + "UMask": "0x50", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.RRQ_MISS", + "PerPkg": "1", + "UMask": "0x60", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.WBQ_HIT", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.WBQ_MISS", + "PerPkg": "1", + "UMask": "0xA0", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_HIT", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_MISS", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_HIT", + "PerPkg": "1", + "UMask": "0x18", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_MISS", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; All from Local IO", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO", + "PerPkg": "1", + "UMask": "0x34", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; All from Local iA and IO", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL_IO_IA", + "PerPkg": "1", + "UMask": "0x35", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Hits from Local", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL_HIT", + "PerPkg": "1", + "UMask": "0x15", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Misses from Local", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL_MISS", + "PerPkg": "1", + "UMask": "0x25", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; All from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", + "PerPkg": "1", + "UMask": "0x34", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Hits from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Misses from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Hits from Local", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_HIT", + "PerPkg": "1", + "UMask": "0x17", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Misses from Local", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_MISS", + "PerPkg": "1", + "UMask": "0x27", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; VNA Credits", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VNA", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; VN0 Credits", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; AD REQ Credits", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_REQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; AD RSP VN0 Credits", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; BL RSP Credits", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_RSP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; BL DRS Credits", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; BL NCB Credits", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; BL NCS Credits", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; AD VNA Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL VNA Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_BL", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; AD REQ VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_REQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; AD RSP VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL RSP VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_RSP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL DRS VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCB VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; Non UPI AK Request", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; Non UPI IV Request", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; Non UPI AK Request", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; Non UPI IV Request", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; Non UPI AK Request", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; Non UPI IV Request", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; Non UPI AK Request", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; Non UPI IV Request", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; Non UPI AK Request", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; Non UPI IV Request", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; Non UPI AK Request", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; Non UPI IV Request", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; Non UPI AK Request", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; Non UPI IV Request", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; ANY0", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; All", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Broadcast snoop for Local Requests", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Broadcast snoops for Remote Requests", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Directed snoops for Local Requests", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Directed snoops for Remote Requests", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspI", + "Counter": "0,1,2,3", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspS", + "Counter": "0,1,2,3", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspIFwd", + "Counter": "0,1,2,3", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspSFwd", + "Counter": "0,1,2,3", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; Rsp*WB", + "Counter": "0,1,2,3", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB", + "Counter": "0,1,2,3", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspCnflct", + "Counter": "0,1,2,3", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspFwd", + "Counter": "0,1,2,3", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "EventCode": "0xC0", + "EventName": "UNC_CHA_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Write Requests", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.WRITE", + "PerPkg": "1", + "UMask": "0x05", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; External Snoop Request", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP", + "PerPkg": "1", + "UMask": "0x09", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.ANY", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Local", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Remote", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE", + "PerPkg": "1", + "UMask": "0x91", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.F_STATE", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Local - All Lines", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "PerPkg": "1", + "UMask": "0x2F", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; IRQ", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IRQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; SF/LLC Evictions", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.EVICT", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; PRQ", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PRQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; IPQ", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IPQ", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Hit (Not a Miss)", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.HIT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Miss", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", + "PerPkg": "1", + "UMask": "0x37", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; All", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL", + "PerPkg": "1", + "UMask": "0xFF", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IPQ_HIT", + "PerPkg": "1", + "UMask": "0x18", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IPQ_MISS", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.RRQ_HIT", + "PerPkg": "1", + "UMask": "0x50", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS", + "PerPkg": "1", + "UMask": "0x60", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.WBQ_HIT", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.WBQ_MISS", + "PerPkg": "1", + "UMask": "0xA0", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; IRQ", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; SF/LLC Evictions", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; PRQ", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; IPQ", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Hit (Not a Miss)", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Miss", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", + "PerPkg": "1", + "UMask": "0x37", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.ALL", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0xFF", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_HIT", + "PerPkg": "1", + "UMask": "0x18", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_MISS", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "Source Throttle", + "Counter": "0,1,2,3", + "EventCode": "0xA4", + "EventName": "UNC_CHA_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; ANY0", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; ANY0", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; ANY0", + "Counter": "0,1,2,3", + "EventCode": "0x2D", + "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; ANY0", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; ANY0", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; ANY0", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; IV", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; IV", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; IV", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "FaST wire asserted; Vertical", + "Counter": "0,1,2,3", + "EventCode": "0xA5", + "EventName": "UNC_CHA_FAST_ASSERTED.VERT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Local - Lines in M State", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Local - Lines in E State", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", + "PerPkg": "1", + "UMask": "0x22", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Local - Lines in S State", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Local - Lines in F State", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Remote - Lines in M State", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M", + "PerPkg": "1", + "UMask": "0x81", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Remote - Lines in E State", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E", + "PerPkg": "1", + "UMask": "0x82", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Remote - Lines in S State", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S", + "PerPkg": "1", + "UMask": "0x84", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Remote - Lines in F State", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_F", + "PerPkg": "1", + "UMask": "0x88", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Remote - All Lines", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "PerPkg": "1", + "UMask": "0x8F", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; All from Local", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC", + "PerPkg": "1", + "UMask": "0x37", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; RdCur misses from Local IO", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RDCUR", + "Filter": "config1=0x43C33", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; RFO misses from Local IO", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "Filter": "config1=0x40033", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; ItoM misses from Local IO", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Filter": "config1=0x49033", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; ITOM Misses from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", + "Filter": "config1=0x49033", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RDCUR isses from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RDCUR", + "Filter": "config1=0x43C33", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RFO misses from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", + "Filter": "config1=0x40033", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in IODC", + "Counter": "0,1,2,3", + "EventCode": "0x64", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.IODC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in SF/LLC", + "Counter": "0,1,2,3", + "EventCode": "0x64", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in SF/LLC", + "Counter": "0,1,2,3", + "EventCode": "0x64", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in TOR", + "Counter": "0,1,2,3", + "EventCode": "0x64", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Memory mode related events; Counts the number of times CHA saw NM Set conflict in TOR and the transaction was rejected", + "Counter": "0,1,2,3", + "EventCode": "0x64", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR_REJECT", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts; Port 0", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts; Port 1", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts; Port 2", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts; Port 3", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Num Link Correctable Errors", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "UNC_IIO_LINK_NUM_CORR_ERR", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Num Link Retries", + "Counter": "0,1,2,3", + "EventCode": "0xE", + "EventName": "UNC_IIO_LINK_NUM_RETRIES", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number packets that passed the Mask/Match Filter", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_IIO_MASK_MATCH", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus; PCIE bus", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and PCIE bus", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; PCIE bus", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and PCIE bus", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and !(PCIE bus)", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "UNC_IIO_NOTHING", + "Counter": "0,1,2,3", + "EventName": "UNC_IIO_NOTHING", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Symbol Times on Link", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_IIO_SYMBOL_TIMES", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; Vtd hit", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.L4_PAGE_HIT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; context cache miss", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.CTXT_MISS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; L1 miss", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.L1_MISS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; L2 miss", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.L2_MISS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; L3 miss", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.L3_MISS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; TLB miss", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.TLB_MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; TLB is full", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.TLB_FULL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; TLB miss", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.TLB1_MISS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_IIO_VTD_OCCUPANCY", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card reading from DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card reading from DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card writing to DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card writing to DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Total Write Cache Occupancy; Any Source", + "Counter": "0,1", + "EventCode": "0xF", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Total Write Cache Occupancy; Snoops", + "Counter": "0,1", + "EventCode": "0xF", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "IRP Clocks", + "Counter": "0,1", + "EventCode": "0x1", + "EventName": "UNC_I_CLOCKTICKS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; PCIRdCur", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; CRd", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.CRD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; DRd", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.DRD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; PCIDCAHin5t", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; WbMtoI", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.WBMTOI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; CLFlush", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF RF full", + "Counter": "0,1", + "EventCode": "0x17", + "EventName": "UNC_I_FAF_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF allocation -- sent to ADQ", + "Counter": "0,1", + "EventCode": "0x16", + "EventName": "UNC_I_FAF_TRANSACTIONS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "All Inserts Inbound (p2p + faf + cset)", + "Counter": "0,1", + "EventCode": "0x1E", + "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "All Inserts Outbound (BL, AK, Snoops)", + "Counter": "0,1", + "EventCode": "0x1E", + "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Fastpath Requests", + "Counter": "0,1", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.FAST_REQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Fastpath Rejects", + "Counter": "0,1", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.FAST_REJ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary", + "Counter": "0,1", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.2ND_RD_INSERT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary", + "Counter": "0,1", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.2ND_WR_INSERT", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary", + "Counter": "0,1", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary", + "Counter": "0,1", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.FAST_XFER", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary", + "Counter": "0,1", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.PF_ACK_HINT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0", + "Counter": "0,1", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.UNKNOWN", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line", + "Counter": "0,1", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SLOW_I", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line", + "Counter": "0,1", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SLOW_S", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line", + "Counter": "0,1", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SLOW_E", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line", + "Counter": "0,1", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SLOW_M", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Lost Forward", + "Counter": "0,1", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.LOST_FWD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Received Invalid", + "Counter": "0,1", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Received Valid", + "Counter": "0,1", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Requests", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_I_P2P_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Occupancy", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_P2P_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; P2P reads", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.RD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; P2P Writes", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.WR", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; P2P Message", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.MSG", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; P2P completions", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; Match if remote only", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.REM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; match if remote and target matches", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; match if local only", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.LOC", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; match if local and target matches", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Miss", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.MISS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Hit I", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_I", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Hit E or S", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_ES", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Hit M", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_M", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; SnpCode", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPCODE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; SnpData", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPDATA", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; SnpInv", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPINV", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Reads", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.READS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Writes", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.WRITES", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Read Prefetches", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.RD_PREF", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Atomic", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.ATOMIC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Other", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.OTHER", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "No AD Egress Credit Stalls", + "Counter": "0,1", + "EventCode": "0x1A", + "EventName": "UNC_I_TxR2_AD_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "AK Egress Allocations", + "Counter": "0,1", + "EventCode": "0xB", + "EventName": "UNC_I_TxC_AK_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Cycles Full", + "Counter": "0,1", + "EventCode": "0x5", + "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Inserts", + "Counter": "0,1", + "EventCode": "0x2", + "EventName": "UNC_I_TxC_BL_DRS_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Occupancy", + "Counter": "0,1", + "EventCode": "0x8", + "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Cycles Full", + "Counter": "0,1", + "EventCode": "0x6", + "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Inserts", + "Counter": "0,1", + "EventCode": "0x3", + "EventName": "UNC_I_TxC_BL_NCB_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Occupancy", + "Counter": "0,1", + "EventCode": "0x9", + "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Cycles Full", + "Counter": "0,1", + "EventCode": "0x7", + "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Inserts", + "Counter": "0,1", + "EventCode": "0x4", + "EventName": "UNC_I_TxC_BL_NCS_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Occupancy", + "Counter": "0,1", + "EventCode": "0xA", + "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "No BL Egress Credit Stalls", + "Counter": "0,1", + "EventCode": "0x1B", + "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", + "EventCode": "0xD", + "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", + "EventCode": "0xE", + "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Request Queue Occupancy", + "Counter": "0,1", + "EventCode": "0xC", + "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", + "PerPkg": "1", + "UMask": "0x72", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", + "PerPkg": "1", + "UMask": "0x74", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", + "PerPkg": "1", + "UMask": "0x78", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", + "PerPkg": "1", + "UMask": "0x7e", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that miss the IIO cache", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", + "PerPkg": "1", + "UMask": "0x71", + "Unit": "IRP" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_UPI_PHY_INIT_CYCLES", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "L1 Req Nack", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_UPI_POWER_L1_NACK", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "L1 Req (same as L1 Ack)", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_UPI_POWER_L1_REQ", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "Counter": "0,1,2,3", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "Counter": "0,1,2,3", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "Counter": "0,1,2,3", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "Counter": "0,1,2,3", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Cycles in L0. Receive side", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_UPI_RxL0_POWER_CYCLES", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "VN0 Credit Consumed", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "VN1 Credit Consumed", + "Counter": "0,1,2,3", + "EventCode": "0x3A", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "VNA Credit Consumed", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received; Slot 0", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.SLOT0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received; Slot 1", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.SLOT1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received; Slot 2", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.SLOT2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received; Data", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.DATA", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received; LLCRD Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.LLCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received; LLCTRL", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.LLCTRL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.PROTHDR", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.PROT_HDR", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.REQ", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.SNP", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.RSP", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.WB", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.WB", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.NCB", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.NCS", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "UPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets; Slot 0", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets; Slot 1", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets; Slot 2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Cycles in L0. Transmit side", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_UPI_TxL0_POWER_CYCLES", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent; Slot 0", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.SLOT0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent; Slot 1", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.SLOT1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent; Slot 2", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.SLOT2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent; LLCRD Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.LLCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent; LLCTRL", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.LLCTRL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.PROTHDR", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.PROT_HDR", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.REQ", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.SNP", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.WB", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.WB", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.NCB", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.NCS", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Tx Flit Buffer Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_UPI_TxL_INSERTS", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Tx Flit Buffer Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x42", + "EventName": "UNC_UPI_TxL_OCCUPANCY", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "Counter": "0,1,2,3", + "EventCode": "0x45", + "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "VNA Credits Pending Return - Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x44", + "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received; Protocol Header", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.PROTHDR", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent; Protocol Header", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.PROTHDR", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.LOC", + "PerPkg": "1", + "UMaskExt": "0x02", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.REM", + "PerPkg": "1", + "UMaskExt": "0x04", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.DATA_HDR", + "PerPkg": "1", + "UMaskExt": "0x08", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.NON_DATA_HDR", + "PerPkg": "1", + "UMaskExt": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.DUAL_SLOT_HDR", + "PerPkg": "1", + "UMaskExt": "0x20", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.SGL_SLOT_HDR", + "PerPkg": "1", + "UMaskExt": "0x40", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_NODATA", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_DATA", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received; Idle", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.IDLE", + "PerPkg": "1", + "UMask": "0x47", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Request", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Request Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC", + "PerPkg": "1", + "UMask": "0x0108", + "UMaskExt": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Snoop", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", + "PerPkg": "1", + "UMask": "0x09", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Snoop Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC", + "PerPkg": "1", + "UMask": "0x0109", + "UMaskExt": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA", + "PerPkg": "1", + "UMask": "0x0A", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "PerPkg": "1", + "UMask": "0x010A", + "UMaskExt": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", + "PerPkg": "1", + "UMask": "0x0C", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "PerPkg": "1", + "UMask": "0x010C", + "UMaskExt": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Writeback", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB", + "PerPkg": "1", + "UMask": "0x0D", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Writeback", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC", + "PerPkg": "1", + "UMask": "0x010D", + "UMaskExt": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", + "PerPkg": "1", + "UMask": "0x0E", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC", + "PerPkg": "1", + "UMask": "0x010E", + "UMaskExt": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", + "PerPkg": "1", + "UMask": "0x0F", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC", + "PerPkg": "1", + "UMask": "0x010F", + "UMaskExt": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Request", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Request Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC", + "PerPkg": "1", + "UMask": "0x108", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", + "PerPkg": "1", + "UMask": "0x09", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC", + "PerPkg": "1", + "UMask": "0x109", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", + "PerPkg": "1", + "UMask": "0x0A", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "PerPkg": "1", + "UMask": "0x10A", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", + "PerPkg": "1", + "UMask": "0x0C", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "PerPkg": "1", + "UMask": "0x10C", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB", + "PerPkg": "1", + "UMask": "0x0D", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC", + "PerPkg": "1", + "UMask": "0x10D", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", + "PerPkg": "1", + "UMask": "0x0E", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC", + "PerPkg": "1", + "UMask": "0x10E", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", + "PerPkg": "1", + "UMask": "0x0F", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC", + "PerPkg": "1", + "UMask": "0x10F", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - Conflict", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT", + "PerPkg": "1", + "UMask": "0x01AA", + "UMaskExt": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - Invalid", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI", + "PerPkg": "1", + "UMask": "0x012A", + "UMaskExt": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations; Slot 0", + "Counter": "0,1,2,3", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations; Slot 1", + "Counter": "0,1,2,3", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "UPI LL" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations; Slot 2", + "Counter": "0,1,2,3", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Conflict", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT", + "PerPkg": "1", + "UMask": "0x1AA", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Invalid", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI", + "PerPkg": "1", + "UMask": "0x12A", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VNA", + "Counter": "0,1,2", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN0 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN0 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN0 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN1 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN1 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN1 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty; VN1 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty; VN1 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty; VN1 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN0", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN0", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN1", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN1", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty; VNA Messages", + "Counter": "0,1,2", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty; Writebacks", + "Counter": "0,1,2", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty; Requests", + "Counter": "0,1,2", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty; Snoops", + "Counter": "0,1,2", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of uclks in domain", + "Counter": "0,1,2", + "EventCode": "0x1", + "EventName": "UNC_M3UPI_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "D2U Sent", + "Counter": "0,1,2", + "EventCode": "0x2A", + "EventName": "UNC_M3UPI_D2U_SENT", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)", + "Counter": "0,1,2", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO0_IIO1_NCB", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; IIO2", + "Counter": "0,1,2", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; IIO3", + "Counter": "0,1,2", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; IIO4", + "Counter": "0,1,2", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; IIO5", + "Counter": "0,1,2", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; All IIO targets for NCS are in single mask. ORs them together", + "Counter": "0,1,2", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; Selected M2p BL NCS credits", + "Counter": "0,1,2", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; AD - Slot 0", + "Counter": "0,1,2", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; AD - Slot 1", + "Counter": "0,1,2", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; AD - Slot 2", + "Counter": "0,1,2", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; BL - Slot 0", + "Counter": "0,1,2", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; AK - Slot 0", + "Counter": "0,1,2", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; AK - Slot 2", + "Counter": "0,1,2", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN0 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN0 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN0 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN1 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN1 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN1 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN1 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN0 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN0 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN0 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN1 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN1 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN1 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN1 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN0 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN0 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN0 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN1 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN1 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN1 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN0 REQ Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN0 SNP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN0 RSP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN0 WB Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN1 REQ Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN1 SNP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN1 RSP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_WB", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN0 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN0 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN1 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN1 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN1 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_WB", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN0 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN0 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN0 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN1 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN1 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN1 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN1 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_WB", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AK Flow Q Inserts", + "Counter": "0,1,2", + "EventCode": "0x2F", + "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AK Flow Q Occupancy", + "EventCode": "0x1E", + "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN0 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN0 NCB Messages", + "Counter": "0,1,2", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN0 NCS Messages", + "Counter": "0,1,2", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN1 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN1 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN1 NCS Messages", + "Counter": "0,1,2", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN1 NCB Messages", + "Counter": "0,1,2", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN0 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN0 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN0 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN1 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN1 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN1 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN1 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN0 NCS Messages", + "Counter": "0,1,2", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN0 NCB Messages", + "Counter": "0,1,2", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN0 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN1_NCB Messages", + "Counter": "0,1,2", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN1_NCS Messages", + "Counter": "0,1,2", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN1 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN1 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN0 RSP Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN0 WB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN0 NCB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN0 NCS Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN1 RSP Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN1 WB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN1_NCS Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN1_NCB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_WB", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN0 NCS Messages", + "Counter": "0,1,2", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN1 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN1 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN1 NCB Messages", + "Counter": "0,1,2", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_WB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCB Messages", + "Counter": "0,1,2", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCS Messages", + "Counter": "0,1,2", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCS Messages", + "Counter": "0,1,2", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCB Messages", + "Counter": "0,1,2", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; CHA on VN0", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_CHA", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; CHA on VN1", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_CHA", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN0", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_NON_IDLE", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN1", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_NON_IDLE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Snoop Arbitration; FlowQ Won", + "Counter": "0,1,2", + "EventCode": "0x3D", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_NONSNP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Snoop Arbitration; FlowQ Won", + "Counter": "0,1,2", + "EventCode": "0x3D", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_NONSNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", + "Counter": "0,1,2", + "EventCode": "0x3D", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_VN2SNP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", + "Counter": "0,1,2", + "EventCode": "0x3D", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_VN0SNP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0", + "Counter": "0,1,2", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1", + "Counter": "0,1,2", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2", + "Counter": "0,1,2", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3", + "Counter": "0,1,2", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4", + "Counter": "0,1,2", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5", + "Counter": "0,1,2", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0", + "Counter": "0,1,2", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1", + "Counter": "0,1,2", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2", + "Counter": "0,1,2", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3", + "Counter": "0,1,2", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4", + "Counter": "0,1,2", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5", + "Counter": "0,1,2", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0", + "Counter": "0,1,2", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1", + "Counter": "0,1,2", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2", + "Counter": "0,1,2", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3", + "Counter": "0,1,2", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4", + "Counter": "0,1,2", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5", + "Counter": "0,1,2", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0", + "Counter": "0,1,2", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1", + "Counter": "0,1,2", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2", + "Counter": "0,1,2", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3", + "Counter": "0,1,2", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4", + "Counter": "0,1,2", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5", + "Counter": "0,1,2", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0", + "Counter": "0,1,2", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1", + "Counter": "0,1,2", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2", + "Counter": "0,1,2", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3", + "Counter": "0,1,2", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4", + "Counter": "0,1,2", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5", + "Counter": "0,1,2", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0", + "Counter": "0,1,2", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1", + "Counter": "0,1,2", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2", + "Counter": "0,1,2", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3", + "Counter": "0,1,2", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4", + "Counter": "0,1,2", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5", + "Counter": "0,1,2", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0", + "Counter": "0,1,2", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1", + "Counter": "0,1,2", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2", + "Counter": "0,1,2", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3", + "Counter": "0,1,2", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4", + "Counter": "0,1,2", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5", + "Counter": "0,1,2", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2", + "EventCode": "0xC0", + "EventName": "UNC_M3UPI_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Up", + "Counter": "0,1,2", + "EventCode": "0xAE", + "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Down", + "Counter": "0,1,2", + "EventCode": "0xAE", + "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Even", + "Counter": "0,1,2", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", + "Counter": "0,1,2", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Even", + "Counter": "0,1,2", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", + "Counter": "0,1,2", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Even", + "Counter": "0,1,2", + "EventCode": "0xA9", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", + "Counter": "0,1,2", + "EventCode": "0xA9", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Even", + "Counter": "0,1,2", + "EventCode": "0xA9", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", + "Counter": "0,1,2", + "EventCode": "0xA9", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Even", + "Counter": "0,1,2", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", + "Counter": "0,1,2", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Even", + "Counter": "0,1,2", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", + "Counter": "0,1,2", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Left", + "Counter": "0,1,2", + "EventCode": "0xAD", + "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Right", + "Counter": "0,1,2", + "EventCode": "0xAD", + "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD", + "Counter": "0,1,2", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK", + "Counter": "0,1,2", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL", + "Counter": "0,1,2", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV", + "Counter": "0,1,2", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; AD", + "Counter": "0,1,2", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core", + "Counter": "0,1,2", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core", + "Counter": "0,1,2", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache", + "Counter": "0,1,2", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AD", + "Counter": "0,1,2", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AK", + "Counter": "0,1,2", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; BL", + "Counter": "0,1,2", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; IV", + "Counter": "0,1,2", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1", + "Counter": "0,1,2", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; AD", + "Counter": "0,1,2", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core", + "Counter": "0,1,2", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core", + "Counter": "0,1,2", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache", + "Counter": "0,1,2", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Source Throttle", + "Counter": "0,1,2", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN0", + "Counter": "0,1,2", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN1", + "Counter": "0,1,2", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN0", + "Counter": "0,1,2", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN1", + "Counter": "0,1,2", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN0", + "Counter": "0,1,2", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN1", + "Counter": "0,1,2", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; AD, BL Parallel Win", + "Counter": "0,1,2", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on Idle", + "Counter": "0,1,2", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on BL Arb", + "Counter": "0,1,2", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 1", + "Counter": "0,1,2", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 2", + "Counter": "0,1,2", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events; Any In BGF FIFO", + "Counter": "0,1,2", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events; Any in BGF Path", + "Counter": "0,1,2", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events; No D2K For Arb", + "Counter": "0,1,2", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.NO_D2K_FOR_ARB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy; VNA In Use", + "Counter": "0,1,2", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy; Packets in BGF FIFO", + "Counter": "0,1,2", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy; Packets in BGF Path", + "Counter": "0,1,2", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy; Transmit Credits", + "Counter": "0,1,2", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy; D2K Credits", + "Counter": "0,1,2", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy", + "Counter": "0,1,2", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy", + "Counter": "0,1,2", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent; All", + "Counter": "0,1,2", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent; No BGF Credits", + "Counter": "0,1,2", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_BGF", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent; No TxQ Credits", + "Counter": "0,1,2", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_TXQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 0", + "Counter": "0,1,2", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 1", + "Counter": "0,1,2", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC", + "Counter": "0,1,2", + "EventCode": "0x5A", + "EventName": "UNC_M3UPI_RxC_FLITS_MISC", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit; One Message", + "Counter": "0,1,2", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit; Two Messages", + "Counter": "0,1,2", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.2_MSGS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit; Three Messages", + "Counter": "0,1,2", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.3_MSGS", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit; One Message in non-VNA", + "Counter": "0,1,2", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG_VNX", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; All", + "Counter": "0,1,2", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Needs Data Flit", + "Counter": "0,1,2", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 0", + "Counter": "0,1,2", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 1", + "Counter": "0,1,2", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1", + "Counter": "0,1,2", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Bubble", + "Counter": "0,1,2", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Not Avail", + "Counter": "0,1,2", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Acumullate", + "Counter": "0,1,2", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Accumulate Ready", + "Counter": "0,1,2", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Accumulate Wasted", + "Counter": "0,1,2", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Blocked", + "Counter": "0,1,2", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Message", + "Counter": "0,1,2", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Parallel Ok", + "Counter": "0,1,2", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Parallel Message", + "Counter": "0,1,2", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_MSG", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Parallel Flit Finished", + "Counter": "0,1,2", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_FLIT", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall", + "Counter": "0,1,2", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall - No Message", + "Counter": "0,1,2", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; All", + "Counter": "0,1,2", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; No BGF Credits", + "Counter": "0,1,2", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_CRD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; No TxQ Credits", + "Counter": "0,1,2", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_CRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; No BGF Credits + No Extra Message Slotted", + "Counter": "0,1,2", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_NO_MSG", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; No TxQ Credits + No Extra Message Slotted", + "Counter": "0,1,2", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_NO_MSG", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; Sent - One Slot Taken", + "Counter": "0,1,2", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ONE_TAKEN", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; Sent - Two Slots Taken", + "Counter": "0,1,2", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.TWO_TAKEN", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; Sent - Three Slots Taken", + "Counter": "0,1,2", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.THREE_TAKEN", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; VN0", + "Counter": "0,1,2", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; VN1", + "Counter": "0,1,2", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.VN1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Parallel Attempt", + "Counter": "0,1,2", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Parallel Success", + "Counter": "0,1,2", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Parallel AD Lost", + "Counter": "0,1,2", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_AD_LOST", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Parallel BL Lost", + "Counter": "0,1,2", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_BL_LOST", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Can't Slot AD", + "Counter": "0,1,2", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Can't Slot BL", + "Counter": "0,1,2", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "SMI3 Prefetch Messages; Arrived", + "Counter": "0,1,2", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARRIVED", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "SMI3 Prefetch Messages; Lost Arbitration", + "Counter": "0,1,2", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARB_LOST", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "SMI3 Prefetch Messages; Slotted", + "Counter": "0,1,2", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.SLOTTED", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "SMI3 Prefetch Messages; Dropped - Old", + "Counter": "0,1,2", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_OLD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "SMI3 Prefetch Messages; Dropped - Wrap", + "Counter": "0,1,2", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_WRAP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Used", + "Counter": "0,1,2", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.USED", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Corrected", + "Counter": "0,1,2", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Level < 1", + "Counter": "0,1,2", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Level < 4", + "Counter": "0,1,2", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Level < 5", + "Counter": "0,1,2", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Any In Use", + "Counter": "0,1,2", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; IV - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; IFV - Credit", + "Counter": "0,1,2", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0", + "Counter": "0,1,2", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1", + "Counter": "0,1,2", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2", + "Counter": "0,1,2", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3", + "Counter": "0,1,2", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4", + "Counter": "0,1,2", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5", + "Counter": "0,1,2", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0", + "Counter": "0,1,2", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1", + "Counter": "0,1,2", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2", + "Counter": "0,1,2", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3", + "Counter": "0,1,2", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4", + "Counter": "0,1,2", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5", + "Counter": "0,1,2", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0", + "Counter": "0,1,2", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1", + "Counter": "0,1,2", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2", + "Counter": "0,1,2", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3", + "Counter": "0,1,2", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4", + "Counter": "0,1,2", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5", + "Counter": "0,1,2", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0", + "Counter": "0,1,2", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1", + "Counter": "0,1,2", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2", + "Counter": "0,1,2", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3", + "Counter": "0,1,2", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4", + "Counter": "0,1,2", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5", + "Counter": "0,1,2", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", + "Counter": "0,1,2", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce", + "Counter": "0,1,2", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce", + "Counter": "0,1,2", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", + "Counter": "0,1,2", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", + "Counter": "0,1,2", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", + "Counter": "0,1,2", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce", + "Counter": "0,1,2", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; IV", + "Counter": "0,1,2", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", + "Counter": "0,1,2", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV", + "Counter": "0,1,2", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG0", "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", "UMask": "0x04", - "Unit": "IIO" + "Unit": "M3UPI" }, { - "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", - "FCMask": "0x07", + "BriefDescription": "CMS Vert Egress Allocations; IV", + "Counter": "0,1,2", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.IV", "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x08", + "Unit": "M3UPI" }, { - "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG1", "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG1", "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x20", + "Unit": "M3UPI" }, { - "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG1", "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG0", "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", "UMask": "0x01", - "Unit": "IIO" + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", - "FCMask": "0x07", + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG0", "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x08", - "Unit": "IIO" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", - "FCMask": "0x07", + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG0", "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x08", - "Unit": "IIO" + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", - "FCMask": "0x07", + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG1", "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x08", - "Unit": "IIO" + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", - "FCMask": "0x07", + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG1", "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x08", - "Unit": "IIO" + "UMask": "0x20", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG1", "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG0", "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part1 to the MMIO space of an IIO target.In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG0", "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", "UMask": "0x02", - "Unit": "IIO" + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG0", "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "Total IRP occupancy of inbound read and write requests.", - "Counter": "0,1", - "EventCode": "0xF", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "BriefDescription": "CMS Vert Egress Occupancy; IV", + "Counter": "0,1,2", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.IV", "PerPkg": "1", - "PublicDescription": "Total IRP occupancy of inbound read and write requests. This is effectively the sum of read occupancy and write occupancy.", - "UMask": "0x4", - "Unit": "IRP" + "UMask": "0x08", + "Unit": "M3UPI" }, { - "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.", - "Counter": "0,1", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.PCITOM", + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG1", "PerPkg": "1", - "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.", "UMask": "0x10", - "Unit": "IRP" + "Unit": "M3UPI" }, { - "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.", - "Counter": "0,1", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.RFO", + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG1", "PerPkg": "1", - "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.", - "UMask": "0x8", - "Unit": "IRP" + "UMask": "0x20", + "Unit": "M3UPI" }, { - "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.", - "Counter": "0,1", - "EventCode": "0x18", - "EventName": "UNC_I_FAF_INSERTS", + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG1", "PerPkg": "1", - "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.", - "Unit": "IRP" + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "Occupancy of the IRP FAF queue.", - "Counter": "0,1", - "EventCode": "0x19", - "EventName": "UNC_I_FAF_OCCUPANCY", + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG0", "PerPkg": "1", - "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.", - "Unit": "IRP" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "Inbound write (fast path) requests received by the IRP.", - "Counter": "0,1", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG0", "PerPkg": "1", - "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", - "UMask": "0x8", - "Unit": "IRP" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "Traffic in which the M2M to iMC Bypass was not taken", - "Counter": "0,1,2,3", - "EventCode": "0x22", - "EventName": "UNC_M2M_BYPASS_M2M_Egress.NOT_TAKEN", + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG0", "PerPkg": "1", - "PublicDescription": "Counts traffic in which the M2M (Mesh to Memory) to iMC (Memory Controller) bypass was not taken", - "UMask": "0x2", - "Unit": "M2M" + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG1", "PerPkg": "1", - "PublicDescription": "Counts cycles when direct to core mode (which bypasses the CHA) was disabled", - "Unit": "M2M" + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "Messages sent direct to core (bypassing the CHA)", - "Counter": "0,1,2,3", - "EventCode": "0x23", - "EventName": "UNC_M2M_DIRECT2CORE_TAKEN", + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG1", "PerPkg": "1", - "PublicDescription": "Counts when messages were sent direct to core (bypassing the CHA)", - "Unit": "M2M" + "UMask": "0x20", + "Unit": "M3UPI" }, { - "BriefDescription": "Number of reads in which direct to core transaction were overridden", - "Counter": "0,1,2,3", - "EventCode": "0x25", - "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG1", "PerPkg": "1", - "PublicDescription": "Counts reads in which direct to core transactions (which would have bypassed the CHA) were overridden", - "Unit": "M2M" + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden", - "Counter": "0,1,2,3", - "EventCode": "0x28", - "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", + "BriefDescription": "Vertical AD Ring In Use; Up and Even", + "Counter": "0,1,2", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN", "PerPkg": "1", - "PublicDescription": "Counts reads in which direct to Intel Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overridden", - "Unit": "M2M" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "Cycles when direct to Intel UPI was disabled", - "Counter": "0,1,2,3", - "EventCode": "0x27", - "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", + "BriefDescription": "Vertical AD Ring In Use; Up and Odd", + "Counter": "0,1,2", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD", "PerPkg": "1", - "PublicDescription": "Counts cycles when the ability to send messages direct to the Intel Ultra Path Interconnect (bypassing the CHA) was disabled", - "Unit": "M2M" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "Messages sent direct to the Intel UPI", - "Counter": "0,1,2,3", - "EventCode": "0x26", - "EventName": "UNC_M2M_DIRECT2UPI_TAKEN", + "BriefDescription": "Vertical AD Ring In Use; Down and Even", + "Counter": "0,1,2", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN", "PerPkg": "1", - "PublicDescription": "Counts when messages were sent direct to the Intel Ultra Path Interconnect (bypassing the CHA)", - "Unit": "M2M" + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Down and Odd", + "Counter": "0,1,2", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" }, { - "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden", - "Counter": "0,1,2,3", - "EventCode": "0x29", - "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", + "BriefDescription": "Vertical AK Ring In Use; Up and Even", + "Counter": "0,1,2", + "EventCode": "0xA8", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN", "PerPkg": "1", - "PublicDescription": "Counts when a read message that was sent direct to the Intel Ultra Path Interconnect (bypassing the CHA) was overridden", - "Unit": "M2M" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)", - "Counter": "0,1,2,3", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", + "BriefDescription": "Vertical AK Ring In Use; Up and Odd", + "Counter": "0,1,2", + "EventCode": "0xA8", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in Any State (A, I, S or unused)", - "UMask": "0x1", - "Unit": "M2M" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)", - "Counter": "0,1,2,3", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", + "BriefDescription": "Vertical AK Ring In Use; Down and Even", + "Counter": "0,1,2", + "EventCode": "0xA8", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in the A (SnoopAll) state, indicating the cacheline is stored in another socket in any state, and we must snoop the other sockets to make sure we get the latest data. The data may be stored in any state in the local socket.", - "UMask": "0x8", - "Unit": "M2M" + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)", - "Counter": "0,1,2,3", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", + "BriefDescription": "Vertical AK Ring In Use; Down and Odd", + "Counter": "0,1,2", + "EventCode": "0xA8", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the I (Invalid) state indicating the cacheline is not stored in another socket, and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket.", - "UMask": "0x2", - "Unit": "M2M" + "UMask": "0x08", + "Unit": "M3UPI" }, { - "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)", - "Counter": "0,1,2,3", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", + "BriefDescription": "Vertical BL Ring in Use; Up and Even", + "Counter": "0,1,2", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the S (Shared) state indicating the cacheline is either stored in another socket in the S(hared) state , and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket.", - "UMask": "0x4", - "Unit": "M2M" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "Multi-socket cacheline Directory update from A to I", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I", + "BriefDescription": "Vertical BL Ring in Use; Up and Odd", + "Counter": "0,1,2", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from A (SnoopAll) to I (Invalid)", - "UMask": "0x20", - "Unit": "M2M" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "Multi-socket cacheline Directory update from A to S", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S", + "BriefDescription": "Vertical BL Ring in Use; Down and Even", + "Counter": "0,1,2", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from A (SnoopAll) to S (Shared)", - "UMask": "0x40", - "Unit": "M2M" + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "Multi-socket cacheline Directory update from/to Any state", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", + "BriefDescription": "Vertical BL Ring in Use; Down and Odd", + "Counter": "0,1,2", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory to a new state", - "UMask": "0x1", - "Unit": "M2M" + "UMask": "0x08", + "Unit": "M3UPI" }, { - "BriefDescription": "Multi-socket cacheline Directory update from I to A", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A", + "BriefDescription": "Vertical IV Ring in Use; Up", + "Counter": "0,1,2", + "EventCode": "0xAC", + "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from I (Invalid) to A (SnoopAll)", - "UMask": "0x4", - "Unit": "M2M" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "Multi-socket cacheline Directory update from I to S", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S", + "BriefDescription": "Vertical IV Ring in Use; Down", + "Counter": "0,1,2", + "EventCode": "0xAC", + "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from I (Invalid) to S (Shared)", - "UMask": "0x2", - "Unit": "M2M" + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "Multi-socket cacheline Directory update from S to A", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A", + "BriefDescription": "D2C Sent", + "Counter": "0,1,2", + "EventCode": "0x2B", + "EventName": "UNC_M3UPI_D2C_SENT", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from S (Shared) to A (SnoopAll)", - "UMask": "0x10", - "Unit": "M2M" + "Unit": "M3UPI" }, { - "BriefDescription": "Multi-socket cacheline Directory update from S to I", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I", + "BriefDescription": "FaST wire asserted; Vertical", + "Counter": "0,1,2", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_FAST_ASSERTED.VERT", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from S (Shared) to I (Invalid)", - "UMask": "0x8", - "Unit": "M2M" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "Reads to iMC issued", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.ALL", + "BriefDescription": "FaST wire asserted; Horizontal", + "Counter": "0,1,2", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_FAST_ASSERTED.HORZ", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller).", - "UMask": "0x4", - "Unit": "M2M" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "Reads to iMC issued at Normal Priority (Non-Isochronous)", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.NORMAL", + "BriefDescription": "Sent Header Flit", + "Counter": "0,1,2", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_1", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller). It only counts normal priority non-isochronous reads.", - "UMask": "0x1", - "Unit": "M2M" + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "Read requests to Intel Optane DC persistent memory issued to the iMC from M2M", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.TO_PMM", + "BriefDescription": "Sent Header Flit", + "Counter": "0,1,2", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_2", "PerPkg": "1", - "PublicDescription": "M2M Reads Issued to iMC; All, regardless of priority.", - "UMask": "0x8", - "Unit": "M2M" + "UMask": "0x20", + "Unit": "M3UPI" }, { - "BriefDescription": "Writes to iMC issued", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.ALL", + "BriefDescription": "Sent Header Flit", + "Counter": "0,1,2", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_3", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) issues writes to the iMC (Memory Controller).", - "UMask": "0x10", - "Unit": "M2M" + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority.", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.NI", + "BriefDescription": "CMS Vertical Egress NACKs; IV", + "Counter": "0,1,2", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.IV", "PerPkg": "1", - "PublicDescription": "M2M Writes Issued to iMC; All, regardless of priority.", - "UMask": "0x80", - "Unit": "M2M" + "UMask": "0x08", + "Unit": "M3UPI" }, { - "BriefDescription": "Partial Non-Isochronous writes to the iMC", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", + "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", + "Counter": "0,1,2", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.IV", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) issues partial writes to the iMC (Memory Controller). It only counts normal priority non-isochronous writes.", - "UMask": "0x2", - "Unit": "M2M" + "UMask": "0x08", + "Unit": "M3UPI" }, { - "BriefDescription": "Write requests to Intel Optane DC persistent memory issued to the iMC from M2M", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.TO_PMM", + "BriefDescription": "UPI0 BL Credits Empty; VNA", + "Counter": "0,1,2", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA", "PerPkg": "1", - "PublicDescription": "M2M Writes Issued to iMC; All, regardless of priority.", - "UMask": "0x20", - "Unit": "M2M" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "Prefecth requests that got turn into a demand request", - "Counter": "0,1,2,3", - "EventCode": "0x56", - "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS", + "BriefDescription": "UPI0 BL Credits Empty; VN0 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address. Explanatory Side Note: The Prefecth queue is made of CAM (Content Addressable Memory)", - "Unit": "M2M" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "Inserts into the Memory Controller Prefetch Queue", - "Counter": "0,1,2,3", - "EventCode": "0x57", - "EventName": "UNC_M2M_PREFCAM_INSERTS", + "BriefDescription": "UPI0 BL Credits Empty; VN0 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) recieves a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory", - "Unit": "M2M" + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "AD Ingress (from CMS) Queue Inserts", - "Counter": "0,1,2,3", - "EventCode": "0x1", - "EventName": "UNC_M2M_RxC_AD_INSERTS", + "BriefDescription": "UPI0 BL Credits Empty; VN0 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB", "PerPkg": "1", - "PublicDescription": "Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop). This is generally used for reads, and", - "Unit": "M2M" + "UMask": "0x08", + "Unit": "M3UPI" }, { - "BriefDescription": "AD Ingress (from CMS) Occupancy", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", + "BriefDescription": "Message Received; VLW", + "Counter": "0,1", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", "PerPkg": "1", - "PublicDescription": "AD Ingress (from CMS) Occupancy", - "Unit": "M2M" + "UMask": "0x1", + "Unit": "UBOX" }, { - "BriefDescription": "BL Ingress (from CMS) Allocations", - "Counter": "0,1,2,3", - "EventCode": "0x5", - "EventName": "UNC_M2M_RxC_BL_INSERTS", + "BriefDescription": "Message Received; MSI", + "Counter": "0,1", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", "PerPkg": "1", - "PublicDescription": "BL Ingress (from CMS) Allocations", - "Unit": "M2M" + "UMask": "0x2", + "Unit": "UBOX" }, { - "BriefDescription": "BL Ingress (from CMS) Occupancy", - "Counter": "0,1,2,3", - "EventCode": "0x6", - "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", + "BriefDescription": "Message Received; IPI", + "Counter": "0,1", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", "PerPkg": "1", - "PublicDescription": "BL Ingress (from CMS) Occupancy", - "Unit": "M2M" + "UMask": "0x4", + "Unit": "UBOX" }, { - "BriefDescription": "Dirty line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode", - "Counter": "0,1,2,3", - "EventCode": "0x2C", - "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY", + "BriefDescription": "Message Received", + "Counter": "0,1", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", "PerPkg": "1", - "PublicDescription": "Tag Hit; Read Hit from NearMem, Dirty Line", - "UMask": "0x02", - "Unit": "M2M" + "UMask": "0x8", + "Unit": "UBOX" }, { - "BriefDescription": "Clean line underfill read hits to Near Memory(DRAM cache) in Memory Mode", - "Counter": "0,1,2,3", - "EventCode": "0x2C", - "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN", + "BriefDescription": "Message Received", + "Counter": "0,1", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.INT_PRIO", "PerPkg": "1", - "PublicDescription": "Tag Hit; Underfill Rd Hit from NearMem, Clean Line", - "UMask": "0x04", - "Unit": "M2M" + "UMask": "0x10", + "Unit": "UBOX" }, { - "BriefDescription": "Dirty line underfill read hits to Near Memory(DRAM cache) in Memory Mode", - "Counter": "0,1,2,3", - "EventCode": "0x2C", - "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY", + "BriefDescription": "IDI Lock/SplitLock Cycles", + "Counter": "0,1", + "EventCode": "0x44", + "EventName": "UNC_U_LOCK_CYCLES", "PerPkg": "1", - "PublicDescription": "Tag Hit; Underfill Rd Hit from NearMem, Dirty Line", - "UMask": "0x08", - "Unit": "M2M" + "Unit": "UBOX" }, { - "BriefDescription": "AD Egress (to CMS) Allocations", - "Counter": "0,1,2,3", - "EventCode": "0x9", - "EventName": "UNC_M2M_TxC_AD_INSERTS", + "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", + "Counter": "0,1", + "EventCode": "0x45", + "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", + "Counter": "0,1", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.RDRAND", "PerPkg": "1", - "PublicDescription": "AD Egress (to CMS) Allocations", - "Unit": "M2M" + "UMask": "0x1", + "Unit": "UBOX" }, { - "BriefDescription": "AD Egress (to CMS) Occupancy", - "Counter": "0,1,2,3", - "EventCode": "0xA", - "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", + "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", + "Counter": "0,1", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.RDSEED", "PerPkg": "1", - "PublicDescription": "AD Egress (to CMS) Occupancy", - "Unit": "M2M" + "UMask": "0x2", + "Unit": "UBOX" }, { - "BriefDescription": "BL Egress (to CMS) Allocations; All", - "Counter": "0,1,2,3", - "EventCode": "0x15", - "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", + "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "Counter": "0,1", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", "PerPkg": "1", - "PublicDescription": "BL Egress (to CMS) Allocations; All", - "UMask": "0x03", - "Unit": "M2M" + "UMask": "0x4", + "Unit": "UBOX" }, { - "BriefDescription": "BL Egress (to CMS) Occupancy; All", - "Counter": "0,1,2,3", - "EventCode": "0x16", - "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.ALL", + "BriefDescription": "RACU Request", + "Counter": "0,1", + "EventCode": "0x46", + "EventName": "UNC_U_RACU_REQUESTS", "PerPkg": "1", - "PublicDescription": "BL Egress (to CMS) Occupancy; All", - "UMask": "0x03", - "Unit": "M2M" + "Unit": "UBOX" }, { - "BriefDescription": "Prefetches generated by the flow control queue of the M3UPI unit.", - "Counter": "0,1,2", - "EventCode": "0x29", - "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", + "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", + "Counter": "FIXED", + "EventCode": "0xff", + "EventName": "UNC_U_CLOCKTICKS", "PerPkg": "1", - "PublicDescription": "Count cases where flow control queue that sits between the Intel Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller)", - "Unit": "M3UPI" + "Unit": "UBOX" }, { - "BriefDescription": "Clocks of the Intel Ultra Path Interconnect (UPI)", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE", "Counter": "0,1,2,3", - "EventCode": "0x1", - "EventName": "UNC_UPI_CLOCKTICKS", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.CORE_GTONE", "PerPkg": "1", - "PublicDescription": "Counts clockticks of the fixed frequency clock controlling the Intel Ultra Path Interconnect (UPI). This clock runs at1/8th the 'GT/s' speed of the UPI link. For example, a 9.6GT/s link will have a fixed Frequency of 1.2 Ghz.", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE", + "UMask": "0x42", + "Unit": "CHA" }, { - "BriefDescription": "Data Response packets that go direct to core", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE", "Counter": "0,1,2,3", - "EventCode": "0x12", - "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.EVICT_GTONE", "PerPkg": "1", - "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to core bypassing the CHA.", - "UMask": "0x1", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE", + "UMask": "0x82", + "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_DIRECT_ATTEMPTS.D2U", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP", "Counter": "0,1,2,3", "Deprecated": "1", - "EventCode": "0x12", - "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K", + "EventCode": "0x53", + "EventName": "UNC_H_DIR_LOOKUP.NO_SNP", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_UPI_DIRECT_ATTEMPTS.D2U", + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP", "UMask": "0x2", - "Unit": "UPI LL" + "Unit": "CHA" }, { - "BriefDescription": "Data Response packets that go direct to Intel UPI", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP", "Counter": "0,1,2,3", - "EventCode": "0x12", - "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U", + "Deprecated": "1", + "EventCode": "0x53", + "EventName": "UNC_H_DIR_LOOKUP.SNP", "PerPkg": "1", - "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to Intel Ultra Path Interconnect (UPI) bypassing the CHA .", - "UMask": "0x2", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Cycles Intel UPI is in L1 power mode (shutdown)", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA", "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_UPI_L1_POWER_CYCLES", + "Deprecated": "1", + "EventCode": "0x54", + "EventName": "UNC_H_DIR_UPDATE.HA", "PerPkg": "1", - "PublicDescription": "Counts cycles when the Intel Ultra Path Interconnect (UPI) is in L1 power mode. L1 is a mode that totally shuts down the UPI link. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdown.", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Cycles the Rx of the Intel UPI is in L0p power mode", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR", "Counter": "0,1,2,3", - "EventCode": "0x25", - "EventName": "UNC_UPI_RxL0P_POWER_CYCLES", + "Deprecated": "1", + "EventCode": "0x54", + "EventName": "UNC_H_DIR_UPDATE.TOR", "PerPkg": "1", - "PublicDescription": "Counts cycles when the the receive side (Rx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR", + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS", "Counter": "0,1,2,3", - "EventCode": "0x31", - "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", + "Deprecated": "1", + "EventCode": "0x5F", + "EventName": "UNC_H_HITME_HIT.EX_RDS", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS", "UMask": "0x1", - "Unit": "UPI LL" + "Unit": "CHA" }, { - "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S", "Counter": "0,1,2,3", - "EventCode": "0x31", - "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", + "Deprecated": "1", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.RFO_HIT_S", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", - "UMask": "0x2", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S", + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "FLITs received which bypassed the Slot0 Recieve Buffer", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL", "Counter": "0,1,2,3", - "EventCode": "0x31", - "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) whcih bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", - "UMask": "0x4", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL", + "UMask": "0x10", + "Unit": "CHA" }, { - "BriefDescription": "Valid data FLITs received from any slot", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE", "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE", "PerPkg": "1", - "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.", - "UMask": "0x0F", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE", + "UMask": "0x20", + "Unit": "CHA" }, { - "BriefDescription": "Null FLITs received from any slot", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS", "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.READS", "PerPkg": "1", - "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.", - "UMask": "0x27", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS", + "UMask": "0x3", + "Unit": "CHA" }, { - "BriefDescription": "Protocol header and credit FLITs received from any slot", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS_LOCAL", "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.READS_LOCAL", "PerPkg": "1", - "PublicDescription": "Counts protocol header and credit FLITs (80 bit FLow control unITs) received from any of the 3 UPI slots on this UPI unit.", - "UMask": "0x97", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS_LOCAL", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.ALL_NULL", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES", "Counter": "0,1,2,3", "Deprecated": "1", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.NULL", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.WRITES", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.ALL_NULL", - "UMask": "0x20", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES", + "UMask": "0xC", + "Unit": "CHA" }, { - "BriefDescription": "Cycles in which the Tx of the Intel Ultra Path Interconnect (UPI) is in L0p power mode", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES_LOCAL", "Counter": "0,1,2,3", - "EventCode": "0x27", - "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", "PerPkg": "1", - "PublicDescription": "Counts cycles when the transmit side (Tx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES_LOCAL", + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "FLITs that bypassed the TxL Buffer", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ", "Counter": "0,1,2,3", - "EventCode": "0x41", - "EventName": "UNC_UPI_TxL_BYPASSED", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.IRQ", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link. However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR mode, increasing latency to transfer out to the link.", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Null FLITs transmitted from any slot", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.PA_MATCH", "PerPkg": "1", - "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel Ulra Path Interconnect (UPI) slots on this UPI unit.", - "UMask": "0x27", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "UMask": "0x80", + "Unit": "CHA" }, { - "BriefDescription": "Valid Flits Sent; Data", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.DATA", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ", + "Deprecated": "1", + "EventCode": "0x11", + "EventName": "UNC_H_RxC_OCCUPANCY.IRQ", "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..", - "UMask": "0x8", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Idle FLITs transmitted", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD", "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.IDLE", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPIFWD", "PerPkg": "1", - "PublicDescription": "Counts when the Intel Ultra Path Interconnect(UPI) transmits an idle FLIT(80 bit FLow control unITs). Every UPI cycle must be sending either data FLITs, protocol/credit FLITs or idle FLITs.", - "UMask": "0x47", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD", + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Protocol header and credit FLITs transmitted across any slot", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD", "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", "PerPkg": "1", - "PublicDescription": "Counts protocol header and credit FLITs (80 bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Interconnect) slots on this UPI unit.", - "UMask": "0x97", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD", + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_NULL", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB", "Counter": "0,1,2,3", "Deprecated": "1", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.NULL", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_NULL", + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB", "UMask": "0x20", - "Unit": "UPI LL" + "Unit": "CHA" } ] diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json new file mode 100644 index 000000000000..64301a600ede --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json @@ -0,0 +1,201 @@ +[ + { + "BriefDescription": "pclk Cycles", + "Counter": "0,1,2,3", + "EventName": "UNC_P_CLOCKTICKS", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_P_CORE_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "UNC_P_DEMOTIONS", + "Counter": "0,1,2,3", + "EventCode": "0x30", + "EventName": "UNC_P_DEMOTIONS", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Phase Shed 0 Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x75", + "EventName": "UNC_P_FIVR_PS_PS0_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Phase Shed 1 Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x76", + "EventName": "UNC_P_FIVR_PS_PS1_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Phase Shed 2 Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x77", + "EventName": "UNC_P_FIVR_PS_PS2_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Phase Shed 3 Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x78", + "EventName": "UNC_P_FIVR_PS_PS3_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Thermal Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Power Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Cycles spent changing Frequency", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "UNC_P_FREQ_TRANS_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "UNC_P_MCP_PROCHOT_CYCLES", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_P_MCP_PROCHOT_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Memory Phase Shedding Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C0", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C2E", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C3", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C6", + "Counter": "0,1,2,3", + "EventCode": "0x2D", + "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_P_PMAX_THROTTLED_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Number of cores in C-State; C0 and C1", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Number of cores in C-State; C3", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Number of cores in C-State; C6 and C7", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "External Prochot", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Internal Prochot", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Total Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "VR Hot", + "Counter": "0,1,2,3", + "EventCode": "0x42", + "EventName": "UNC_P_VR_HOT_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + } +] -- cgit v1.2.3 From 575c3640a4aa475c8620a9120b6df340731fc9a0 Mon Sep 17 00:00:00 2001 From: Zhengjun Xing Date: Fri, 12 Aug 2022 16:52:32 +0800 Subject: perf vendor events: Update events and metrics for haswellx Update the events to v25, the metrics are based on TMA 4.4 full, update events and metrics for haswellx by the latest event converter tools. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py to download and generate the latest events and metrics. Manually copy the haswellx files into perf. Signed-off-by: Xing Zhengjun Tested-by: Ian Rogers Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20220812085239.3089231-5-zhengjun.xing@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/haswellx/hsx-metrics.json | 411 ++++++++++++++++++++- .../pmu-events/arch/x86/haswellx/uncore-cache.json | 173 +-------- 2 files changed, 413 insertions(+), 171 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json b/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json index 5c9e008ca995..d31d76db9d84 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json @@ -74,12 +74,6 @@ "MetricGroup": "Branches;Fed;FetchBW", "MetricName": "UpTB" }, - { - "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", - "MetricGroup": "Pipeline;Mem", - "MetricName": "CPI" - }, { "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", @@ -327,6 +321,12 @@ "MetricGroup": "SoC", "MetricName": "Socket_CLKS" }, + { + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "cbox_0@event\\=0x0@ / #num_dies / duration_time / 1000000000", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" + }, { "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", @@ -374,5 +374,404 @@ "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C7_Pkg_Residency" + }, + { + "BriefDescription": "CPU operating frequency (in GHz)", + "MetricExpr": "( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ ) / 1000000000", + "MetricGroup": "", + "MetricName": "cpu_operating_frequency", + "ScaleUnit": "1GHz" + }, + { + "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.", + "MetricExpr": " CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY ", + "MetricGroup": "", + "MetricName": "cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions", + "MetricExpr": " MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY ", + "MetricGroup": "", + "MetricName": "loads_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions", + "MetricExpr": " MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY ", + "MetricGroup": "", + "MetricName": "stores_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions", + "MetricExpr": " L1D.REPLACEMENT / INST_RETIRED.ANY ", + "MetricGroup": "", + "MetricName": "l1d_mpi_includes_data_plus_rfo_with_prefetches", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions", + "MetricExpr": " MEM_LOAD_UOPS_RETIRED.L1_HIT / INST_RETIRED.ANY ", + "MetricGroup": "", + "MetricName": "l1d_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions", + "MetricExpr": " L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY ", + "MetricGroup": "", + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions", + "MetricExpr": " MEM_LOAD_UOPS_RETIRED.L2_HIT / INST_RETIRED.ANY ", + "MetricGroup": "", + "MetricName": "l2_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions", + "MetricExpr": " L2_LINES_IN.ALL / INST_RETIRED.ANY ", + "MetricGroup": "", + "MetricName": "l2_mpi_includes_code_plus_data_plus_rfo_with_prefetches", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions", + "MetricExpr": " MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY ", + "MetricGroup": "", + "MetricName": "l2_demand_data_read_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions", + "MetricExpr": " L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY ", + "MetricGroup": "", + "MetricName": "l2_demand_code_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.", + "MetricExpr": " ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY ", + "MetricGroup": "", + "MetricName": "itlb_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.", + "MetricExpr": " ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY ", + "MetricGroup": "", + "MetricName": "itlb_large_page_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "MetricExpr": " DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY ", + "MetricGroup": "", + "MetricName": "dtlb_load_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "MetricExpr": " DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY ", + "MetricGroup": "", + "MetricName": "dtlb_store_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Intel(R) Quick Path Interconnect (QPI) data transmit bandwidth (MB/sec)", + "MetricExpr": "( UNC_Q_TxL_FLITS_G0.DATA * 8 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "qpi_data_transmit_bw_only_data", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory read bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory write bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory bandwidth (MB/sec)", + "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "memory_bandwidth_total", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", + "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x19e@ * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "io_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x1c8\\,filter_tid\\=0x3e@ * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "io_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "100 * ( IDQ.DSB_UOPS / UOPS_ISSUED.ANY )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_frodecoded_icache_dsb", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "100 * ( IDQ.MITE_UOPS / UOPS_ISSUED.ANY )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_frolegacy_decode_pipeline_mite", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "100 * ( IDQ.MS_UOPS / UOPS_ISSUED.ANY )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_fromicrocode_sequencer_ms", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Uops delivered from loop stream detector(LSD) as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "100 * ( UOPS_ISSUED.ANY - IDQ.MITE_UOPS - IDQ.MS_UOPS - IDQ.DSB_UOPS ) / UOPS_ISSUED.ANY ", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_froloop_streadetector_lsd", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x192@ ) / INST_RETIRED.ANY ", + "MetricGroup": "", + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x181@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x191@ ) / INST_RETIRED.ANY ", + "MetricGroup": "", + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "MetricExpr": "100 * cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ / ( cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ )", + "MetricGroup": "", + "MetricName": "numa_percent_reads_addressed_to_local_dram", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "MetricExpr": "100 * cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ / ( cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ )", + "MetricGroup": "", + "MetricName": "numa_percent_reads_addressed_to_remote_dram", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", + "MetricExpr": "100 * ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "TmaL1, PGO", + "MetricName": "tma_frontend_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", + "MetricExpr": "100 * ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "Frontend, TmaL2", + "MetricName": "tma_fetch_latency_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", + "MetricExpr": "100 * ( ICACHE.IFDATA_STALL / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "BigFoot, FetchLat, IcMiss", + "MetricName": "tma_icache_misses_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.", + "MetricExpr": "100 * ( ( 14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "BigFoot, FetchLat, MemoryTLB", + "MetricName": "tma_itlb_misses_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.", + "MetricExpr": "100 * ( ( 12 ) * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "FetchLat", + "MetricName": "tma_branch_resteers_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "MetricExpr": "100 * ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "DSBmiss, FetchLat", + "MetricName": "tma_dsb_switches_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", + "MetricExpr": "100 * ( ILD_STALL.LCP / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "FetchLat", + "MetricName": "tma_lcp_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", + "MetricExpr": "100 * ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "FetchLat, MicroSeq", + "MetricName": "tma_ms_switches_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", + "MetricExpr": "100 * ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "FetchBW, Frontend, TmaL2", + "MetricName": "tma_fetch_bandwidth_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "MetricExpr": "100 * ( ( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricGroup": "DSBmiss, FetchBW", + "MetricName": "tma_mite_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "MetricExpr": "100 * ( ( IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricGroup": "DSB, FetchBW", + "MetricName": "tma_dsb_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "MetricExpr": "100 * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "TmaL1", + "MetricName": "tma_bad_speculation_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", + "MetricExpr": "100 * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "BadSpec, BrMispredicts, TmaL2", + "MetricName": "tma_branch_mispredicts_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", + "MetricExpr": "100 * ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", + "MetricGroup": "BadSpec, MachineClears, TmaL2", + "MetricName": "tma_machine_clears_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", + "MetricExpr": "100 * ( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", + "MetricGroup": "TmaL1", + "MetricName": "tma_backend_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "MetricExpr": "100 * ( ( ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.STALLS_LDM_PENDING ) ) + RESOURCE_STALLS.SB ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE ) ) + ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) ) / 2 - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) if #SMT_on else ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE ) ) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) ) ) * ( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) )", + "MetricGroup": "Backend, TmaL2", + "MetricName": "tma_memory_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.", + "MetricExpr": "100 * ( max( ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.STALLS_LDM_PENDING ) ) - CYCLE_ACTIVITY.STALLS_L1D_PENDING ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) )", + "MetricGroup": "CacheMisses, MemoryBound, TmaL3mem", + "MetricName": "tma_l1_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.", + "MetricExpr": "100 * ( ( CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "CacheMisses, MemoryBound, TmaL3mem", + "MetricName": "tma_l2_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.", + "MetricExpr": "100 * ( ( MEM_LOAD_UOPS_RETIRED.L3_HIT / ( MEM_LOAD_UOPS_RETIRED.L3_HIT + ( 7 ) * MEM_LOAD_UOPS_RETIRED.L3_MISS ) ) * CYCLE_ACTIVITY.STALLS_L2_PENDING / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "CacheMisses, MemoryBound, TmaL3mem", + "MetricName": "tma_l3_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.", + "MetricExpr": "100 * ( min( ( ( 1 - ( MEM_LOAD_UOPS_RETIRED.L3_HIT / ( MEM_LOAD_UOPS_RETIRED.L3_HIT + ( 7 ) * MEM_LOAD_UOPS_RETIRED.L3_MISS ) ) ) * CYCLE_ACTIVITY.STALLS_L2_PENDING / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricGroup": "MemoryBound, TmaL3mem", + "MetricName": "tma_drabound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.", + "MetricExpr": "100 * ( RESOURCE_STALLS.SB / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "MemoryBound, TmaL3mem", + "MetricName": "tma_store_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "MetricExpr": "100 * ( ( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) - ( ( ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.STALLS_LDM_PENDING ) ) + RESOURCE_STALLS.SB ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE ) ) + ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) ) / 2 - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) if #SMT_on else ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE ) ) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) ) ) * ( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) )", + "MetricGroup": "Backend, TmaL2, Compute", + "MetricName": "tma_core_bound_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.", + "MetricExpr": "100 * ( 10 * ARITH.DIVIDER_UOPS / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "", + "MetricName": "tma_divider_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "MetricExpr": "100 * ( ( ( ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE ) ) + ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) ) / 2 - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) if #SMT_on else ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE ) ) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) ) - RESOURCE_STALLS.SB - ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.STALLS_LDM_PENDING ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "PortsUtil", + "MetricName": "tma_ports_utilization_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ", + "MetricExpr": "100 * ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "TmaL1", + "MetricName": "tma_retiring_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.", + "MetricExpr": "100 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", + "MetricGroup": "Retire, TmaL2", + "MetricName": "tma_light_operations_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.", + "MetricExpr": "100 * ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Retire, TmaL2", + "MetricName": "tma_heavy_operations_percent", + "ScaleUnit": "1%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", + "MetricExpr": "100 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "MicroSeq", + "MetricName": "tma_microcode_sequencer_percent", + "ScaleUnit": "1%" } ] diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json b/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json index 03598904d746..56047f9c6f20 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json @@ -964,20 +964,19 @@ "Unit": "CBO" }, { - "BriefDescription": "PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode", + "BriefDescription": "TOR Inserts; Opcode Match", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE", - "Filter": "filter_opc=0x180,filter_tid=0x3e", + "EventName": "UNC_C_TOR_INSERTS.OPCODE", "PerPkg": "1", "UMask": "0x1", "Unit": "CBO" }, { - "BriefDescription": "PCIe writes (partial cache line)", + "BriefDescription": "PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.OPCODE", + "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE", "Filter": "filter_opc=0x180,filter_tid=0x3e", "PerPkg": "1", "UMask": "0x1", @@ -994,17 +993,6 @@ "UMask": "0x1", "Unit": "CBO" }, - { - "BriefDescription": "L2 demand and L2 prefetch code references to LLC", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.OPCODE", - "Filter": "filter_opc=0x181", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", - "Unit": "CBO" - }, { "BriefDescription": "Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode", "Counter": "0,1,2,3", @@ -1016,17 +1004,6 @@ "UMask": "0x1", "Unit": "CBO" }, - { - "BriefDescription": "Streaming stores (full cache line)", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.OPCODE", - "Filter": "filter_opc=0x18c", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", - "Unit": "CBO" - }, { "BriefDescription": "Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode", "Counter": "0,1,2,3", @@ -1038,17 +1015,6 @@ "UMask": "0x1", "Unit": "CBO" }, - { - "BriefDescription": "Streaming stores (partial cache line)", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.OPCODE", - "Filter": "filter_opc=0x18d", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", - "Unit": "CBO" - }, { "BriefDescription": "PCIe read current. Derived from unc_c_tor_inserts.opcode", "Counter": "0,1,2,3", @@ -1060,17 +1026,6 @@ "UMask": "0x1", "Unit": "CBO" }, - { - "BriefDescription": "PCIe read current", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.OPCODE", - "Filter": "filter_opc=0x19e", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", - "Unit": "CBO" - }, { "BriefDescription": "PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode", "Counter": "0,1,2,3", @@ -1082,17 +1037,6 @@ "UMask": "0x1", "Unit": "CBO" }, - { - "BriefDescription": "PCIe write references (full cache line)", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.OPCODE", - "Filter": "filter_opc=0x1c8,filter_tid=0x3e", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x1", - "Unit": "CBO" - }, { "BriefDescription": "TOR Inserts; Evictions", "Counter": "0,1,2,3", @@ -1121,21 +1065,19 @@ "Unit": "CBO" }, { - "BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode", + "BriefDescription": "TOR Inserts; Miss Opcode Match", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "LLC_MISSES.DATA_READ", - "Filter": "filter_opc=0x182", + "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", "PerPkg": "1", - "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" }, { - "BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches", + "BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", + "EventName": "LLC_MISSES.DATA_READ", "Filter": "filter_opc=0x182", "PerPkg": "1", "ScaleUnit": "64Bytes", @@ -1153,17 +1095,6 @@ "UMask": "0x3", "Unit": "CBO" }, - { - "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", - "Filter": "filter_opc=0x187", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", - "Unit": "CBO" - }, { "BriefDescription": "MMIO reads. Derived from unc_c_tor_inserts.miss_opcode", "Counter": "0,1,2,3", @@ -1175,17 +1106,6 @@ "UMask": "0x3", "Unit": "CBO" }, - { - "BriefDescription": "MMIO reads", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", - "Filter": "filter_opc=0x187,filter_nc=1", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", - "Unit": "CBO" - }, { "BriefDescription": "MMIO writes. Derived from unc_c_tor_inserts.miss_opcode", "Counter": "0,1,2,3", @@ -1197,17 +1117,6 @@ "UMask": "0x3", "Unit": "CBO" }, - { - "BriefDescription": "MMIO writes", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", - "Filter": "filter_opc=0x18f,filter_nc=1", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", - "Unit": "CBO" - }, { "BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode", "Counter": "0,1,2,3", @@ -1219,17 +1128,6 @@ "UMask": "0x3", "Unit": "CBO" }, - { - "BriefDescription": "LLC prefetch misses for RFO", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", - "Filter": "filter_opc=0x190", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", - "Unit": "CBO" - }, { "BriefDescription": "LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode", "Counter": "0,1,2,3", @@ -1241,17 +1139,6 @@ "UMask": "0x3", "Unit": "CBO" }, - { - "BriefDescription": "LLC prefetch misses for code reads", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", - "Filter": "filter_opc=0x191", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", - "Unit": "CBO" - }, { "BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode", "Counter": "0,1,2,3", @@ -1263,17 +1150,6 @@ "UMask": "0x3", "Unit": "CBO" }, - { - "BriefDescription": "LLC prefetch misses for data reads", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", - "Filter": "filter_opc=0x192", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", - "Unit": "CBO" - }, { "BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode", "Counter": "0,1,2,3", @@ -1285,17 +1161,6 @@ "UMask": "0x3", "Unit": "CBO" }, - { - "BriefDescription": "LLC misses for PCIe read current", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", - "Filter": "filter_opc=0x19e", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", - "Unit": "CBO" - }, { "BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode", "Counter": "0,1,2,3", @@ -1307,17 +1172,6 @@ "UMask": "0x3", "Unit": "CBO" }, - { - "BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", - "Filter": "filter_opc=0x1c8", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", - "Unit": "CBO" - }, { "BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode", "Counter": "0,1,2,3", @@ -1329,17 +1183,6 @@ "UMask": "0x3", "Unit": "CBO" }, - { - "BriefDescription": "PCIe write misses (full cache line)", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", - "Filter": "filter_opc=0x1c8,filter_tid=0x3e", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x3", - "Unit": "CBO" - }, { "BriefDescription": "TOR Inserts; NID and Opcode Matched", "Counter": "0,1,2,3", -- cgit v1.2.3 From b8d4fbfb04e1041905d8c0afaa545508eba9cb40 Mon Sep 17 00:00:00 2001 From: Zhengjun Xing Date: Fri, 12 Aug 2022 16:52:33 +0800 Subject: perf vendor events: Update events and metrics for icelakex Update the events to v1.15, the metrics are based on TMA 4.4 full, update events and metrics for icelakex by the latest event converter tools. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py to download and generate the latest events and metrics. Manually copy the icelakex files into perf. Signed-off-by: Xing Zhengjun Tested-by: Ian Rogers Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20220812085239.3089231-6-zhengjun.xing@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/icelakex/icx-metrics.json | 6 + .../arch/x86/icelakex/uncore-memory.json | 1523 + .../pmu-events/arch/x86/icelakex/uncore-other.json | 38506 ++++++++++++++++++- .../pmu-events/arch/x86/icelakex/uncore-power.json | 225 + 4 files changed, 39018 insertions(+), 1242 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json index 0abdfe433a2c..e905458b34b8 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json @@ -486,6 +486,12 @@ "MetricGroup": "SoC", "MetricName": "Socket_CLKS" }, + { + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "cha_0@event\\=0x0@ / #num_dies / duration_time / 1000000000", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" + }, { "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json index 5f0d2c462940..6872ae4b29d9 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json @@ -329,5 +329,1528 @@ "PerPkg": "1", "UMask": "0x01", "Unit": "iMC" + }, + { + "BriefDescription": "Read Data Buffer Inserts", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x17", + "EventName": "UNC_M_RDB_INSERTS", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses : Scoreboard Accesses Accepted", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M_SB_ACCESSES.ACCEPTS", + "PerPkg": "1", + "UMask": "0x05", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses : Scoreboard Accesses Rejected", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M_SB_ACCESSES.REJECTS", + "PerPkg": "1", + "UMask": "0x0A", + "Unit": "iMC" + }, + { + "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_M_CAS_COUNT.RD_REG", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM underfill read CAS commands issued", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Activate Count : Activate due to Bypass", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x01", + "EventName": "UNC_M_ACT_COUNT.BYP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_M_CAS_COUNT.WR_PRE", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x47", + "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x47", + "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x47", + "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x47", + "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_M_RPQ_CYCLES_NE.PCH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_M_RPQ_CYCLES_NE.PCH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses : Read Accepts", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M_SB_ACCESSES.RD_ACCEPTS", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses : Read Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M_SB_ACCESSES.RD_REJECTS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses : NM read completions", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M_SB_ACCESSES.WR_ACCEPTS", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses : NM write completions", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M_SB_ACCESSES.WR_REJECTS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses : FM read completions", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M_SB_ACCESSES.NM_RD_CMPS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses : FM write completions", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M_SB_ACCESSES.NM_WR_CMPS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses : Write Accepts", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M_SB_ACCESSES.FM_RD_CMPS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses : Write Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M_SB_ACCESSES.FM_WR_CMPS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": ": Alloc", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD9", + "EventName": "UNC_M_SB_CANARY.ALLOC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": ": Dealloc", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD9", + "EventName": "UNC_M_SB_CANARY.DEALLOC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": ": Reject", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD9", + "EventName": "UNC_M_SB_CANARY.VLD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.NM_RD_STARVED", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xd9", + "EventName": "UNC_M_SB_CANARY.NMRD_STARVED", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.NM_WR_STARVED", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xd9", + "EventName": "UNC_M_SB_CANARY.NMWR_STARVED", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_RD_STARVED", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xd9", + "EventName": "UNC_M_SB_CANARY.FMRD_STARVED", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_WR_STARVED", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xd9", + "EventName": "UNC_M_SB_CANARY.FMWR_STARVED", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_TGR_WR_STARVED", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xd9", + "EventName": "UNC_M_SB_CANARY.FMTGRWR_STARVED", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Inserts : Reads", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_M_SB_INSERTS.RDS", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Inserts : Writes", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_M_SB_INSERTS.WRS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Inserts : Block region reads", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_M_SB_INSERTS.BLOCK_RDS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Inserts : Block region writes", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_M_SB_INSERTS.BLOCK_WRS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Occupancy : Reads", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD5", + "EventName": "UNC_M_SB_OCCUPANCY.RDS", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Occupancy : Block region reads", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD5", + "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_RDS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Occupancy : Block region writes", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD5", + "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_WRS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of Scoreboard Requests Rejected : NM requests rejected due to set conflict", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_M_SB_REJECT.NM_SET_CNFLT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of Scoreboard Requests Rejected : FM requests rejected due to full address conflict", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_M_SB_REJECT.FM_ADDR_CNFLT", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of Scoreboard Requests Rejected : Patrol requests rejected due to set conflict", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_M_SB_REJECT.PATROL_SET_CNFLT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of Scoreboard Requests Rejected", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_M_SB_REJECT.CANARY", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_RD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xd7", + "EventName": "UNC_M_SB_STRV_ALLOC.NMRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_RD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xd7", + "EventName": "UNC_M_SB_STRV_ALLOC.FMRD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_WR", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xd7", + "EventName": "UNC_M_SB_STRV_ALLOC.NMWR", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_WR", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xd7", + "EventName": "UNC_M_SB_STRV_ALLOC.FMWR", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_TGR", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xd7", + "EventName": "UNC_M_SB_STRV_ALLOC.FMTGR", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_RD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xde", + "EventName": "UNC_M_SB_STRV_DEALLOC.NMRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_RD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xde", + "EventName": "UNC_M_SB_STRV_DEALLOC.FMRD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_WR", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xde", + "EventName": "UNC_M_SB_STRV_DEALLOC.NMWR", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_WR", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xde", + "EventName": "UNC_M_SB_STRV_DEALLOC.FMWR", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_TGR", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xde", + "EventName": "UNC_M_SB_STRV_DEALLOC.FMTGR", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_RD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xd8", + "EventName": "UNC_M_SB_STRV_OCC.NMRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_RD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xd8", + "EventName": "UNC_M_SB_STRV_OCC.FMRD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_WR", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xd8", + "EventName": "UNC_M_SB_STRV_OCC.NMWR", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_WR", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xd8", + "EventName": "UNC_M_SB_STRV_OCC.FMWR", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_TGR", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xd8", + "EventName": "UNC_M_SB_STRV_OCC.FMTGR", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_SB_TAGGED.NEW", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xDD", + "EventName": "UNC_M_SB_TAGGED.NEW", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_SB_TAGGED.RD_HIT", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xDD", + "EventName": "UNC_M_SB_TAGGED.RD_HIT", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_SB_TAGGED.RD_MISS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xDD", + "EventName": "UNC_M_SB_TAGGED.RD_MISS", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_SB_TAGGED.DDR4_CMP", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xDD", + "EventName": "UNC_M_SB_TAGGED.DDR4_CMP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_SB_TAGGED.OCC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xDD", + "EventName": "UNC_M_SB_TAGGED.OCC", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x21", + "EventName": "UNC_M_WPQ_CYCLES_NE.PCH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x21", + "EventName": "UNC_M_WPQ_CYCLES_NE.PCH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_M_WPQ_READ_HIT.PCH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_M_WPQ_READ_HIT.PCH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x24", + "EventName": "UNC_M_WPQ_WRITE_HIT.PCH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x24", + "EventName": "UNC_M_WPQ_WRITE_HIT.PCH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_PCLS.RD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_M_PCLS.RD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_PCLS.WR", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_M_PCLS.WR", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_PCLS.TOTAL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_M_PCLS.TOTAL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Prefetch Inserts : All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xDA", + "EventName": "UNC_M_SB_PREF_INSERTS.ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Prefetch Occupancy : All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xDB", + "EventName": "UNC_M_SB_PREF_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of Scoreboard Requests Rejected", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_M_SB_REJECT.DDR_EARLY_CMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge All Commands", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x44", + "EventName": "UNC_M_DRAM_PRE_ALL", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_PARITY_ERRORS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2c", + "EventName": "UNC_M_PARITY_ERRORS", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Channel PPD Cycles", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x85", + "EventName": "UNC_M_POWER_CHANNEL_PPD", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Clock-Enabled Self-Refresh", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x43", + "EventName": "UNC_M_POWER_SELF_REFRESH", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Data Buffer Full", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_M_RDB_FULL", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Data Buffer Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_M_RDB_NOT_EMPTY", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Data Buffer Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x1A", + "EventName": "UNC_M_RDB_OCCUPANCY", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Full Cycles", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x12", + "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Full Cycles", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x15", + "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Cycles Full", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD1", + "EventName": "UNC_M_SB_CYCLES_FULL", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Cycles Not-Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_M_SB_CYCLES_NE", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Full Cycles", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x22", + "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Full Cycles", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x16", + "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_M_CAS_COUNT.WR_NONPRE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands. : Precharge due to page miss", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", + "PerPkg": "1", + "UMask": "0x0c", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_PREF_OCCUPANCY.PMM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xdb", + "EventName": "UNC_M_SB_PREF_OCCUPANCY.PMEM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xd2", + "EventName": "UNC_M_SB_ACCESSES.NMRD_CMPS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xd2", + "EventName": "UNC_M_SB_ACCESSES.NMWR_CMPS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Commands : RPQ GNTs", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xEA", + "EventName": "UNC_M_PMM_CMD1.RPQ_GNTS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Commands : Underfill GNTs", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xEA", + "EventName": "UNC_M_PMM_CMD1.WPQ_GNTS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Commands : Misc GNTs", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xEA", + "EventName": "UNC_M_PMM_CMD1.MISC_GNT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Commands : Misc Commands (error, flow ACKs)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xEA", + "EventName": "UNC_M_PMM_CMD1.MISC", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Commands - Part 2 : Opportunistic Reads", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xEB", + "EventName": "UNC_M_PMM_CMD2.OPP_RD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Commands - Part 2 : Expected No data packet (ERID matched NDP encoding)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xEB", + "EventName": "UNC_M_PMM_CMD2.NODATA_EXP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Commands - Part 2 : Unexpected No data packet (ERID matched a Read, but data was a NDP)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xEB", + "EventName": "UNC_M_PMM_CMD2.NODATA_UNEXP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Commands - Part 2 : Read Requests - Slot 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xEB", + "EventName": "UNC_M_PMM_CMD2.REQS_SLOT0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Commands - Part 2 : Read Requests - Slot 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xEB", + "EventName": "UNC_M_PMM_CMD2.REQS_SLOT1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Commands - Part 2 : ECC Errors", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xEB", + "EventName": "UNC_M_PMM_CMD2.PMM_ECC_ERROR", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Commands - Part 2 : ERID detectable parity error", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xEB", + "EventName": "UNC_M_PMM_CMD2.PMM_ERID_ERROR", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Commands - Part 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xEB", + "EventName": "UNC_M_PMM_CMD2.PMM_ERID_STARVED", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Read Pending Queue Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Read Pending Queue Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Write Pending Queue Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE4", + "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.CAS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Write Pending Queue Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE4", + "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.PWR", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xd2", + "EventName": "UNC_M_SB_ACCESSES.FMRD_CMPS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0xd2", + "EventName": "UNC_M_SB_ACCESSES.FMWR_CMPS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Inserts : Persistent Mem reads", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_M_SB_INSERTS.PMM_RDS", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Inserts : Persistent Mem writes", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_M_SB_INSERTS.PMM_WRS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Occupancy : Persistent Mem reads", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD5", + "EventName": "UNC_M_SB_OCCUPANCY.PMM_RDS", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Occupancy : Persistent Mem writes", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD5", + "EventName": "UNC_M_SB_OCCUPANCY.PMM_WRS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_SB_TAGGED.PMM0_CMP", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xDD", + "EventName": "UNC_M_SB_TAGGED.PMM0_CMP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_SB_TAGGED.PMM1_CMP", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xDD", + "EventName": "UNC_M_SB_TAGGED.PMM1_CMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_SB_TAGGED.PMM2_CMP", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xDD", + "EventName": "UNC_M_SB_TAGGED.PMM2_CMP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Prefetch Inserts : DDR4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xDA", + "EventName": "UNC_M_SB_PREF_INSERTS.DDR", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Prefetch Inserts : Persistent Mem", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xDA", + "EventName": "UNC_M_SB_PREF_INSERTS.PMM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Prefetch Occupancy : DDR4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xDB", + "EventName": "UNC_M_SB_PREF_OCCUPANCY.DDR", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Read Queue Cycles Full", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_M_PMM_RPQ_CYCLES_FULL", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Read Queue Cycles Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_M_PMM_RPQ_CYCLES_NE", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Write Queue Cycles Full", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE6", + "EventName": "UNC_M_PMM_WPQ_CYCLES_FULL", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Write Queue Cycles Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE5", + "EventName": "UNC_M_PMM_WPQ_CYCLES_NE", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_PMM_WPQ_FLUSH", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe8", + "EventName": "UNC_M_PMM_WPQ_FLUSH", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_PMM_WPQ_FLUSH_CYC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe9", + "EventName": "UNC_M_PMM_WPQ_FLUSH_CYC", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Prefetch Occupancy : Persistent Mem", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xdb", + "EventName": "UNC_M_SB_PREF_OCCUPANCY.PMM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": "Free running counter that increments for the Memory Controller", + "Counter": "4", + "CounterType": "FREERUN", + "EventName": "UNC_M_CLOCKTICKS_FREERUN", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": ": Valid", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD9", + "EventName": "UNC_M_SB_CANARY.NM_RD_STARVED", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "iMC" + }, + { + "BriefDescription": ": Near Mem Read Starved", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD9", + "EventName": "UNC_M_SB_CANARY.NM_WR_STARVED", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": ": Near Mem Write Starved", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD9", + "EventName": "UNC_M_SB_CANARY.FM_RD_STARVED", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": ": Far Mem Read Starved", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD9", + "EventName": "UNC_M_SB_CANARY.FM_WR_STARVED", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": ": Far Mem Write Starved", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD9", + "EventName": "UNC_M_SB_CANARY.FM_TGR_WR_STARVED", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": ": Near Mem Read - Set", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD7", + "EventName": "UNC_M_SB_STRV_ALLOC.NM_RD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": ": Far Mem Read - Set", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD7", + "EventName": "UNC_M_SB_STRV_ALLOC.FM_RD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": ": Near Mem Write - Set", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD7", + "EventName": "UNC_M_SB_STRV_ALLOC.NM_WR", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": ": Far Mem Write - Set", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD7", + "EventName": "UNC_M_SB_STRV_ALLOC.FM_WR", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "iMC" + }, + { + "BriefDescription": ": Near Mem Read - Clear", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD7", + "EventName": "UNC_M_SB_STRV_ALLOC.FM_TGR", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": ": Near Mem Read - Set", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xDE", + "EventName": "UNC_M_SB_STRV_DEALLOC.NM_RD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": ": Far Mem Read - Set", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xDE", + "EventName": "UNC_M_SB_STRV_DEALLOC.FM_RD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": ": Near Mem Write - Set", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xDE", + "EventName": "UNC_M_SB_STRV_DEALLOC.NM_WR", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": ": Far Mem Write - Set", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xDE", + "EventName": "UNC_M_SB_STRV_DEALLOC.FM_WR", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "iMC" + }, + { + "BriefDescription": ": Near Mem Read - Clear", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xDE", + "EventName": "UNC_M_SB_STRV_DEALLOC.FM_TGR", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": ": Near Mem Read", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD8", + "EventName": "UNC_M_SB_STRV_OCC.NM_RD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": ": Far Mem Read", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD8", + "EventName": "UNC_M_SB_STRV_OCC.FM_RD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": ": Near Mem Write", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD8", + "EventName": "UNC_M_SB_STRV_OCC.NM_WR", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": ": Far Mem Write", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD8", + "EventName": "UNC_M_SB_STRV_OCC.FM_WR", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "iMC" + }, + { + "BriefDescription": ": Near Mem Read - Clear", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD8", + "EventName": "UNC_M_SB_STRV_OCC.FM_TGR", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" } ] diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json index 71e052667e50..7783aa2ef5d1 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json @@ -402,2134 +402,38156 @@ "UMaskExt": "0xCC43FE", "Unit": "CHA" }, + { + "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x01", + "EventName": "UNC_IIO_CLOCKTICKS", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Misc Events - Set 1 : Lost Forward", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x1F", + "EventName": "UNC_I_MISC1.LOST_FWD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.PCITOM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops : WbMtoI", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.WBMTOI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in any state", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in A state", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in I state", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in S state", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2e", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Tag Hit : Clean NearMem Read Hit", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2C", + "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Tag Hit : Dirty NearMem Read Hit", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2C", + "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Clockticks of the mesh to memory (M2M)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventName": "UNC_M2M_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number requests PCIe makes of the main die : All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x85", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x0f", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "IRP" + }, + { + "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound write (fast path) requests received by the IRP", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "IRP" + }, + { + "BriefDescription": "Valid Flits Received : All Data", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", + "PerPkg": "1", + "UMask": "0x0F", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received : All Non Data", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", + "PerPkg": "1", + "UMask": "0x97", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent : All Data", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", + "PerPkg": "1", + "UMask": "0x0F", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent : All Non Data", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", + "PerPkg": "1", + "UMask": "0x97", + "Unit": "UPI LL" + }, + { + "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_CHA_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Clockticks of the IO coherency tracker (IRP)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x01", + "EventName": "UNC_I_CLOCKTICKS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF RF full", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x17", + "EventName": "UNC_I_FAF_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_I_FAF_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Occupancy of the IRP FAF queue", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_I_FAF_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF allocation -- sent to ADQ", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x16", + "EventName": "UNC_I_FAF_TRANSACTIONS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_M2M_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Clockticks of the mesh to PCI (M2P)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x01", + "EventName": "UNC_M2P_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_M2P_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Clockticks of the mesh to UPI (M3UPI)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x01", + "EventName": "UNC_M3UPI_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of kfclks", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x01", + "EventName": "UNC_UPI_CLOCKTICKS", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Cycles in L1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x21", + "EventName": "UNC_UPI_L1_POWER_CYCLES", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Cycles in L0p", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x27", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", + "PerPkg": "1", + "UMask": "0xC88FFD01", + "UMaskExt": "0xC88FFD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF", + "PerPkg": "1", + "UMask": "0xC897FD01", + "UMaskExt": "0xC897FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", + "PerPkg": "1", + "UMask": "0xC887FD01", + "UMaskExt": "0xC887FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", + "PerPkg": "1", + "UMask": "0xC88FFE01", + "UMaskExt": "0xC88FFE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", + "PerPkg": "1", + "UMask": "0xC897FE01", + "UMaskExt": "0xC897FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", + "PerPkg": "1", + "UMask": "0xC887FE01", + "UMaskExt": "0xC887FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", + "PerPkg": "1", + "UMask": "0xCC43FD04", + "UMaskExt": "0xCC43FD", + "Unit": "CHA" + }, + { + "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", + "Counter": "FIXED", + "CounterType": "FIXED", + "EventCode": "0xff", + "EventName": "UNC_U_CLOCKTICKS", + "PerPkg": "1", + "Unit": "UBOX" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "PerPkg": "1", + "UMask": "0xCC43FF04", + "UMaskExt": "0xCC43FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", + "PerPkg": "1", + "UMask": "0xC887FF01", + "UMaskExt": "0xC887FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", + "PerPkg": "1", + "UMask": "0xC807FF01", + "UMaskExt": "0xC807FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO", + "PerPkg": "1", + "UMask": "0xCCC7FF01", + "UMaskExt": "0xCCC7FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF", + "PerPkg": "1", + "UMask": "0xC897FF01", + "UMaskExt": "0xC897FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRDs issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", + "PerPkg": "1", + "UMask": "0xC80FFF01", + "UMaskExt": "0xC80FFF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", + "PerPkg": "1", + "UMask": "0xC807FF01", + "UMaskExt": "0xC807FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD", + "PerPkg": "1", + "UMask": "0xC817FF01", + "UMaskExt": "0xC817FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", + "PerPkg": "1", + "UMask": "0xC80FFF01", + "UMaskExt": "0xC80FFF", + "Unit": "CHA" + }, + { + "BriefDescription": "Valid Flits Sent : Null FLITs transmitted to any slot", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", + "PerPkg": "1", + "UMask": "0x27", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received : Null FLITs received from any slot", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", + "PerPkg": "1", + "UMask": "0x27", + "Unit": "UPI LL" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL", + "PerPkg": "1", + "UMask": "0xC816FE01", + "UMaskExt": "0xC816FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE", + "PerPkg": "1", + "UMask": "0xC8177E01", + "UMaskExt": "0xC8177E", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "PerPkg": "1", + "UMask": "0xC816FE01", + "UMaskExt": "0xC816FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "PerPkg": "1", + "UMask": "0xC8177E01", + "UMaskExt": "0xC8177E", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; DRd Pref misses from local IA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", + "PerPkg": "1", + "UMask": "0xC896FE01", + "UMaskExt": "0xC896FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; DRd Pref misses from local IA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", + "PerPkg": "1", + "UMask": "0xC8977E01", + "UMaskExt": "0xC8977E", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL", + "PerPkg": "1", + "UMask": "0xC806FE01", + "UMaskExt": "0xC806FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE", + "PerPkg": "1", + "UMask": "0xC8077E01", + "UMaskExt": "0xC8077E", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL", + "PerPkg": "1", + "UMask": "0xC886FE01", + "UMaskExt": "0xC886FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE", + "PerPkg": "1", + "UMask": "0xC8877E01", + "UMaskExt": "0xC8877E", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", + "PerPkg": "1", + "UMask": "0xC8C7FF01", + "UMaskExt": "0xC8C7FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM", + "PerPkg": "1", + "UMask": "0xCC57FF01", + "UMaskExt": "0xCC57FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "PerPkg": "1", + "UMask": "0xCD43FF04", + "UMaskExt": "0xCD43FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", + "PerPkg": "1", + "UMask": "0xCD43FD04", + "UMaskExt": "0xCD43FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "PerPkg": "1", + "UMask": "0xCD43FE04", + "UMaskExt": "0xCD43FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM", + "PerPkg": "1", + "UMask": "0xC8178A01", + "UMaskExt": "0xC8178A", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM", + "PerPkg": "1", + "UMask": "0xC8168A01", + "UMaskExt": "0xC8168A", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM", + "PerPkg": "1", + "UMask": "0xC8170A01", + "UMaskExt": "0xC8170A", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR", + "PerPkg": "1", + "UMask": "0xc867fe01", + "UMaskExt": "0xc867fe", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR", + "PerPkg": "1", + "UMask": "0xc86ffe01", + "UMaskExt": "0xc86ffe", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM", + "PerPkg": "1", + "UMask": "0xC8178A01", + "UMaskExt": "0xC8178A", + "Unit": "CHA" + }, + { + "BriefDescription": "Free running counter that increments for IIO clocktick", + "CounterType": "FREERUN", + "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : PMM - All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.TO_PMM", + "PerPkg": "1", + "UMask": "0x0720", + "UMaskExt": "0x07", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : PMM - All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.TO_PMM", + "PerPkg": "1", + "UMask": "0x1C80", + "UMaskExt": "0x1C", + "Unit": "M2M" + }, + { + "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "PerPkg": "1", + "UMask": "0xCCD7FE01", + "UMaskExt": "0xCCD7FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "PerPkg": "1", + "UMask": "0xC8F3FE04", + "UMaskExt": "0xC8F3FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", + "PerPkg": "1", + "UMask": "0xc8f3fe04", + "UMaskExt": "0xc8f3fe", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "PerPkg": "1", + "UMask": "0xC8178601", + "UMaskExt": "0xC81786", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR", + "PerPkg": "1", + "UMask": "0xC8168601", + "UMaskExt": "0xC81686", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR", + "PerPkg": "1", + "UMask": "0xC8170601", + "UMaskExt": "0xC81706", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", + "PerPkg": "1", + "UMask": "0xC8178601", + "UMaskExt": "0xC81786", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", + "PerPkg": "1", + "UMask": "0xC8F3FD04", + "UMaskExt": "0xC8F3FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "PerPkg": "1", + "UMask": "0xC8F3FF04", + "UMaskExt": "0xC8F3FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA", + "PerPkg": "1", + "UMask": "0xCCD7FF01", + "UMaskExt": "0xCCD7FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", + "PerPkg": "1", + "UMask": "0xC8F3FF04", + "UMaskExt": "0xC8F3FF", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", + "PerPkg": "1", + "UMask": "0x1BC1FF", + "UMaskExt": "0x1BC1", + "Unit": "CHA" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 7", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 6", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 5", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 3", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 2", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 1", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", + "PerPkg": "1", + "UMask": "0x78", + "Unit": "IRP" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0xff", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0xff", + "Unit": "IIO" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to locally HOMed memory", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", + "PerPkg": "1", + "UMask": "0xCC42FF04", + "UMaskExt": "0xCC42FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to remotely HOMed memory", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", + "PerPkg": "1", + "UMask": "0xCC437F04", + "UMaskExt": "0xCC437F", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to locally HOMed memory", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", + "PerPkg": "1", + "UMask": "0xCD42FF04", + "UMaskExt": "0xCD42FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to remotely HOMed memory", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", + "PerPkg": "1", + "UMask": "0xCD437F04", + "UMaskExt": "0xCD437F", + "Unit": "CHA" + }, + { + "BriefDescription": "Multi-socket cacheline directory state lookups : Snoop Not Needed", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x53", + "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Multi-socket cacheline directory state lookups : Snoop Needed", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x53", + "EventName": "UNC_CHA_DIR_LOOKUP.SNP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x54", + "EventName": "UNC_CHA_DIR_UPDATE.HA", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Multi-socket cacheline directory state updates : Directory Updated memory write from TOR pipe", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x54", + "EventName": "UNC_CHA_DIR_UPDATE.TOR", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.EX_RDS", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Local - All Lines", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "PerPkg": "1", + "UMask": "0x200F", + "UMaskExt": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Remote - All Lines", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "PerPkg": "1", + "UMask": "0x800F", + "UMaskExt": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x64", + "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.TOR", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x64", + "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.SF", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x64", + "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.LLC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Counter 0 Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x1F", + "EventName": "UNC_CHA_COUNTER0_OCCUPANCY", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of times that an RFO hit in S state", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.RFO_HIT_S", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and remote INVITOE requests sent to the CHA's home agent", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.INVITOE", + "PerPkg": "1", + "UMask": "0x30", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : RspI", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPI", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : RspIFwd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : RspS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : RspSFwd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL", + "PerPkg": "1", + "UMask": "0xC001FFff", + "UMaskExt": "0xC001FF", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCRD", + "PerPkg": "1", + "UMask": "0xcccffd01", + "UMaskExt": "0xcccffd", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDRD", + "PerPkg": "1", + "UMask": "0xccd7fd01", + "UMaskExt": "0xccd7fd", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "PerPkg": "1", + "UMask": "0xC80FFD01", + "UMaskExt": "0xC80FFD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "PerPkg": "1", + "UMask": "0xC817FD01", + "UMaskExt": "0xC817FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO", + "PerPkg": "1", + "UMask": "0xCCC7FD01", + "UMaskExt": "0xCCC7FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "PerPkg": "1", + "UMask": "0xC807FD01", + "UMaskExt": "0xC807FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO", + "PerPkg": "1", + "UMask": "0xCCC7FE01", + "UMaskExt": "0xCCC7FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "PerPkg": "1", + "UMask": "0xc803fe04", + "UMaskExt": "0xc803fe", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", + "PerPkg": "1", + "UMask": "0xc803fe04", + "UMaskExt": "0xc803fe", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", + "PerPkg": "1", + "UMask": "0xcc43fe04", + "UMaskExt": "0xcc43fe", + "Unit": "CHA" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Snoop Responses : Hit M", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_M", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "IRP" + }, + { + "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.RFO", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "IRP" + }, + { + "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x28", + "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles when Direct2UPI was Disabled", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x27", + "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x29", + "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.NI", + "PerPkg": "1", + "UMaskExt": "0x1E", + "Unit": "M2M" + }, + { + "BriefDescription": "Tag Hit : Clean NearMem Underfill Hit", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2C", + "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Tag Hit : Dirty NearMem Underfill Hit", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2C", + "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Tag Miss", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x61", + "EventName": "UNC_M2M_TAG_MISS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC Bypass : Not Taken", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x22", + "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x24", + "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of reads in which direct to core transaction was overridden", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x25", + "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.ALL", + "PerPkg": "1", + "UMask": "0x0704", + "UMaskExt": "0x07", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.NORMAL", + "PerPkg": "1", + "UMask": "0x0701", + "UMaskExt": "0x07", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : All Writes - All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.ALL", + "PerPkg": "1", + "UMask": "0x1C10", + "UMaskExt": "0x1C", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FULL", + "PerPkg": "1", + "UMask": "0x1C01", + "UMaskExt": "0x1C", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", + "PerPkg": "1", + "UMask": "0x1C02", + "UMaskExt": "0x1C", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Allocations", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x01", + "EventName": "UNC_M2M_RxC_AD_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Allocations", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x05", + "EventName": "UNC_M2M_RxC_BL_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x06", + "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Allocations", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x09", + "EventName": "UNC_M2M_TxC_AD_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x0A", + "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Allocations : All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x65", + "EventName": "UNC_CHA_2LM_NM_INVITOX.LOCAL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x65", + "EventName": "UNC_CHA_2LM_NM_INVITOX.REMOTE", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x65", + "EventName": "UNC_CHA_2LM_NM_INVITOX.SETCONFLICT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x70", + "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS2.MEMWR", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x70", + "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS2.MEMWRNI", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Bypass : Taken", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Bypass : Not Taken", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Single Snoop Target from Remote", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.REMOTE_ONE", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Single External Snoops", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Single Core Requests", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", + "PerPkg": "1", + "UMask": "0x41", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Single Eviction", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", + "PerPkg": "1", + "UMask": "0x81", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", + "PerPkg": "1", + "UMask": "0xF1", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Multiple Snoop Targets from Remote", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.REMOTE_GTONE", + "PerPkg": "1", + "UMask": "0x22", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Multiple External Snoops", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", + "PerPkg": "1", + "UMask": "0x22", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requests", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", + "PerPkg": "1", + "UMask": "0x42", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", + "PerPkg": "1", + "UMask": "0x82", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", + "PerPkg": "1", + "UMask": "0xF2", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6E", + "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6E", + "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6E", + "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.GO", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket ownership read requests that hit in S state", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket WBMtoE requests", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.WBMTOE", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket writeback to I or S requests", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed : Remote socket read requests", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5E", + "EventName": "UNC_CHA_HITME_LOOKUP.READ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed : Remote socket write (i.e. writeback) requests", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5E", + "EventName": "UNC_CHA_HITME_LOOKUP.WRITE", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests to shared line", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests that are not to shared line", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket read or invalidate requests", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache to SHARed", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.SHARED", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache on RdInvOwn even if not RspFwdI*", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Deallocate HtiME$ on Reads without RspFwdI*", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "HA to iMC Reads Issued : ISOCH", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x59", + "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Lines in M state", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Lines in E state", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Lines in S State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Local Only", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY", + "PerPkg": "1", + "UMaskExt": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Remote Only", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ONLY", + "PerPkg": "1", + "UMaskExt": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Local - Lines in M State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", + "PerPkg": "1", + "UMask": "0x2001", + "UMaskExt": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Local - Lines in E State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", + "PerPkg": "1", + "UMask": "0x2002", + "UMaskExt": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Local - Lines in S State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", + "PerPkg": "1", + "UMask": "0x2004", + "UMaskExt": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Remote - Lines in M State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M", + "PerPkg": "1", + "UMask": "0x8001", + "UMaskExt": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Remote - Lines in E State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E", + "PerPkg": "1", + "UMask": "0x8002", + "UMaskExt": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Remote - Lines in S State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S", + "PerPkg": "1", + "UMask": "0x8004", + "UMaskExt": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc : Silent Snoop Eviction", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc : Write Combining Aliasing", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.WC_ALIASING", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc : CV0 Prefetch Victim", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc : CV0 Prefetch Miss", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : Local InvItoE", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.LOCAL_INVITOE", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : Local Rd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.LOCAL_READ", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : Remote Rd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.REMOTE_READ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : Remote Rd InvItoE", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.REMOTE_READINVITOE", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : Off", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.OFF_PWRHEURISTIC", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.RMW_SETMATCH", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_PAMATCH", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLOWSNP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_WAYMATCH", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLWAYRSV", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.PTL_INPIPE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.IRQ_SETMATCH_VICP", + "PerPkg": "1", + "UMaskExt": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.FSF_VICP", + "PerPkg": "1", + "UMaskExt": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.ONE_FSF_VIC", + "PerPkg": "1", + "UMaskExt": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.TORID_MATCH_GO_P", + "PerPkg": "1", + "UMaskExt": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.IPQ_SETMATCH_VICP", + "PerPkg": "1", + "UMaskExt": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.WAY_MATCH", + "PerPkg": "1", + "UMaskExt": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.ONE_RSP_CON", + "PerPkg": "1", + "UMaskExt": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.IDX_INPIPE", + "PerPkg": "1", + "UMaskExt": "0x100", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.SETMATCHENTRYWSCT", + "PerPkg": "1", + "UMaskExt": "0x200", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.ALLRSFWAYS_RES", + "PerPkg": "1", + "UMaskExt": "0x800", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.RRQ_SETMATCH_VICP", + "PerPkg": "1", + "UMaskExt": "0x1000", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.ISMQ_SETMATCH_VICP", + "PerPkg": "1", + "UMaskExt": "0x2000", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.SF_WAYS_RES", + "PerPkg": "1", + "UMaskExt": "0x4000", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.LLC_WAYS_RES", + "PerPkg": "1", + "UMaskExt": "0x8000", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.NOTALLOWSNOOP", + "PerPkg": "1", + "UMaskExt": "0x10000", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.TOPA_MATCH", + "PerPkg": "1", + "UMaskExt": "0x20000", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.IVEGRCREDIT", + "PerPkg": "1", + "UMaskExt": "0x40000", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.BLEGRCREDIT", + "PerPkg": "1", + "UMaskExt": "0x80000", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.ADEGRCREDIT", + "PerPkg": "1", + "UMaskExt": "0x100000", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.AKEGRCREDIT", + "PerPkg": "1", + "UMaskExt": "0x200000", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.HACREDIT", + "PerPkg": "1", + "UMaskExt": "0x400000", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_REQ", + "PerPkg": "1", + "UMaskExt": "0x800000", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_RSP", + "PerPkg": "1", + "UMaskExt": "0x1000000", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_RSP", + "PerPkg": "1", + "UMaskExt": "0x2000000", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB", + "PerPkg": "1", + "UMaskExt": "0x4000000", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB", + "PerPkg": "1", + "UMaskExt": "0x8000000", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS", + "PerPkg": "1", + "UMaskExt": "0x10000000", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC8", + "PerPkg": "1", + "UMaskExt": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC9", + "PerPkg": "1", + "UMaskExt": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC10", + "PerPkg": "1", + "UMaskExt": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC11", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC11", + "PerPkg": "1", + "UMaskExt": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC12", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC12", + "PerPkg": "1", + "UMaskExt": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC13", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC13", + "PerPkg": "1", + "UMaskExt": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : IRQ", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IRQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : IPQ", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IPQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : PRQ", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.PRQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : PRQ", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : RRQ", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.RRQ", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : WBQ", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.WBQ", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : ANY0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : HA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC Victim", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF Victim", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Victim", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC Victim", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Victim", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 1 : ANY0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x25", + "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 1 : HA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x25", + "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 1 : ANY0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2D", + "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 1 : HA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2D", + "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy : IRQ", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy : IPQ", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy : RRQ", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy : WBQ", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : ANY0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : HA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : LLC Victim", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : SF Victim", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : Victim", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : PhyAddr Match", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC Victim", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Victim", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : ANY0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : HA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : SF Victim", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : Victim", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : ANY0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : HA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : LLC Victim", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : SF Victim", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : Victim", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : LLC OR SF Way", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : PhyAddr Match", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : ANY0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : HA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : LLC Victim", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : SF Victim", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : Victim", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : LLC OR SF Way", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : PhyAddr Match", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : Snoops sent for Local Requests", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : Snoops sent for Remote Requests", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : Broadcast snoops for Local Requests", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : Broadcast snoops for Remote Requests", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : Directed snoops for Local Requests", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : Directed snoops for Remote Requests", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : Rsp*WB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPWB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : Rsp*Fwd*WB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPFWDWB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : RSPCNFLCT*", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : RspFwd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspI", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspIFwd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspSFwd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : Rsp*WB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspCnflct", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspFwd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : MtoI RspIDataM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit SF", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit SF", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "WbPushMtoI : Pushed to LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x56", + "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "WbPushMtoI : Pushed to Memory", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x56", + "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC8", + "PerPkg": "1", + "UMaskExt": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC9", + "PerPkg": "1", + "UMaskExt": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC10", + "PerPkg": "1", + "UMaskExt": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC11", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC11", + "PerPkg": "1", + "UMaskExt": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC12", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC12", + "PerPkg": "1", + "UMaskExt": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC13", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC13", + "PerPkg": "1", + "UMaskExt": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Sent (on 0?)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.SENT0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Sent (on 1?)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.SENT1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOTLB lookups first", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOTLB lookups all", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOTLB Hits to a 4K Page", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.4K_HITS", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOTLB Hits to a 2M Page", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.2M_HITS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOTLB Hits to a 1G Page", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.1G_HITS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOTLB Fills (same as IOTLB miss)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.MISSES", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": ": Context cache lookups", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": ": Context cache hits", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": ": PageWalk cache lookup", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOMMU memory access", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": ": Cycles PWT full", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.CYC_PWT_FULL", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": ": Interrupt Entry cache lookup", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": ": Interrupt Entry cache hit", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : PCIE bus", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : PCIE bus", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number requests PCIe makes of the main die : Drop request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x85", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU.ALL.DROP", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Total Write Cache Occupancy : Any Source", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x0F", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "IRP" + }, + { + "BriefDescription": "Total Write Cache Occupancy : Snoops", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x0F", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops : CLFlush", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "IRP" + }, + { + "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_I_IRP_ALL.EVICTS", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x1e", + "EventName": "UNC_I_MISC0.FAST_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x1E", + "EventName": "UNC_I_MISC0.FAST_REJ", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x1e", + "EventName": "UNC_I_MISC0.2ND_RD_INSERT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x1e", + "EventName": "UNC_I_MISC0.2ND_WR_INSERT", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x1E", + "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x1E", + "EventName": "UNC_I_MISC0.FAST_XFER", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x1E", + "EventName": "UNC_I_MISC0.PF_ACK_HINT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x1E", + "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.SLOW_I", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.SLOW_S", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.SLOW_E", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.SLOW_M", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Received Invalid", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x1F", + "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Received Valid", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x1F", + "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : P2P reads", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.RD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : P2P Writes", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.WR", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : P2P Message", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.MSG", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : P2P completions", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : Match if remote only", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.REM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : match if remote and target matches", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : match if local only", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.LOC", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : match if local and target matches", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : Miss", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.MISS", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : Hit I", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_I", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : Hit E or S", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_ES", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : SnpCode", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPCODE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : SnpData", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPDATA", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : SnpInv", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPINV", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count : Writes", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.WRITES", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count : Atomic", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.ATOMIC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count : Other", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.OTHER", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count : Select Source", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "M2M to iMC Bypass : Taken", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x22", + "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC Bypass : Taken", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x21", + "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC Bypass : Not Taken", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x21", + "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On Dirty Line in I State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On Dirty Line in S State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On Dirty Line in L State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On Dirty Line in A State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On NonDirty Line in I State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On NonDirty Line in S State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On NonDirty Line in L State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On NonDirty Line in A State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On Dirty Line in I State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On Dirty Line in S State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On Dirty Line in L State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On Dirty Line in A State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On NonDirty Line in I State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On NonDirty Line in S State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On NonDirty Line in L State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On NonDirty Line in A State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL", + "PerPkg": "1", + "UMask": "0x0101", + "UMaskExt": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH", + "PerPkg": "1", + "UMask": "0x0102", + "UMaskExt": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH0_ALL", + "PerPkg": "1", + "UMask": "0x0104", + "UMaskExt": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR", + "PerPkg": "1", + "UMask": "0x0140", + "UMaskExt": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL", + "PerPkg": "1", + "UMask": "0x0201", + "UMaskExt": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH", + "PerPkg": "1", + "UMask": "0x0202", + "UMaskExt": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH1_ALL", + "PerPkg": "1", + "UMask": "0x0204", + "UMaskExt": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR", + "PerPkg": "1", + "UMask": "0x0240", + "UMaskExt": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH2_FROM_TGR", + "PerPkg": "1", + "UMask": "0x0440", + "UMaskExt": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL", + "PerPkg": "1", + "UMask": "0x0401", + "UMaskExt": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL", + "PerPkg": "1", + "UMask": "0x0402", + "UMaskExt": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH", + "PerPkg": "1", + "UMask": "0x0404", + "UMaskExt": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH", + "PerPkg": "1", + "UMask": "0x0408", + "UMaskExt": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL", + "PerPkg": "1", + "UMask": "0x0410", + "UMaskExt": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR", + "PerPkg": "1", + "UMaskExt": "0x05", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_NI", + "PerPkg": "1", + "UMaskExt": "0x06", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL", + "PerPkg": "1", + "UMask": "0x0801", + "UMaskExt": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL", + "PerPkg": "1", + "UMask": "0x0802", + "UMaskExt": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH", + "PerPkg": "1", + "UMask": "0x0804", + "UMaskExt": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH", + "PerPkg": "1", + "UMask": "0x0808", + "UMaskExt": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL", + "PerPkg": "1", + "UMask": "0x0810", + "UMaskExt": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR", + "PerPkg": "1", + "UMaskExt": "0x09", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_NI", + "PerPkg": "1", + "UMaskExt": "0x0A", + "Unit": "M2M" + }, + { + "BriefDescription": "Number Packet Header Matches : Mesh Match", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4C", + "EventName": "UNC_M2M_PKT_MATCH.MESH", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Number Packet Header Matches : MC Match", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4C", + "EventName": "UNC_M2M_PKT_MATCH.MC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Full : Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_FULL.CH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Full : Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_FULL.CH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Full : Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_FULL.CH2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts : Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts : Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Not Empty : Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_NE.CH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Not Empty : Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_NE.CH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Not Empty : Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_NE.CH2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Occupancy : Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Occupancy : Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Occupancy : Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound Ring Transactions on AK : NDR Transactions", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x39", + "EventName": "UNC_M2M_TxC_AK.NDR", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound Ring Transactions on AK : CRD Transactions to Cbo", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x39", + "EventName": "UNC_M2M_TxC_AK.CRD_CBO", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x1D", + "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x1D", + "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1", + "PerPkg": "1", + "UMask": "0x88", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1", + "PerPkg": "1", + "UMask": "0xA0", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full : All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty : All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations : All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x1F", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x1F", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy : All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Cache", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_CACHE", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Core", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_CORE", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to QPI", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_UPI", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Full : All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Not Empty : All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x1B", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x1B", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x1C", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x1C", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "WPQ Flush : Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x58", + "EventName": "UNC_M2M_WPQ_FLUSH.CH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "WPQ Flush : Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x58", + "EventName": "UNC_M2M_WPQ_FLUSH.CH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "WPQ Flush : Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x58", + "EventName": "UNC_M2M_WPQ_FLUSH.CH2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full : Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WR_TRACKER_FULL.CH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full : Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WR_TRACKER_FULL.CH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full : Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WR_TRACKER_FULL.CH2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full : Mirror", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x56", + "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts : Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x56", + "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts : Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x56", + "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WR_TRACKER_NE.CH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WR_TRACKER_NE.CH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty : Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WR_TRACKER_NE.CH2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty : Mirror", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x63", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x63", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x63", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x62", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x62", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x62", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy : Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x55", + "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy : Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x55", + "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy : Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x55", + "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy : Mirror", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x55", + "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Posted Inserts : Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5E", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Posted Inserts : Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5E", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Posted Inserts : Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5E", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Posted Occupancy : Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5D", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Posted Occupancy : Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5D", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Posted Occupancy : Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5D", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.ALL", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.AD_0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.BL_0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.AD_1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.BL_1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_1", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CBox AD Credits Empty : VNA Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty : Writebacks", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty : Requests", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty : Snoops", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : IIO2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : IIO3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : IIO4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : IIO5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : Selected M2p BL NCS credits", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received : AD - Slot 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received : AD - Slot 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received : AD - Slot 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received : BL - Slot 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received : AK - Slot 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received : AK - Slot 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0 : REQ on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0 : SNP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0 : RSP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0 : RSP on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0 : WB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0 : NCB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0 : NCS on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1 : REQ on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1 : SNP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1 : RSP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1 : RSP on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1 : WB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1 : NCB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1 : NCS on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.VN01_PARALLEL_WIN", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : Max Parallel Win", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.ALL_PARALLEL_WIN", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0 : REQ on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0 : SNP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0 : RSP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0 : RSP on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0 : WB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0 : NCB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0 : NCS on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1 : REQ on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1 : SNP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1 : RSP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1 : RSP on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1 : WB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1 : NCB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1 : NCS on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0 : REQ on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0 : SNP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0 : RSP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0 : RSP on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0 : WB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0 : NCB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0 : NCS on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1 : REQ on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1 : SNP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1 : RSP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1 : RSP on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1 : WB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1 : NCB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1 : NCS on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL Arb", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 1", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 2", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events : Any In BGF FIFO", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events : Any in BGF Path", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events : No D2K For Arb", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN0_NO_D2K_FOR_ARB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN1_NO_D2K_FOR_ARB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT1_FOR_D2K", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT2_FOR_D2K", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy : VNA In Use", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy : Packets in BGF FIFO", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy : Packets in BGF Path", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy : Transmit Credits", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy : D2K Credits", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy : Credits Consumed", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.CONSUMED", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent : All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent : TSV High", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.TSV_HI", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent : Cycle valid for Flit", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.VALID_FOR_FLIT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent : No BGF Credits", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_BGF", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent : No TxQ Credits", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_TXQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit : All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit : Needs Data Flit", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1 : Acumullate", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1 : Accumulate Ready", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1 : Accumulate Wasted", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Message", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_DURING", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_AFTER", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_SENT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_AFTER", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall - No Message", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2 : Parallel Ok", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2 : Parallel Message", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_MSG", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2 : Parallel Flit Finished", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_FLIT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit : One Message", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit : Two Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.2_MSGS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit : Three Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.3_MSGS", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit : One Message in non-VNA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG_VNX", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit : One Slot Taken", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit : Two Slots Taken", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_2", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit : All Slots Taken", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_3", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent : All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent : TSV High", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.TSV_HI", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent : Cycle valid for Flit", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.VALID_FOR_FLIT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent : No BGF Credits", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_CRD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent : No TxQ Credits", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent : No BGF Credits + No Extra Message Slotted", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_NO_MSG", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent : No TxQ Credits + No Extra Message Slotted", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_NO_MSG", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held : VN0", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_HELD.VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held : VN1", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_HELD.VN1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held : Parallel Attempt", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held : Parallel Success", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held : Can't Slot AD", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held : Can't Slot BL", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : REQ on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : SNP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : WB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCS on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : REQ on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : SNP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : WB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCS on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : WB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : WB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit : REQ on AD", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit : SNP on AD", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit : RSP on AD", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit : RSP on BL", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit : WB on BL", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit : NCB on BL", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit : NCS on BL", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit : REQ on AD", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit : SNP on AD", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit : RSP on AD", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit : RSP on BL", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit : WB on BL", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit : NCB on BL", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit : NCS on BL", + "Counter": "0,1,2", + "CounterType": "PGMABLE", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits : Corrected", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5A", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits : Level < 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5A", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits : Level < 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5A", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits : Level < 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5A", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits : Level < 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5A", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT10", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits : Any In Use", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5A", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN0 REQ Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN0 SNP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN0 RSP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN0 WB Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN1 REQ Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN1 SNP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN1 RSP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN1 WB Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN0 REQ Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN0 SNP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN0 RSP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN0 WB Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN1 REQ Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN1 SNP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN1 RSP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN1 WB Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts : VN0 REQ Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts : VN0 SNP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts : VN0 RSP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts : VN0 WB Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts : VN1 REQ Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts : VN1 SNP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts : VN1 RSP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy : VN0 REQ Messages", + "CounterType": "PGMABLE", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy : VN0 SNP Messages", + "CounterType": "PGMABLE", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy : VN0 RSP Messages", + "CounterType": "PGMABLE", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy : VN0 WB Messages", + "CounterType": "PGMABLE", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy : VN1 REQ Messages", + "CounterType": "PGMABLE", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy : VN1 SNP Messages", + "CounterType": "PGMABLE", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy : VN1 RSP Messages", + "CounterType": "PGMABLE", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN0 RSP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN0 WB Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN0 NCB Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN0 NCS Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN1 RSP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN1 WB Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN1 NCS Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN1 NCB Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN0 REQ Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN0 SNP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN0 RSP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN0 WB Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN1 REQ Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN1 SNP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN1 RSP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN1 WB Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN0 RSP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN0 WB Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN0 NCB Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN0 NCS Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN1 RSP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN1 WB Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN1_NCS Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN1_NCB Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages", + "CounterType": "PGMABLE", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages", + "CounterType": "PGMABLE", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages", + "CounterType": "PGMABLE", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN0 NCS Messages", + "CounterType": "PGMABLE", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages", + "CounterType": "PGMABLE", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages", + "CounterType": "PGMABLE", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages", + "CounterType": "PGMABLE", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN1_NCB Messages", + "CounterType": "PGMABLE", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages", + "CounterType": "PGMABLE", + "EventCode": "0x1F", + "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_LOCAL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages", + "CounterType": "PGMABLE", + "EventCode": "0x1F", + "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_THROUGH", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages", + "CounterType": "PGMABLE", + "EventCode": "0x1F", + "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_WRPULL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages", + "CounterType": "PGMABLE", + "EventCode": "0x1F", + "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_LOCAL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages", + "CounterType": "PGMABLE", + "EventCode": "0x1F", + "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_THROUGH", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages", + "CounterType": "PGMABLE", + "EventCode": "0x1F", + "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_WRPULL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty : VNA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty : VN0 REQ Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty : VN0 SNP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty : VN0 RSP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty : VN1 REQ Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty : VN1 SNP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty : VN1 RSP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty : VNA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty : VN0 REQ Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty : VN0 RSP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty : VN0 SNP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty : VN1 REQ Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty : VN1 RSP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty : VN1 SNP Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used : REQ on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used : SNP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used : RSP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used : RSP on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used : WB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used : NCB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits : REQ on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits : SNP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits : RSP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits : RSP on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits : WB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits : NCB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used : REQ on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used : SNP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used : RSP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used : RSP on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used : WB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used : NCB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits : REQ on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits : SNP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits : RSP on AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits : RSP on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits : WB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits : NCB on BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0", + "PerPkg": "1", + "UMask": "0x81", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0", + "PerPkg": "1", + "UMask": "0x82", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0", + "PerPkg": "1", + "UMask": "0x84", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1", + "PerPkg": "1", + "UMask": "0xA0", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1", + "PerPkg": "1", + "UMask": "0xC0", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7D", + "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7D", + "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7D", + "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7D", + "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7D", + "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7D", + "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7D", + "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7D", + "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARRIVED", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_XPT_PFTCH.ARRIVED", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_XPT_PFTCH.BYPASS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_XPT_PFTCH.BYPASS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_XPT_PFTCH.ARB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_ARB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_ARB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_XPT_PFTCH.FLITTED", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_XPT_PFTCH.FLITTED", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_OLD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_OLD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Received : VLW", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received : MSI", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received : IPI", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received : Doorbell", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received : Interrupt", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.INT_PRIO", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x45", + "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.RDRAND", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.RDSEED", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "UBOX" + }, + { + "BriefDescription": "Direct packet attempts : D2C", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Direct packet attempts : D2K", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Request, Match Opcode", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC", + "PerPkg": "1", + "UMask": "0x108", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Snoop", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", + "PerPkg": "1", + "UMask": "0x09", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Snoop, Match Opcode", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC", + "PerPkg": "1", + "UMask": "0x109", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA", + "PerPkg": "1", + "UMask": "0x0A", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data, Match Opcode", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "PerPkg": "1", + "UMask": "0x10A", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Response - Data", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", + "PerPkg": "1", + "UMask": "0x0C", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Response - Data, Match Opcode", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "PerPkg": "1", + "UMask": "0x10C", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Writeback", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB", + "PerPkg": "1", + "UMask": "0x0D", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Writeback, Match Opcode", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC", + "PerPkg": "1", + "UMask": "0x10D", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", + "PerPkg": "1", + "UMask": "0x0E", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC", + "PerPkg": "1", + "UMask": "0x10E", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", + "PerPkg": "1", + "UMask": "0x0F", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC", + "PerPkg": "1", + "UMask": "0x10F", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Response - Conflict", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT", + "PerPkg": "1", + "UMask": "0x1AA", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Response - Invalid", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI", + "PerPkg": "1", + "UMask": "0x12A", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "UPI LL" + }, + { + "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received : Slot 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.SLOT0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received : Slot 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.SLOT1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received : Slot 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.SLOT2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received : Data", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.DATA", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received : LLCRD Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.LLCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.NULL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received : LLCTRL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.LLCTRL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received : Protocol Header", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.PROTHDR", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received : Null FLITs received from any slot", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.IDLE", + "PerPkg": "1", + "UMask": "0x47", + "Unit": "UPI LL" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations : Slot 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations : Slot 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "UPI LL" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations : Slot 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "UPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets : Slot 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets : Slot 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "UPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets : Slot 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Request, Match Opcode", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC", + "PerPkg": "1", + "UMask": "0x108", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Snoop", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", + "PerPkg": "1", + "UMask": "0x09", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Snoop, Match Opcode", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC", + "PerPkg": "1", + "UMask": "0x109", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", + "PerPkg": "1", + "UMask": "0x0A", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "PerPkg": "1", + "UMask": "0x10A", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", + "PerPkg": "1", + "UMask": "0x0C", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data, Match Opcode", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "PerPkg": "1", + "UMask": "0x10C", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Writeback", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB", + "PerPkg": "1", + "UMask": "0x0D", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Writeback, Match Opcode", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC", + "PerPkg": "1", + "UMask": "0x10D", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", + "PerPkg": "1", + "UMask": "0x0E", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC", + "PerPkg": "1", + "UMask": "0x10E", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", + "PerPkg": "1", + "UMask": "0x0F", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC", + "PerPkg": "1", + "UMask": "0x10F", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Conflict", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT", + "PerPkg": "1", + "UMask": "0x1AA", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Invalid", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI", + "PerPkg": "1", + "UMask": "0x12A", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent : Slot 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.SLOT0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent : Slot 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.SLOT1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent : Slot 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.SLOT2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent : Data", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.DATA", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent : LLCRD Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.LLCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.NULL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent : LLCTRL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.LLCTRL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent : Protocol Header", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.PROTHDR", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent : Idle", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.IDLE", + "PerPkg": "1", + "UMask": "0x47", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Cache Lookups : I State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.I", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : SnoopFilter - S State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.SF_S", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : SnoopFilter - E State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.SF_E", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : SnoopFilter - H State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.SF_H", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : S State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.S", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : E State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.E", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : M State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.M", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : F State", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.F", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : RFO Requests", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO", + "PerPkg": "1", + "UMask": "0x1BC8FF", + "UMaskExt": "0x1BC8", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : IRQ - iA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : SF/LLC Evictions", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.EVICT", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PRQ - IOSF", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : IPQ", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IPQ", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : IRQ - Non iA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PRQ - Non IOSF", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RRQ", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.RRQ", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WBQ", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.WBQ", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All from Local IO", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO", + "PerPkg": "1", + "UMask": "0xC000FF04", + "UMaskExt": "0xC000FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All from Local iA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA", + "PerPkg": "1", + "UMask": "0xC000FF01", + "UMaskExt": "0xC000FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All from Local iA and IO", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", + "PerPkg": "1", + "UMask": "0xC000FF05", + "UMaskExt": "0xC000FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just Hits", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.HIT", + "PerPkg": "1", + "UMaskExt": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just Misses", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.MISS", + "PerPkg": "1", + "UMaskExt": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.DDR", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.DDR4", + "PerPkg": "1", + "UMaskExt": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : MMCFG Access", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.MMCFG", + "PerPkg": "1", + "UMaskExt": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just Local Targets", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT", + "PerPkg": "1", + "UMaskExt": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just Remote Targets", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.REMOTE_TGT", + "PerPkg": "1", + "UMaskExt": "0x100", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC", + "PerPkg": "1", + "UMaskExt": "0x200", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC", + "PerPkg": "1", + "UMaskExt": "0x400", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just NearMem", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM", + "PerPkg": "1", + "UMaskExt": "0x400000", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just NotNearMem", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM", + "PerPkg": "1", + "UMaskExt": "0x800000", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just NonCoherent", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.NONCOH", + "PerPkg": "1", + "UMaskExt": "0x1000000", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just ISOC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ISOC", + "PerPkg": "1", + "UMaskExt": "0x2000000", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : IRQ - iA", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : SF/LLC Evictions", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : PRQ - IOSF", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : IPQ", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : IRQ - Non iA", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : PRQ - Non IOSF", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All from Local IO", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO", + "PerPkg": "1", + "UMask": "0xC000FF04", + "UMaskExt": "0xC000FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All from Local iA", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA", + "PerPkg": "1", + "UMask": "0xC000FF01", + "UMaskExt": "0xC000FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All from Local iA and IO", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", + "PerPkg": "1", + "UMask": "0xC000FF05", + "UMaskExt": "0xC000FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just Hits", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", + "PerPkg": "1", + "UMaskExt": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just Misses", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", + "PerPkg": "1", + "UMaskExt": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : MMCFG Access", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG", + "PerPkg": "1", + "UMaskExt": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just Local Targets", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT", + "PerPkg": "1", + "UMaskExt": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just Remote Targets", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.REMOTE_TGT", + "PerPkg": "1", + "UMaskExt": "0x100", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC", + "PerPkg": "1", + "UMaskExt": "0x200", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC", + "PerPkg": "1", + "UMaskExt": "0x400", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just NearMem", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM", + "PerPkg": "1", + "UMaskExt": "0x400000", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just NotNearMem", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM", + "PerPkg": "1", + "UMaskExt": "0x800000", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just NonCoherent", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH", + "PerPkg": "1", + "UMaskExt": "0x1000000", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just ISOC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC", + "PerPkg": "1", + "UMaskExt": "0x2000000", + "Unit": "CHA" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS", + "PerPkg": "1", + "UMaskExt": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS", + "PerPkg": "1", + "UMaskExt": "0x0C", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Full : Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6B", + "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Full : Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6B", + "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Full : Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6B", + "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6C", + "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6C", + "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6C", + "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA0_INVAL", + "PerPkg": "1", + "UMaskExt": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA1_INVAL", + "PerPkg": "1", + "UMaskExt": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_MISS_INVAL", + "PerPkg": "1", + "UMaskExt": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_RSP_PDRESET", + "PerPkg": "1", + "UMaskExt": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped : XPT - Ch 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6F", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped : UPI - Ch 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6F", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_UPI", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped : XPT - Ch 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6F", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped : UPI - Ch 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6F", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_UPI", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped : XPT - Ch 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6F", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_XPT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped : UPI - Ch 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6F", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_UPI", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY", + "PerPkg": "1", + "UMaskExt": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH", + "PerPkg": "1", + "UMaskExt": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.UPI_THRESH", + "PerPkg": "1", + "UMaskExt": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY", + "PerPkg": "1", + "UMaskExt": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH", + "PerPkg": "1", + "UMaskExt": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.UPI_THRESH", + "PerPkg": "1", + "UMaskExt": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x72", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_SECURE_DROP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x72", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.NOT_PF_SAD_REGION", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x72", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_HIT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x72", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.STOP_B2B", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x72", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.ERRORBLK_RxC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x72", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_AD_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x72", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_FULL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x72", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.WPQ_PROXY", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x72", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.RPQ_PROXY", + "PerPkg": "1", + "UMaskExt": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x72", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.XPT_THRESH", + "PerPkg": "1", + "UMaskExt": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x72", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.UPI_THRESH", + "PerPkg": "1", + "UMaskExt": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6D", + "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6D", + "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_UPI", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6D", + "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6D", + "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_UPI", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6D", + "EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_XPT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6D", + "EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_UPI", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Occupancy : Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6A", + "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Occupancy : Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6A", + "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Occupancy : Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6A", + "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": ": Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x76", + "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": ": Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x76", + "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": ": Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x76", + "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7A", + "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7A", + "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7A", + "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x55", + "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x55", + "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x47", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x47", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x47", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x47", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x1a", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x1a", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x1a", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x1a", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Shared Credits Returned : Agent0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x17", + "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Shared Credits Returned : Agent1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x17", + "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Shared Credits Returned : Agent2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x17", + "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x41", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x41", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x41", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x41", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4b", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4b", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4b", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4b", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "P2P Credit Occupancy : Local NCB", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "P2P Credit Occupancy : Local NCS", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "P2P Credit Occupancy : Remote NCB", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "P2P Credit Occupancy : Remote NCS", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "P2P Credit Occupancy : All", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Dedicated Credits Received : Local NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Dedicated Credits Received : Local NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Dedicated Credits Received : Remote NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Dedicated Credits Received : Remote NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Dedicated Credits Received : All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Shared Credits Received : Local NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Shared Credits Received : Local NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Shared Credits Received : Remote NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Shared Credits Received : Remote NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Shared Credits Received : All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - DRS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x48", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_DRS", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x48", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x48", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCS", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - DRS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x48", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_DRS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x48", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x48", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - DRS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x49", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_DRS", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x49", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x49", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCS", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x1b", + "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCB", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x1b", + "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x1b", + "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x1b", + "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x1b", + "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x1b", + "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Shared Credits Returned : Agent0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Shared Credits Returned : Agent1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Shared Credits Returned : Agent2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x45", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x45", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x45", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - DRS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_DRS", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCS", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - DRS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_DRS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - DRS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x43", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_DRS", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x43", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x43", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCS", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - DRS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4c", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_DRS", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4c", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4c", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCS", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - DRS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4c", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_DRS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4c", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4c", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - DRS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4d", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_DRS", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4d", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4d", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCS", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x2d", + "EventName": "UNC_M2P_TxC_CREDITS.PRQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x4D", + "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x4D", + "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x4D", + "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x4D", + "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x4D", + "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x4D", + "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x4D", + "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x4D", + "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x4F", + "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x4F", + "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "UBOX" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x81", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x81", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x81", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x89", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x89", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x89", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8B", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8B", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8B", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x85", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x85", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x85", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x87", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x87", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x87", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8D", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8D", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8D", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8F", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8F", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8F", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal asserted : Vertical", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.VERT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal asserted : Horizontal", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.HORZ", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal asserted : DPT Local", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_LOCAL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal asserted : DPT Remote", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_NONLOCAL", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_IV", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Up", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xBA", + "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Down", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xBA", + "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB6", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB6", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB6", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB6", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xBB", + "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xBB", + "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xBB", + "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xBB", + "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB7", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB7", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB7", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB7", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB8", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB8", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB8", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB8", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal IV Ring in Use : Left", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB9", + "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal IV Ring in Use : Right", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB9", + "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE6", + "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE6", + "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAC", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAC", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAC", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAC", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAA", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAA", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAA", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAA", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAA", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.AKC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAD", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAD", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAD", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAD", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAD", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAB", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAB", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAB", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAB", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAB", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AKC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : IFV - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD1", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD1", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD1", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD3", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD3", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD3", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD5", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD5", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD5", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD7", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD7", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD7", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA6", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA6", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA6", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA6", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA6", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA6", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA5", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA5", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA5", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA5", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA5", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA5", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA5", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_ALL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV_AG1", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_VERT_STARVED1.TGC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB0", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB0", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Down and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB0", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Down and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB0", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB4", + "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB4", + "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Down and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB4", + "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB4", + "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB1", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB1", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Down and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB1", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Down and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB1", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB2", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB2", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Down and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB2", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Down and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB2", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical IV Ring in Use : Up", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB3", + "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical IV Ring in Use : Down", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB3", + "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB5", + "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB5", + "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Down and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB5", + "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB5", + "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x81", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x81", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x81", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x89", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x89", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x89", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8B", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8B", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8B", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x85", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x85", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x85", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x87", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x87", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x87", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8D", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8D", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8D", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8F", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8F", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8F", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Distress signal asserted : Vertical", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Distress signal asserted : Horizontal", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Distress signal asserted : DPT Local", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Distress signal asserted : DPT Remote", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Up", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xBA", + "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Down", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xBA", + "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB6", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB6", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB6", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB6", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xBB", + "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xBB", + "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xBB", + "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xBB", + "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB7", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB7", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB7", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB7", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB8", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB8", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB8", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB8", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal IV Ring in Use : Left", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB9", + "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal IV Ring in Use : Right", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB9", + "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE6", + "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE6", + "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAC", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAC", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAC", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAC", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAA", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAA", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAA", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAA", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAA", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAD", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAD", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAD", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAD", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAD", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAB", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAB", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAB", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAB", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAB", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE5", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE5", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE5", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE5", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE5", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE5", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : IFV - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD1", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD1", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD1", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD3", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD3", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD3", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD5", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD5", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD5", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD7", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD7", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD7", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB0", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB0", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Down and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB0", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Down and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB0", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB4", + "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB4", + "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Down and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB4", + "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB4", + "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB1", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB1", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Down and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB1", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Down and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB1", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB2", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB2", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Down and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB2", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Down and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB2", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical IV Ring in Use : Up", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB3", + "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical IV Ring in Use : Down", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB3", + "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB5", + "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB5", + "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Down and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB5", + "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB5", + "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x81", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x81", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x81", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x89", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x89", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x89", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8b", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8b", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8b", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x85", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x85", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x85", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x87", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x87", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x87", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8d", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8d", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8d", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8f", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8f", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8f", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Distress signal asserted : Vertical", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.VERT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Distress signal asserted : Horizontal", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.HORZ", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Distress signal asserted : DPT Local", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_LOCAL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Distress signal asserted : DPT Remote", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_NONLOCAL", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_IV", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Up", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xba", + "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Down", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xba", + "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb6", + "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb6", + "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb6", + "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb6", + "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xbb", + "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xbb", + "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xbb", + "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xbb", + "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb7", + "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb7", + "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb7", + "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb7", + "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb8", + "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb8", + "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb8", + "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb8", + "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal IV Ring in Use : Left", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb9", + "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal IV Ring in Use : Right", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb9", + "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe6", + "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe6", + "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xac", + "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xac", + "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xac", + "EventName": "UNC_M2P_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xac", + "EventName": "UNC_M2P_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xaa", + "EventName": "UNC_M2P_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xaa", + "EventName": "UNC_M2P_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xaa", + "EventName": "UNC_M2P_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xaa", + "EventName": "UNC_M2P_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xaa", + "EventName": "UNC_M2P_RING_BOUNCES_VERT.AKC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xad", + "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xad", + "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xad", + "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xad", + "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xad", + "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xab", + "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xab", + "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xab", + "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xab", + "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xab", + "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AKC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe5", + "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe5", + "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe5", + "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe5", + "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe5", + "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe5", + "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : IFV - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd1", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd1", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd1", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd3", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd3", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd3", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd7", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd7", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd7", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa6", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa6", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa6", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa6", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa6", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa6", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa5", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa5", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa5", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa5", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa5", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa5", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xa5", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_ALL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9c", + "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9c", + "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9c", + "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9c", + "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9d", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9d", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9d", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9d", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.IV_AG1", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9d", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9d", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9d", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9e", + "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9e", + "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x95", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x95", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x97", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x97", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x93", + "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x93", + "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x99", + "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x99", + "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x91", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x91", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9a", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9a", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9a", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9a", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9a", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9a", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9a", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9b", + "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9b", + "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9b", + "EventName": "UNC_M2P_TxR_VERT_STARVED1.TGC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb0", + "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb0", + "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Down and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb0", + "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Down and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb0", + "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb4", + "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb4", + "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Down and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb4", + "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb4", + "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb1", + "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb1", + "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Down and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb1", + "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Down and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb1", + "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb2", + "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb2", + "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Down and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb2", + "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Down and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb2", + "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical IV Ring in Use : Up", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb3", + "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical IV Ring in Use : Down", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb3", + "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb5", + "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb5", + "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Down and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb5", + "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xb5", + "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x81", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x81", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x81", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x89", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x89", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x89", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8B", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8B", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8B", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x85", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x85", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x85", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x87", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x87", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x87", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8D", + "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8D", + "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8D", + "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8F", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8F", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8F", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Distress signal asserted : Vertical", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.VERT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Distress signal asserted : Horizontal", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.HORZ", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Distress signal asserted : DPT Local", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_LOCAL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Distress signal asserted : DPT Remote", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_NONLOCAL", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_STALL_IV", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Up", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xBA", + "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Down", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xBA", + "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB6", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB6", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB6", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB6", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xBB", + "EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xBB", + "EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xBB", + "EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xBB", + "EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB7", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB7", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB7", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB7", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB8", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB8", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB8", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB8", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal IV Ring in Use : Left", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB9", + "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal IV Ring in Use : Right", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB9", + "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE6", + "EventName": "UNC_M3UPI_MISC_EXTERNAL.MBE_INST0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE6", + "EventName": "UNC_M3UPI_MISC_EXTERNAL.MBE_INST1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAC", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAC", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAC", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAC", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AKC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAD", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAD", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAD", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAD", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAD", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AKC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE5", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE5", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE5", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE5", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE5", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE5", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_M3UPI_RxR_BYPASS.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_M3UPI_RxR_BYPASS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE2", + "EventName": "UNC_M3UPI_RxR_BYPASS.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : IFV - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_M3UPI_RxR_INSERTS.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_M3UPI_RxR_INSERTS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE1", + "EventName": "UNC_M3UPI_RxR_INSERTS.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xE0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD1", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD1", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD1", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD3", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD3", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD3", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD5", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD5", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD5", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD7", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD7", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD7", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_ALL", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_ALL", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_UNCRD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_UNCRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AKC_UNCRD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_ALL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV_AG1", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : IV", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.IV_AG0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.TGC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Down and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Down and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Down and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Down and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Down and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Down and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Down and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical IV Ring in Use : Up", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical IV Ring in Use : Down", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB5", + "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB5", + "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Down and Even", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB5", + "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xB5", + "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Source Throttle", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xae", + "EventName": "UNC_CHA_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe4", + "EventName": "UNC_CHA_RxR_CRD_STARVED_1", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counting disabled", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_IIO_NOTHING", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "PWT occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_IIO_PWT_OCCUPANCY", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Symbol Times on Link", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_IIO_SYMBOL_TIMES", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "P2P Requests", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x14", + "EventName": "UNC_I_P2P_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Occupancy", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x15", + "EventName": "UNC_I_P2P_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "AK Egress Allocations", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x0B", + "EventName": "UNC_I_TxC_AK_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Cycles Full", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x05", + "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Inserts", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_I_TxC_BL_DRS_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Occupancy", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x08", + "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Cycles Full", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x06", + "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Inserts", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x03", + "EventName": "UNC_I_TxC_BL_NCB_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Occupancy", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x09", + "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Cycles Full", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x07", + "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Inserts", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_I_TxC_BL_NCS_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Occupancy", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x0A", + "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x1C", + "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "No AD0 Egress Credits Stalls", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x1A", + "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "No AD1 Egress Credits Stalls", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x1B", + "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "No BL Egress Credit Stalls", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x1D", + "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x0D", + "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x0E", + "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Request Queue Occupancy", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x0C", + "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x60", + "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x64", + "EventName": "UNC_M2M_MIRR_WRQ_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x65", + "EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x73", + "EventName": "UNC_M2M_PREFCAM_CIS_DROPS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x79", + "EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x78", + "EventName": "UNC_M2M_PREFCAM_RxC_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x77", + "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Source Throttle", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xae", + "EventName": "UNC_M2M_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Full", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x03", + "EventName": "UNC_M2M_RxC_AD_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5C", + "EventName": "UNC_M2M_RxC_AK_WR_CMP", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Full", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x08", + "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x07", + "EventName": "UNC_M2M_RxC_BL_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe4", + "EventName": "UNC_M2M_RxR_CRD_STARVED_1", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x33", + "EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Retry - Mem Mirroring Mode", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_ACCEPTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Retry - Mem Mirroring Mode", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_REJECTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Scoreboard Accepts", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2F", + "EventName": "UNC_M2M_SCOREBOARD_RD_ACCEPTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Scoreboard Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x30", + "EventName": "UNC_M2M_SCOREBOARD_RD_REJECTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Scoreboard Accepts", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x31", + "EventName": "UNC_M2M_SCOREBOARD_WR_ACCEPTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Scoreboard Rejects", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x32", + "EventName": "UNC_M2M_SCOREBOARD_WR_REJECTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number AD Ingress Credits", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x41", + "EventName": "UNC_M2M_TGR_AD_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number BL Ingress Credits", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_M2M_TGR_BL_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Credit Acquired", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x0d", + "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Credits Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x0e", + "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Full", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x0c", + "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x0b", + "EventName": "UNC_M2M_TxC_AD_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No AD Egress (to CMS) Credits", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x0f", + "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x10", + "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AKC Credits", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5F", + "EventName": "UNC_M2M_TxC_AKC_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Source Throttle", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xae", + "EventName": "UNC_M2P_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe4", + "EventName": "UNC_M2P_RxR_CRD_STARVED_1", + "PerPkg": "1", + "Unit": "M2PCIe" + }, { "BriefDescription": "CMS Clockticks", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xc0", - "EventName": "UNC_CHA_CMS_CLOCKTICKS", + "EventCode": "0xc0", + "EventName": "UNC_M3UPI_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "D2C Sent", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2B", + "EventName": "UNC_M3UPI_D2C_SENT", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "D2U Sent", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_M3UPI_D2U_SENT", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Source Throttle", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xae", + "EventName": "UNC_M3UPI_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xe4", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED_1", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AK Flow Q Inserts", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2F", + "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AK Flow Q Occupancy", + "CounterType": "PGMABLE", + "EventCode": "0x1E", + "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "FlowQ Generated Prefetch", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x29", + "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "IDI Lock/SplitLock Cycles", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x44", + "EventName": "UNC_U_LOCK_CYCLES", + "PerPkg": "1", + "Unit": "UBOX" + }, + { + "BriefDescription": "RACU Request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x46", + "EventName": "UNC_U_RACU_REQUESTS", + "PerPkg": "1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x16", + "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_UPI_PHY_INIT_CYCLES", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "L1 Req Nack", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_UPI_POWER_L1_NACK", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "L1 Req (same as L1 Ack)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x22", + "EventName": "UNC_UPI_POWER_L1_REQ", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Cycles in L0p", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x25", + "EventName": "UNC_UPI_RxL0P_POWER_CYCLES", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Cycles in L0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x24", + "EventName": "UNC_UPI_RxL0_POWER_CYCLES", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "CRC Errors Detected", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x0B", + "EventName": "UNC_UPI_RxL_CRC_ERRORS", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "LLR Requests Sent", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x08", + "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "VN0 Credit Consumed", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x39", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "VN1 Credit Consumed", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x3A", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "VNA Credit Consumed", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x28", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x29", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Cycles in L0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x26", + "EventName": "UNC_UPI_TxL0_POWER_CYCLES", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Tx Flit Buffer Bypassed", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x41", + "EventName": "UNC_UPI_TxL_BYPASSED", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Tx Flit Buffer Allocations", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x40", + "EventName": "UNC_UPI_TxL_INSERTS", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Tx Flit Buffer Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_UPI_TxL_OCCUPANCY", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x45", + "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "VNA Credits Pending Return - Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x44", + "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.ALL", + "PerPkg": "1", + "UMask": "0x1FFFFF", + "UMaskExt": "0x1FFF", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD", + "PerPkg": "1", + "UMask": "0x1bc1ff", + "UMaskExt": "0x1bc1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Flush or Invalidate Requests", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV", + "PerPkg": "1", + "UMask": "0x1A44FF", + "UMaskExt": "0x1A44", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE", + "PerPkg": "1", + "UMask": "0x1bd0ff", + "UMaskExt": "0x1bd0", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOC_HOM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCALLY_HOMED_ADDRESS", + "PerPkg": "1", + "UMask": "0x0bdfff", + "UMaskExt": "0x0bdf", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REM_HOM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTELY_HOMED_ADDRESS", + "PerPkg": "1", + "UMask": "0x15dfff", + "UMaskExt": "0x15df", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Flush or Invalidate requests that come from a Remote socket", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV_REMOTE", + "PerPkg": "1", + "UMask": "0x1A04FF", + "UMaskExt": "0x1A04", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Requests that come from a Remote socket", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_REMOTE", + "PerPkg": "1", + "UMask": "0x1A01FF", + "UMaskExt": "0x1A01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : RFO Requests that come from a Remote socket", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO_REMOTE", + "PerPkg": "1", + "UMask": "0x1A08FF", + "UMaskExt": "0x1A08", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE_REMOTE", + "PerPkg": "1", + "UMask": "0x1a10ff", + "UMaskExt": "0x1a10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Snoop Requests from a Remote Socket", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP", + "PerPkg": "1", + "UMask": "0x1C19FF", + "UMaskExt": "0x1C19", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Flush or Invalidate Requests that come from the local socket (usually the core)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV_LOCAL", + "PerPkg": "1", + "UMask": "0x1844FF", + "UMaskExt": "0x1844", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request that come from the local socket (usually the core)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL", + "PerPkg": "1", + "UMask": "0x19C1FF", + "UMaskExt": "0x19C1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : RFO Requests that come from the local socket (usually the core)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO_LOCAL", + "PerPkg": "1", + "UMask": "0x19C8FF", + "UMaskExt": "0x19C8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE_LOCAL", + "PerPkg": "1", + "UMask": "0x19d0ff", + "UMaskExt": "0x19d0", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LLC_PF_LOCAL", + "PerPkg": "1", + "UMask": "0x189dff", + "UMaskExt": "0x189d", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT", + "PerPkg": "1", + "UMask": "0xC827FD01", + "UMaskExt": "0xC827FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF", + "PerPkg": "1", + "UMask": "0xC8A7FD01", + "UMaskExt": "0xC8A7FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", + "PerPkg": "1", + "UMask": "0xC827FE01", + "UMaskExt": "0xC827FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", + "PerPkg": "1", + "UMask": "0xC8A7FE01", + "UMaskExt": "0xC8A7FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF", + "PerPkg": "1", + "UMask": "0xC88FFD01", + "UMaskExt": "0xC88FFD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF", + "PerPkg": "1", + "UMask": "0xC897FD01", + "UMaskExt": "0xC897FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT", + "PerPkg": "1", + "UMask": "0xC827FD01", + "UMaskExt": "0xC827FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF", + "PerPkg": "1", + "UMask": "0xC8A7FD01", + "UMaskExt": "0xC8A7FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF", + "PerPkg": "1", + "UMask": "0xC887FD01", + "UMaskExt": "0xC887FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF", + "PerPkg": "1", + "UMask": "0xC88FFE01", + "UMaskExt": "0xC88FFE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF", + "PerPkg": "1", + "UMask": "0xC897FE01", + "UMaskExt": "0xC897FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", + "PerPkg": "1", + "UMask": "0xC827FE01", + "UMaskExt": "0xC827FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF", + "PerPkg": "1", + "UMask": "0xC8A7FE01", + "UMaskExt": "0xC8A7FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF", + "PerPkg": "1", + "UMask": "0xC887FE01", + "UMaskExt": "0xC887FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO", + "PerPkg": "1", + "UMask": "0xC803FD04", + "UMaskExt": "0xC803FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM", + "PerPkg": "1", + "UMask": "0xCC43FD04", + "UMaskExt": "0xCC43FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO", + "PerPkg": "1", + "UMask": "0xC803FD04", + "UMaskExt": "0xC803FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by IO Devices", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", + "PerPkg": "1", + "UMask": "0xC803FF04", + "UMaskExt": "0xC803FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD", + "PerPkg": "1", + "UMask": "0xC817FF01", + "UMaskExt": "0xC817FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT", + "PerPkg": "1", + "UMask": "0xC827FF01", + "UMaskExt": "0xC827FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF", + "PerPkg": "1", + "UMask": "0xC8A7FF01", + "UMaskExt": "0xC8A7FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; CRd Pref from local IA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF", + "PerPkg": "1", + "UMask": "0xC88FFF01", + "UMaskExt": "0xC88FFF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO", + "PerPkg": "1", + "UMask": "0xC803FF04", + "UMaskExt": "0xC803FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM", + "PerPkg": "1", + "UMask": "0xCC43FF04", + "UMaskExt": "0xCC43FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF", + "PerPkg": "1", + "UMask": "0xC887FF01", + "UMaskExt": "0xC887FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO", + "PerPkg": "1", + "UMask": "0xCCC7FF01", + "UMaskExt": "0xCCC7FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT", + "PerPkg": "1", + "UMask": "0xC827FF01", + "UMaskExt": "0xC827FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF", + "PerPkg": "1", + "UMask": "0xC8A7FF01", + "UMaskExt": "0xC8A7FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; CRd Pref from local IA", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF", + "PerPkg": "1", + "UMask": "0xC88FFF01", + "UMaskExt": "0xC88FFF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF", + "PerPkg": "1", + "UMask": "0xC897FF01", + "UMaskExt": "0xC897FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL", + "PerPkg": "1", + "UMask": "0xC896FE01", + "UMaskExt": "0xC896FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE", + "PerPkg": "1", + "UMask": "0xC8977E01", + "UMaskExt": "0xC8977E", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL", + "PerPkg": "1", + "UMask": "0xC806FE01", + "UMaskExt": "0xC806FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE", + "PerPkg": "1", + "UMask": "0xC8077E01", + "UMaskExt": "0xC8077E", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL", + "PerPkg": "1", + "UMask": "0xC886FE01", + "UMaskExt": "0xC886FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE", + "PerPkg": "1", + "UMask": "0xC8877E01", + "UMaskExt": "0xC8877E", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CLFlushOpts issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT", + "PerPkg": "1", + "UMask": "0xC8D7FF01", + "UMaskExt": "0xC8D7FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM", + "PerPkg": "1", + "UMask": "0xCC47FF01", + "UMaskExt": "0xCC47FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI", + "PerPkg": "1", + "UMask": "0xCC23FF04", + "UMaskExt": "0xCC23FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH", + "PerPkg": "1", + "UMask": "0xC8C3FF04", + "UMaskExt": "0xC8C3FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI", + "PerPkg": "1", + "UMask": "0xcc27ff01", + "UMaskExt": "0xcc27ff", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_PMM", + "PerPkg": "1", + "UMask": "0xC8978A01", + "UMaskExt": "0xC8978A", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_PMM", + "PerPkg": "1", + "UMask": "0xC8968A01", + "UMaskExt": "0xC8968A", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_PMM", + "PerPkg": "1", + "UMask": "0xC8970A01", + "UMaskExt": "0xC8970A", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_PMM", + "PerPkg": "1", + "UMask": "0xc8678a01", + "UMaskExt": "0xc8678a", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_PMM", + "PerPkg": "1", + "UMask": "0xc8668a01", + "UMaskExt": "0xc8668a", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_PMM", + "PerPkg": "1", + "UMask": "0xc8670a01", + "UMaskExt": "0xc8670a", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_DRAM", + "PerPkg": "1", + "UMask": "0xC8678601", + "UMaskExt": "0xC86786", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_DRAM", + "PerPkg": "1", + "UMask": "0xC8668601", + "UMaskExt": "0xC86686", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_PMM", + "PerPkg": "1", + "UMask": "0xc86f8a01", + "UMaskExt": "0xc86f8a", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM", + "PerPkg": "1", + "UMask": "0xc86e8a01", + "UMaskExt": "0xc86e8a", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM", + "PerPkg": "1", + "UMask": "0xc86f0a01", + "UMaskExt": "0xc86f0a", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_DRAM", + "PerPkg": "1", + "UMask": "0xC86F8601", + "UMaskExt": "0xC86F86", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DRAM", + "PerPkg": "1", + "UMask": "0xC86E8601", + "UMaskExt": "0xC86E86", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM", + "PerPkg": "1", + "UMask": "0xC8168A01", + "UMaskExt": "0xC8168A", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM", + "PerPkg": "1", + "UMask": "0xC8170A01", + "UMaskExt": "0xC8170A", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_PMM", + "PerPkg": "1", + "UMask": "0xC8978A01", + "UMaskExt": "0xC8978A", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_PMM", + "PerPkg": "1", + "UMask": "0xC8968A01", + "UMaskExt": "0xC8968A", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_PMM", + "PerPkg": "1", + "UMask": "0xC8970A01", + "UMaskExt": "0xC8970A", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR", + "PerPkg": "1", + "UMask": "0xc867fe01", + "UMaskExt": "0xc867fe", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_PMM", + "PerPkg": "1", + "UMask": "0xc8678a01", + "UMaskExt": "0xc8678a", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_LOCAL_PMM", + "PerPkg": "1", + "UMask": "0xc8668a01", + "UMaskExt": "0xc8668a", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_REMOTE_PMM", + "PerPkg": "1", + "UMask": "0xc8670a01", + "UMaskExt": "0xc8670a", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiL misses from local IA", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR", + "PerPkg": "1", + "UMask": "0xc86ffe01", + "UMaskExt": "0xc86ffe", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiL misses from local IA", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_PMM", + "PerPkg": "1", + "UMask": "0xc86f8a01", + "UMaskExt": "0xc86f8a", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiL misses from local IA", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM", + "PerPkg": "1", + "UMask": "0xc86e8a01", + "UMaskExt": "0xc86e8a", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiL misses from local IA", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM", + "PerPkg": "1", + "UMask": "0xc86f0a01", + "UMaskExt": "0xc86f0a", + "Unit": "CHA" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "Counter": "1", + "CounterType": "FREERUN", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "Counter": "2", + "CounterType": "FREERUN", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "Counter": "3", + "CounterType": "FREERUN", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "Counter": "4", + "CounterType": "FREERUN", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "Counter": "5", + "CounterType": "FREERUN", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "Counter": "6", + "CounterType": "FREERUN", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "Counter": "7", + "CounterType": "FREERUN", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "Counter": "8", + "CounterType": "FREERUN", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "Counter": "9", + "CounterType": "FREERUN", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "Counter": "13", + "CounterType": "FREERUN", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "Counter": "12", + "CounterType": "FREERUN", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "Counter": "11", + "CounterType": "FREERUN", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "Counter": "10", + "CounterType": "FREERUN", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "Counter": "15", + "CounterType": "FREERUN", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "Counter": "14", + "CounterType": "FREERUN", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "Counter": "16", + "CounterType": "FREERUN", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", + "PerPkg": "1", + "UMask": "0xC86FFE01", + "UMaskExt": "0xC86FFE", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "UNC_M2P_TxC_CREDITS.PMM", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x2D", + "EventName": "UNC_M2P_TxC_CREDITS.PMM", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_1", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_0", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_1", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_0", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Distress signal asserted : PMM Local", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.PMM_LOCAL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Distress signal asserted : PMM Remote", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.PMM_NONLOCAL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cache Lookups : RFO Request Filter", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F", + "PerPkg": "1", + "UMaskExt": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Transactions homed locally Filter", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F", + "PerPkg": "1", + "UMaskExt": "0x800", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Transactions homed remotely Filter", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_F", + "PerPkg": "1", + "UMaskExt": "0x1000", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Remote snoop request Filter", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP_F", + "PerPkg": "1", + "UMaskExt": "0x400", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : All Request Filter", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F", + "PerPkg": "1", + "UMaskExt": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Data Read Request Filter", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F", + "PerPkg": "1", + "UMaskExt": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Write Request Filter", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F", + "PerPkg": "1", + "UMaskExt": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Flush or Invalidate Filter", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F", + "PerPkg": "1", + "UMaskExt": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : CRd Request Filter", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F", + "PerPkg": "1", + "UMaskExt": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Local request Filter", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F", + "PerPkg": "1", + "UMaskExt": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Local LLC prefetch requests (from LLC) Filter", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL_F", + "PerPkg": "1", + "UMaskExt": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Remote non-snoop request Filter", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.PREF_OR_DMND_REMOTE_F", + "PerPkg": "1", + "UMaskExt": "0x200", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : All Misses", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL", + "PerPkg": "1", + "UMask": "0x1fe001", + "UMaskExt": "0x1fe0", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL", + "PerPkg": "1", + "UMask": "0x1fc1ff", + "UMaskExt": "0x1fc1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Data Read Misses", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS", + "PerPkg": "1", + "UMask": "0x1bc101", + "UMaskExt": "0x1bc1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DMND_READ_LOCAL", + "PerPkg": "1", + "UMask": "0x841ff", + "UMaskExt": "0x841", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL", + "PerPkg": "1", + "UMask": "0x842ff", + "UMaskExt": "0x842", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.RFO_LOCAL", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO_PREF_LOCAL", + "PerPkg": "1", + "UMask": "0x888ff", + "UMaskExt": "0x888", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_REMOTE", + "PerPkg": "1", + "UMask": "0x17c2ff", + "UMaskExt": "0x17c2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : All transactions from Remote Agents", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.ALL_REMOTE", + "PerPkg": "1", + "UMask": "0x1e20ff", + "UMaskExt": "0x1e20", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal asserted : PMM Local", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_LOCAL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Distress signal asserted : PMM Remote", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_NONLOCAL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO1_NCB", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : IIO5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.UBOX_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M2M_DISTRESS_PMM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xF2", + "EventName": "UNC_M2M_DISTRESS_PMM", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_DISTRESS_PMM_MEMMODE", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xF1", + "EventName": "UNC_M2M_DISTRESS_PMM_MEMMODE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.ISOCH", + "PerPkg": "1", + "UMask": "0x0702", + "UMaskExt": "0x07", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : From TGR - All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.FROM_TGR", + "PerPkg": "1", + "UMask": "0x0740", + "UMaskExt": "0x07", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", + "PerPkg": "1", + "UMask": "0x1C04", + "UMaskExt": "0x1C", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", + "PerPkg": "1", + "UMask": "0x1C08", + "UMaskExt": "0x1C", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : DDR - All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_MEM", + "PerPkg": "1", + "UMask": "0x1C20", + "UMaskExt": "0x1C", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_CACHE", + "PerPkg": "1", + "UMask": "0x1C40", + "UMaskExt": "0x1C", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : From TGR - All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR", + "PerPkg": "1", + "UMaskExt": "0x1D", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.NI_MISS", + "PerPkg": "1", + "UMaskExt": "0x1C", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Full : All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6B", + "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH", + "PerPkg": "1", + "UMask": "0x07", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6C", + "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH", + "PerPkg": "1", + "UMask": "0x07", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped : XPT - All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6f", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH", + "PerPkg": "1", + "UMask": "0x15", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped : UPI - All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6f", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.UPI_ALLCH", + "PerPkg": "1", + "UMask": "0x2a", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Occupancy : All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6A", + "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH", + "PerPkg": "1", + "UMask": "0x07", + "Unit": "M2M" + }, + { + "BriefDescription": ": All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x76", + "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH", + "PerPkg": "1", + "UMask": "0x07", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : PMM - Ch0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH0_TO_PMM", + "PerPkg": "1", + "UMask": "0x0120", + "UMaskExt": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : DDR - Ch0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM", + "PerPkg": "1", + "UMask": "0x0108", + "UMaskExt": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - Ch0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE", + "PerPkg": "1", + "UMask": "0x0110", + "UMaskExt": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : PMM - Ch1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH1_TO_PMM", + "PerPkg": "1", + "UMask": "0x0220", + "UMaskExt": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : DDR - Ch1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM", + "PerPkg": "1", + "UMask": "0x0208", + "UMaskExt": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - Ch1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE", + "PerPkg": "1", + "UMask": "0x0210", + "UMaskExt": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : DDR - All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_MEM", + "PerPkg": "1", + "UMask": "0x0708", + "UMaskExt": "0x07", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_CACHE", + "PerPkg": "1", + "UMask": "0x0710", + "UMaskExt": "0x07", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : PMM - Ch0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_PMM", + "PerPkg": "1", + "UMask": "0x0480", + "UMaskExt": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : DDR - Ch0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM", + "PerPkg": "1", + "UMask": "0x0420", + "UMaskExt": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - Ch0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_CACHE", + "PerPkg": "1", + "UMask": "0x0440", + "UMaskExt": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : PMM - Ch1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_PMM", + "PerPkg": "1", + "UMask": "0x0880", + "UMaskExt": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : DDR - Ch1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_MEM", + "PerPkg": "1", + "UMask": "0x0820", + "UMaskExt": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - Ch1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_CACHE", + "PerPkg": "1", + "UMask": "0x0840", + "UMaskExt": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4F", + "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4F", + "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4F", + "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x51", + "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x51", + "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x51", + "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x7A", + "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Distress signal asserted : PMM Local", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_LOCAL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Distress signal asserted : PMM Remote", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_NONLOCAL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6d", + "EventName": "UNC_M2M_PREFCAM_INSERTS.UPI_ALLCH", + "PerPkg": "1", + "UMask": "0x2a", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x6D", + "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH", + "PerPkg": "1", + "UMask": "0x15", + "Unit": "M2M" + }, + { + "BriefDescription": ": PWC Hit to a 4K page", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_4K_HITS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": ": PWC Hit to a 2M page", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": ": PWC Hit to a 1G page", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": ": PWT Hit to a 256T page", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": ": PageWalk cache fill", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": ": Global IOTLB invalidation cycles", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_GBL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": ": Domain-selective IOTLB invalidation cycles", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_DOMAIN", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": ": Page-selective IOTLB invalidation cycles", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PAGE", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": ": Context cache global invalidation cycles", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_GBL", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": ": Domain-selective Context cache invalidation cycles", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DOMAIN", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": ": Device-selective Context cache invalidation cycles", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DEVICE", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : MsgB", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Multi-cast", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Ubox", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Memory", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Remote P2P", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Local P2P", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Confined P2P", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Abort", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "ITC address map 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x8F", + "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": ": Issuing to IOMMU", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": ": Processing response from IOMMU", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": ": Request Ownership", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": ": Issuing final read or write of line", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": ": Writing line", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": ": Passing data to be written", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Occupancy of outbound request queue : To device", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC5", + "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request - cacheline complete : Request Ownership", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x91", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN", + "FCMask": "0x07", "PerPkg": "1", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x04", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC", + "BriefDescription": "PCIe Request - cacheline complete : Issuing final read or write of line", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", + "EventCode": "0x91", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC88FFD01", - "UMaskExt": "0xC88FFD", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x08", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC", + "BriefDescription": "PCIe Request - cacheline complete : Writing line", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF", + "EventCode": "0x91", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC897FD01", - "UMaskExt": "0xC897FD", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x10", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC", + "BriefDescription": "PCIe Request - cacheline complete : Passing data to be written", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", + "EventCode": "0x91", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC887FD01", - "UMaskExt": "0xC887FD", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x20", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC", + "BriefDescription": "PCIe Request complete : Issuing to IOMMU", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC88FFE01", - "UMaskExt": "0xC88FFE", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x01", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC", + "BriefDescription": "PCIe Request complete : Processing response from IOMMU", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC897FE01", - "UMaskExt": "0xC897FE", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x02", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC", + "BriefDescription": "PCIe Request complete : Request Ownership", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC887FE01", - "UMaskExt": "0xC887FE", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x04", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", + "BriefDescription": "PCIe Request complete : Issuing final read or write of line", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xCC43FD04", - "UMaskExt": "0xCC43FD", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x08", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices", + "BriefDescription": "PCIe Request complete : Writing line", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.WR", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xCC43FF04", - "UMaskExt": "0xCC43FF", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x10", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores", + "BriefDescription": "PCIe Request complete : Passing data to be written", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.DATA", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC887FF01", - "UMaskExt": "0xC887FF", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x20", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores", + "BriefDescription": "PCIe Request - pass complete : Request Ownership", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", + "EventCode": "0x90", + "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC807FF01", - "UMaskExt": "0xC807FF", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x04", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores", + "BriefDescription": "PCIe Request - pass complete : Issuing final read or write of line", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO", + "EventCode": "0x90", + "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xCCC7FF01", - "UMaskExt": "0xCCC7FF", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x08", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores", + "BriefDescription": "PCIe Request - pass complete : Writing line", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF", + "EventCode": "0x90", + "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC897FF01", - "UMaskExt": "0xC897FF", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x10", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : CRDs issued by iA Cores", + "BriefDescription": "PCIe Request - pass complete : Passing data to be written", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", + "EventCode": "0x90", + "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC80FFF01", - "UMaskExt": "0xC80FFF", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x20", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores", + "BriefDescription": "Incoming arbitration requests : Issuing to IOMMU", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC807FF01", - "UMaskExt": "0xC807FF", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x01", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores", + "BriefDescription": "Incoming arbitration requests : Processing response from IOMMU", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC817FF01", - "UMaskExt": "0xC817FF", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x02", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores", + "BriefDescription": "Incoming arbitration requests : Request Ownership", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC80FFF01", - "UMaskExt": "0xC80FFF", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x04", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally", + "BriefDescription": "Incoming arbitration requests : Issuing final read or write of line", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC816FE01", - "UMaskExt": "0xC816FE", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x08", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely", + "BriefDescription": "Incoming arbitration requests : Writing line", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC8177E01", - "UMaskExt": "0xC8177E", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x10", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally", + "BriefDescription": "Incoming arbitration requests : Passing data to be written", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC816FE01", - "UMaskExt": "0xC816FE", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests granted : Issuing to IOMMU", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x01", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely", + "BriefDescription": "Incoming arbitration requests granted : Processing response from IOMMU", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC8177E01", - "UMaskExt": "0xC8177E", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x02", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts; DRd Pref misses from local IA", + "BriefDescription": "Incoming arbitration requests granted : Request Ownership", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC896FE01", - "UMaskExt": "0xC896FE", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x04", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts; DRd Pref misses from local IA", + "BriefDescription": "Incoming arbitration requests granted : Issuing final read or write of line", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC8977E01", - "UMaskExt": "0xC8977E", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x08", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally", + "BriefDescription": "Incoming arbitration requests granted : Writing line", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.WR", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC806FE01", - "UMaskExt": "0xC806FE", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x10", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely", + "BriefDescription": "Incoming arbitration requests granted : Passing data to be written", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC8077E01", - "UMaskExt": "0xC8077E", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x20", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally", + "BriefDescription": "Outbound cacheline requests issued : 64B requests issued to device", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL", + "EventCode": "0xD0", + "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC886FE01", - "UMaskExt": "0xC886FE", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x08", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", + "BriefDescription": "Outbound TLP (transaction layer packet) requests issued : To device", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE", + "EventCode": "0xD1", + "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC8877E01", - "UMaskExt": "0xC8877E", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x08", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores", + "BriefDescription": "Number requests sent to PCIe from main die : From IRP", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", + "EventCode": "0xC2", + "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.IRP", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC8C7FF01", - "UMaskExt": "0xC8C7FF", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x01", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores", + "BriefDescription": "Number requests sent to PCIe from main die : From ITC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM", + "EventCode": "0xC2", + "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.ITC", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xCC57FF01", - "UMaskExt": "0xCC57FF", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x02", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices", + "BriefDescription": "Number requests sent to PCIe from main die : Completion allocations", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "EventCode": "0xc2", + "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.PREALLOC", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xCD43FF04", - "UMaskExt": "0xCD43FF", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x04", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF", "PerPkg": "1", - "UMask": "0xCD43FD04", - "UMaskExt": "0xCD43FD", + "UMask": "0xC867FF01", + "UMaskExt": "0xC867FF", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL", "PerPkg": "1", - "UMask": "0xCD43FE04", - "UMaskExt": "0xCD43FE", + "UMask": "0xC86FFF01", + "UMaskExt": "0xC86FFF", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC", + "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL", "PerPkg": "1", - "UMask": "0xC8178A01", - "UMaskExt": "0xC8178A", + "UMask": "0xC87FDE01", + "UMaskExt": "0xC87FDE", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", + "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL", "PerPkg": "1", - "UMask": "0xC8168A01", - "UMaskExt": "0xC8168A", + "UMask": "0xC80EFE01", + "UMaskExt": "0xC80EFE", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", + "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE", "PerPkg": "1", - "UMask": "0xC8170A01", - "UMaskExt": "0xC8170A", + "UMask": "0xC80F7E01", + "UMaskExt": "0xC80F7E", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL", "PerPkg": "1", - "UMask": "0xc867fe01", - "UMaskExt": "0xc867fe", + "UMask": "0xC88EFE01", + "UMaskExt": "0xC88EFE", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE", "PerPkg": "1", - "UMask": "0xc86ffe01", - "UMaskExt": "0xc86ffe", + "UMask": "0xC88F7E01", + "UMaskExt": "0xC88F7E", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC", + "BriefDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR", "PerPkg": "1", - "UMask": "0xC8178A01", - "UMaskExt": "0xC8178A", + "UMask": "0xCD47FF01", + "UMaskExt": "0xCD47FF", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC", + "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM", "PerPkg": "1", - "UMask": "0xCCD7FE01", - "UMaskExt": "0xCCD7FE", + "UMask": "0xCC47FD01", + "UMaskExt": "0xCC47FD", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC", + "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM", "PerPkg": "1", - "UMask": "0xC8F3FE04", - "UMaskExt": "0xC8F3FE", + "UMask": "0xCC47FE01", + "UMaskExt": "0xCC47FE", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC", + "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF", "PerPkg": "1", - "UMask": "0xc8f3fe04", - "UMaskExt": "0xc8f3fe", + "UMask": "0xC877DE01", + "UMaskExt": "0xC877DE", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC", + "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE", "PerPkg": "1", - "UMask": "0xC8178601", - "UMaskExt": "0xC81786", + "UMask": "0xCCCFFF01", + "UMaskExt": "0xCCCFFF", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", + "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in TOR", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR", + "EventCode": "0x64", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR", "PerPkg": "1", - "UMask": "0xC8168601", - "UMaskExt": "0xC81686", + "UMask": "0x04", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", + "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR", + "EventCode": "0x64", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF", "PerPkg": "1", - "UMask": "0xC8170601", - "UMaskExt": "0xC81706", + "UMask": "0x01", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC", + "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", + "EventCode": "0x64", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC", "PerPkg": "1", - "UMask": "0xC8178601", - "UMaskExt": "0xC81786", + "UMask": "0x02", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC", + "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE", "PerPkg": "1", - "UMask": "0xC8F3FD04", - "UMaskExt": "0xC8F3FD", + "UMask": "0xCCCFFD01", + "UMaskExt": "0xCCCFFD", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices", + "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA", "PerPkg": "1", - "UMask": "0xC8F3FF04", - "UMaskExt": "0xC8F3FF", + "UMask": "0xCCD7FD01", + "UMaskExt": "0xCCD7FD", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores", + "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE", "PerPkg": "1", - "UMask": "0xCCD7FF01", - "UMaskExt": "0xCCD7FF", + "UMask": "0xCCCFFE01", + "UMaskExt": "0xCCCFFE", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices", + "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC", "CounterType": "PGMABLE", "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE", "PerPkg": "1", - "UMask": "0xC8F3FF04", - "UMaskExt": "0xC8F3FF", + "UMask": "0xCCCFFD01", + "UMaskExt": "0xCCCFFD", "Unit": "CHA" }, { - "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC", "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA", "PerPkg": "1", - "UMask": "0x1BC1FF", - "UMaskExt": "0x1BC1", + "UMask": "0xCCD7FD01", + "UMaskExt": "0xCCD7FD", "Unit": "CHA" }, { - "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x01", - "EventName": "UNC_IIO_CLOCKTICKS", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "Counter": "0,1", + "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xCCCFFE01", + "UMaskExt": "0xCCCFFE", + "Unit": "CHA" }, { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "Counter": "0,1", + "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xCCD7FE01", + "UMaskExt": "0xCCD7FE", + "Unit": "CHA" }, { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "Counter": "0,1", + "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", + "EventCode": "0x65", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL", "PerPkg": "1", - "PortMask": "0x04", "UMask": "0x01", - "Unit": "IIO" + "Unit": "CHA" }, { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "Counter": "0,1", + "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", + "EventCode": "0x65", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x02", + "Unit": "CHA" }, { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "Counter": "0,1", + "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", - "FCMask": "0x07", + "EventCode": "0x65", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT", "PerPkg": "1", - "PortMask": "0x01", "UMask": "0x04", - "Unit": "IIO" + "Unit": "CHA" }, { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "Counter": "0,1", + "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", - "FCMask": "0x07", + "EventCode": "0x70", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x01", + "Unit": "CHA" }, { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "Counter": "0,1", + "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", - "FCMask": "0x07", + "EventCode": "0x70", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x02", + "Unit": "CHA" }, { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "Counter": "0,1", + "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "FCMask": "0x07", + "EventCode": "0x70", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI", "PerPkg": "1", - "PortMask": "0x08", "UMask": "0x04", - "Unit": "IIO" + "Unit": "CHA" }, { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "Counter": "0,1", + "BriefDescription": "UNC_CHA_PMM_QOS.SLOW_INSERT", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0", - "FCMask": "0x07", + "EventCode": "0x66", + "EventName": "UNC_CHA_PMM_QOS.SLOW_INSERT", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x80", - "Unit": "IIO" + "UMask": "0x01", + "Unit": "CHA" }, { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "Counter": "0,1", + "BriefDescription": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1", - "FCMask": "0x07", + "EventCode": "0x66", + "EventName": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x80", - "Unit": "IIO" + "UMask": "0x02", + "Unit": "CHA" }, { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "Counter": "0,1", + "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2", - "FCMask": "0x07", + "EventCode": "0x66", + "EventName": "UNC_CHA_PMM_QOS.THROTTLE", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x80", - "Unit": "IIO" + "UMask": "0x04", + "Unit": "CHA" }, { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "Counter": "0,1", + "BriefDescription": "UNC_CHA_PMM_QOS.REJ_IRQ", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3", - "FCMask": "0x07", + "EventCode": "0x66", + "EventName": "UNC_CHA_PMM_QOS.REJ_IRQ", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x80", - "Unit": "IIO" + "UMask": "0x08", + "Unit": "CHA" }, { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "Counter": "2,3", + "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_PRQ", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", + "EventCode": "0x66", + "EventName": "UNC_CHA_PMM_QOS.THROTTLE_PRQ", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x10", + "Unit": "CHA" }, { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "Counter": "2,3", + "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_IRQ", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", + "EventCode": "0x66", + "EventName": "UNC_CHA_PMM_QOS.THROTTLE_IRQ", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x20", + "Unit": "CHA" }, { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "Counter": "2,3", + "BriefDescription": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", + "EventCode": "0x66", + "EventName": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x40", + "Unit": "CHA" }, { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "Counter": "2,3", + "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", + "EventCode": "0x67", + "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO", "PerPkg": "1", - "PortMask": "0x08", "UMask": "0x01", - "Unit": "IIO" + "Unit": "CHA" }, { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "Counter": "2,3", + "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", - "FCMask": "0x07", + "EventCode": "0x67", + "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x02", + "Unit": "CHA" }, { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "Counter": "2,3", + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", - "FCMask": "0x07", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.IRQ_PMM", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x20", + "Unit": "CHA" }, { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "Counter": "2,3", + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", - "FCMask": "0x07", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.PRQ_PMM", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x40", + "Unit": "CHA" }, { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "Counter": "2,3", + "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", - "FCMask": "0x07", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.PMM_MEMMODE_TOR_MATCH", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x04", - "Unit": "IIO" + "UMaskExt": "0x08", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "BriefDescription": "Pipe Rejects", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.PMM_MEMMODE_TORMATCH_MULTI", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x01", - "Unit": "IIO" + "UMaskExt": "0x400", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "BriefDescription": "TOR Inserts : PMM Access", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PMM", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x01", - "Unit": "IIO" + "UMaskExt": "0x08", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : PMM Access", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PMM", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x01", - "Unit": "IIO" + "UMaskExt": "0x08", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "BriefDescription": "Distress signal asserted : PMM Local", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.PMM_LOCAL", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x10", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "BriefDescription": "Distress signal asserted : PMM Remote", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", - "FCMask": "0x07", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.PMM_NONLOCAL", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x20", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0xC8678A01", + "UMaskExt": "0xC8678A", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0xC8668A01", + "UMaskExt": "0xC8668A", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remote memory", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0xC8670A01", + "UMaskExt": "0xC8670A", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x80", - "Unit": "IIO" + "UMask": "0xC86F8A01", + "UMaskExt": "0xC86F8A", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x80", - "Unit": "IIO" + "UMask": "0xC86E8A01", + "UMaskExt": "0xC86E8A", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x80", - "Unit": "IIO" + "UMask": "0xC86F0A01", + "UMaskExt": "0xC86F0A", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x80", - "Unit": "IIO" + "UMask": "0xC8678A01", + "UMaskExt": "0xC8678A", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally", "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xC8668A01", + "UMaskExt": "0xC8668A", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely", "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xC8670A01", + "UMaskExt": "0xC8670A", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC", "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xC86F8A01", + "UMaskExt": "0xC86F8A", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally", "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xC86E8A01", + "UMaskExt": "0xC86E8A", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely", "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0xC86F0A01", + "UMaskExt": "0xC86F0A", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "BriefDescription": "TOR Inserts : DDR4 Access", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.DDR", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x04", - "Unit": "IIO" + "UMaskExt": "0x04", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : DDR4 Access", "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x04", - "Unit": "IIO" + "UMaskExt": "0x04", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0xC8978601", + "UMaskExt": "0xC89786", + "Unit": "CHA" }, { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "Counter": "2,3", + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xC8968601", + "UMaskExt": "0xC89686", + "Unit": "CHA" }, { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "Counter": "2,3", + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xC8970601", + "UMaskExt": "0xC89706", + "Unit": "CHA" }, { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "Counter": "2,3", + "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xC8678601", + "UMaskExt": "0xC86786", + "Unit": "CHA" }, { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "Counter": "2,3", + "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xC8668601", + "UMaskExt": "0xC86686", + "Unit": "CHA" }, { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "Counter": "2,3", + "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0xC8670601", + "UMaskExt": "0xC86706", + "Unit": "CHA" }, { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "Counter": "2,3", + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0xC86F8601", + "UMaskExt": "0xC86F86", + "Unit": "CHA" }, { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "Counter": "2,3", + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0xC86E8601", + "UMaskExt": "0xC86E86", + "Unit": "CHA" }, { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "Counter": "2,3", + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0xC86F0601", + "UMaskExt": "0xC86F06", + "Unit": "CHA" }, { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "Counter": "0,1", + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xC8168601", + "UMaskExt": "0xC81686", + "Unit": "CHA" }, { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "Counter": "0,1", + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xC8170601", + "UMaskExt": "0xC81706", + "Unit": "CHA" }, { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "Counter": "0,1", + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xC8978601", + "UMaskExt": "0xC89786", + "Unit": "CHA" }, { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "Counter": "0,1", + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xC8968601", + "UMaskExt": "0xC89686", + "Unit": "CHA" }, { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "Counter": "0,1", + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0xC8970601", + "UMaskExt": "0xC89706", + "Unit": "CHA" }, { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "Counter": "0,1", + "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0xC8678601", + "UMaskExt": "0xC86786", + "Unit": "CHA" }, - { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", - "FCMask": "0x07", + { + "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0xC8668601", + "UMaskExt": "0xC86686", + "Unit": "CHA" }, { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "Counter": "0,1", + "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0xC8670601", + "UMaskExt": "0xC86706", + "Unit": "CHA" }, { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "Counter": "0,1", + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x80", - "Unit": "IIO" + "UMask": "0xC86F8601", + "UMaskExt": "0xC86F86", + "Unit": "CHA" }, { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "Counter": "0,1", + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x80", - "Unit": "IIO" + "UMask": "0xC86E8601", + "UMaskExt": "0xC86E86", + "Unit": "CHA" }, { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "Counter": "0,1", + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x80", - "Unit": "IIO" + "UMask": "0xC86F0601", + "UMaskExt": "0xC86F06", + "Unit": "CHA" }, { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "Counter": "0,1", + "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC", "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x80", - "Unit": "IIO" + "UMask": "0xC8F3FD04", + "UMaskExt": "0xC8F3FD", + "Unit": "CHA" }, { - "BriefDescription": "Number requests PCIe makes of the main die : All", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores", "CounterType": "PGMABLE", - "EventCode": "0x85", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xCCD7FF01", + "UMaskExt": "0xCCD7FF", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", - "FCMask": "0x07", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xC867FE01", + "UMaskExt": "0xC867FE", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC", "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xC867FE01", + "UMaskExt": "0xC867FE", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC", "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xC86FFE01", + "UMaskExt": "0xC86FFE", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally", "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xC80EFE01", + "UMaskExt": "0xC80EFE", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely", "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0xC80F7E01", + "UMaskExt": "0xC80F7E", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally", "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0xC88EFE01", + "UMaskExt": "0xC88EFE", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0xC88F7E01", + "UMaskExt": "0xC88F7E", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores", "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0xC8C7FF01", + "UMaskExt": "0xC8C7FF", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xC8D7FF01", + "UMaskExt": "0xC8D7FF", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xCD47FF01", + "UMaskExt": "0xCD47FF", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xCC57FF01", + "UMaskExt": "0xCC57FF", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xCC27FF01", + "UMaskExt": "0xCC27FF", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0xCC47FF01", + "UMaskExt": "0xCC47FF", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0xCC47FD01", + "UMaskExt": "0xCC47FD", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0xCC47FE01", + "UMaskExt": "0xCC47FE", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0xC877DE01", + "UMaskExt": "0xC877DE", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x80", - "Unit": "IIO" + "UMask": "0xC87FDE01", + "UMaskExt": "0xC87FDE", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x80", - "Unit": "IIO" + "UMask": "0xC867FF01", + "UMaskExt": "0xC867FF", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x80", - "Unit": "IIO" + "UMask": "0xC86FFF01", + "UMaskExt": "0xC86FFF", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores", "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7", - "FCMask": "0x07", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x80", - "Unit": "IIO" + "UMask": "0xCCCFFF01", + "UMaskExt": "0xCCCFFF", + "Unit": "CHA" }, { - "BriefDescription": "Free running counter that increments for IIO clocktick", - "CounterType": "FREERUN", - "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", + "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI", "PerPkg": "1", - "Unit": "IIO" + "UMask": "0xCC23FF04", + "UMaskExt": "0xCC23FF", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices", "CounterType": "PGMABLE", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", - "FCMask": "0x04", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x03", - "Unit": "IIO" + "UMask": "0xC8C3FF04", + "UMaskExt": "0xC8C3FF", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices", "CounterType": "PGMABLE", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", - "FCMask": "0x04", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x03", - "Unit": "IIO" + "UMask": "0xCD43FF04", + "UMaskExt": "0xCD43FF", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", "CounterType": "PGMABLE", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", - "FCMask": "0x04", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x03", - "Unit": "IIO" + "UMask": "0xCD43FD04", + "UMaskExt": "0xCD43FD", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", - "Counter": "0,1,2,3", + "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", "CounterType": "PGMABLE", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", - "FCMask": "0x04", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x03", - "Unit": "IIO" + "UMask": "0xCD43FE04", + "UMaskExt": "0xCD43FE", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4", + "BriefDescription": "TOR Inserts; WCiLF misses from local IA", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", - "FCMask": "0x04", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_DDR", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x03", - "Unit": "IIO" + "UMask": "0xc8678601", + "UMaskExt": "0xc86786", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5", + "BriefDescription": "TOR Inserts; WCiLF misses from local IA", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", - "FCMask": "0x04", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_DDR", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x03", - "Unit": "IIO" + "UMask": "0xc8668601", + "UMaskExt": "0xc86686", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6", + "BriefDescription": "TOR Inserts; WCiLF misses from local IA", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", - "FCMask": "0x04", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_DDR", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x03", - "Unit": "IIO" + "UMask": "0xc8670601", + "UMaskExt": "0xc86706", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7", + "BriefDescription": "TOR Inserts; WCiL misses from local IA", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", - "FCMask": "0x04", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_DDR", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x03", - "Unit": "IIO" + "UMask": "0xc86f8601", + "UMaskExt": "0xc86f86", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0", - "Counter": "2,3", + "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", - "FCMask": "0x04", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR", "PerPkg": "1", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0xc86e8601", + "UMaskExt": "0xc86e86", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 7", - "Counter": "2,3", + "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", - "FCMask": "0x04", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR", "PerPkg": "1", - "UMask": "0x80", - "Unit": "IIO" + "UMask": "0xc86f0601", + "UMaskExt": "0xc86f06", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 6", - "Counter": "2,3", + "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", "CounterType": "PGMABLE", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", - "FCMask": "0x04", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_DDR", "PerPkg": "1", - "UMask": "0x40", - "Unit": "IIO" + "UMask": "0xc8678601", + "UMaskExt": "0xc86786", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 5", - "Counter": "2,3", + "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", "CounterType": "PGMABLE", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", - "FCMask": "0x04", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_LOCAL_DDR", "PerPkg": "1", - "UMask": "0x20", - "Unit": "IIO" + "UMask": "0xc8668601", + "UMaskExt": "0xc86686", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4", - "Counter": "2,3", + "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", "CounterType": "PGMABLE", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", - "FCMask": "0x04", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_REMOTE_DDR", "PerPkg": "1", - "UMask": "0x10", - "Unit": "IIO" + "UMask": "0xc8670601", + "UMaskExt": "0xc86706", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 3", - "Counter": "2,3", + "BriefDescription": "TOR Occupancy; WCiL misses from local IA", "CounterType": "PGMABLE", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", - "FCMask": "0x04", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_DDR", "PerPkg": "1", - "UMask": "0x08", - "Unit": "IIO" + "UMask": "0xc86f8601", + "UMaskExt": "0xc86f86", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 2", - "Counter": "2,3", + "BriefDescription": "TOR Occupancy; WCiL misses from local IA", "CounterType": "PGMABLE", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", - "FCMask": "0x04", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR", "PerPkg": "1", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0xc86e8601", + "UMaskExt": "0xc86e86", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 1", - "Counter": "2,3", + "BriefDescription": "TOR Occupancy; WCiL misses from local IA", "CounterType": "PGMABLE", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", - "FCMask": "0x04", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR", "PerPkg": "1", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0xc86f0601", + "UMaskExt": "0xc86f06", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7", + "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", - "FCMask": "0x04", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE", "PerPkg": "1", - "PortMask": "0xff", - "UMask": "0x03", - "Unit": "IIO" + "UMask": "0xcc3fff01", + "UMaskExt": "0xcc3fff", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7", - "Counter": "2,3", + "BriefDescription": "Responses to snoops of any type that miss the IIO cache", + "Counter": "0,1", "CounterType": "PGMABLE", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", - "FCMask": "0x04", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", "PerPkg": "1", - "UMask": "0xff", - "Unit": "IIO" + "UMask": "0x71", + "Unit": "IRP" }, { - "BriefDescription": "Misc Events - Set 1 : Lost Forward", + "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO", "Counter": "0,1", "CounterType": "PGMABLE", - "EventCode": "0x1F", - "EventName": "UNC_I_MISC1.LOST_FWD", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x7e", "Unit": "IRP" }, { - "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline", + "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache", "Counter": "0,1", "CounterType": "PGMABLE", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.PCITOM", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x74", "Unit": "IRP" }, { - "BriefDescription": "Coherent Ops : WbMtoI", + "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache", "Counter": "0,1", "CounterType": "PGMABLE", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.WBMTOI", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x72", "Unit": "IRP" }, { - "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory", - "Counter": "0,1", + "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores that missed the LLC", "CounterType": "PGMABLE", - "EventCode": "0x0f", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_SPECITOM", "PerPkg": "1", - "UMask": "0x04", - "Unit": "IRP" + "UMask": "0xcc57fe01", + "UMaskExt": "0xcc57fe", + "Unit": "CHA" }, { - "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)", - "Counter": "0,1", + "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x20", - "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_SPECITOM", + "PerPkg": "1", + "UMask": "0xcc57fe01", + "UMaskExt": "0xcc57fe", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE", + "PerPkg": "1", + "UMask": "0xC837FE01", + "UMaskExt": "0xC837FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE", + "PerPkg": "1", + "UMask": "0xC837FD01", + "UMaskExt": "0xC837FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE", "PerPkg": "1", - "UMask": "0x01", - "Unit": "IRP" + "UMask": "0xC837FF01", + "UMaskExt": "0xC837FF", + "Unit": "CHA" }, { - "BriefDescription": "Inbound write (fast path) requests received by the IRP", - "Counter": "0,1", + "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores that hit in the LLC", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_SPECITOM", "PerPkg": "1", - "UMask": "0x08", - "Unit": "IRP" + "UMask": "0xcc57fd01", + "UMaskExt": "0xcc57fd", + "Unit": "CHA" }, { - "BriefDescription": "Clockticks of the IO coherency tracker (IRP)", - "Counter": "0,1", + "BriefDescription": "TOR Inserts : WBStoIs issued by an IA Core. Non Modified Write Backs", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x01", - "EventName": "UNC_I_CLOCKTICKS", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI", "PerPkg": "1", - "Unit": "IRP" + "UMask": "0xcc67ff01", + "UMaskExt": "0xcc67ff", + "Unit": "CHA" }, { - "BriefDescription": "FAF RF full", - "Counter": "0,1", + "BriefDescription": "TOR Inserts : WBEFtoIs issued by an IA Core. Non Modified Write Backs", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x17", - "EventName": "UNC_I_FAF_FULL", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI", "PerPkg": "1", - "Unit": "IRP" + "UMask": "0xcc37ff01", + "UMaskExt": "0xcc37ff", + "Unit": "CHA" }, { - "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue", - "Counter": "0,1", + "BriefDescription": "TOR Inserts : WBMtoEs issued by an IA Core. Non Modified Write Backs", + "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x18", - "EventName": "UNC_I_FAF_INSERTS", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE", "PerPkg": "1", - "Unit": "IRP" + "UMask": "0xcc2fff01", + "UMaskExt": "0xcc2fff", + "Unit": "CHA" }, { - "BriefDescription": "Occupancy of the IRP FAF queue", - "Counter": "0,1", + "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk", "CounterType": "PGMABLE", - "EventCode": "0x19", - "EventName": "UNC_I_FAF_OCCUPANCY", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE", "PerPkg": "1", - "Unit": "IRP" + "UMask": "0xC837FF01", + "UMaskExt": "0xC837FF", + "Unit": "CHA" }, { - "BriefDescription": "FAF allocation -- sent to ADQ", - "Counter": "0,1", + "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC", "CounterType": "PGMABLE", - "EventCode": "0x16", - "EventName": "UNC_I_FAF_TRANSACTIONS", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE", "PerPkg": "1", - "Unit": "IRP" + "UMask": "0xC837FD01", + "UMaskExt": "0xC837FD", + "Unit": "CHA" }, { - "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache", - "Counter": "0,1", + "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC", "CounterType": "PGMABLE", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE", "PerPkg": "1", - "UMask": "0x78", - "Unit": "IRP" + "UMask": "0xC837FE01", + "UMaskExt": "0xC837FE", + "Unit": "CHA" }, { - "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in any state", + "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", + "EventCode": "0x77", + "EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY", "PerPkg": "1", - "UMask": "0x01", "Unit": "M2M" }, { - "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in A state", + "BriefDescription": "Cache Lookups : Code Read Misses", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_MISS", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M2M" + "UMask": "0x1BD001", + "UMaskExt": "0x1BD0", + "Unit": "CHA" }, { - "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in I state", + "BriefDescription": "Cache Lookups : RFO Misses", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO_MISS", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "UMask": "0x1BC801", + "UMaskExt": "0x1BC8", + "Unit": "CHA" }, { - "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in S state", + "BriefDescription": "Cache Lookups : Reads", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2M" + "UMask": "0x1BD9FF", + "UMaskExt": "0x1BD9", + "Unit": "CHA" }, { - "BriefDescription": "Tag Hit : Clean NearMem Read Hit", + "BriefDescription": "Cache Lookups : Read Misses", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x2C", - "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "UMask": "0x1BD901", + "UMaskExt": "0x1BD9", + "Unit": "CHA" }, { - "BriefDescription": "Tag Hit : Dirty NearMem Read Hit", + "BriefDescription": "Cache Lookups : Locally HOMed Read Misses", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x2C", - "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_LOC_HOM", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "UMask": "0x0BD901", + "UMaskExt": "0x0BD9", + "Unit": "CHA" }, { - "BriefDescription": "Clockticks of the mesh to memory (M2M)", + "BriefDescription": "Cache Lookups : Remotely HOMed Read Misses", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventName": "UNC_M2M_CLOCKTICKS", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_REM_HOM", "PerPkg": "1", - "Unit": "M2M" + "UMask": "0x13D901", + "UMaskExt": "0x13D9", + "Unit": "CHA" }, { - "BriefDescription": "CMS Clockticks", + "BriefDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xc0", - "EventName": "UNC_M2M_CMS_CLOCKTICKS", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_LOC_HOM", "PerPkg": "1", - "Unit": "M2M" + "UMask": "0x09D9FF", + "UMaskExt": "0x09D9", + "Unit": "CHA" }, { - "BriefDescription": "M2M Reads Issued to iMC : PMM - All Channels", + "BriefDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.TO_PMM", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_REMOTE_LOC_HOM", "PerPkg": "1", - "UMask": "0x0720", - "UMaskExt": "0x07", - "Unit": "M2M" + "UMask": "0x0A19FF", + "UMaskExt": "0x0A19", + "Unit": "CHA" }, { - "BriefDescription": "M2M Writes Issued to iMC : PMM - All Channels", + "BriefDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.TO_PMM", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_REM_HOM", "PerPkg": "1", - "UMask": "0x1C80", - "UMaskExt": "0x1C", - "Unit": "M2M" + "UMask": "0x11D9FF", + "UMaskExt": "0x11D9", + "Unit": "CHA" }, { - "BriefDescription": "Clockticks of the mesh to PCI (M2P)", + "BriefDescription": "Cache Lookups : Reads that Hit the Snoop Filter", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x01", - "EventName": "UNC_M2P_CLOCKTICKS", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_SF_HIT", "PerPkg": "1", - "Unit": "M2PCIe" + "UMask": "0x1BD90E", + "UMaskExt": "0x1BD9", + "Unit": "CHA" }, { - "BriefDescription": "CMS Clockticks", + "BriefDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0xc0", - "EventName": "UNC_M2P_CMS_CLOCKTICKS", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_OR_SNOOP_REMOTE_MISS_REM_HOM", "PerPkg": "1", - "Unit": "M2PCIe" + "UMask": "0x161901", + "UMaskExt": "0x1619", + "Unit": "CHA" }, { - "BriefDescription": "Clockticks of the mesh to UPI (M3UPI)", + "BriefDescription": "PCIe Completion Buffer Inserts : All Ports", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x01", - "EventName": "UNC_M3UPI_CLOCKTICKS", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL", + "FCMask": "0x04", "PerPkg": "1", - "Unit": "M3UPI" + "PortMask": "0xFF", + "UMask": "0x03", + "Unit": "IIO" }, { - "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", - "Counter": "FIXED", - "CounterType": "FIXED", - "EventCode": "0xff", - "EventName": "UNC_U_CLOCKTICKS", + "BriefDescription": "Cache Lookups : Filters Requests for those that write info into the cache", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER", "PerPkg": "1", - "Unit": "UBOX" + "UMask": "0x1A42FF", + "UMaskExt": "0x1A42", + "Unit": "CHA" }, { - "BriefDescription": "Valid Flits Received : All Data", + "BriefDescription": "Cache Lookups : Transactions homed locally", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOC_HOM", "PerPkg": "1", - "UMask": "0x0F", - "Unit": "UPI LL" + "UMask": "0x0BDFFF", + "UMaskExt": "0x0BDF", + "Unit": "CHA" }, { - "BriefDescription": "Valid Flits Received : All Non Data", + "BriefDescription": "Cache Lookups : Transactions homed remotely", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REM_HOM", "PerPkg": "1", - "UMask": "0x97", - "Unit": "UPI LL" + "UMask": "0x15DFFF", + "UMaskExt": "0x15DF", + "Unit": "CHA" }, { - "BriefDescription": "Valid Flits Sent : All Data", + "BriefDescription": "Cache Lookups : CRd Requests that come from a Remote socket", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE", "PerPkg": "1", - "UMask": "0x0F", - "Unit": "UPI LL" + "UMask": "0x1A10FF", + "UMaskExt": "0x1A10", + "Unit": "CHA" }, { - "BriefDescription": "Valid Flits Sent : All Non Data", + "BriefDescription": "Cache Lookups : CRd Requests that come from the local socket (usually the core)", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL", "PerPkg": "1", - "UMask": "0x97", - "Unit": "UPI LL" + "UMask": "0x19D0FF", + "UMaskExt": "0x19D0", + "Unit": "CHA" }, { - "BriefDescription": "Number of kfclks", + "BriefDescription": "Cache and Snoop Filter Lookups; Prefetch requests to the LLC that come from the local socket (usually the core)", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x01", - "EventName": "UNC_UPI_CLOCKTICKS", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL", "PerPkg": "1", - "Unit": "UPI LL" + "UMask": "0x189DFF", + "UMaskExt": "0x189D", + "Unit": "CHA" }, { - "BriefDescription": "Cycles in L1", + "BriefDescription": "Cache Lookups : Code Reads", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x21", - "EventName": "UNC_UPI_L1_POWER_CYCLES", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ", "PerPkg": "1", - "Unit": "UPI LL" + "UMask": "0x1BD0FF", + "UMaskExt": "0x1BD0", + "Unit": "CHA" }, { - "BriefDescription": "Cycles in L0p", + "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 0", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x27", - "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", + "EventCode": "0x74", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI", "PerPkg": "1", - "Unit": "UPI LL" + "UMask": "0x01", + "Unit": "M2M" }, { - "BriefDescription": "Valid Flits Sent : Null FLITs transmitted to any slot", + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0xFF", + "Unit": "IIO" + }, + { + "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - All Channels", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", + "EventCode": "0x75", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH", "PerPkg": "1", - "UMask": "0x27", - "Unit": "UPI LL" + "UMask": "0x15", + "Unit": "M2M" }, { - "BriefDescription": "Valid Flits Received : Null FLITs received from any slot", + "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 2", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", + "EventCode": "0x75", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI", "PerPkg": "1", - "UMask": "0x27", - "Unit": "UPI LL" + "UMask": "0x10", + "Unit": "M2M" }, { - "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to locally HOMed memory", + "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 1", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", + "EventCode": "0x75", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI", "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xCD42FF04", - "UMaskExt": "0xCD42FF", - "Unit": "CHA" + "UMask": "0x04", + "Unit": "M2M" }, { - "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to remotely HOMed memory", + "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 0", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", + "EventCode": "0x75", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI", "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xCD437F04", - "UMaskExt": "0xCD437F", - "Unit": "CHA" + "UMask": "0x01", + "Unit": "M2M" }, { - "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to locally HOMed memory", + "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- All Channels", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", + "EventCode": "0x74", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH", "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xCC42FF04", - "UMaskExt": "0xCC42FF", - "Unit": "CHA" + "UMask": "0x15", + "Unit": "M2M" }, { - "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to remotely HOMed memory", + "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 2", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", + "EventCode": "0x74", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI", "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xCC437F04", - "UMaskExt": "0xCC437F", - "Unit": "CHA" + "UMask": "0x10", + "Unit": "M2M" }, { - "BriefDescription": "Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode.", + "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 1", "Counter": "0,1,2,3", "CounterType": "PGMABLE", - "EventCode": "0x2e", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", + "EventCode": "0x74", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI", "PerPkg": "1", - "PublicDescription": "Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode.", - "UMask": "0x01", + "UMask": "0x04", "Unit": "M2M" } ] diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json index 2d1368958762..281f3605881d 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json @@ -6,5 +6,230 @@ "EventName": "UNC_P_CLOCKTICKS", "PerPkg": "1", "Unit": "PCU" + }, + { + "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x60", + "EventName": "UNC_P_CORE_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "UNC_P_DEMOTIONS", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x30", + "EventName": "UNC_P_DEMOTIONS", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Phase Shed 0 Cycles", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x75", + "EventName": "UNC_P_FIVR_PS_PS0_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Phase Shed 1 Cycles", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x76", + "EventName": "UNC_P_FIVR_PS_PS1_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Phase Shed 2 Cycles", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x77", + "EventName": "UNC_P_FIVR_PS_PS2_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Phase Shed 3 Cycles", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x78", + "EventName": "UNC_P_FIVR_PS_PS3_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "AVX256 Frequency Clipping", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x49", + "EventName": "UNC_P_FREQ_CLIP_AVX256", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "AVX512 Frequency Clipping", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x4a", + "EventName": "UNC_P_FREQ_CLIP_AVX512", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Thermal Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Power Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x05", + "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x73", + "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Cycles spent changing Frequency", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x74", + "EventName": "UNC_P_FREQ_TRANS_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Memory Phase Shedding Cycles", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2F", + "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2A", + "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C2E", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2B", + "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2C", + "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2D", + "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x06", + "EventName": "UNC_P_PMAX_THROTTLED_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "External Prochot", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x0A", + "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Internal Prochot", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x09", + "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Total Core C State Transition Cycles", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x72", + "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "VR Hot", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x42", + "EventName": "UNC_P_VR_HOT_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Number of cores in C-State : C0 and C1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Number of cores in C-State : C3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Number of cores in C-State : C6 and C7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", + "PerPkg": "1", + "Unit": "PCU" } ] -- cgit v1.2.3 From cb73eeb95a2c293fa011e3151d9d57e249122a18 Mon Sep 17 00:00:00 2001 From: Zhengjun Xing Date: Fri, 12 Aug 2022 16:52:34 +0800 Subject: perf vendor events: Update metrics for ivytown MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The metrics are based on TMA 4.4 full, add new metrics “UNCORE_FREQ” for ivytown. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py to download and generate the latest events and metrics. Manually copy the ivytown files into perf. Signed-off-by: Xing Zhengjun Tested-by: Ian Rogers Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20220812085239.3089231-7-zhengjun.xing@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json b/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json index 782d68e1cd0d..19c7f3b41102 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json @@ -354,6 +354,12 @@ "MetricGroup": "SoC", "MetricName": "Socket_CLKS" }, + { + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "cbox_0@event\\=0x0@ / #num_dies / duration_time / 1000000000", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" + }, { "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", -- cgit v1.2.3 From b823ee183dc4224f29a8b5e172b647256da24c0e Mon Sep 17 00:00:00 2001 From: Zhengjun Xing Date: Fri, 12 Aug 2022 16:52:35 +0800 Subject: perf vendor events: Update metrics for jaketown MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The metrics are based on TMA 4.4 full, add new metrics “UNCORE_FREQ” for jaketown. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py to download and generate the latest events and metrics. Manually copy the jaketown files into perf. Signed-off-by: Xing Zhengjun Tested-by: Ian Rogers Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20220812085239.3089231-8-zhengjun.xing@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json b/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json index 2711cbe536b8..c0fbb4f31241 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json @@ -208,6 +208,12 @@ "MetricGroup": "SoC", "MetricName": "Socket_CLKS" }, + { + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "cbox_0@event\\=0x0@ / #num_dies / duration_time / 1000000000", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" + }, { "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", -- cgit v1.2.3 From 107630e6a57544dae5357834244ebbffd0ba4c92 Mon Sep 17 00:00:00 2001 From: Zhengjun Xing Date: Fri, 12 Aug 2022 16:52:36 +0800 Subject: perf vendor events: Update events for knightslanding Update the events to v9, update events for knightslanding by the latest event converter tools. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py to download and generate the latest events and metrics. Manually copy the knightslanding files into perf. Signed-off-by: Xing Zhengjun Tested-by: Ian Rogers Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20220812085239.3089231-9-zhengjun.xing@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/knightslanding/uncore-other.json | 213 +++++++++++++++++++++ 1 file changed, 213 insertions(+) diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json index a87d7431ef45..a5e1a9a47e73 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json @@ -1,4 +1,67 @@ [ + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT", + "PerPkg": "1", + "UMask": "0x18", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ ", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ or PRQ", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOC_ALL", + "PerPkg": "1", + "UMask": "0x37", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, { "BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode.", "Counter": "0,1,2,3", @@ -3497,6 +3560,156 @@ "UMask": "0x08", "Unit": "CHA" }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -SF/LLC Evictions", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_H_TOR_INSERTS.EVICT", + "PerPkg": "1", + "UMask": "0x32", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -Hit (Not a Miss)", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_H_TOR_INSERTS.HIT", + "PerPkg": "1", + "UMask": "0x1F", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_H_TOR_INSERTS.IPQ", + "PerPkg": "1", + "UMask": "0x38", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_H_TOR_INSERTS.IRQ", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -Miss", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_H_TOR_INSERTS.MISS", + "PerPkg": "1", + "UMask": "0x2F", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_H_TOR_INSERTS.PRQ", + "PerPkg": "1", + "UMask": "0x34", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -SF/LLC Evictions", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.EVICT", + "PerPkg": "1", + "UMask": "0x32", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -Hit (Not a Miss)", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.HIT", + "PerPkg": "1", + "UMask": "0x1F", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IPQ", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.IPQ", + "PerPkg": "1", + "UMask": "0x38", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IPQ hit", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.IPQ_HIT", + "PerPkg": "1", + "UMask": "0x18", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IPQ miss", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.IPQ_MISS", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IRQ or PRQ", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.IRQ", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IRQ or PRQ hit", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.IRQ_HIT", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IRQ or PRQ miss", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.IRQ_MISS", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -Miss", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.MISS", + "PerPkg": "1", + "UMask": "0x2F", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -PRQ", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.PRQ", + "PerPkg": "1", + "UMask": "0x34", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -PRQ hit", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.PRQ_HIT", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -PRQ miss", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.PRQ_MISS", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, { "BriefDescription": "Uncore Clocks", "Counter": "0,1,2,3", -- cgit v1.2.3 From 74d8ca6d85a31c537a7934683bfda617ee95a452 Mon Sep 17 00:00:00 2001 From: Zhengjun Xing Date: Fri, 12 Aug 2022 16:52:37 +0800 Subject: perf vendor events: Update metrics for sapphirerapids MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The metrics are based on TMA 4.4 full, add new metrics “UNCORE_FREQ” for sapphirerapids. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py to download and generate the latest events and metrics. Manually copy the sapphirerapids files into perf. Signed-off-by: Xing Zhengjun Tested-by: Ian Rogers Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20220812085239.3089231-10-zhengjun.xing@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json index b9adef1fb72e..e194dfc5c25b 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json @@ -491,6 +491,12 @@ "MetricGroup": "SoC", "MetricName": "Socket_CLKS" }, + { + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "uncore_cha_0@event\\=0x1@ / #num_dies / duration_time / 1000000000", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" + }, { "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", -- cgit v1.2.3 From ce87616d0dff3a9b80158bb9a9f6c20c1a88b378 Mon Sep 17 00:00:00 2001 From: Zhengjun Xing Date: Fri, 12 Aug 2022 16:52:38 +0800 Subject: perf vendor events: Update events and metrics for skylakex Update the events to v1.28, the metrics are based on TMA 4.4 full, update events and metrics for skylakex by the latest event converter tools. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py to download and generate the latest events and metrics. Manually copy the skylakex files into perf. Signed-off-by: Xing Zhengjun Tested-by: Ian Rogers Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20220812085239.3089231-11-zhengjun.xing@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/skylakex/skx-metrics.json | 6 + .../arch/x86/skylakex/uncore-memory.json | 3566 ++- .../pmu-events/arch/x86/skylakex/uncore-other.json | 23442 +++++++++++++++++-- .../pmu-events/arch/x86/skylakex/uncore-power.json | 201 + 4 files changed, 25488 insertions(+), 1727 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json diff --git a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json b/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json index d65420bda04f..6a6764e1504b 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json @@ -697,6 +697,12 @@ "MetricGroup": "SoC", "MetricName": "Socket_CLKS" }, + { + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "cha_0@event\\=0x0@ / #num_dies / duration_time / 1000000000", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" + }, { "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json index 56709633c379..0746fcf2ebd9 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json @@ -1,4 +1,31 @@ [ + { + "BriefDescription": "DRAM Page Activate commands sent due to a write request", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_M_ACT_COUNT.WR", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "All DRAM Read CAS Commands issued (does not include underfills)", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_REG", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Underfill Read CAS Commands issued", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, { "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd", "Counter": "0,1,2,3", @@ -19,6 +46,15 @@ "UMask": "0x3", "Unit": "iMC" }, + { + "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.WR_WMM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, { "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr", "Counter": "0,1,2,3", @@ -39,6 +75,15 @@ "UMask": "0xC", "Unit": "iMC" }, + { + "BriefDescription": "All DRAM CAS Commands issued", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.ALL", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, { "BriefDescription": "Memory controller clock ticks", "Counter": "0,1,2,3", @@ -85,98 +130,3543 @@ "Unit": "iMC" }, { - "BriefDescription": "Pre-charge for writes", + "BriefDescription": "Read Pending Queue Allocations", "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_M_PRE_COUNT.WR", + "EventCode": "0x10", + "EventName": "UNC_M_RPQ_INSERTS", "PerPkg": "1", - "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "DRAM Page Activate commands sent due to a write request", + "BriefDescription": "Read Pending Queue Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_M_RPQ_OCCUPANCY", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_M_WPQ_INSERTS", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x81", + "EventName": "UNC_M_WPQ_OCCUPANCY", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Activate Count; Activate due to Read", "Counter": "0,1,2,3", "EventCode": "0x1", - "EventName": "UNC_M_ACT_COUNT.WR", + "EventName": "UNC_M_ACT_COUNT.RD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Activate Count; Activate due to Bypass", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_M_ACT_COUNT.BYP", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "ACT command issued by 2 cycle bypass", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_M_BYP_CMDS.ACT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "CAS command issued by 2 cycle bypass", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_M_BYP_CMDS.CAS", "PerPkg": "1", - "PublicDescription": "Counts DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Controller). Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS (Column Access Select) command.", "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "All DRAM CAS Commands issued", + "BriefDescription": "PRE command issued by 2 cycle bypass", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_M_BYP_CMDS.PRE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode", "Counter": "0,1,2,3", "EventCode": "0x4", - "EventName": "UNC_M_CAS_COUNT.ALL", + "EventName": "UNC_M_CAS_COUNT.WR_RMM", "PerPkg": "1", - "PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM, so this event increments for every read and write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.", - "UMask": "0xF", + "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "All DRAM Read CAS Commands issued (does not include underfills)", + "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in WMM", "Counter": "0,1,2,3", "EventCode": "0x4", - "EventName": "UNC_M_CAS_COUNT.RD_REG", + "EventName": "UNC_M_CAS_COUNT.RD_WMM", "PerPkg": "1", - "PublicDescription": "Counts CAS (Column Access Select) regular read commands issued to DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every regular read. This event only counts regular reads and does not includes underfill reads due to partial write requests. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.", - "UMask": "0x1", + "UMask": "0x10", "Unit": "iMC" }, { - "BriefDescription": "DRAM Underfill Read CAS Commands issued", + "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in RMM", "Counter": "0,1,2,3", "EventCode": "0x4", - "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", + "EventName": "UNC_M_CAS_COUNT.RD_RMM", "PerPkg": "1", - "PublicDescription": "Counts CAS (Column Access Select) underfill read commands issued to DRAM due to a partial write, on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this command counts underfill reads. Partial writes must be completed by first reading in the underfill from DRAM and then merging in the partial write data before writing the full line back to DRAM. This event will generally count about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ (due to a previous write request).", - "UMask": "0x2", + "UMask": "0x20", "Unit": "iMC" }, { - "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode", + "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Read ISOCH Mode", "Counter": "0,1,2,3", "EventCode": "0x4", - "EventName": "UNC_M_CAS_COUNT.WR_WMM", + "EventName": "UNC_M_CAS_COUNT.RD_ISOCH", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Write ISOCH Mode", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.WR_ISOCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge All Commands", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_M_DRAM_PRE_ALL", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_M_DRAM_REFRESH.PANIC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_M_DRAM_REFRESH.HIGH", "PerPkg": "1", - "PublicDescription": "Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode.", "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "Read Pending Queue Allocations", + "BriefDescription": "ECC Correctable Errors", "Counter": "0,1,2,3", - "EventCode": "0x10", - "EventName": "UNC_M_RPQ_INSERTS", + "EventCode": "0x9", + "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", "PerPkg": "1", - "PublicDescription": "Counts the number of read requests allocated into the Read Pending Queue (RPQ). This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. The requests deallocate after the read CAS command has been issued to DRAM. This event counts both Isochronous and non-Isochronous requests which were issued to the RPQ.", "Unit": "iMC" }, { - "BriefDescription": "Read Pending Queue Occupancy", + "BriefDescription": "Cycles in a Major Mode; Read Major Mode", "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_M_RPQ_OCCUPANCY", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.READ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Cycles in a Major Mode; Write Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.WRITE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries in the Read Pending Queue (RPQ) at each cycle. This can then be used to calculate both the average occupancy of the queue (in conjunction with the number of cycles not empty) and the average latency in the queue (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate from the RPQ after the CAS command has been issued to memory.", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "Write Pending Queue Allocations", + "BriefDescription": "Cycles in a Major Mode; Partial Major Mode", "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_M_WPQ_INSERTS", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.PARTIAL", "PerPkg": "1", - "PublicDescription": "Counts the number of writes requests allocated into the Write Pending Queue (WPQ). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (Memory Controller). The write requests deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.", + "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "Write Pending Queue Occupancy", + "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode", "Counter": "0,1,2,3", - "EventCode": "0x81", - "EventName": "UNC_M_WPQ_OCCUPANCY", + "EventCode": "0x7", + "EventName": "UNC_M_MAJOR_MODES.ISOCH", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "Channel DLLOFF Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_M_POWER_CHANNEL_DLLOFF", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Critical Throttle Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_POWER_PCU_THROTTLING", + "Counter": "0,1,2,3", + "EventCode": "0x42", + "EventName": "UNC_M_POWER_PCU_THROTTLING", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Preemption Count; Read over Read Preemption", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Preemption Count; Read over Write Preemption", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Pre-charge for writes", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_M_PRE_COUNT.WR", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_M_PRE_COUNT.BYP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS issued with LOW priority", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M_RD_CAS_PRIO.LOW", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS issued with MEDIUM priority", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M_RD_CAS_PRIO.MED", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS issued with HIGH priority", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M_RD_CAS_PRIO.HIGH", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M_RD_CAS_PRIO.PANIC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Full Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_M_RPQ_CYCLES_FULL", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_M_RPQ_CYCLES_NE", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter", + "Counter": "0,1,2,3", + "EventCode": "0xC0", + "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Transition from WMM to RMM because of low threshold", + "Counter": "0,1,2,3", + "EventCode": "0xC0", + "EventName": "UNC_M_WMM_TO_RMM.STARVE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Transition from WMM to RMM because of low threshold", + "Counter": "0,1,2,3", + "EventCode": "0xC0", + "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Full Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_M_WPQ_CYCLES_FULL", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_M_WPQ_CYCLES_NE", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_M_WPQ_READ_HIT", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_M_WPQ_WRITE_HIT", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Not getting the requested Major Mode", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_M_WRONG_MM", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "UNC_M_WR_CAS_RANK0.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xB9", + "EventName": "UNC_M_WR_CAS_RANK1.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 0", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK0", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 1", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 2", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 3", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK3", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 4", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK4", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 5", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK5", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 6", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK6", + "PerPkg": "1", + "UMask": "0x6", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 7", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK7", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 8", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK8", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 9", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK9", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 10", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK10", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 11", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK11", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 12", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK12", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 13", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK13", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 14", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK14", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank 15", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK15", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; All Banks", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANKG0", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANKG1", + "PerPkg": "1", + "UMask": "0x12", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANKG2", + "PerPkg": "1", + "UMask": "0x13", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)", + "Counter": "0,1,2,3", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANKG3", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "iMC" + }, + { + "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter", + "Counter": "FIXED", + "EventCode": "0xff", + "EventName": "UNC_M_CLOCKTICKS_F", "PerPkg": "1", - "PublicDescription": "Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller). They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. Is there a filter of sorts???", "Unit": "iMC" } ] diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json index abe2d068ea0c..f55aeadc630f 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json @@ -1,140 +1,151 @@ [ { - "BriefDescription": "Uncore cache clock ticks", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CLOCKTICKS", "Counter": "0,1,2,3", - "EventName": "UNC_CHA_CLOCKTICKS", + "Deprecated": "1", + "EventName": "UNC_C_CLOCKTICKS", "PerPkg": "1", "Unit": "CHA" }, { - "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss", + "BriefDescription": "Core Cross Snoops Issued; Multiple Core Requests", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_MISSES.UNCACHEABLE", - "Filter": "config1=0x40e33", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", "PerPkg": "1", - "UMask": "0x21", + "UMask": "0x42", "Unit": "CHA" }, { - "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ", + "BriefDescription": "Core Cross Snoops Issued; Multiple Eviction", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", - "Filter": "config1=0x40e33", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", "PerPkg": "1", - "UMask": "0x21", + "UMask": "0x82", "Unit": "CHA" }, { - "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss", + "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_MISSES.MMIO_READ", - "Filter": "config1=0x40040e33", + "EventCode": "0x53", + "EventName": "UNC_CHA_DIR_LOOKUP.SNP", "PerPkg": "1", - "UMask": "0x21", + "UMask": "0x01", "Unit": "CHA" }, { - "BriefDescription": "MMIO reads", + "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", - "Filter": "config1=0x40040e33", + "EventCode": "0x53", + "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP", "PerPkg": "1", - "UMask": "0x21", + "UMask": "0x02", "Unit": "CHA" }, { - "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss", + "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_MISSES.MMIO_WRITE", - "Filter": "config1=0x40041e33", + "EventCode": "0x54", + "EventName": "UNC_CHA_DIR_UPDATE.HA", "PerPkg": "1", - "UMask": "0x21", + "UMask": "0x01", "Unit": "CHA" }, { - "BriefDescription": "MMIO writes", + "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", - "Filter": "config1=0x40041e33", + "EventCode": "0x54", + "EventName": "UNC_CHA_DIR_UPDATE.TOR", "PerPkg": "1", - "UMask": "0x21", + "UMask": "0x02", "Unit": "CHA" }, { - "BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss", + "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.STREAMING_FULL", - "Filter": "config1=0x41833", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.EX_RDS", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x21", + "UMask": "0x01", "Unit": "CHA" }, { - "BriefDescription": "Streaming stores (full cache line)", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", - "Filter": "config1=0x41833", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.DATA_READ", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x21", + "UMask": "0x3", "Unit": "CHA" }, { - "BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", - "Filter": "config1=0x41a33", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x21", + "UMask": "0x9", "Unit": "CHA" }, { - "BriefDescription": "Streaming stores (partial cache line)", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M", "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", - "Filter": "config1=0x41a33", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.M_STATE", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x21", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "read requests from home agent", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E", "Counter": "0,1,2,3", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.E_STATE", "PerPkg": "1", - "UMask": "0x03", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "read requests from local home agent", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S", "Counter": "0,1,2,3", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.S_STATE", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.F_STATE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of times that an RFO hit in S state", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.RFO_HIT_S", + "PerPkg": "1", + "UMask": "0x08", "Unit": "CHA" }, { - "BriefDescription": "read requests from remote home agent", + "BriefDescription": "read requests from home agent", "Counter": "0,1,2,3", "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", + "EventName": "UNC_CHA_REQUESTS.READS", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x03", "Unit": "CHA" }, { @@ -146,6 +157,15 @@ "UMask": "0x0C", "Unit": "CHA" }, + { + "BriefDescription": "read requests from local home agent", + "Counter": "0,1,2,3", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, { "BriefDescription": "write requests from local home agent", "Counter": "0,1,2,3", @@ -156,477 +176,411 @@ "Unit": "CHA" }, { - "BriefDescription": "write requests from remote home agent", + "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data", "Counter": "0,1,2,3", "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data", + "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data", "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UPI_DATA_BANDWIDTH_TX", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", "PerPkg": "1", - "ScaleUnit": "7.11E-06Bytes", - "UMask": "0xf", - "Unit": "UPI LL" + "UMask": "0x20", + "Unit": "CHA" }, { - "BriefDescription": "UPI interconnect send bandwidth for payload", + "BriefDescription": "RspIFwd Snoop Responses Received", "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD", "PerPkg": "1", - "ScaleUnit": "7.11E-06Bytes", - "UMask": "0xf", - "Unit": "UPI LL" + "UMask": "0x04", + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 0", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", - "FCMask": "0x07", + "BriefDescription": "RspSFwd Snoop Responses Received", + "Counter": "0,1,2,3", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD", "PerPkg": "1", - "PortMask": "0x01", - "ScaleUnit": "4Bytes", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x08", + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 1", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", - "FCMask": "0x07", + "BriefDescription": "Rsp*Fwd*WB Snoop Responses Received", + "Counter": "0,1,2,3", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSP_FWD_WB", "PerPkg": "1", - "PortMask": "0x02", - "ScaleUnit": "4Bytes", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x20", + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 2", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", - "FCMask": "0x07", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPCNFLCTS", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", "PerPkg": "1", - "PortMask": "0x04", - "ScaleUnit": "4Bytes", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x40", + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 3", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "FCMask": "0x07", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IRQ", "PerPkg": "1", - "PortMask": "0x08", - "ScaleUnit": "4Bytes", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x31", + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "LLC_MISSES.PCIE_READ", - "FCMask": "0x07", - "Filter": "ch_mask=0x1f", - "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "MetricName": "LLC_MISSES.PCIE_READ", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IRQ", "PerPkg": "1", - "PortMask": "0x01", - "ScaleUnit": "4Bytes", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x31", + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth reading at IIO", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "Filter": "ch_mask=0x1f", - "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "MetricName": "LLC_MISSES.PCIE_READ", + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.REM_ALL", "PerPkg": "1", - "PortMask": "0x01", - "ScaleUnit": "4Bytes", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x30", + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 0", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_FAST_ASSERTED.HORZ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xA5", + "EventName": "UNC_C_FAST_ASSERTED", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; IRQ", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IRQ", "PerPkg": "1", - "PortMask": "0x01", - "ScaleUnit": "4Bytes", "UMask": "0x01", - "Unit": "IIO" + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 1", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", "PerPkg": "1", - "PortMask": "0x02", - "ScaleUnit": "4Bytes", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x80", + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 2", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", + "BriefDescription": "Ingress (from CMS) Occupancy; IRQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ", "PerPkg": "1", - "PortMask": "0x04", - "ScaleUnit": "4Bytes", "UMask": "0x01", - "Unit": "IIO" + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 3", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT", "PerPkg": "1", - "PortMask": "0x08", - "ScaleUnit": "4Bytes", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x11", + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "LLC_MISSES.PCIE_WRITE", - "FCMask": "0x07", - "Filter": "ch_mask=0x1f", - "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "MetricName": "LLC_MISSES.PCIE_WRITE", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS", "PerPkg": "1", - "PortMask": "0x01", - "ScaleUnit": "4Bytes", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x21", + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth writing at IIO", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "Filter": "ch_mask=0x1f", - "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "MetricName": "LLC_MISSES.PCIE_WRITE", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_HIT", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT", "PerPkg": "1", - "PortMask": "0x01", - "ScaleUnit": "4Bytes", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x14", + "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoops Issued; Multiple Core Requests", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_MISS", "Counter": "0,1,2,3", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS", "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x42", + "UMask": "0x24", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoops Issued; Multiple Eviction", - "Counter": "0,1,2,3", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_HIT", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_HIT", "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x82", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed", - "Counter": "0,1,2,3", - "EventCode": "0x53", - "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_MISS", "PerPkg": "1", - "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed", - "UMask": "0x02", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed", + "BriefDescription": "TOR Inserts; Hits from Local IO", "Counter": "0,1,2,3", - "EventCode": "0x53", - "EventName": "UNC_CHA_DIR_LOOKUP.SNP", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", "PerPkg": "1", - "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed", - "UMask": "0x01", + "UMask": "0x14", "Unit": "CHA" }, { - "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe", + "BriefDescription": "TOR Inserts; Misses from Local IO", "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "UNC_CHA_DIR_UPDATE.HA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", "PerPkg": "1", - "PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", - "UMask": "0x01", + "UMask": "0x24", "Unit": "CHA" }, { - "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe", + "BriefDescription": "TOR Inserts; All from Local iA", "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "UNC_CHA_DIR_UPDATE.TOR", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA", "PerPkg": "1", - "PublicDescription": "Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", - "UMask": "0x02", + "UMask": "0x31", "Unit": "CHA" }, { - "BriefDescription": "FaST wire asserted; Horizontal", + "BriefDescription": "TOR Inserts; Hits from Local iA", "Counter": "0,1,2,3", - "EventCode": "0xA5", - "EventName": "UNC_CHA_FAST_ASSERTED.HORZ", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", - "UMask": "0x02", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state", + "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC", "Counter": "0,1,2,3", - "EventCode": "0x5F", - "EventName": "UNC_CHA_HITME_HIT.EX_RDS", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", "PerPkg": "1", - "PublicDescription": "Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state. This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*)", - "UMask": "0x01", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "Normal priority reads issued to the memory controller from the CHA", - "Counter": "0,1,2,3", - "EventCode": "0x59", - "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", + "BriefDescription": "TOR Occupancy; All from Local iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", "PerPkg": "1", - "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.", - "UMask": "0x01", + "UMask": "0x31", "Unit": "CHA" }, { - "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH", - "Counter": "0,1,2,3", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", + "BriefDescription": "TOR Occupancy; Hits from Local iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", "PerPkg": "1", - "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels.", - "UMask": "0x01", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "Lines Victimized; Lines in E state", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E", + "BriefDescription": "TOR Occupancy; Misses from Local iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x02", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "Lines Victimized; Lines in F State", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_F", + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCS VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCS", "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x08", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "Lines Victimized; Lines in M state", + "BriefDescription": "FaST wire asserted; Horizontal", "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M", + "EventCode": "0xA5", + "EventName": "UNC_CHA_FAST_ASSERTED.HORZ", "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x01", + "UMask": "0x02", "Unit": "CHA" }, { - "BriefDescription": "Lines Victimized; Lines in S State", + "BriefDescription": "Clockticks of the uncore caching & home agent (CHA)", "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S", + "EventName": "UNC_CHA_CLOCKTICKS", "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x04", "Unit": "CHA" }, { - "BriefDescription": "Number of times that an RFO hit in S state.", + "BriefDescription": "Normal priority reads issued to the memory controller from the CHA", "Counter": "0,1,2,3", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.RFO_HIT_S", + "EventCode": "0x59", + "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", "PerPkg": "1", - "PublicDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.", - "UMask": "0x08", + "UMask": "0x01", "Unit": "CHA" }, { - "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data", + "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH", "Counter": "0,1,2,3", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", "PerPkg": "1", - "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", - "UMask": "0x10", + "UMask": "0x01", "Unit": "CHA" }, { - "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data", + "BriefDescription": "Read requests from a remote socket", "Counter": "0,1,2,3", "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", + "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", "PerPkg": "1", - "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", - "UMask": "0x20", + "UMask": "0x02", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Allocations; IRQ", + "BriefDescription": "RspI Snoop Responses Received", "Counter": "0,1,2,3", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.IRQ", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPI", "PerPkg": "1", - "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x01", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", + "BriefDescription": "Rsp*WB Snoop Responses Received", "Counter": "0,1,2,3", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB", "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", - "UMask": "0x80", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Occupancy; IRQ", - "EventCode": "0x11", - "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ", + "BriefDescription": "RspCnflct* Snoop Responses Received", + "Counter": "0,1,2,3", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCTS", "PerPkg": "1", - "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", - "UMask": "0x01", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Snoop filter capacity evictions for E-state entries.", + "BriefDescription": "Snoop filter capacity evictions for M-state entries", "Counter": "0,1,2,3", "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.E_STATE", + "EventName": "UNC_CHA_SF_EVICTION.M_STATE", "PerPkg": "1", - "PublicDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.", - "UMask": "0x02", + "UMask": "0x01", "Unit": "CHA" }, { - "BriefDescription": "Snoop filter capacity evictions for M-state entries.", + "BriefDescription": "Snoop filter capacity evictions for E-state entries", "Counter": "0,1,2,3", "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.M_STATE", + "EventName": "UNC_CHA_SF_EVICTION.E_STATE", "PerPkg": "1", - "PublicDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.", - "UMask": "0x01", + "UMask": "0x02", "Unit": "CHA" }, { - "BriefDescription": "Snoop filter capacity evictions for S-state entries.", + "BriefDescription": "Snoop filter capacity evictions for S-state entries", "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_CHA_SF_EVICTION.S_STATE", "PerPkg": "1", - "PublicDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.", "UMask": "0x04", "Unit": "CHA" }, { - "BriefDescription": "RspCnflct* Snoop Responses Received", + "BriefDescription": "This event is deprecated. ", "Counter": "0,1,2,3", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCTS", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL", "PerPkg": "1", - "PublicDescription": "Counts when a a transaction with the opcode type RspCnflct* Snoop Response was received. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent. This triggers conflict resolution hardware. This covers both the opcode RspCnflct and RspCnflctWbI.", - "UMask": "0x40", + "UMask": "0x30", "Unit": "CHA" }, { - "BriefDescription": "RspI Snoop Responses Received", + "BriefDescription": "Lines Victimized; Lines in M state", "Counter": "0,1,2,3", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPI", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M", "PerPkg": "1", - "PublicDescription": "Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data).", "UMask": "0x01", "Unit": "CHA" }, { - "BriefDescription": "RspIFwd Snoop Responses Received", + "BriefDescription": "Lines Victimized; Lines in E state", "Counter": "0,1,2,3", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Lines in S State", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S", "PerPkg": "1", - "PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.", "UMask": "0x04", "Unit": "CHA" }, { - "BriefDescription": "RspSFwd Snoop Responses Received", + "BriefDescription": "Lines Victimized; Lines in F State", "Counter": "0,1,2,3", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_F", "PerPkg": "1", - "PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.", "UMask": "0x08", "Unit": "CHA" }, { - "BriefDescription": "Rsp*Fwd*WB Snoop Responses Received", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC", "Counter": "0,1,2,3", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSP_FWD_WB", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", + "Filter": "config1=0x40433", "PerPkg": "1", - "PublicDescription": "Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to its home socket, and the cacheline was forwarded to the requestor socket. This snoop response is only used in >= 4 socket systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to its home socket to be written back to memory.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Rsp*WB Snoop Responses Received", - "Counter": "0,1,2,3", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB", - "PerPkg": "1", - "PublicDescription": "Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to its home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership.", - "UMask": "0x10", + "UMask": "0x11", "Unit": "CHA" }, { @@ -636,40 +590,36 @@ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", "Filter": "config1=0x40233", "PerPkg": "1", - "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC", + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", - "Filter": "config1=0x40433", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", + "Filter": "config1=0x40033", "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", - "Filter": "config1=0x4b233", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", + "Filter": "config1=0x4b433", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", - "Filter": "config1=0x4b433", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", + "Filter": "config1=0x4b233", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", "UMask": "0x11", "Unit": "CHA" }, @@ -680,19 +630,17 @@ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefRFO", "Filter": "config1=0x4b033", "PerPkg": "1", - "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", - "Filter": "config1=0x40033", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Filter": "config1=0x40433", "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x11", + "UMask": "0x21", "Unit": "CHA" }, { @@ -702,29 +650,16 @@ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", "Filter": "config1=0x40233", "PerPkg": "1", - "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", - "Filter": "config1=0x40433", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", - "Filter": "config1=0x4b233", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", + "Filter": "config1=0x40033", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", "UMask": "0x21", "Unit": "CHA" }, @@ -735,42 +670,36 @@ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", "Filter": "config1=0x4b433", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC", + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO", - "Filter": "config1=0x4b033", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", + "Filter": "config1=0x4b233", "PerPkg": "1", - "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC", + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC", "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", - "Filter": "config1=0x40033", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO", + "Filter": "config1=0x4b033", "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL", - "Filter": "CHAfilter1", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "Filter": "config1=0x40433", "PerPkg": "1", - "PublicDescription": "This event is deprecated. ", - "UMask": "0x30", + "UMask": "0x11", "Unit": "CHA" }, { @@ -779,37 +708,33 @@ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", "Filter": "config1=0x40233", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", - "Filter": "config1=0x40433", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "Filter": "config1=0x40033", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", - "Filter": "config1=0x4b233", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", + "Filter": "config1=0x4b433", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", - "Filter": "config1=0x4b433", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", + "Filter": "config1=0x4b233", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", "UMask": "0x11", "Unit": "CHA" }, @@ -819,18 +744,16 @@ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", "Filter": "config1=0x4b033", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", - "Filter": "config1=0x40033", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Filter": "config1=0x40433", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", - "UMask": "0x11", + "UMask": "0x21", "Unit": "CHA" }, { @@ -839,27 +762,15 @@ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", "Filter": "config1=0x40233", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", - "Filter": "config1=0x40433", - "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", - "Filter": "config1=0x4b233", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "Filter": "config1=0x40033", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", "UMask": "0x21", "Unit": "CHA" }, @@ -869,1824 +780,21977 @@ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", "Filter": "config1=0x4b433", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", - "Filter": "config1=0x4b033", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", + "Filter": "config1=0x4b233", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", - "Filter": "config1=0x40033", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", + "Filter": "config1=0x4b033", "PerPkg": "1", - "PublicDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CLOCKTICKS", + "BriefDescription": "Clockticks of the IIO Traffic Controller", "Counter": "0,1,2,3", - "Deprecated": "1", - "EventName": "UNC_C_CLOCKTICKS", + "EventCode": "0x1", + "EventName": "UNC_IIO_CLOCKTICKS", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_CLOCKTICKS", - "Unit": "CHA" + "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_FAST_ASSERTED.HORZ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "Counter": "0,1", "Deprecated": "1", - "EventCode": "0xA5", - "EventName": "UNC_C_FAST_ASSERTED", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0", + "FCMask": "0x7", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_FAST_ASSERTED.HORZ", - "UMask": "0x02", - "Unit": "CHA" + "PortMask": "0x1", + "UMask": "0x1", + "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "Counter": "0,1", "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.E_STATE", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1", + "FCMask": "0x7", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E", - "UMask": "0x2", - "Unit": "CHA" + "PortMask": "0x2", + "UMask": "0x1", + "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "Counter": "0,1", "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.F_STATE", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2", + "FCMask": "0x7", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F", - "UMask": "0x8", - "Unit": "CHA" + "PortMask": "0x4", + "UMask": "0x1", + "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "Counter": "0,1", "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.M_STATE", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3", + "FCMask": "0x7", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M", + "PortMask": "0x8", "UMask": "0x1", - "Unit": "CHA" + "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "Counter": "0,1", "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.S_STATE", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0", + "FCMask": "0x7", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S", + "PortMask": "0x1", "UMask": "0x4", - "Unit": "CHA" + "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "Counter": "0,1", "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.REM_ALL", - "Filter": "CHAfilter1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1", + "FCMask": "0x7", "PerPkg": "1", - "PublicDescription": "This event is deprecated. ", - "UMask": "0x30", - "Unit": "CHA" + "PortMask": "0x2", + "UMask": "0x4", + "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "Counter": "0,1", "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.CORE_GTONE", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2", + "FCMask": "0x7", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE", - "UMask": "0x42", - "Unit": "CHA" + "PortMask": "0x4", + "UMask": "0x4", + "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "Counter": "0,1", "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.EVICT_GTONE", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3", + "FCMask": "0x7", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE", - "UMask": "0x82", - "Unit": "CHA" + "PortMask": "0x8", + "UMask": "0x4", + "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x53", - "EventName": "UNC_H_DIR_LOOKUP.NO_SNP", + "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part2", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part3", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO, part 0", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "ScaleUnit": "4Bytes", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO, part 1", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "ScaleUnit": "4Bytes", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO, part 2", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "ScaleUnit": "4Bytes", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO, part 3", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "ScaleUnit": "4Bytes", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "LLC_MISSES.PCIE_WRITE", + "FCMask": "0x07", + "Filter": "ch_mask=0x1f", + "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "MetricName": "LLC_MISSES.PCIE_WRITE", + "PerPkg": "1", + "PortMask": "0x01", + "ScaleUnit": "4Bytes", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth reading at IIO, part 0", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "ScaleUnit": "4Bytes", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth reading at IIO, part 1", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "ScaleUnit": "4Bytes", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth reading at IIO, part 2", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "ScaleUnit": "4Bytes", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth reading at IIO, part 3", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "ScaleUnit": "4Bytes", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "LLC_MISSES.PCIE_READ", + "FCMask": "0x07", + "Filter": "ch_mask=0x1f", + "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "MetricName": "LLC_MISSES.PCIE_READ", + "PerPkg": "1", + "PortMask": "0x01", + "ScaleUnit": "4Bytes", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part1 to Memory", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x0f", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x0f", + "Unit": "IIO" + }, + { + "BriefDescription": "Total IRP occupancy of inbound read and write requests", + "Counter": "0,1", + "EventCode": "0xF", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.RFO", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.PCITOM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue", + "Counter": "0,1", + "EventCode": "0x18", + "EventName": "UNC_I_FAF_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Occupancy of the IRP FAF queue", + "Counter": "0,1", + "EventCode": "0x19", + "EventName": "UNC_I_FAF_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound write (fast path) requests received by the IRP", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Clocks of the Intel Ultra Path Interconnect (UPI)", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_UPI_CLOCKTICKS", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Data Response packets that go direct to core", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_DIRECT_ATTEMPTS.D2U", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Cycles Intel UPI is in L1 power mode (shutdown)", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_UPI_L1_POWER_CYCLES", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Cycles the Rx of the Intel UPI is in L0p power mode", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_UPI_RxL0P_POWER_CYCLES", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI LL" + }, + { + "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.ALL_NULL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.NULL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Cycles in which the Tx of the Intel Ultra Path Interconnect (UPI) is in L0p power mode", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "FLITs that bypassed the TxL Buffer", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_UPI_TxL_BYPASSED", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent; Data", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.DATA", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_NULL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.NULL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Protocol header and credit FLITs received from any slot", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", + "PerPkg": "1", + "UMask": "0x97", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Protocol header and credit FLITs transmitted across any slot", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", + "PerPkg": "1", + "UMask": "0x97", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Idle FLITs transmitted", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.IDLE", + "PerPkg": "1", + "UMask": "0x47", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Null FLITs transmitted from any slot", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", + "PerPkg": "1", + "UMask": "0x27", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Null FLITs received from any slot", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", + "PerPkg": "1", + "UMask": "0x27", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid data FLITs received from any slot", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", + "PerPkg": "1", + "UMask": "0x0F", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UPI_DATA_BANDWIDTH_TX", + "PerPkg": "1", + "ScaleUnit": "7.11E-06Bytes", + "UMask": "0xf", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UPI interconnect send bandwidth for payload", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", + "PerPkg": "1", + "ScaleUnit": "7.11E-06Bytes", + "UMask": "0xf", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Data Response packets that go direct to Intel UPI", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Traffic in which the M2M to iMC Bypass was not taken", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_M2M_BYPASS_M2M_Egress.NOT_TAKEN", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages sent direct to core (bypassing the CHA)", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_M2M_DIRECT2CORE_TAKEN", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of reads in which direct to core transaction were overridden", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)", + "Counter": "0,1,2,3", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)", + "Counter": "0,1,2,3", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)", + "Counter": "0,1,2,3", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)", + "Counter": "0,1,2,3", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from/to Any state", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from I to S", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from I to A", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from S to I", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from S to A", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from A to I", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from A to S", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Reads to iMC issued at Normal Priority (Non-Isochronous)", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.NORMAL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Reads to iMC issued", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.ALL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Partial Non-Isochronous writes to the iMC", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Writes to iMC issued", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.ALL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.NI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch requests that got turn into a demand request", + "Counter": "0,1,2,3", + "EventCode": "0x56", + "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Inserts into the Memory Controller Prefetch Queue", + "Counter": "0,1,2,3", + "EventCode": "0x57", + "EventName": "UNC_M2M_PREFCAM_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", + "EventCode": "0x1", + "EventName": "UNC_M2M_RxC_AD_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_M2M_RxC_BL_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_M2M_TxC_AD_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Allocations; All", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Occupancy; All", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles when direct to Intel UPI was disabled", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages sent direct to the Intel UPI", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_M2M_DIRECT2UPI_TAKEN", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetches generated by the flow control queue of the M3UPI unit", + "Counter": "0,1,2", + "EventCode": "0x29", + "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CHA to iMC Bypass; Taken", + "Counter": "0,1,2,3", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Bypass; Intermediate bypass Taken", + "Counter": "0,1,2,3", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Bypass; Not Taken", + "Counter": "0,1,2,3", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Single External Snoops", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Single Core Requests", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", + "PerPkg": "1", + "UMask": "0x41", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Single Eviction", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", + "PerPkg": "1", + "UMask": "0x81", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Any Single Snoop", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", + "PerPkg": "1", + "UMask": "0xE1", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Multiple External Snoops", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", + "PerPkg": "1", + "UMask": "0x22", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Any Cycle with Multiple Snoops", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", + "PerPkg": "1", + "UMask": "0xE2", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; External Snoop to Remote Node", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_REMOTE", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Core Request to Remote Node", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_REMOTE", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Eviction to Remote Node", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_REMOTE", + "PerPkg": "1", + "UMask": "0x84", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Any Snoop to Remote Node", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_REMOTE", + "PerPkg": "1", + "UMask": "0xE4", + "Unit": "CHA" + }, + { + "BriefDescription": "Counter 0 Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x1F", + "EventName": "UNC_CHA_COUNTER0_OCCUPANCY", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; Shared hit and op is RdInvOwn, RdInv, Inv*", + "Counter": "0,1,2,3", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE", + "Counter": "0,1,2,3", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.WBMTOE", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", + "Counter": "0,1,2,3", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*", + "Counter": "0,1,2,3", + "EventCode": "0x5E", + "EventName": "UNC_CHA_HITME_LOOKUP.READ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", + "Counter": "0,1,2,3", + "EventCode": "0x5E", + "EventName": "UNC_CHA_HITME_LOOKUP.WRITE", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Misses in HitMe Cache; SF/LLC HitS/F and op is RdInvOwn", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Misses in HitMe Cache; No SF/LLC HitS/F and op is RdInvOwn", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Misses in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache to SHARed", + "Counter": "0,1,2,3", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.SHARED", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache on RdInvOwn even if not RspFwdI*", + "Counter": "0,1,2,3", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Deallocate HtiME$ on Reads without RspFwdI*", + "Counter": "0,1,2,3", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "HA to iMC Reads Issued; ISOCH", + "Counter": "0,1,2,3", + "EventCode": "0x59", + "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Writes Issued to the iMC by the HA; Partial Non-ISOCH", + "Counter": "0,1,2,3", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Full Line", + "Counter": "0,1,2,3", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Partial", + "Counter": "0,1,2,3", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Writes Issued to the iMC by the HA; Full Line MIG", + "Counter": "0,1,2,3", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_MIG", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Writes Issued to the iMC by the HA; Partial MIG", + "Counter": "0,1,2,3", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations", + "Counter": "0,1,2,3", + "EventCode": "0x62", + "EventName": "UNC_CHA_IODC_ALLOC.INVITOM", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations dropped due to IODC Full", + "Counter": "0,1,2,3", + "EventCode": "0x62", + "EventName": "UNC_CHA_IODC_ALLOC.IODCFULL", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IDOC allocation dropped due to OSB gate", + "Counter": "0,1,2,3", + "EventCode": "0x62", + "EventName": "UNC_CHA_IODC_ALLOC.OSBGATED", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoE", + "Counter": "0,1,2,3", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOE", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoI", + "Counter": "0,1,2,3", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOI", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbPushMtoI", + "Counter": "0,1,2,3", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.WBPUSHMTOI", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to conflicting transaction", + "Counter": "0,1,2,3", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.SNPOUT", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to any reason", + "Counter": "0,1,2,3", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.ALL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITE", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.WRITE", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.ANY", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.ANY", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOCAL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.LOCAL", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.REMOTE", + "PerPkg": "1", + "UMask": "0x91", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.LOCAL", + "PerPkg": "1", + "UMask": "0x2f", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.REMOTE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc; Silent Snoop Eviction", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc; Write Combining Aliasing", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.WC_ALIASING", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc; CV0 Prefetch Victim", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc; CV0 Prefetch Miss", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast", + "Counter": "0,1,2,3", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC0_SMI0", + "Counter": "0,1,2,3", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC0_SMI0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC1_SMI1", + "Counter": "0,1,2,3", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC1_SMI1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC0_SMI2", + "Counter": "0,1,2,3", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.EDC0_SMI2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC1_SMI3", + "Counter": "0,1,2,3", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.EDC1_SMI3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC2_SMI4", + "Counter": "0,1,2,3", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.EDC2_SMI4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC3_SMI5", + "Counter": "0,1,2,3", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.EDC3_SMI5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "write requests from remote home agent", + "Counter": "0,1,2,3", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.ALL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Local Requests", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Remote Requests", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.BCST_LOC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_REMOTE", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.BCST_REM", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.DIRECT_LOC", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.DIRECT_REM", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : RspS", + "Counter": "0,1,2,3", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_WBWB", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSP_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received; RspFwd", + "Counter": "0,1,2,3", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPI", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPIFWD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPSFWD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_FWD_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPCNFLCT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPFWD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.EVICT", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.EVICT", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.PRQ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.PRQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IPQ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IPQ", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.HIT", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.HIT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.MISS", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.EVICT", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.EVICT", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.PRQ", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.PRQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IPQ", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IPQ", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.HIT", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.HIT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.MISS", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "WbPushMtoI; Pushed to LLC", + "Counter": "0,1,2,3", + "EventCode": "0x56", + "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "WbPushMtoI; Pushed to Memory", + "Counter": "0,1,2,3", + "EventCode": "0x56", + "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC0_SMI0", + "Counter": "0,1,2,3", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC1_SMI1", + "Counter": "0,1,2,3", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC0_SMI2", + "Counter": "0,1,2,3", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC1_SMI3", + "Counter": "0,1,2,3", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC2_SMI4", + "Counter": "0,1,2,3", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC3_SMI5", + "Counter": "0,1,2,3", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOC_IO", + "PerPkg": "1", + "UMask": "0x34", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOC_IA", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOC_ALL", + "PerPkg": "1", + "UMask": "0x37", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IO", + "PerPkg": "1", + "UMask": "0x34", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IA", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.LOC_ALL", + "PerPkg": "1", + "UMask": "0x37", + "Unit": "CHA" + }, + { + "BriefDescription": "Core PMA Events; C1 State", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.C1_STATE", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Core PMA Events; C1 Transition", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.C1_TRANSITION", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Core PMA Events; C6 State", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.C6_STATE", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Core PMA Events; C6 Transition", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.C6_TRANSITION", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Core PMA Events; GV", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.GV", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CMS_CLOCKTICKS", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_H_CLOCK", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Up", + "Counter": "0,1,2,3", + "EventCode": "0xAE", + "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Down", + "Counter": "0,1,2,3", + "EventCode": "0xAE", + "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA7", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA7", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA7", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA7", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA9", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA9", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA9", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA9", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Even", + "Counter": "0,1,2,3", + "EventCode": "0xAB", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xAB", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Even", + "Counter": "0,1,2,3", + "EventCode": "0xAB", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xAB", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Left", + "Counter": "0,1,2,3", + "EventCode": "0xAD", + "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Right", + "Counter": "0,1,2,3", + "EventCode": "0xAD", + "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; AD", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AD", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AK", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; BL", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; IV", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; AD", + "Counter": "0,1,2,3", + "EventCode": "0xA2", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core", + "Counter": "0,1,2,3", + "EventCode": "0xA2", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core", + "Counter": "0,1,2,3", + "EventCode": "0xA2", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache", + "Counter": "0,1,2,3", + "EventCode": "0xA2", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SRC_THRTL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xA4", + "EventName": "UNC_C_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; IRQ Rejected", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; IPQ", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IPQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; PRQ", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.PRQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; PRQ", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; RRQ", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.RRQ", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; WBQ", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.WBQ", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; AD REQ on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; AD RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; BL RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; BL WB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; BL NCB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; BL NCS on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ANY0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.ANY_IPQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; HA", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; LLC Victim", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; SF Victim", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; Victim", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; Merging these two together to make room for ANY_REJECT_*0", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; Allow Snoop", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; PhyAddr Match", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.ANY_REJECT_IRQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Merging these two together to make room for ANY_REJECT_*0", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; AD REQ on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; AD RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; BL RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; BL WB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; BL NCB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; BL NCS on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; AD REQ on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; AD RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; BL RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; BL WB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; BL NCB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; BL NCS on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x25", + "EventName": "UNC_H_RxC_ISMQ1_REJECT.ANY_ISMQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; HA", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x2D", + "EventName": "UNC_H_RxC_ISMQ1_RETRY.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; HA", + "Counter": "0,1,2,3", + "EventCode": "0x2D", + "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy; IPQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy; RRQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy; WBQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; AD REQ on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; AD RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; BL RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; BL WB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; BL NCB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; BL NCS on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; HA", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; LLC Victim", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; SF Victim", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; Victim", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; Merging these two together to make room for ANY_REJECT_*0", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; Allow Snoop", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; PhyAddr Match", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.ANY_PRQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC OR SF Way", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; AD REQ on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; AD RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; BL RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; BL WB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; BL NCB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; BL NCS on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; HA", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; LLC Victim", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; SF Victim", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; Victim", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; Merging these two together to make room for ANY_REJECT_*0", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; Allow Snoop", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; PhyAddr Match", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; AD REQ on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; AD RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; BL RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; BL WB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; BL NCB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; BL NCS on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ANY0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.ANY_RRQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; HA", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; LLC Victim", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; SF Victim", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; Victim", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; Merging these two together to make room for ANY_REJECT_*0", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; Allow Snoop", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; PhyAddr Match", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; AD REQ on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; AD RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; BL RSP on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; BL WB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; BL NCB on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; BL NCS on VN0", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ANY0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.ANY_WBQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; HA", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; LLC Victim", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; SF Victim", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; Victim", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; Merging these two together to make room for ANY_REJECT_*0", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; Allow Snoop", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; PhyAddr Match", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; IFV - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.IV", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.IV_AG1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.IV", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.IV", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.IV", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; IV", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.IV", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Up and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA6", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Up and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA6", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Down and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA6", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Down and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA6", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Up and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA8", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Up and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA8", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Down and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA8", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Down and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA8", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Up and Even", + "Counter": "0,1,2,3", + "EventCode": "0xAA", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Up and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xAA", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Down and Even", + "Counter": "0,1,2,3", + "EventCode": "0xAA", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Down and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xAA", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical IV Ring in Use; Up", + "Counter": "0,1,2,3", + "EventCode": "0xAC", + "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical IV Ring in Use; Down", + "Counter": "0,1,2,3", + "EventCode": "0xAC", + "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; External RspHitFSE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Core RspHitFSE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE", + "PerPkg": "1", + "UMask": "0x41", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Evict RspHitFSE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE", + "PerPkg": "1", + "UMask": "0x81", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Any RspHitFSE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE", + "PerPkg": "1", + "UMask": "0xE1", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; External RspSFwdFE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE", + "PerPkg": "1", + "UMask": "0x22", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdFE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE", + "PerPkg": "1", + "UMask": "0x42", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdFE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE", + "PerPkg": "1", + "UMask": "0x82", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdFE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE", + "PerPkg": "1", + "UMask": "0xE2", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; External RspIFwdFE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdFE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdFE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE", + "PerPkg": "1", + "UMask": "0x84", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Any RspIFwdFE", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE", + "PerPkg": "1", + "UMask": "0xE4", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; External RspSFwdM", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdM", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM", + "PerPkg": "1", + "UMask": "0x48", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdM", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM", + "PerPkg": "1", + "UMask": "0x88", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdM", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM", + "PerPkg": "1", + "UMask": "0xE8", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; External RspIFwdM", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM", + "PerPkg": "1", + "UMask": "0x30", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdM", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM", + "PerPkg": "1", + "UMask": "0x50", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdM", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM", + "PerPkg": "1", + "UMask": "0xF0", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT", + "PerPkg": "1", + "UMask": "0x18", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.RRQ_HIT", + "PerPkg": "1", + "UMask": "0x50", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.RRQ_MISS", + "PerPkg": "1", + "UMask": "0x60", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.WBQ_HIT", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.WBQ_MISS", + "PerPkg": "1", + "UMask": "0xA0", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_HIT", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_MISS", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_HIT", + "PerPkg": "1", + "UMask": "0x18", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_MISS", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; All from Local IO", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO", + "PerPkg": "1", + "UMask": "0x34", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; All from Local iA and IO", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL_IO_IA", + "PerPkg": "1", + "UMask": "0x35", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Hits from Local", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL_HIT", + "PerPkg": "1", + "UMask": "0x15", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Misses from Local", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL_MISS", + "PerPkg": "1", + "UMask": "0x25", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; All from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", + "PerPkg": "1", + "UMask": "0x34", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Hits from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Misses from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Hits from Local", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_HIT", + "PerPkg": "1", + "UMask": "0x17", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Misses from Local", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_MISS", + "PerPkg": "1", + "UMask": "0x27", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; VNA Credits", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VNA", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; VN0 Credits", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VN0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; AD REQ Credits", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_REQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; AD RSP VN0 Credits", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; BL RSP Credits", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_RSP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; BL DRS Credits", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; BL NCB Credits", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; BL NCS Credits", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; AD VNA Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL VNA Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_BL", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; AD REQ VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_REQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; AD RSP VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL RSP VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_RSP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL DRS VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCB VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; Non UPI AK Request", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; Non UPI IV Request", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; Non UPI AK Request", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; Non UPI IV Request", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; Non UPI AK Request", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; Non UPI IV Request", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; Non UPI AK Request", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; Non UPI IV Request", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; Non UPI AK Request", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; Non UPI IV Request", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; Non UPI AK Request", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; Non UPI IV Request", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; Non UPI AK Request", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; Non UPI IV Request", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; ANY0", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; All", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Broadcast snoop for Local Requests", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Broadcast snoops for Remote Requests", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Directed snoops for Local Requests", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Directed snoops for Remote Requests", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspI", + "Counter": "0,1,2,3", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspS", + "Counter": "0,1,2,3", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspIFwd", + "Counter": "0,1,2,3", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspSFwd", + "Counter": "0,1,2,3", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; Rsp*WB", + "Counter": "0,1,2,3", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB", + "Counter": "0,1,2,3", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspCnflct", + "Counter": "0,1,2,3", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspFwd", + "Counter": "0,1,2,3", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "EventCode": "0xC0", + "EventName": "UNC_CHA_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Write Requests", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.WRITE", + "PerPkg": "1", + "UMask": "0x05", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; External Snoop Request", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP", + "PerPkg": "1", + "UMask": "0x09", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.ANY", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Local", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Remote", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE", + "PerPkg": "1", + "UMask": "0x91", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.F_STATE", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Local - All Lines", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "PerPkg": "1", + "UMask": "0x2F", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; IRQ", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IRQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; SF/LLC Evictions", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.EVICT", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; PRQ", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PRQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; IPQ", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IPQ", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Hit (Not a Miss)", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.HIT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Miss", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", + "PerPkg": "1", + "UMask": "0x37", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IPQ_HIT", + "PerPkg": "1", + "UMask": "0x18", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IPQ_MISS", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.RRQ_HIT", + "PerPkg": "1", + "UMask": "0x50", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS", + "PerPkg": "1", + "UMask": "0x60", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.WBQ_HIT", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.WBQ_MISS", + "PerPkg": "1", + "UMask": "0xA0", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; IRQ", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; SF/LLC Evictions", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; PRQ", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; IPQ", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Hit (Not a Miss)", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Miss", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", + "PerPkg": "1", + "UMask": "0x37", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_HIT", + "PerPkg": "1", + "UMask": "0x18", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_MISS", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "Source Throttle", + "Counter": "0,1,2,3", + "EventCode": "0xA4", + "EventName": "UNC_CHA_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; ANY0", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; ANY0", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; ANY0", + "Counter": "0,1,2,3", + "EventCode": "0x2D", + "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; ANY0", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; ANY0", + "Counter": "0,1,2,3", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; ANY0", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; IV", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; IV", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; IV", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "CHA" + }, + { + "BriefDescription": "FaST wire asserted; Vertical", + "Counter": "0,1,2,3", + "EventCode": "0xA5", + "EventName": "UNC_CHA_FAST_ASSERTED.VERT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Local - Lines in M State", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Local - Lines in E State", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", + "PerPkg": "1", + "UMask": "0x22", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Local - Lines in S State", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Local - Lines in F State", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Remote - Lines in M State", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M", + "PerPkg": "1", + "UMask": "0x81", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Remote - Lines in E State", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E", + "PerPkg": "1", + "UMask": "0x82", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Remote - Lines in S State", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S", + "PerPkg": "1", + "UMask": "0x84", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Remote - Lines in F State", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_F", + "PerPkg": "1", + "UMask": "0x88", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Remote - All Lines", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "PerPkg": "1", + "UMask": "0x8F", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; All from Local", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC", + "PerPkg": "1", + "UMask": "0x37", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; RdCur misses from Local IO", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RDCUR", + "Filter": "config1=0x43C33", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; RFO misses from Local IO", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "Filter": "config1=0x40033", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; ItoM misses from Local IO", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Filter": "config1=0x49033", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; ITOM Misses from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", + "Filter": "config1=0x49033", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RDCUR misses from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RDCUR", + "Filter": "config1=0x43C33", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RFO misses from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", + "Filter": "config1=0x40033", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts; Port 0", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts; Port 1", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts; Port 2", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts; Port 3", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Num Link Correctable Errors", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "UNC_IIO_LINK_NUM_CORR_ERR", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Num Link Retries", + "Counter": "0,1,2,3", + "EventCode": "0xE", + "EventName": "UNC_IIO_LINK_NUM_RETRIES", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number packets that passed the Mask/Match Filter", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_IIO_MASK_MATCH", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus; PCIE bus", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and PCIE bus", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; PCIE bus", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and PCIE bus", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and !(PCIE bus)", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "UNC_IIO_NOTHING", + "Counter": "0,1,2,3", + "EventName": "UNC_IIO_NOTHING", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Symbol Times on Link", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_IIO_SYMBOL_TIMES", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; Vtd hit", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.L4_PAGE_HIT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; context cache miss", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.CTXT_MISS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; L1 miss", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.L1_MISS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; L2 miss", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.L2_MISS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; L3 miss", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.L3_MISS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; TLB miss", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.TLB_MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; TLB is full", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.TLB_FULL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; TLB miss", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.TLB1_MISS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_IIO_VTD_OCCUPANCY", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1", + "Counter": "0,1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1", + "Counter": "2,3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card reading from DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card reading from DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card writing to DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card writing to DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "Counter": "0,1,2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Total Write Cache Occupancy; Any Source", + "Counter": "0,1", + "EventCode": "0xF", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Total Write Cache Occupancy; Snoops", + "Counter": "0,1", + "EventCode": "0xF", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "IRP Clocks", + "Counter": "0,1", + "EventCode": "0x1", + "EventName": "UNC_I_CLOCKTICKS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; PCIRdCur", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; CRd", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.CRD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; DRd", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.DRD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; PCIDCAHin5t", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; WbMtoI", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.WBMTOI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; CLFlush", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF RF full", + "Counter": "0,1", + "EventCode": "0x17", + "EventName": "UNC_I_FAF_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF allocation -- sent to ADQ", + "Counter": "0,1", + "EventCode": "0x16", + "EventName": "UNC_I_FAF_TRANSACTIONS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "All Inserts Inbound (p2p + faf + cset)", + "Counter": "0,1", + "EventCode": "0x1E", + "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "All Inserts Outbound (BL, AK, Snoops)", + "Counter": "0,1", + "EventCode": "0x1E", + "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Fastpath Requests", + "Counter": "0,1", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.FAST_REQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Fastpath Rejects", + "Counter": "0,1", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.FAST_REJ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary", + "Counter": "0,1", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.2ND_RD_INSERT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary", + "Counter": "0,1", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.2ND_WR_INSERT", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary", + "Counter": "0,1", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary", + "Counter": "0,1", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.FAST_XFER", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary", + "Counter": "0,1", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.PF_ACK_HINT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0", + "Counter": "0,1", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.UNKNOWN", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line", + "Counter": "0,1", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SLOW_I", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line", + "Counter": "0,1", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SLOW_S", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line", + "Counter": "0,1", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SLOW_E", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line", + "Counter": "0,1", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SLOW_M", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Lost Forward", + "Counter": "0,1", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.LOST_FWD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Received Invalid", + "Counter": "0,1", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Received Valid", + "Counter": "0,1", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Requests", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "UNC_I_P2P_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Occupancy", + "Counter": "0,1", + "EventCode": "0x15", + "EventName": "UNC_I_P2P_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; P2P reads", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.RD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; P2P Writes", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.WR", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; P2P Message", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.MSG", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; P2P completions", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; Match if remote only", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.REM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; match if remote and target matches", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; match if local only", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.LOC", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; match if local and target matches", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Miss", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.MISS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Hit I", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_I", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Hit E or S", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_ES", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Hit M", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_M", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; SnpCode", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPCODE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; SnpData", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPDATA", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; SnpInv", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPINV", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Reads", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.READS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Writes", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.WRITES", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Read Prefetches", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.RD_PREF", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Atomic", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.ATOMIC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Other", + "Counter": "0,1", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.OTHER", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "No AD Egress Credit Stalls", + "Counter": "0,1", + "EventCode": "0x1A", + "EventName": "UNC_I_TxR2_AD_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "AK Egress Allocations", + "Counter": "0,1", + "EventCode": "0xB", + "EventName": "UNC_I_TxC_AK_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Cycles Full", + "Counter": "0,1", + "EventCode": "0x5", + "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Inserts", + "Counter": "0,1", + "EventCode": "0x2", + "EventName": "UNC_I_TxC_BL_DRS_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Occupancy", + "Counter": "0,1", + "EventCode": "0x8", + "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Cycles Full", + "Counter": "0,1", + "EventCode": "0x6", + "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Inserts", + "Counter": "0,1", + "EventCode": "0x3", + "EventName": "UNC_I_TxC_BL_NCB_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Occupancy", + "Counter": "0,1", + "EventCode": "0x9", + "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Cycles Full", + "Counter": "0,1", + "EventCode": "0x7", + "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Inserts", + "Counter": "0,1", + "EventCode": "0x4", + "EventName": "UNC_I_TxC_BL_NCS_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Occupancy", + "Counter": "0,1", + "EventCode": "0xA", + "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "No BL Egress Credit Stalls", + "Counter": "0,1", + "EventCode": "0x1B", + "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", + "EventCode": "0xD", + "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", + "EventCode": "0xE", + "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Request Queue Occupancy", + "Counter": "0,1", + "EventCode": "0xC", + "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", + "PerPkg": "1", + "UMask": "0x72", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", + "PerPkg": "1", + "UMask": "0x74", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", + "PerPkg": "1", + "UMask": "0x78", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", + "PerPkg": "1", + "UMask": "0x7e", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that miss the IIO cache", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", + "PerPkg": "1", + "UMask": "0x71", + "Unit": "IRP" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_UPI_PHY_INIT_CYCLES", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "L1 Req Nack", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "UNC_UPI_POWER_L1_NACK", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "L1 Req (same as L1 Ack)", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_UPI_POWER_L1_REQ", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "Counter": "0,1,2,3", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "Counter": "0,1,2,3", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "Counter": "0,1,2,3", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "Counter": "0,1,2,3", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Cycles in L0. Receive side", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_UPI_RxL0_POWER_CYCLES", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "CRC Errors Detected", + "Counter": "0,1,2,3", + "EventCode": "0xB", + "EventName": "UNC_UPI_RxL_CRC_ERRORS", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "LLR Requests Sent", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "VN0 Credit Consumed", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "VN1 Credit Consumed", + "Counter": "0,1,2,3", + "EventCode": "0x3A", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "VNA Credit Consumed", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received; Slot 0", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.SLOT0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received; Slot 1", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.SLOT1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received; Slot 2", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.SLOT2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received; Data", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.DATA", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received; LLCRD Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.LLCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received; LLCTRL", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.LLCTRL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.PROTHDR", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.PROT_HDR", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.REQ", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.SNP", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.RSP", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.WB", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.WB", + "PerPkg": "1", + "UMask": "0xB", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.NCB", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.NCS", + "PerPkg": "1", + "UMask": "0xD", + "Unit": "UPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets; Slot 0", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets; Slot 1", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI LL" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets; Slot 2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "Counter": "0,1,2,3", + "EventCode": "0x29", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Cycles in L0. Transmit side", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "UNC_UPI_TxL0_POWER_CYCLES", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent; Slot 0", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.SLOT0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent; Slot 1", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.SLOT1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent; Slot 2", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.SLOT2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent; LLCRD Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.LLCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent; LLCTRL", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.LLCTRL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.PROTHDR", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.PROT_HDR", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.REQ", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.SNP", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.WB", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.WB", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.NCB", + "PerPkg": "1", + "UMask": "0xE", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.NCS", + "PerPkg": "1", + "UMask": "0xF", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Tx Flit Buffer Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_UPI_TxL_INSERTS", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Tx Flit Buffer Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x42", + "EventName": "UNC_UPI_TxL_OCCUPANCY", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "Counter": "0,1,2,3", + "EventCode": "0x45", + "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "VNA Credits Pending Return - Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x44", + "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY", + "PerPkg": "1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received; Protocol Header", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.PROTHDR", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Sent; Protocol Header", + "Counter": "0,1,2,3", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.PROTHDR", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI LL" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.LOC", + "PerPkg": "1", + "UMaskExt": "0x02", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.REM", + "PerPkg": "1", + "UMaskExt": "0x04", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.DATA_HDR", + "PerPkg": "1", + "UMaskExt": "0x08", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.NON_DATA_HDR", + "PerPkg": "1", + "UMaskExt": "0x10", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.DUAL_SLOT_HDR", + "PerPkg": "1", + "UMaskExt": "0x20", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. ", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.SGL_SLOT_HDR", + "PerPkg": "1", + "UMaskExt": "0x40", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_NODATA", + "PerPkg": "1", + "UMask": "0xA", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_DATA", + "PerPkg": "1", + "UMask": "0xC", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Valid Flits Received; Idle", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.IDLE", + "PerPkg": "1", + "UMask": "0x47", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Request", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Request Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC", + "PerPkg": "1", + "UMask": "0x0108", + "UMaskExt": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Snoop", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", + "PerPkg": "1", + "UMask": "0x09", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Snoop Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC", + "PerPkg": "1", + "UMask": "0x0109", + "UMaskExt": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA", + "PerPkg": "1", + "UMask": "0x0A", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "PerPkg": "1", + "UMask": "0x010A", + "UMaskExt": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", + "PerPkg": "1", + "UMask": "0x0C", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "PerPkg": "1", + "UMask": "0x010C", + "UMaskExt": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Writeback", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB", + "PerPkg": "1", + "UMask": "0x0D", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Writeback", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC", + "PerPkg": "1", + "UMask": "0x010D", + "UMaskExt": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", + "PerPkg": "1", + "UMask": "0x0E", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC", + "PerPkg": "1", + "UMask": "0x010E", + "UMaskExt": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", + "PerPkg": "1", + "UMask": "0x0F", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC", + "PerPkg": "1", + "UMask": "0x010F", + "UMaskExt": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Request", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Request Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC", + "PerPkg": "1", + "UMask": "0x108", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", + "PerPkg": "1", + "UMask": "0x09", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC", + "PerPkg": "1", + "UMask": "0x109", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", + "PerPkg": "1", + "UMask": "0x0A", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "PerPkg": "1", + "UMask": "0x10A", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", + "PerPkg": "1", + "UMask": "0x0C", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "PerPkg": "1", + "UMask": "0x10C", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB", + "PerPkg": "1", + "UMask": "0x0D", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC", + "PerPkg": "1", + "UMask": "0x10D", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", + "PerPkg": "1", + "UMask": "0x0E", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC", + "PerPkg": "1", + "UMask": "0x10E", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", + "PerPkg": "1", + "UMask": "0x0F", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC", + "PerPkg": "1", + "UMask": "0x10F", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - Conflict", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT", + "PerPkg": "1", + "UMask": "0x01AA", + "UMaskExt": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - Invalid", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI", + "PerPkg": "1", + "UMask": "0x012A", + "UMaskExt": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations; Slot 0", + "Counter": "0,1,2,3", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "UPI LL" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations; Slot 1", + "Counter": "0,1,2,3", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "UPI LL" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations; Slot 2", + "Counter": "0,1,2,3", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Conflict", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT", + "PerPkg": "1", + "UMask": "0x1AA", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Invalid", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI", + "PerPkg": "1", + "UMask": "0x12A", + "UMaskExt": "0x1", + "Unit": "UPI LL" + }, + { + "BriefDescription": "M2M to iMC Bypass; Taken", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_M2M_BYPASS_M2M_Egress.TAKEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles - at UCLK", + "Counter": "0,1,2,3", + "EventName": "UNC_M2M_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On Dirty Line in I State", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On Dirty Line in S State", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On Dirty Line in L State", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On Dirty Line in A State", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On NonDirty Line in I State", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On NonDirty Line in S State", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On NonDirty Line in L State", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On NonDirty Line in A State", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On Dirty Line in I State", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On Dirty Line in S State", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On Dirty Line in L State", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On Dirty Line in A State", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On NonDirty Line in I State", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On NonDirty Line in S State", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On NonDirty Line in L State", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On NonDirty Line in A State", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC; Critical Priority", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.ISOCH", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC; All, regardless of priority", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.FROM_TRANSGRESS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC; Full Line Non-ISOCH", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FULL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC; ISOCH Full Line", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC; ISOCH Partial", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FROM_TRANSGRESS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Number Packet Header Matches; Mesh Match", + "Counter": "0,1,2,3", + "EventCode": "0x4C", + "EventName": "UNC_M2M_PKT_MATCH.MESH", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number Packet Header Matches; MC Match", + "Counter": "0,1,2,3", + "EventCode": "0x4C", + "EventName": "UNC_M2M_PKT_MATCH.MC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Full", + "Counter": "0,1,2,3", + "EventCode": "0x53", + "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "UNC_M2M_PREFCAM_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x55", + "EventName": "UNC_M2M_PREFCAM_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Number AD Ingress Credits", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_M2M_TGR_AD_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number BL Ingress Credits", + "Counter": "0,1,2,3", + "EventCode": "0x42", + "EventName": "UNC_M2M_TGR_BL_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Full; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Full; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Full; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Not Empty; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Not Empty; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Not Empty; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Occupancy; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Occupancy; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Occupancy; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Pending Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x48", + "EventName": "UNC_M2M_TRACKER_PENDING_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x61", + "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x61", + "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x61", + "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Down", + "Counter": "0,1,2,3", + "EventCode": "0xAE", + "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Up", + "Counter": "0,1,2,3", + "EventCode": "0xAE", + "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA7", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA7", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA7", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA7", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA9", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA9", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA9", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA9", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Even", + "Counter": "0,1,2,3", + "EventCode": "0xAB", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xAB", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Even", + "Counter": "0,1,2,3", + "EventCode": "0xAB", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xAB", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Left", + "Counter": "0,1,2,3", + "EventCode": "0xAD", + "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Right", + "Counter": "0,1,2,3", + "EventCode": "0xAD", + "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV", + "Counter": "0,1,2,3", + "EventCode": "0xA1", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; AD", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache", + "Counter": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AD", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AK", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; BL", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; IV", + "Counter": "0,1,2,3", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; AD", + "Counter": "0,1,2,3", + "EventCode": "0xA2", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core", + "Counter": "0,1,2,3", + "EventCode": "0xA2", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core", + "Counter": "0,1,2,3", + "EventCode": "0xA2", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache", + "Counter": "0,1,2,3", + "EventCode": "0xA2", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Source Throttle", + "Counter": "0,1,2,3", + "EventCode": "0xA4", + "EventName": "UNC_M2M_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Full", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x3", + "EventName": "UNC_M2M_RxC_AD_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Full", + "Counter": "0,1,2,3", + "EventCode": "0x8", + "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_M2M_RxC_BL_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB4", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; IFV - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5", + "Counter": "0,1,2,3", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Credits Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0xE", + "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Credit Acquired", + "Counter": "0,1,2,3", + "EventCode": "0xD", + "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Full", + "Counter": "0,1,2,3", + "EventCode": "0xC", + "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Not Empty", + "Counter": "0,1,2,3", + "EventCode": "0xB", + "EventName": "UNC_M2M_TxC_AD_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No AD Egress (to CMS) Credits", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound Ring Transactions on AK; CRD Transactions to Cbo", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_M2M_TxC_AK.CRD_CBO", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound Ring Transactions on AK; NDR Transactions", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_M2M_TxC_AK.NDR", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x1F", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x1F", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_CACHE", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_CORE", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x1A", + "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x1A", + "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Full; All", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Not Empty; All", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce", + "Counter": "0,1,2,3", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; IV", + "Counter": "0,1,2,3", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", + "Counter": "0,1,2,3", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV", + "Counter": "0,1,2,3", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; IV", + "Counter": "0,1,2,3", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; IV", + "Counter": "0,1,2,3", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG0", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Down and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA6", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Down and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA6", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Up and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA6", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Up and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA6", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Down and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA8", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Down and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA8", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Up and Even", + "Counter": "0,1,2,3", + "EventCode": "0xA8", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Up and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xA8", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Down and Even", + "Counter": "0,1,2,3", + "EventCode": "0xAA", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Down and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xAA", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Up and Even", + "Counter": "0,1,2,3", + "EventCode": "0xAA", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Up and Odd", + "Counter": "0,1,2,3", + "EventCode": "0xAA", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical IV Ring in Use; Down", + "Counter": "0,1,2,3", + "EventCode": "0xAC", + "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical IV Ring in Use; Up", + "Counter": "0,1,2,3", + "EventCode": "0xAC", + "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_TxC_BL.DRS_UPI", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0x40", + "EventName": "UNC_NoUnit_TxC_BL.DRS_UPI", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_UPI", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; IV", + "Counter": "0,1,2,3", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", + "Counter": "0,1,2,3", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC Bypass; Taken", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC Bypass; Not Taken", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "EventCode": "0xC0", + "EventName": "UNC_M2M_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "FaST wire asserted; Vertical", + "Counter": "0,1,2,3", + "EventCode": "0xA5", + "EventName": "UNC_M2M_FAST_ASSERTED.VERT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "FaST wire asserted; Horizontal", + "Counter": "0,1,2,3", + "EventCode": "0xA5", + "EventName": "UNC_M2M_FAST_ASSERTED.HORZ", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 1", + "Counter": "0,1,2,3", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 2", + "Counter": "0,1,2,3", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1", + "PerPkg": "1", + "UMask": "0x88", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1", + "PerPkg": "1", + "UMask": "0xA0", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; All", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; Read Credit Request", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; Write Credit Request", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; Write Compare Request", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; All", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Read Credit Request", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Write Credit Request", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Write Compare Request", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Prefetch Read Cam Hit", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; All", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; Read Credit Request", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; Write Credit Request", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; Write Compare Request", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; All", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Sideband", + "Counter": "0,1,2,3", + "EventCode": "0x6B", + "EventName": "UNC_M2M_TxC_AK_SIDEBAND.RD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Sideband", + "Counter": "0,1,2,3", + "EventCode": "0x6B", + "EventName": "UNC_M2M_TxC_AK_SIDEBAND.WR", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M2M" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VNA", + "Counter": "0,1,2", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN0 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN0 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN0 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN1 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN1 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN1 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty; VN1 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty; VN1 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty; VN1 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN0", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN0", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN1", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN1", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty; VNA Messages", + "Counter": "0,1,2", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty; Writebacks", + "Counter": "0,1,2", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty; Requests", + "Counter": "0,1,2", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty; Snoops", + "Counter": "0,1,2", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of uclks in domain", + "Counter": "0,1,2", + "EventCode": "0x1", + "EventName": "UNC_M3UPI_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "D2U Sent", + "Counter": "0,1,2", + "EventCode": "0x2A", + "EventName": "UNC_M3UPI_D2U_SENT", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)", + "Counter": "0,1,2", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO0_IIO1_NCB", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; IIO2", + "Counter": "0,1,2", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; IIO3", + "Counter": "0,1,2", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; IIO4", + "Counter": "0,1,2", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; IIO5", + "Counter": "0,1,2", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; All IIO targets for NCS are in single mask. ORs them together", + "Counter": "0,1,2", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; Selected M2p BL NCS credits", + "Counter": "0,1,2", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; AD - Slot 0", + "Counter": "0,1,2", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; AD - Slot 1", + "Counter": "0,1,2", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; AD - Slot 2", + "Counter": "0,1,2", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; BL - Slot 0", + "Counter": "0,1,2", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; AK - Slot 0", + "Counter": "0,1,2", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; AK - Slot 2", + "Counter": "0,1,2", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN0 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN0 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN0 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN1 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN1 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN1 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN1 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN0 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN0 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN0 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN1 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN1 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN1 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN1 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN0 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN0 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN0 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN1 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN1 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN1 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN0 REQ Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN0 SNP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN0 RSP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN0 WB Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN1 REQ Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN1 SNP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN1 RSP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_WB", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN0 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN0 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN1 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN1 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN1 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_WB", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN0 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN0 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN0 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN1 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN1 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN1 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN1 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_WB", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AK Flow Q Inserts", + "Counter": "0,1,2", + "EventCode": "0x2F", + "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AK Flow Q Occupancy", + "EventCode": "0x1E", + "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN0 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN0 NCB Messages", + "Counter": "0,1,2", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN0 NCS Messages", + "Counter": "0,1,2", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN1 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN1 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN1 NCS Messages", + "Counter": "0,1,2", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN1 NCB Messages", + "Counter": "0,1,2", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN0 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN0 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN0 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN1 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN1 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN1 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN1 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN0 NCS Messages", + "Counter": "0,1,2", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN0 NCB Messages", + "Counter": "0,1,2", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN0 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN1_NCB Messages", + "Counter": "0,1,2", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN1_NCS Messages", + "Counter": "0,1,2", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN1 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN1 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN0 RSP Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN0 WB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN0 NCB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN0 NCS Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN1 RSP Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN1 WB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN1_NCS Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN1_NCB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_WB", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN0 NCS Messages", + "Counter": "0,1,2", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN1 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN1 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN1 NCB Messages", + "Counter": "0,1,2", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_WB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCB Messages", + "Counter": "0,1,2", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCS Messages", + "Counter": "0,1,2", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 WB Messages", + "Counter": "0,1,2", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCS Messages", + "Counter": "0,1,2", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCB Messages", + "Counter": "0,1,2", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; CHA on VN0", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_CHA", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; CHA on VN1", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_CHA", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN0", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_NON_IDLE", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN1", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_NON_IDLE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Snoop Arbitration; FlowQ Won", + "Counter": "0,1,2", + "EventCode": "0x3D", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_NONSNP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Snoop Arbitration; FlowQ Won", + "Counter": "0,1,2", + "EventCode": "0x3D", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_NONSNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", + "Counter": "0,1,2", + "EventCode": "0x3D", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_VN2SNP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", + "Counter": "0,1,2", + "EventCode": "0x3D", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_VN0SNP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0", + "Counter": "0,1,2", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1", + "Counter": "0,1,2", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2", + "Counter": "0,1,2", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3", + "Counter": "0,1,2", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4", + "Counter": "0,1,2", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5", + "Counter": "0,1,2", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0", + "Counter": "0,1,2", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1", + "Counter": "0,1,2", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2", + "Counter": "0,1,2", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3", + "Counter": "0,1,2", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4", + "Counter": "0,1,2", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5", + "Counter": "0,1,2", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0", + "Counter": "0,1,2", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1", + "Counter": "0,1,2", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2", + "Counter": "0,1,2", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3", + "Counter": "0,1,2", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4", + "Counter": "0,1,2", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5", + "Counter": "0,1,2", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0", + "Counter": "0,1,2", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1", + "Counter": "0,1,2", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2", + "Counter": "0,1,2", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3", + "Counter": "0,1,2", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4", + "Counter": "0,1,2", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5", + "Counter": "0,1,2", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0", + "Counter": "0,1,2", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1", + "Counter": "0,1,2", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2", + "Counter": "0,1,2", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3", + "Counter": "0,1,2", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4", + "Counter": "0,1,2", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5", + "Counter": "0,1,2", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0", + "Counter": "0,1,2", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1", + "Counter": "0,1,2", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2", + "Counter": "0,1,2", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3", + "Counter": "0,1,2", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4", + "Counter": "0,1,2", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5", + "Counter": "0,1,2", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR1", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP", "UMask": "0x2", - "Unit": "CHA" + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0", + "Counter": "0,1,2", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1", + "Counter": "0,1,2", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2", + "Counter": "0,1,2", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3", + "Counter": "0,1,2", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4", + "Counter": "0,1,2", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5", + "Counter": "0,1,2", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2", + "EventCode": "0xC0", + "EventName": "UNC_M3UPI_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Up", + "Counter": "0,1,2", + "EventCode": "0xAE", + "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Down", + "Counter": "0,1,2", + "EventCode": "0xAE", + "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Even", + "Counter": "0,1,2", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", + "Counter": "0,1,2", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Even", + "Counter": "0,1,2", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", + "Counter": "0,1,2", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Even", + "Counter": "0,1,2", + "EventCode": "0xA9", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", + "Counter": "0,1,2", + "EventCode": "0xA9", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Even", + "Counter": "0,1,2", + "EventCode": "0xA9", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", + "Counter": "0,1,2", + "EventCode": "0xA9", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Even", + "Counter": "0,1,2", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", + "Counter": "0,1,2", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Even", + "Counter": "0,1,2", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", + "Counter": "0,1,2", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Left", + "Counter": "0,1,2", + "EventCode": "0xAD", + "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Right", + "Counter": "0,1,2", + "EventCode": "0xAD", + "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD", + "Counter": "0,1,2", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK", + "Counter": "0,1,2", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL", + "Counter": "0,1,2", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV", + "Counter": "0,1,2", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; AD", + "Counter": "0,1,2", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core", + "Counter": "0,1,2", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core", + "Counter": "0,1,2", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache", + "Counter": "0,1,2", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AD", + "Counter": "0,1,2", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AK", + "Counter": "0,1,2", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; BL", + "Counter": "0,1,2", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; IV", + "Counter": "0,1,2", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1", + "Counter": "0,1,2", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; AD", + "Counter": "0,1,2", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core", + "Counter": "0,1,2", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core", + "Counter": "0,1,2", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache", + "Counter": "0,1,2", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Source Throttle", + "Counter": "0,1,2", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN0", + "Counter": "0,1,2", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN1", + "Counter": "0,1,2", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN0", + "Counter": "0,1,2", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN1", + "Counter": "0,1,2", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN0", + "Counter": "0,1,2", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN1", + "Counter": "0,1,2", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; AD, BL Parallel Win", + "Counter": "0,1,2", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on Idle", + "Counter": "0,1,2", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on BL Arb", + "Counter": "0,1,2", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 1", + "Counter": "0,1,2", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 2", + "Counter": "0,1,2", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events; Any In BGF FIFO", + "Counter": "0,1,2", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events; Any in BGF Path", + "Counter": "0,1,2", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events; No D2K For Arb", + "Counter": "0,1,2", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.NO_D2K_FOR_ARB", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy; VNA In Use", + "Counter": "0,1,2", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy; Packets in BGF FIFO", + "Counter": "0,1,2", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy; Packets in BGF Path", + "Counter": "0,1,2", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy; Transmit Credits", + "Counter": "0,1,2", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy; D2K Credits", + "Counter": "0,1,2", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy", + "Counter": "0,1,2", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy", + "Counter": "0,1,2", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent; All", + "Counter": "0,1,2", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent; No BGF Credits", + "Counter": "0,1,2", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_BGF", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent; No TxQ Credits", + "Counter": "0,1,2", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_TXQ", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 0", + "Counter": "0,1,2", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 1", + "Counter": "0,1,2", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC", + "Counter": "0,1,2", + "EventCode": "0x5A", + "EventName": "UNC_M3UPI_RxC_FLITS_MISC", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit; One Message", + "Counter": "0,1,2", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit; Two Messages", + "Counter": "0,1,2", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.2_MSGS", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit; Three Messages", + "Counter": "0,1,2", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.3_MSGS", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit; One Message in non-VNA", + "Counter": "0,1,2", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG_VNX", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; All", + "Counter": "0,1,2", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Needs Data Flit", + "Counter": "0,1,2", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 0", + "Counter": "0,1,2", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 1", + "Counter": "0,1,2", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1", + "Counter": "0,1,2", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Bubble", + "Counter": "0,1,2", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Not Avail", + "Counter": "0,1,2", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Acumullate", + "Counter": "0,1,2", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Accumulate Ready", + "Counter": "0,1,2", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Accumulate Wasted", + "Counter": "0,1,2", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Blocked", + "Counter": "0,1,2", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Message", + "Counter": "0,1,2", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Parallel Ok", + "Counter": "0,1,2", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Parallel Message", + "Counter": "0,1,2", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_MSG", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Parallel Flit Finished", + "Counter": "0,1,2", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_FLIT", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall", + "Counter": "0,1,2", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall - No Message", + "Counter": "0,1,2", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; All", + "Counter": "0,1,2", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; No BGF Credits", + "Counter": "0,1,2", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_CRD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; No TxQ Credits", + "Counter": "0,1,2", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_CRD", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; No BGF Credits + No Extra Message Slotted", + "Counter": "0,1,2", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_NO_MSG", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; No TxQ Credits + No Extra Message Slotted", + "Counter": "0,1,2", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_NO_MSG", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; Sent - One Slot Taken", + "Counter": "0,1,2", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ONE_TAKEN", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; Sent - Two Slots Taken", + "Counter": "0,1,2", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.TWO_TAKEN", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; Sent - Three Slots Taken", + "Counter": "0,1,2", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.THREE_TAKEN", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; VN0", + "Counter": "0,1,2", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.VN0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; VN1", + "Counter": "0,1,2", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.VN1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Parallel Attempt", + "Counter": "0,1,2", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Parallel Success", + "Counter": "0,1,2", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Parallel AD Lost", + "Counter": "0,1,2", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_AD_LOST", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Parallel BL Lost", + "Counter": "0,1,2", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_BL_LOST", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Can't Slot AD", + "Counter": "0,1,2", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Can't Slot BL", + "Counter": "0,1,2", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; REQ on AD", + "Counter": "0,1,2", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; SNP on AD", + "Counter": "0,1,2", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; RSP on AD", + "Counter": "0,1,2", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; RSP on BL", + "Counter": "0,1,2", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; WB on BL", + "Counter": "0,1,2", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; NCB on BL", + "Counter": "0,1,2", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; NCS on BL", + "Counter": "0,1,2", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "SMI3 Prefetch Messages; Arrived", + "Counter": "0,1,2", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARRIVED", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "SMI3 Prefetch Messages; Lost Arbitration", + "Counter": "0,1,2", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARB_LOST", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "SMI3 Prefetch Messages; Slotted", + "Counter": "0,1,2", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.SLOTTED", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "SMI3 Prefetch Messages; Dropped - Old", + "Counter": "0,1,2", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_OLD", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "SMI3 Prefetch Messages; Dropped - Wrap", + "Counter": "0,1,2", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_WRAP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Used", + "Counter": "0,1,2", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.USED", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Corrected", + "Counter": "0,1,2", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Level < 1", + "Counter": "0,1,2", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Level < 4", + "Counter": "0,1,2", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Level < 5", + "Counter": "0,1,2", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Any In Use", + "Counter": "0,1,2", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; IV - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x53", - "EventName": "UNC_H_DIR_LOOKUP.SNP", + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP", - "UMask": "0x1", - "Unit": "CHA" + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x54", - "EventName": "UNC_H_DIR_UPDATE.HA", + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA", - "UMask": "0x1", - "Unit": "CHA" + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x54", - "EventName": "UNC_H_DIR_UPDATE.TOR", + "BriefDescription": "Transgress Injection Starvation; IFV - Credit", + "Counter": "0,1,2", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR", - "UMask": "0x2", - "Unit": "CHA" + "UMask": "0x80", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5F", - "EventName": "UNC_H_HITME_HIT.EX_RDS", + "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", + "Counter": "0,1,2", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0", + "Counter": "0,1,2", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1", + "Counter": "0,1,2", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2", + "Counter": "0,1,2", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3", + "Counter": "0,1,2", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4", + "Counter": "0,1,2", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5", + "Counter": "0,1,2", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0", + "Counter": "0,1,2", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1", + "Counter": "0,1,2", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2", + "Counter": "0,1,2", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3", + "Counter": "0,1,2", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4", + "Counter": "0,1,2", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5", + "Counter": "0,1,2", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0", + "Counter": "0,1,2", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1", + "Counter": "0,1,2", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2", + "Counter": "0,1,2", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3", + "Counter": "0,1,2", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4", + "Counter": "0,1,2", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5", + "Counter": "0,1,2", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0", + "Counter": "0,1,2", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1", + "Counter": "0,1,2", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2", + "Counter": "0,1,2", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3", + "Counter": "0,1,2", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x08", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4", + "Counter": "0,1,2", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5", + "Counter": "0,1,2", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_BNC", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AK_BNC", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS", - "UMask": "0x1", - "Unit": "CHA" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x39", - "EventName": "UNC_H_MISC.RFO_HIT_S", + "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_BNC", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S", - "UMask": "0x8", - "Unit": "CHA" + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL", + "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL", "UMask": "0x10", - "Unit": "CHA" + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE", + "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE", - "UMask": "0x20", - "Unit": "CHA" + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.READS", + "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_BNC", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS", - "UMask": "0x3", - "Unit": "CHA" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS_LOCAL", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.READS_LOCAL", + "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK_BNC", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS_LOCAL", - "UMask": "0x1", - "Unit": "CHA" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.WRITES", + "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_BNC", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES", - "UMask": "0xC", - "Unit": "CHA" + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES_LOCAL", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", + "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", + "Counter": "0,1,2", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV_BNC", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES_LOCAL", - "UMask": "0x4", - "Unit": "CHA" + "UMask": "0x08", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x13", - "EventName": "UNC_H_RxC_INSERTS.IRQ", + "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ", - "UMask": "0x1", - "Unit": "CHA" + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x19", - "EventName": "UNC_H_RxC_IRQ1_REJECT.PA_MATCH", + "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", - "UMask": "0x80", - "Unit": "CHA" + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ", - "Deprecated": "1", - "EventCode": "0x11", - "EventName": "UNC_H_RxC_OCCUPANCY.IRQ", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_BNC", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ", - "UMask": "0x1", - "Unit": "CHA" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPCNFLCTS", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK_BNC", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPCNFLCTS", - "UMask": "0x40", - "Unit": "CHA" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSPIFWD", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_BNC", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD", - "UMask": "0x4", - "Unit": "CHA" + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce", + "Counter": "0,1,2", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV_BNC", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD", - "UMask": "0x8", - "Unit": "CHA" + "UMask": "0x08", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB", - "UMask": "0x20", - "Unit": "CHA" + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "Clockticks of the IIO Traffic Controller", - "Counter": "0,1,2,3", - "EventCode": "0x1", - "EventName": "UNC_IIO_CLOCKTICKS", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD", "PerPkg": "1", - "PublicDescription": "Counts clockticks of the 1GHz trafiic controller clock in the IIO unit.", - "Unit": "IIO" + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3", - "Counter": "0,1,2,3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", - "FCMask": "0x4", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_BNC", "PerPkg": "1", - "PortMask": "0x0f", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3", - "UMask": "0x03", - "Unit": "IIO" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", - "Counter": "0,1,2,3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", - "FCMask": "0x4", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK_BNC", "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", - "UMask": "0x03", - "Unit": "IIO" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", - "Counter": "0,1,2,3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", - "FCMask": "0x4", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_BNC", "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", - "UMask": "0x03", - "Unit": "IIO" + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", - "Counter": "0,1,2,3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", - "FCMask": "0x4", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce", + "Counter": "0,1,2", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV_BNC", "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", - "UMask": "0x03", - "Unit": "IIO" + "UMask": "0x08", + "Unit": "M3UPI" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", - "Counter": "0,1,2,3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", - "FCMask": "0x4", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD", "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", - "UMask": "0x03", - "Unit": "IIO" + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3", - "Counter": "2,3", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", - "FCMask": "0x04", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD", "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3", - "UMask": "0x0f", - "Unit": "IIO" + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0", - "Counter": "2,3", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", - "FCMask": "0x04", + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_BNC", "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0", "UMask": "0x01", - "Unit": "IIO" + "Unit": "M3UPI" }, { - "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1", - "Counter": "2,3", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", - "FCMask": "0x04", + "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK_BNC", "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1", "UMask": "0x02", - "Unit": "IIO" + "Unit": "M3UPI" }, { - "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2", - "Counter": "2,3", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", - "FCMask": "0x04", + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_BNC", "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2", "UMask": "0x04", - "Unit": "IIO" + "Unit": "M3UPI" }, { - "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3", - "Counter": "2,3", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", - "FCMask": "0x04", + "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", + "Counter": "0,1,2", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV_BNC", "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3", "UMask": "0x08", - "Unit": "IIO" + "Unit": "M3UPI" }, { - "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", - "FCMask": "0x07", + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD", "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", - "FCMask": "0x07", + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD", "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part2", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", - "FCMask": "0x07", + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_BNC", "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part3", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", - "FCMask": "0x07", + "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK_BNC", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_BNC", "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", "UMask": "0x04", - "Unit": "IIO" + "Unit": "M3UPI" }, { - "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", + "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", + "Counter": "0,1,2", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV_BNC", "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x08", + "Unit": "M3UPI" }, { - "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD", "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x20", + "Unit": "M3UPI" }, { - "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD", "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_BNC", "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", "UMask": "0x01", - "Unit": "IIO" + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", - "FCMask": "0x07", + "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK_BNC", "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x08", - "Unit": "IIO" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", - "FCMask": "0x07", + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_BNC", "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x08", - "Unit": "IIO" + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", - "FCMask": "0x07", + "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", + "Counter": "0,1,2", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV_BNC", "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", "UMask": "0x08", - "Unit": "IIO" + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", - "FCMask": "0x07", + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", + "Counter": "0,1,2", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD", "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x08", - "Unit": "IIO" + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", + "Counter": "0,1,2", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD", "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce", + "Counter": "0,1,2", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_BNC", "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce", + "Counter": "0,1,2", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK_BNC", "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", "UMask": "0x02", - "Unit": "IIO" + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", + "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce", + "Counter": "0,1,2", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_BNC", "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", - "FCMask": "0x07", + "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce", + "Counter": "0,1,2", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV_BNC", "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", "UMask": "0x08", - "Unit": "IIO" + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", - "FCMask": "0x07", + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0", "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x08", - "Unit": "IIO" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", - "FCMask": "0x07", + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG0", "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x08", - "Unit": "IIO" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", - "FCMask": "0x07", + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0", "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x08", - "Unit": "IIO" + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1", "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG1", "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x20", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1", "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0", "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", - "Counter": "0,1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0", - "FCMask": "0x7", + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0", "PerPkg": "1", - "PortMask": "0x1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", - "UMask": "0x4", - "Unit": "IIO" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", - "Counter": "0,1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1", - "FCMask": "0x7", + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0", "PerPkg": "1", - "PortMask": "0x2", - "PublicDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", - "UMask": "0x4", - "Unit": "IIO" + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", - "Counter": "0,1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2", - "FCMask": "0x7", + "BriefDescription": "CMS Vertical ADS Used; IV", + "Counter": "0,1,2", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV", "PerPkg": "1", - "PortMask": "0x4", - "PublicDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", - "UMask": "0x4", - "Unit": "IIO" + "UMask": "0x08", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "Counter": "0,1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3", - "FCMask": "0x7", + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1", "PerPkg": "1", - "PortMask": "0x8", - "PublicDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "UMask": "0x4", - "Unit": "IIO" + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", - "Counter": "0,1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0", - "FCMask": "0x7", + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1", "PerPkg": "1", - "PortMask": "0x1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", - "UMask": "0x1", - "Unit": "IIO" + "UMask": "0x20", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", - "Counter": "0,1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1", - "FCMask": "0x7", + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1", "PerPkg": "1", - "PortMask": "0x2", - "PublicDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", - "UMask": "0x1", - "Unit": "IIO" + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", - "Counter": "0,1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2", - "FCMask": "0x7", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG0", "PerPkg": "1", - "PortMask": "0x4", - "PublicDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", - "UMask": "0x1", - "Unit": "IIO" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "Counter": "0,1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3", - "FCMask": "0x7", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG0", "PerPkg": "1", - "PortMask": "0x8", - "PublicDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "UMask": "0x1", - "Unit": "IIO" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", - "FCMask": "0x07", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG0", "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", "UMask": "0x04", - "Unit": "IIO" + "Unit": "M3UPI" }, { - "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", - "FCMask": "0x07", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", + "Counter": "0,1,2", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.IV", "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x08", + "Unit": "M3UPI" }, { - "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", - "FCMask": "0x07", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG1", "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", - "FCMask": "0x07", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG1", "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x20", + "Unit": "M3UPI" }, { - "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG1", "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG0", "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", "UMask": "0x01", - "Unit": "IIO" + "Unit": "M3UPI" }, { - "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG0", "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG0", "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", - "FCMask": "0x07", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV", + "Counter": "0,1,2", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.IV", "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", "UMask": "0x08", - "Unit": "IIO" + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", - "FCMask": "0x07", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG1", "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x08", - "Unit": "IIO" + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", - "FCMask": "0x07", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG1", "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x08", - "Unit": "IIO" + "UMask": "0x20", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", - "FCMask": "0x07", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG1", "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x08", - "Unit": "IIO" + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG0", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG0", "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", "UMask": "0x02", - "Unit": "IIO" + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG0", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", + "BriefDescription": "CMS Vert Egress Allocations; IV", + "Counter": "0,1,2", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.IV", "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x08", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG1", "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG1", "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x20", + "Unit": "M3UPI" }, { - "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", - "FCMask": "0x07", + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG1", "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part1 to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", - "FCMask": "0x07", + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG0", "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", - "FCMask": "0x07", + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG0", "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", - "FCMask": "0x07", + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG0", "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", "UMask": "0x04", - "Unit": "IIO" + "Unit": "M3UPI" }, { - "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG1", "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG1", "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x20", + "Unit": "M3UPI" }, { - "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG1", "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG0", "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", "UMask": "0x01", - "Unit": "IIO" + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", - "FCMask": "0x07", + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG0", "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x08", - "Unit": "IIO" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", - "FCMask": "0x07", + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG0", "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x08", - "Unit": "IIO" + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", - "FCMask": "0x07", + "BriefDescription": "CMS Vert Egress Occupancy; IV", + "Counter": "0,1,2", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.IV", "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", "UMask": "0x08", - "Unit": "IIO" + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", - "FCMask": "0x07", + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG1", "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x08", - "Unit": "IIO" + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG1", "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x20", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG1", "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part1 to the MMIO space of an IIO target.In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG0", "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG0", "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", "UMask": "0x02", - "Unit": "IIO" + "Unit": "M3UPI" }, { - "BriefDescription": "Total IRP occupancy of inbound read and write requests.", - "Counter": "0,1", - "EventCode": "0xF", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0", + "Counter": "0,1,2", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG0", "PerPkg": "1", - "PublicDescription": "Total IRP occupancy of inbound read and write requests. This is effectively the sum of read occupancy and write occupancy.", - "UMask": "0x4", - "Unit": "IRP" + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.", - "Counter": "0,1", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.PCITOM", + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG1", "PerPkg": "1", - "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.", "UMask": "0x10", - "Unit": "IRP" + "Unit": "M3UPI" }, { - "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.", - "Counter": "0,1", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.RFO", + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG1", "PerPkg": "1", - "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.", - "UMask": "0x8", - "Unit": "IRP" + "UMask": "0x20", + "Unit": "M3UPI" }, { - "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.", - "Counter": "0,1", - "EventCode": "0x18", - "EventName": "UNC_I_FAF_INSERTS", + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1", + "Counter": "0,1,2", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG1", "PerPkg": "1", - "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.", - "Unit": "IRP" + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "Occupancy of the IRP FAF queue.", - "Counter": "0,1", - "EventCode": "0x19", - "EventName": "UNC_I_FAF_OCCUPANCY", + "BriefDescription": "Vertical AD Ring In Use; Up and Even", + "Counter": "0,1,2", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN", "PerPkg": "1", - "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.", - "Unit": "IRP" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "Inbound write (fast path) requests received by the IRP.", - "Counter": "0,1", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "BriefDescription": "Vertical AD Ring In Use; Up and Odd", + "Counter": "0,1,2", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD", "PerPkg": "1", - "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", - "UMask": "0x8", - "Unit": "IRP" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "Traffic in which the M2M to iMC Bypass was not taken", - "Counter": "0,1,2,3", - "EventCode": "0x22", - "EventName": "UNC_M2M_BYPASS_M2M_Egress.NOT_TAKEN", + "BriefDescription": "Vertical AD Ring In Use; Down and Even", + "Counter": "0,1,2", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x04", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Down and Odd", + "Counter": "0,1,2", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD", "PerPkg": "1", - "PublicDescription": "Counts traffic in which the M2M (Mesh to Memory) to iMC (Memory Controller) bypass was not taken", - "UMask": "0x2", - "Unit": "M2M" + "UMask": "0x08", + "Unit": "M3UPI" }, { - "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + "BriefDescription": "Vertical AK Ring In Use; Up and Even", + "Counter": "0,1,2", + "EventCode": "0xA8", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN", "PerPkg": "1", - "PublicDescription": "Counts cycles when direct to core mode (which bypasses the CHA) was disabled", - "Unit": "M2M" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "Messages sent direct to core (bypassing the CHA)", - "Counter": "0,1,2,3", - "EventCode": "0x23", - "EventName": "UNC_M2M_DIRECT2CORE_TAKEN", + "BriefDescription": "Vertical AK Ring In Use; Up and Odd", + "Counter": "0,1,2", + "EventCode": "0xA8", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD", "PerPkg": "1", - "PublicDescription": "Counts when messages were sent direct to core (bypassing the CHA)", - "Unit": "M2M" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "Number of reads in which direct to core transaction were overridden", - "Counter": "0,1,2,3", - "EventCode": "0x25", - "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", + "BriefDescription": "Vertical AK Ring In Use; Down and Even", + "Counter": "0,1,2", + "EventCode": "0xA8", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN", "PerPkg": "1", - "PublicDescription": "Counts reads in which direct to core transactions (which would have bypassed the CHA) were overridden", - "Unit": "M2M" + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden", - "Counter": "0,1,2,3", - "EventCode": "0x28", - "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", + "BriefDescription": "Vertical AK Ring In Use; Down and Odd", + "Counter": "0,1,2", + "EventCode": "0xA8", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD", "PerPkg": "1", - "PublicDescription": "Counts reads in which direct to Intel Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overridden", - "Unit": "M2M" + "UMask": "0x08", + "Unit": "M3UPI" }, { - "BriefDescription": "Cycles when direct to Intel UPI was disabled", - "Counter": "0,1,2,3", - "EventCode": "0x27", - "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", + "BriefDescription": "Vertical BL Ring in Use; Up and Even", + "Counter": "0,1,2", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN", "PerPkg": "1", - "PublicDescription": "Counts cycles when the ability to send messages direct to the Intel Ultra Path Interconnect (bypassing the CHA) was disabled", - "Unit": "M2M" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "Messages sent direct to the Intel UPI", - "Counter": "0,1,2,3", - "EventCode": "0x26", - "EventName": "UNC_M2M_DIRECT2UPI_TAKEN", + "BriefDescription": "Vertical BL Ring in Use; Up and Odd", + "Counter": "0,1,2", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD", "PerPkg": "1", - "PublicDescription": "Counts when messages were sent direct to the Intel Ultra Path Interconnect (bypassing the CHA)", - "Unit": "M2M" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden", - "Counter": "0,1,2,3", - "EventCode": "0x29", - "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", + "BriefDescription": "Vertical BL Ring in Use; Down and Even", + "Counter": "0,1,2", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN", "PerPkg": "1", - "PublicDescription": "Counts when a read message that was sent direct to the Intel Ultra Path Interconnect (bypassing the CHA) was overridden", - "Unit": "M2M" + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)", - "Counter": "0,1,2,3", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", + "BriefDescription": "Vertical BL Ring in Use; Down and Odd", + "Counter": "0,1,2", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in Any State (A, I, S or unused)", - "UMask": "0x1", - "Unit": "M2M" + "UMask": "0x08", + "Unit": "M3UPI" }, { - "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)", - "Counter": "0,1,2,3", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", + "BriefDescription": "Vertical IV Ring in Use; Up", + "Counter": "0,1,2", + "EventCode": "0xAC", + "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in the A (SnoopAll) state, indicating the cacheline is stored in another socket in any state, and we must snoop the other sockets to make sure we get the latest data. The data may be stored in any state in the local socket.", - "UMask": "0x8", - "Unit": "M2M" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)", - "Counter": "0,1,2,3", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", + "BriefDescription": "Vertical IV Ring in Use; Down", + "Counter": "0,1,2", + "EventCode": "0xAC", + "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the I (Invalid) state indicating the cacheline is not stored in another socket, and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket.", - "UMask": "0x2", - "Unit": "M2M" + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)", - "Counter": "0,1,2,3", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", + "BriefDescription": "D2C Sent", + "Counter": "0,1,2", + "EventCode": "0x2B", + "EventName": "UNC_M3UPI_D2C_SENT", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the S (Shared) state indicating the cacheline is either stored in another socket in the S(hared) state , and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket.", - "UMask": "0x4", - "Unit": "M2M" + "Unit": "M3UPI" }, { - "BriefDescription": "Multi-socket cacheline Directory update from A to I", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I", + "BriefDescription": "FaST wire asserted; Vertical", + "Counter": "0,1,2", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_FAST_ASSERTED.VERT", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from A (SnoopAll) to I (Invalid)", - "UMask": "0x20", - "Unit": "M2M" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "Multi-socket cacheline Directory update from A to S", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S", + "BriefDescription": "FaST wire asserted; Horizontal", + "Counter": "0,1,2", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_FAST_ASSERTED.HORZ", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from A (SnoopAll) to S (Shared)", - "UMask": "0x40", - "Unit": "M2M" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "Multi-socket cacheline Directory update from/to Any state", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", + "BriefDescription": "Sent Header Flit", + "Counter": "0,1,2", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_1", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory to a new state", - "UMask": "0x1", - "Unit": "M2M" + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "Multi-socket cacheline Directory update from I to A", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A", + "BriefDescription": "Sent Header Flit", + "Counter": "0,1,2", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_2", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from I (Invalid) to A (SnoopAll)", - "UMask": "0x4", - "Unit": "M2M" + "UMask": "0x20", + "Unit": "M3UPI" }, { - "BriefDescription": "Multi-socket cacheline Directory update from I to S", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S", + "BriefDescription": "Sent Header Flit", + "Counter": "0,1,2", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_3", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from I (Invalid) to S (Shared)", - "UMask": "0x2", - "Unit": "M2M" + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "Multi-socket cacheline Directory update from S to A", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A", + "BriefDescription": "CMS Vertical Egress NACKs; IV", + "Counter": "0,1,2", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.IV", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from S (Shared) to A (SnoopAll)", - "UMask": "0x10", - "Unit": "M2M" + "UMask": "0x08", + "Unit": "M3UPI" }, { - "BriefDescription": "Multi-socket cacheline Directory update from S to I", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I", + "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", + "Counter": "0,1,2", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.IV", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from S (Shared) to I (Invalid)", - "UMask": "0x8", - "Unit": "M2M" + "UMask": "0x08", + "Unit": "M3UPI" }, { - "BriefDescription": "Reads to iMC issued", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.ALL", + "BriefDescription": "UPI0 BL Credits Empty; VNA", + "Counter": "0,1,2", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller).", - "UMask": "0x4", - "Unit": "M2M" + "UMask": "0x01", + "Unit": "M3UPI" }, { - "BriefDescription": "Reads to iMC issued at Normal Priority (Non-Isochronous)", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.NORMAL", + "BriefDescription": "UPI0 BL Credits Empty; VN0 REQ Messages", + "Counter": "0,1,2", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller). It only counts normal priority non-isochronous reads.", - "UMask": "0x1", - "Unit": "M2M" + "UMask": "0x02", + "Unit": "M3UPI" }, { - "BriefDescription": "Writes to iMC issued", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.ALL", + "BriefDescription": "UPI0 BL Credits Empty; VN0 RSP Messages", + "Counter": "0,1,2", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) issues writes to the iMC (Memory Controller).", - "UMask": "0x10", - "Unit": "M2M" + "UMask": "0x04", + "Unit": "M3UPI" }, { - "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority.", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.NI", + "BriefDescription": "UPI0 BL Credits Empty; VN0 SNP Messages", + "Counter": "0,1,2", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB", "PerPkg": "1", - "PublicDescription": "M2M Writes Issued to iMC; All, regardless of priority.", - "UMask": "0x80", - "Unit": "M2M" + "UMask": "0x08", + "Unit": "M3UPI" }, { - "BriefDescription": "Partial Non-Isochronous writes to the iMC", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", + "BriefDescription": "Message Received; VLW", + "Counter": "0,1", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) issues partial writes to the iMC (Memory Controller). It only counts normal priority non-isochronous writes.", - "UMask": "0x2", - "Unit": "M2M" + "UMask": "0x1", + "Unit": "UBOX" }, { - "BriefDescription": "Prefetch requests that got turn into a demand request", - "Counter": "0,1,2,3", - "EventCode": "0x56", - "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS", + "BriefDescription": "Message Received; MSI", + "Counter": "0,1", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address. Explanatory Side Note: The Prefetch queue is made of CAM (Content Addressable Memory)", - "Unit": "M2M" + "UMask": "0x2", + "Unit": "UBOX" }, { - "BriefDescription": "Inserts into the Memory Controller Prefetch Queue", - "Counter": "0,1,2,3", - "EventCode": "0x57", - "EventName": "UNC_M2M_PREFCAM_INSERTS", + "BriefDescription": "Message Received; IPI", + "Counter": "0,1", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) receives a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory", - "Unit": "M2M" + "UMask": "0x4", + "Unit": "UBOX" }, { - "BriefDescription": "AD Ingress (from CMS) Queue Inserts", - "Counter": "0,1,2,3", - "EventCode": "0x1", - "EventName": "UNC_M2M_RxC_AD_INSERTS", + "BriefDescription": "Message Received", + "Counter": "0,1", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", "PerPkg": "1", - "PublicDescription": "Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop). This is generally used for reads, and", - "Unit": "M2M" + "UMask": "0x8", + "Unit": "UBOX" }, { - "BriefDescription": "AD Ingress (from CMS) Occupancy", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", + "BriefDescription": "Message Received", + "Counter": "0,1", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.INT_PRIO", "PerPkg": "1", - "PublicDescription": "AD Ingress (from CMS) Occupancy", - "Unit": "M2M" + "UMask": "0x10", + "Unit": "UBOX" }, { - "BriefDescription": "BL Ingress (from CMS) Allocations", - "Counter": "0,1,2,3", - "EventCode": "0x5", - "EventName": "UNC_M2M_RxC_BL_INSERTS", + "BriefDescription": "IDI Lock/SplitLock Cycles", + "Counter": "0,1", + "EventCode": "0x44", + "EventName": "UNC_U_LOCK_CYCLES", "PerPkg": "1", - "PublicDescription": "BL Ingress (from CMS) Allocations", - "Unit": "M2M" + "Unit": "UBOX" }, { - "BriefDescription": "BL Ingress (from CMS) Occupancy", - "Counter": "0,1,2,3", - "EventCode": "0x6", - "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", + "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", + "Counter": "0,1", + "EventCode": "0x45", + "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", "PerPkg": "1", - "PublicDescription": "BL Ingress (from CMS) Occupancy", - "Unit": "M2M" + "UMask": "0x1", + "Unit": "UBOX" }, { - "BriefDescription": "AD Egress (to CMS) Allocations", - "Counter": "0,1,2,3", - "EventCode": "0x9", - "EventName": "UNC_M2M_TxC_AD_INSERTS", + "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", + "Counter": "0,1", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.RDRAND", "PerPkg": "1", - "PublicDescription": "AD Egress (to CMS) Allocations", - "Unit": "M2M" + "UMask": "0x1", + "Unit": "UBOX" }, { - "BriefDescription": "AD Egress (to CMS) Occupancy", - "Counter": "0,1,2,3", - "EventCode": "0xA", - "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", + "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", + "Counter": "0,1", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.RDSEED", "PerPkg": "1", - "PublicDescription": "AD Egress (to CMS) Occupancy", - "Unit": "M2M" + "UMask": "0x2", + "Unit": "UBOX" }, { - "BriefDescription": "BL Egress (to CMS) Allocations; All", - "Counter": "0,1,2,3", - "EventCode": "0x15", - "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", + "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "Counter": "0,1", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", "PerPkg": "1", - "PublicDescription": "BL Egress (to CMS) Allocations; All", - "UMask": "0x03", - "Unit": "M2M" + "UMask": "0x4", + "Unit": "UBOX" }, { - "BriefDescription": "BL Egress (to CMS) Occupancy; All", - "Counter": "0,1,2,3", - "EventCode": "0x16", - "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.ALL", + "BriefDescription": "RACU Request", + "Counter": "0,1", + "EventCode": "0x46", + "EventName": "UNC_U_RACU_REQUESTS", "PerPkg": "1", - "PublicDescription": "BL Egress (to CMS) Occupancy; All", - "UMask": "0x03", - "Unit": "M2M" + "Unit": "UBOX" }, { - "BriefDescription": "Prefetches generated by the flow control queue of the M3UPI unit.", - "Counter": "0,1,2", - "EventCode": "0x29", - "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", + "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", + "Counter": "FIXED", + "EventCode": "0xff", + "EventName": "UNC_U_CLOCKTICKS", "PerPkg": "1", - "PublicDescription": "Count cases where flow control queue that sits between the Intel Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller)", - "Unit": "M3UPI" + "Unit": "UBOX" }, { - "BriefDescription": "Clocks of the Intel Ultra Path Interconnect (UPI)", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE", "Counter": "0,1,2,3", - "EventCode": "0x1", - "EventName": "UNC_UPI_CLOCKTICKS", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.CORE_GTONE", "PerPkg": "1", - "PublicDescription": "Counts clockticks of the fixed frequency clock controlling the Intel Ultra Path Interconnect (UPI). This clock runs at1/8th the 'GT/s' speed of the UPI link. For example, a 9.6GT/s link will have a fixed Frequency of 1.2 Ghz.", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE", + "UMask": "0x42", + "Unit": "CHA" }, { - "BriefDescription": "Data Response packets that go direct to core", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE", "Counter": "0,1,2,3", - "EventCode": "0x12", - "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.EVICT_GTONE", "PerPkg": "1", - "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to core bypassing the CHA.", - "UMask": "0x1", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE", + "UMask": "0x82", + "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_DIRECT_ATTEMPTS.D2U", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP", "Counter": "0,1,2,3", "Deprecated": "1", - "EventCode": "0x12", - "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K", + "EventCode": "0x53", + "EventName": "UNC_H_DIR_LOOKUP.NO_SNP", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_UPI_DIRECT_ATTEMPTS.D2U", + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP", "UMask": "0x2", - "Unit": "UPI LL" + "Unit": "CHA" }, { - "BriefDescription": "Data Response packets that go direct to Intel UPI", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP", "Counter": "0,1,2,3", - "EventCode": "0x12", - "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U", + "Deprecated": "1", + "EventCode": "0x53", + "EventName": "UNC_H_DIR_LOOKUP.SNP", "PerPkg": "1", - "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to Intel Ultra Path Interconnect (UPI) bypassing the CHA .", - "UMask": "0x2", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Cycles Intel UPI is in L1 power mode (shutdown)", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA", "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_UPI_L1_POWER_CYCLES", + "Deprecated": "1", + "EventCode": "0x54", + "EventName": "UNC_H_DIR_UPDATE.HA", "PerPkg": "1", - "PublicDescription": "Counts cycles when the Intel Ultra Path Interconnect (UPI) is in L1 power mode. L1 is a mode that totally shuts down the UPI link. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdown.", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Cycles the Rx of the Intel UPI is in L0p power mode", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR", "Counter": "0,1,2,3", - "EventCode": "0x25", - "EventName": "UNC_UPI_RxL0P_POWER_CYCLES", + "Deprecated": "1", + "EventCode": "0x54", + "EventName": "UNC_H_DIR_UPDATE.TOR", "PerPkg": "1", - "PublicDescription": "Counts cycles when the the receive side (Rx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR", + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS", "Counter": "0,1,2,3", - "EventCode": "0x31", - "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", + "Deprecated": "1", + "EventCode": "0x5F", + "EventName": "UNC_H_HITME_HIT.EX_RDS", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS", "UMask": "0x1", - "Unit": "UPI LL" + "Unit": "CHA" }, { - "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S", "Counter": "0,1,2,3", - "EventCode": "0x31", - "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", + "Deprecated": "1", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.RFO_HIT_S", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", - "UMask": "0x2", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S", + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL", "Counter": "0,1,2,3", - "EventCode": "0x31", - "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", - "UMask": "0x4", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL", + "UMask": "0x10", + "Unit": "CHA" }, { - "BriefDescription": "Valid data FLITs received from any slot", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE", "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE", "PerPkg": "1", - "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.", - "UMask": "0x0F", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE", + "UMask": "0x20", + "Unit": "CHA" }, { - "BriefDescription": "Null FLITs received from any slot", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS", "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.READS", "PerPkg": "1", - "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.", - "UMask": "0x27", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS", + "UMask": "0x3", + "Unit": "CHA" }, { - "BriefDescription": "Protocol header and credit FLITs received from any slot", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS_LOCAL", "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.READS_LOCAL", "PerPkg": "1", - "PublicDescription": "Counts protocol header and credit FLITs (80 bit FLow control unITs) received from any of the 3 UPI slots on this UPI unit.", - "UMask": "0x97", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS_LOCAL", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.ALL_NULL", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES", "Counter": "0,1,2,3", "Deprecated": "1", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.NULL", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.WRITES", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.ALL_NULL", - "UMask": "0x20", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES", + "UMask": "0xC", + "Unit": "CHA" }, { - "BriefDescription": "Cycles in which the Tx of the Intel Ultra Path Interconnect (UPI) is in L0p power mode", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES_LOCAL", "Counter": "0,1,2,3", - "EventCode": "0x27", - "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", "PerPkg": "1", - "PublicDescription": "Counts cycles when the transmit side (Tx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES_LOCAL", + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "FLITs that bypassed the TxL Buffer", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ", "Counter": "0,1,2,3", - "EventCode": "0x41", - "EventName": "UNC_UPI_TxL_BYPASSED", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.IRQ", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link. However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR mode, increasing latency to transfer out to the link.", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Null FLITs transmitted from any slot", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.PA_MATCH", "PerPkg": "1", - "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel Ulra Path Interconnect (UPI) slots on this UPI unit.", - "UMask": "0x27", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "UMask": "0x80", + "Unit": "CHA" }, { - "BriefDescription": "Valid Flits Sent; Data", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.DATA", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ", + "Deprecated": "1", + "EventCode": "0x11", + "EventName": "UNC_H_RxC_OCCUPANCY.IRQ", "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..", - "UMask": "0x8", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Idle FLITs transmitted", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD", "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.IDLE", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPIFWD", "PerPkg": "1", - "PublicDescription": "Counts when the Intel Ultra Path Interconnect(UPI) transmits an idle FLIT(80 bit FLow control unITs). Every UPI cycle must be sending either data FLITs, protocol/credit FLITs or idle FLITs.", - "UMask": "0x47", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD", + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Protocol header and credit FLITs transmitted across any slot", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD", "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", "PerPkg": "1", - "PublicDescription": "Counts protocol header and credit FLITs (80 bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Interconnect) slots on this UPI unit.", - "UMask": "0x97", - "Unit": "UPI LL" + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD", + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_NULL", + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB", "Counter": "0,1,2,3", "Deprecated": "1", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.NULL", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_NULL", + "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB", "UMask": "0x20", - "Unit": "UPI LL" + "Unit": "CHA" } ] diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json b/tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json new file mode 100644 index 000000000000..64301a600ede --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json @@ -0,0 +1,201 @@ +[ + { + "BriefDescription": "pclk Cycles", + "Counter": "0,1,2,3", + "EventName": "UNC_P_CLOCKTICKS", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "UNC_P_CORE_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "UNC_P_DEMOTIONS", + "Counter": "0,1,2,3", + "EventCode": "0x30", + "EventName": "UNC_P_DEMOTIONS", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Phase Shed 0 Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x75", + "EventName": "UNC_P_FIVR_PS_PS0_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Phase Shed 1 Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x76", + "EventName": "UNC_P_FIVR_PS_PS1_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Phase Shed 2 Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x77", + "EventName": "UNC_P_FIVR_PS_PS2_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Phase Shed 3 Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x78", + "EventName": "UNC_P_FIVR_PS_PS3_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Thermal Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x4", + "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Power Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x5", + "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Cycles spent changing Frequency", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "UNC_P_FREQ_TRANS_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "UNC_P_MCP_PROCHOT_CYCLES", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "UNC_P_MCP_PROCHOT_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Memory Phase Shedding Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C0", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C2E", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C3", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C6", + "Counter": "0,1,2,3", + "EventCode": "0x2D", + "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES", + "Counter": "0,1,2,3", + "EventCode": "0x7", + "EventName": "UNC_P_PMAX_THROTTLED_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Number of cores in C-State; C0 and C1", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Number of cores in C-State; C3", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Number of cores in C-State; C6 and C7", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "External Prochot", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Internal Prochot", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Total Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "VR Hot", + "Counter": "0,1,2,3", + "EventCode": "0x42", + "EventName": "UNC_P_VR_HOT_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + } +] -- cgit v1.2.3 From aa0d6e9cc23e996b484725d0a31906809862d678 Mon Sep 17 00:00:00 2001 From: Zhengjun Xing Date: Fri, 12 Aug 2022 16:52:39 +0800 Subject: perf vendor events: Update events for snowridgex Update the events to v1.20, update events for snowridgex by the latest event converter tools. Use script at: https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py to download and generate the latest events and metrics. Manually copy the snowridgex files into perf. Signed-off-by: Xing Zhengjun Tested-by: Ian Rogers Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20220812085239.3089231-12-zhengjun.xing@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/snowridgex/uncore-other.json | 111 +++++---------------- 1 file changed, 27 insertions(+), 84 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json index 4750b3806a51..1701db46696d 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json @@ -132,23 +132,22 @@ "Unit": "CHA" }, { - "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss", + "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", - "EventName": "LLC_MISSES.UNCACHEABLE", - "Filter": "config1=0x40e33", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", "PerPkg": "1", "UMask": "0xC001FE01", "UMaskExt": "0xC001FE", "Unit": "CHA" }, { - "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ", + "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", + "EventName": "LLC_MISSES.UNCACHEABLE", "Filter": "config1=0x40e33", "PerPkg": "1", "UMask": "0xC001FE01", @@ -167,18 +166,6 @@ "UMaskExt": "0xC001FE", "Unit": "CHA" }, - { - "BriefDescription": "MMIO reads", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", - "Filter": "config1=0x40040e33", - "PerPkg": "1", - "UMask": "0xC001FE01", - "UMaskExt": "0xC001FE", - "Unit": "CHA" - }, { "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss", "Counter": "0,1,2,3", @@ -191,18 +178,6 @@ "UMaskExt": "0xC001FE", "Unit": "CHA" }, - { - "BriefDescription": "MMIO writes", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", - "Filter": "config1=0x40041e33", - "PerPkg": "1", - "UMask": "0xC001FE01", - "UMaskExt": "0xC001FE", - "Unit": "CHA" - }, { "BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss", "Counter": "0,1,2,3", @@ -216,19 +191,6 @@ "UMaskExt": "0xC001FE", "Unit": "CHA" }, - { - "BriefDescription": "Streaming stores (full cache line)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", - "Filter": "config1=0x41833", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0xC001FE01", - "UMaskExt": "0xC001FE", - "Unit": "CHA" - }, { "BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss", "Counter": "0,1,2,3", @@ -242,19 +204,6 @@ "UMaskExt": "0xC001FE", "Unit": "CHA" }, - { - "BriefDescription": "Streaming stores (partial cache line)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", - "Filter": "config1=0x41a33", - "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0xC001FE01", - "UMaskExt": "0xC001FE", - "Unit": "CHA" - }, { "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC", "Counter": "0,1,2,3", @@ -829,31 +778,12 @@ "Unit": "IIO" }, { - "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "LLC_MISSES.PCIE_WRITE", - "FCMask": "0x07", - "Filter": "ch_mask=0x1f", - "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "MetricName": "LLC_MISSES.PCIE_WRITE", - "PerPkg": "1", - "PortMask": "0x01", - "ScaleUnit": "4Bytes", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth writing at IIO", + "BriefDescription": "PCI Express bandwidth writing at IIO, part 0", "Counter": "0,1", "CounterType": "PGMABLE", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", "FCMask": "0x07", - "Filter": "ch_mask=0x1f", - "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "MetricName": "LLC_MISSES.PCIE_WRITE", "PerPkg": "1", "PortMask": "0x01", "ScaleUnit": "4Bytes", @@ -900,31 +830,28 @@ "Unit": "IIO" }, { - "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0", + "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0", "Counter": "0,1", "CounterType": "PGMABLE", "EventCode": "0x83", - "EventName": "LLC_MISSES.PCIE_READ", + "EventName": "LLC_MISSES.PCIE_WRITE", "FCMask": "0x07", "Filter": "ch_mask=0x1f", - "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "MetricName": "LLC_MISSES.PCIE_READ", + "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "MetricName": "LLC_MISSES.PCIE_WRITE", "PerPkg": "1", "PortMask": "0x01", "ScaleUnit": "4Bytes", - "UMask": "0x04", + "UMask": "0x01", "Unit": "IIO" }, { - "BriefDescription": "PCI Express bandwidth reading at IIO", + "BriefDescription": "PCI Express bandwidth reading at IIO, part 0", "Counter": "0,1", "CounterType": "PGMABLE", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", "FCMask": "0x07", - "Filter": "ch_mask=0x1f", - "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "MetricName": "LLC_MISSES.PCIE_READ", "PerPkg": "1", "PortMask": "0x01", "ScaleUnit": "4Bytes", @@ -970,6 +897,22 @@ "UMask": "0x04", "Unit": "IIO" }, + { + "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "LLC_MISSES.PCIE_READ", + "FCMask": "0x07", + "Filter": "ch_mask=0x1f", + "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "MetricName": "LLC_MISSES.PCIE_READ", + "PerPkg": "1", + "PortMask": "0x01", + "ScaleUnit": "4Bytes", + "UMask": "0x04", + "Unit": "IIO" + }, { "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", "Counter": "0,1", -- cgit v1.2.3 From 7391db6459388d47d657aad633cb55fc04a8d4fb Mon Sep 17 00:00:00 2001 From: Carsten Haitzler Date: Fri, 12 Aug 2022 13:16:28 +0100 Subject: perf test: Refactor shell tests allowing subdirs This is a prelude to adding more tests to shell tests and in order to support putting those tests into subdirectories, I need to change the test code that scans/finds and runs them. To support subdirs I have to recurse so it's time to refactor the code to allow this and centralize the shell script finding into one location and only one single scan that builds a list of all the found tests in memory instead of it being duplicated in 3 places. This code also optimizes things like knowing the max width of desciption strings (as we can do that while we scan instead of a whole new pass of opening files). It also more cleanly filters scripts to see only *.sh files thus skipping random other files in directories like *~ backup files, other random junk/data files that may appear and the scripts must be executable to make the cut (this ensures the script lib dir is not seen as scripts to run). This avoids perf test running previous older versions of test scripts that are editor backup files as well as skipping perf.data files that may appear and so on. Reviewed-by: Leo Yan Signed-off-by: Carsten Haitzler Tested-by: Leo Yan Cc: Mathieu Poirier Cc: Mike Leach Cc: Suzuki Poulouse Cc: coresight@lists.linaro.org Link: https://lore.kernel.org/r/20220812121641.336465-2-carsten.haitzler@foss.arm.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/Build | 1 + tools/perf/tests/builtin-test-list.c | 207 +++++++++++++++++++++++++++++++++++ tools/perf/tests/builtin-test-list.h | 12 ++ tools/perf/tests/builtin-test.c | 152 +++---------------------- 4 files changed, 238 insertions(+), 134 deletions(-) create mode 100644 tools/perf/tests/builtin-test-list.c create mode 100644 tools/perf/tests/builtin-test-list.h diff --git a/tools/perf/tests/Build b/tools/perf/tests/Build index af2b37ef7c70..2064a640facb 100644 --- a/tools/perf/tests/Build +++ b/tools/perf/tests/Build @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 perf-y += builtin-test.o +perf-y += builtin-test-list.o perf-y += parse-events.o perf-y += dso-data.o perf-y += attr.o diff --git a/tools/perf/tests/builtin-test-list.c b/tools/perf/tests/builtin-test-list.c new file mode 100644 index 000000000000..a65b9e547d82 --- /dev/null +++ b/tools/perf/tests/builtin-test-list.c @@ -0,0 +1,207 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "builtin.h" +#include "builtin-test-list.h" +#include "color.h" +#include "debug.h" +#include "hist.h" +#include "intlist.h" +#include "string2.h" +#include "symbol.h" +#include "tests.h" +#include "util/rlimit.h" + + +/* + * As this is a singleton built once for the run of the process, there is + * no value in trying to free it and just let it stay around until process + * exits when it's cleaned up. + */ +static size_t files_num = 0; +static struct script_file *files = NULL; +static int files_max_width = 0; + +static const char *shell_tests__dir(char *path, size_t size) +{ + const char *devel_dirs[] = { "./tools/perf/tests", "./tests", }; + char *exec_path; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(devel_dirs); ++i) { + struct stat st; + + if (!lstat(devel_dirs[i], &st)) { + scnprintf(path, size, "%s/shell", devel_dirs[i]); + if (!lstat(devel_dirs[i], &st)) + return path; + } + } + + /* Then installed path. */ + exec_path = get_argv_exec_path(); + scnprintf(path, size, "%s/tests/shell", exec_path); + free(exec_path); + return path; +} + +static const char *shell_test__description(char *description, size_t size, + const char *path, const char *name) +{ + FILE *fp; + char filename[PATH_MAX]; + int ch; + + path__join(filename, sizeof(filename), path, name); + fp = fopen(filename, "r"); + if (!fp) + return NULL; + + /* Skip first line - should be #!/bin/sh Shebang */ + do { + ch = fgetc(fp); + } while (ch != EOF && ch != '\n'); + + description = fgets(description, size, fp); + fclose(fp); + + /* Assume first char on line is omment everything after that desc */ + return description ? strim(description + 1) : NULL; +} + +/* Is this full file path a shell script */ +static bool is_shell_script(const char *path) +{ + const char *ext; + + ext = strrchr(path, '.'); + if (!ext) + return false; + if (!strcmp(ext, ".sh")) { /* Has .sh extension */ + if (access(path, R_OK | X_OK) == 0) /* Is executable */ + return true; + } + return false; +} + +/* Is this file in this dir a shell script (for test purposes) */ +static bool is_test_script(const char *path, const char *name) +{ + char filename[PATH_MAX]; + + path__join(filename, sizeof(filename), path, name); + if (!is_shell_script(filename)) return false; + return true; +} + +/* Duplicate a string and fall over and die if we run out of memory */ +static char *strdup_check(const char *str) +{ + char *newstr; + + newstr = strdup(str); + if (!newstr) { + pr_err("Out of memory while duplicating test script string\n"); + abort(); + } + return newstr; +} + +static void append_script(const char *dir, const char *file, const char *desc) +{ + struct script_file *files_tmp; + size_t files_num_tmp; + int width; + + files_num_tmp = files_num + 1; + if (files_num_tmp >= SIZE_MAX) { + pr_err("Too many script files\n"); + abort(); + } + /* Realloc is good enough, though we could realloc by chunks, not that + * anyone will ever measure performance here */ + files_tmp = realloc(files, + (files_num_tmp + 1) * sizeof(struct script_file)); + if (files_tmp == NULL) { + pr_err("Out of memory while building test list\n"); + abort(); + } + /* Add file to end and NULL terminate the struct array */ + files = files_tmp; + files_num = files_num_tmp; + files[files_num - 1].dir = strdup_check(dir); + files[files_num - 1].file = strdup_check(file); + files[files_num - 1].desc = strdup_check(desc); + files[files_num].dir = NULL; + files[files_num].file = NULL; + files[files_num].desc = NULL; + + width = strlen(desc); /* Track max width of desc */ + if (width > files_max_width) + files_max_width = width; +} + +static void append_scripts_in_dir(const char *path) +{ + struct dirent **entlist; + struct dirent *ent; + int n_dirs, i; + char filename[PATH_MAX]; + + /* List files, sorted by alpha */ + n_dirs = scandir(path, &entlist, NULL, alphasort); + if (n_dirs == -1) + return; + for (i = 0; i < n_dirs && (ent = entlist[i]); i++) { + if (ent->d_name[0] == '.') + continue; /* Skip hidden files */ + if (is_test_script(path, ent->d_name)) { /* It's a test */ + char bf[256]; + const char *desc = shell_test__description + (bf, sizeof(bf), path, ent->d_name); + + if (desc) /* It has a desc line - valid script */ + append_script(path, ent->d_name, desc); + } else if (is_directory(path, ent)) { /* Scan the subdir */ + path__join(filename, sizeof(filename), + path, ent->d_name); + append_scripts_in_dir(filename); + } + } + for (i = 0; i < n_dirs; i++) /* Clean up */ + zfree(&entlist[i]); + free(entlist); +} + +const struct script_file *list_script_files(void) +{ + char path_dir[PATH_MAX]; + const char *path; + + if (files) + return files; /* Singleton - we already know our list */ + + path = shell_tests__dir(path_dir, sizeof(path_dir)); /* Walk dir */ + append_scripts_in_dir(path); + + return files; +} + +int list_script_max_width(void) +{ + list_script_files(); /* Ensure we have scanned all scripts */ + return files_max_width; +} diff --git a/tools/perf/tests/builtin-test-list.h b/tools/perf/tests/builtin-test-list.h new file mode 100644 index 000000000000..eb81f3aa6683 --- /dev/null +++ b/tools/perf/tests/builtin-test-list.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +struct script_file { + char *dir; + char *file; + char *desc; +}; + +/* List available script tests to run - singleton - never freed */ +const struct script_file *list_script_files(void); +/* Get maximum width of description string */ +int list_script_max_width(void); diff --git a/tools/perf/tests/builtin-test.c b/tools/perf/tests/builtin-test.c index 81cf241cd109..7122eae1d98d 100644 --- a/tools/perf/tests/builtin-test.c +++ b/tools/perf/tests/builtin-test.c @@ -28,6 +28,8 @@ #include #include +#include "builtin-test-list.h" + static bool dont_fork; struct test_suite *__weak arch_tests[] = { @@ -274,91 +276,6 @@ static int test_and_print(struct test_suite *t, int subtest) return err; } -static const char *shell_test__description(char *description, size_t size, - const char *path, const char *name) -{ - FILE *fp; - char filename[PATH_MAX]; - int ch; - - path__join(filename, sizeof(filename), path, name); - fp = fopen(filename, "r"); - if (!fp) - return NULL; - - /* Skip shebang */ - do { - ch = fgetc(fp); - } while (ch != EOF && ch != '\n'); - - description = fgets(description, size, fp); - fclose(fp); - - return description ? strim(description + 1) : NULL; -} - -#define for_each_shell_test(entlist, nr, base, ent) \ - for (int __i = 0; __i < nr && (ent = entlist[__i]); __i++) \ - if (!is_directory(base, ent) && \ - is_executable_file(base, ent) && \ - ent->d_name[0] != '.') - -static const char *shell_tests__dir(char *path, size_t size) -{ - const char *devel_dirs[] = { "./tools/perf/tests", "./tests", }; - char *exec_path; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(devel_dirs); ++i) { - struct stat st; - if (!lstat(devel_dirs[i], &st)) { - scnprintf(path, size, "%s/shell", devel_dirs[i]); - if (!lstat(devel_dirs[i], &st)) - return path; - } - } - - /* Then installed path. */ - exec_path = get_argv_exec_path(); - scnprintf(path, size, "%s/tests/shell", exec_path); - free(exec_path); - return path; -} - -static int shell_tests__max_desc_width(void) -{ - struct dirent **entlist; - struct dirent *ent; - int n_dirs, e; - char path_dir[PATH_MAX]; - const char *path = shell_tests__dir(path_dir, sizeof(path_dir)); - int width = 0; - - if (path == NULL) - return -1; - - n_dirs = scandir(path, &entlist, NULL, alphasort); - if (n_dirs == -1) - return -1; - - for_each_shell_test(entlist, n_dirs, path, ent) { - char bf[256]; - const char *desc = shell_test__description(bf, sizeof(bf), path, ent->d_name); - - if (desc) { - int len = strlen(desc); - - if (width < len) - width = len; - } - } - - for (e = 0; e < n_dirs; e++) - zfree(&entlist[e]); - free(entlist); - return width; -} - struct shell_test { const char *dir; const char *file; @@ -385,33 +302,17 @@ static int shell_test__run(struct test_suite *test, int subdir __maybe_unused) static int run_shell_tests(int argc, const char *argv[], int i, int width, struct intlist *skiplist) { - struct dirent **entlist; - struct dirent *ent; - int n_dirs, e; - char path_dir[PATH_MAX]; - struct shell_test st = { - .dir = shell_tests__dir(path_dir, sizeof(path_dir)), - }; - - if (st.dir == NULL) - return -1; + struct shell_test st; + const struct script_file *files, *file; - n_dirs = scandir(st.dir, &entlist, NULL, alphasort); - if (n_dirs == -1) { - pr_err("failed to open shell test directory: %s\n", - st.dir); - return -1; - } - - for_each_shell_test(entlist, n_dirs, st.dir, ent) { + files = list_script_files(); + if (!files) + return 0; + for (file = files; file->dir; file++) { int curr = i++; - char desc[256]; struct test_case test_cases[] = { { - .desc = shell_test__description(desc, - sizeof(desc), - st.dir, - ent->d_name), + .desc = file->desc, .run_case = shell_test__run, }, { .name = NULL, } @@ -421,12 +322,13 @@ static int run_shell_tests(int argc, const char *argv[], int i, int width, .test_cases = test_cases, .priv = &st, }; + st.dir = file->dir; if (test_suite.desc == NULL || !perf_test__matches(test_suite.desc, curr, argc, argv)) continue; - st.file = ent->d_name; + st.file = file->file; pr_info("%3d: %-*s:", i, width, test_suite.desc); if (intlist__find(skiplist, i)) { @@ -436,10 +338,6 @@ static int run_shell_tests(int argc, const char *argv[], int i, int width, test_and_print(&test_suite, 0); } - - for (e = 0; e < n_dirs; e++) - zfree(&entlist[e]); - free(entlist); return 0; } @@ -448,7 +346,7 @@ static int __cmd_test(int argc, const char *argv[], struct intlist *skiplist) struct test_suite *t; unsigned int j, k; int i = 0; - int width = shell_tests__max_desc_width(); + int width = list_script_max_width(); for_each_test(j, k, t) { int len = strlen(test_description(t, -1)); @@ -529,36 +427,22 @@ static int __cmd_test(int argc, const char *argv[], struct intlist *skiplist) static int perf_test__list_shell(int argc, const char **argv, int i) { - struct dirent **entlist; - struct dirent *ent; - int n_dirs, e; - char path_dir[PATH_MAX]; - const char *path = shell_tests__dir(path_dir, sizeof(path_dir)); - - if (path == NULL) - return -1; + const struct script_file *files, *file; - n_dirs = scandir(path, &entlist, NULL, alphasort); - if (n_dirs == -1) - return -1; - - for_each_shell_test(entlist, n_dirs, path, ent) { + files = list_script_files(); + if (!files) + return 0; + for (file = files; file->dir; file++) { int curr = i++; - char bf[256]; struct test_suite t = { - .desc = shell_test__description(bf, sizeof(bf), path, ent->d_name), + .desc = file->desc }; if (!perf_test__matches(t.desc, curr, argc, argv)) continue; pr_info("%3d: %s\n", i, t.desc); - } - - for (e = 0; e < n_dirs; e++) - zfree(&entlist[e]); - free(entlist); return 0; } -- cgit v1.2.3 From 8549a26308f945bddb39391643eb102da026f0ef Mon Sep 17 00:00:00 2001 From: David Howells Date: Wed, 10 Aug 2022 18:52:47 +0100 Subject: afs: Enable multipage folio support Enable multipage folio support for the afs filesystem. Support has already been implemented in netfslib, fscache and cachefiles and in most of afs, but I've waited for Matthew Wilcox's latest folio changes. Note that it does require a change to afs_write_begin() to return the correct subpage. This is a "temporary" change as we're working on getting rid of the need for ->write_begin() and ->write_end() completely, at least as far as network filesystems are concerned - but it doesn't prevent afs from making use of the capability. Signed-off-by: David Howells Acked-by: Matthew Wilcox (Oracle) Tested-by: kafs-testing@auristor.com Cc: Marc Dionne Cc: linux-afs@lists.infradead.org Link: https://lore.kernel.org/lkml/2274528.1645833226@warthog.procyon.org.uk/ Signed-off-by: Linus Torvalds --- fs/afs/inode.c | 2 ++ fs/afs/write.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/fs/afs/inode.c b/fs/afs/inode.c index 64dab70d4a4f..6d3a3dbe4928 100644 --- a/fs/afs/inode.c +++ b/fs/afs/inode.c @@ -104,12 +104,14 @@ static int afs_inode_init_from_status(struct afs_operation *op, inode->i_op = &afs_file_inode_operations; inode->i_fop = &afs_file_operations; inode->i_mapping->a_ops = &afs_file_aops; + mapping_set_large_folios(inode->i_mapping); break; case AFS_FTYPE_DIR: inode->i_mode = S_IFDIR | (status->mode & S_IALLUGO); inode->i_op = &afs_dir_inode_operations; inode->i_fop = &afs_dir_file_operations; inode->i_mapping->a_ops = &afs_dir_aops; + mapping_set_large_folios(inode->i_mapping); break; case AFS_FTYPE_SYMLINK: /* Symlinks with a mode of 0644 are actually mountpoints. */ diff --git a/fs/afs/write.c b/fs/afs/write.c index 2c885b22de34..9ebdd36eaf2f 100644 --- a/fs/afs/write.c +++ b/fs/afs/write.c @@ -91,7 +91,7 @@ try_again: goto flush_conflicting_write; } - *_page = &folio->page; + *_page = folio_file_page(folio, pos / PAGE_SIZE); _leave(" = 0"); return 0; -- cgit v1.2.3 From 3f61631d47f115b83c935d0039f95cb68b0c8ab7 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Sun, 14 Aug 2022 15:16:18 -0400 Subject: take care to handle NULL ->proc_lseek() Easily done now, just by clearing FMODE_LSEEK in ->f_mode during proc_reg_open() for such entries. Fixes: 868941b14441 "fs: remove no_llseek" Signed-off-by: Al Viro --- fs/proc/inode.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/fs/proc/inode.c b/fs/proc/inode.c index f130499ad843..f495fdb39151 100644 --- a/fs/proc/inode.c +++ b/fs/proc/inode.c @@ -494,6 +494,9 @@ static int proc_reg_open(struct inode *inode, struct file *file) typeof_member(struct proc_ops, proc_release) release; struct pde_opener *pdeo; + if (!pde->proc_ops->proc_lseek) + file->f_mode &= ~FMODE_LSEEK; + if (pde_is_permanent(pde)) { open = pde->proc_ops->proc_open; if (open) -- cgit v1.2.3 From 9f162193d6e48eb4ff51c2ea3612f1daebca1b7e Mon Sep 17 00:00:00 2001 From: Yury Norov Date: Thu, 11 Aug 2022 22:34:25 -0700 Subject: radix-tree: replace gfp.h inclusion with gfp_types.h Radix tree header includes gfp.h for __GFP_BITS_SHIFT only. Now we have gfp_types.h for this. Fixes powerpc allmodconfig build: In file included from include/linux/nodemask.h:97, from include/linux/mmzone.h:17, from include/linux/gfp.h:7, from include/linux/radix-tree.h:12, from include/linux/idr.h:15, from include/linux/kernfs.h:12, from include/linux/sysfs.h:16, from include/linux/kobject.h:20, from include/linux/pci.h:35, from arch/powerpc/kernel/prom_init.c:24: include/linux/random.h: In function 'add_latent_entropy': >> include/linux/random.h:25:46: error: 'latent_entropy' undeclared (first use in this function); did you mean 'add_latent_entropy'? 25 | add_device_randomness((const void *)&latent_entropy, sizeof(latent_entropy)); | ^~~~~~~~~~~~~~ | add_latent_entropy include/linux/random.h:25:46: note: each undeclared identifier is reported only once for each function it appears in Reported-by: kernel test robot CC: Andy Shevchenko CC: Andrew Morton CC: Jason A. Donenfeld Signed-off-by: Yury Norov Signed-off-by: Linus Torvalds --- include/linux/radix-tree.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/radix-tree.h b/include/linux/radix-tree.h index f7c1d21c2f39..eae67015ce51 100644 --- a/include/linux/radix-tree.h +++ b/include/linux/radix-tree.h @@ -9,7 +9,7 @@ #define _LINUX_RADIX_TREE_H #include -#include +#include #include #include #include -- cgit v1.2.3 From 568035b01cfb107af8d2e4bd2fb9aea22cf5b868 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Sun, 14 Aug 2022 15:50:18 -0700 Subject: Linux 6.0-rc1 --- Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 5f5c43a52455..f09673b6c11d 100644 --- a/Makefile +++ b/Makefile @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0 -VERSION = 5 -PATCHLEVEL = 19 +VERSION = 6 +PATCHLEVEL = 0 SUBLEVEL = 0 -EXTRAVERSION = -NAME = Superb Owl +EXTRAVERSION = -rc1 +NAME = Hurr durr I'ma ninja sloth # *DOCUMENTATION* # To see a list of typical targets execute "make help" -- cgit v1.2.3 From 68a838b84effb7b57ba7d50b1863fc6ae35a54ce Mon Sep 17 00:00:00 2001 From: Maxim Kochetkov Date: Thu, 11 Aug 2022 12:48:40 +0300 Subject: net: qrtr: start MHI channel after endpoit creation MHI channel may generates event/interrupt right after enabling. It may leads to 2 race conditions issues. 1) Such event may be dropped by qcom_mhi_qrtr_dl_callback() at check: if (!qdev || mhi_res->transaction_status) return; Because dev_set_drvdata(&mhi_dev->dev, qdev) may be not performed at this moment. In this situation qrtr-ns will be unable to enumerate services in device. --------------------------------------------------------------- 2) Such event may come at the moment after dev_set_drvdata() and before qrtr_endpoint_register(). In this case kernel will panic with accessing wrong pointer at qcom_mhi_qrtr_dl_callback(): rc = qrtr_endpoint_post(&qdev->ep, mhi_res->buf_addr, mhi_res->bytes_xferd); Because endpoint is not created yet. -------------------------------------------------------------- So move mhi_prepare_for_transfer_autoqueue after endpoint creation to fix it. Fixes: a2e2cc0dbb11 ("net: qrtr: Start MHI channels during init") Signed-off-by: Maxim Kochetkov Reviewed-by: Hemant Kumar Reviewed-by: Manivannan Sadhasivam Reviewed-by: Loic Poulain Signed-off-by: David S. Miller --- net/qrtr/mhi.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/net/qrtr/mhi.c b/net/qrtr/mhi.c index 18196e1c8c2f..9ced13c0627a 100644 --- a/net/qrtr/mhi.c +++ b/net/qrtr/mhi.c @@ -78,11 +78,6 @@ static int qcom_mhi_qrtr_probe(struct mhi_device *mhi_dev, struct qrtr_mhi_dev *qdev; int rc; - /* start channels */ - rc = mhi_prepare_for_transfer_autoqueue(mhi_dev); - if (rc) - return rc; - qdev = devm_kzalloc(&mhi_dev->dev, sizeof(*qdev), GFP_KERNEL); if (!qdev) return -ENOMEM; @@ -96,6 +91,13 @@ static int qcom_mhi_qrtr_probe(struct mhi_device *mhi_dev, if (rc) return rc; + /* start channels */ + rc = mhi_prepare_for_transfer_autoqueue(mhi_dev); + if (rc) { + qrtr_endpoint_unregister(&qdev->ep); + return rc; + } + dev_dbg(qdev->dev, "Qualcomm MHI QRTR driver probed\n"); return 0; -- cgit v1.2.3 From 66ba215cb51323e4e55e38fd5f250e0fae0cbc94 Mon Sep 17 00:00:00 2001 From: "Denis V. Lunev" Date: Thu, 11 Aug 2022 18:20:11 +0300 Subject: neigh: fix possible DoS due to net iface start/stop loop Normal processing of ARP request (usually this is Ethernet broadcast packet) coming to the host is looking like the following: * the packet comes to arp_process() call and is passed through routing procedure * the request is put into the queue using pneigh_enqueue() if corresponding ARP record is not local (common case for container records on the host) * the request is processed by timer (within 80 jiffies by default) and ARP reply is sent from the same arp_process() using NEIGH_CB(skb)->flags & LOCALLY_ENQUEUED condition (flag is set inside pneigh_enqueue()) And here the problem comes. Linux kernel calls pneigh_queue_purge() which destroys the whole queue of ARP requests on ANY network interface start/stop event through __neigh_ifdown(). This is actually not a problem within the original world as network interface start/stop was accessible to the host 'root' only, which could do more destructive things. But the world is changed and there are Linux containers available. Here container 'root' has an access to this API and could be considered as untrusted user in the hosting (container's) world. Thus there is an attack vector to other containers on node when container's root will endlessly start/stop interfaces. We have observed similar situation on a real production node when docker container was doing such activity and thus other containers on the node become not accessible. The patch proposed doing very simple thing. It drops only packets from the same namespace in the pneigh_queue_purge() where network interface state change is detected. This is enough to prevent the problem for the whole node preserving original semantics of the code. v2: - do del_timer_sync() if queue is empty after pneigh_queue_purge() v3: - rebase to net tree Cc: "David S. Miller" Cc: Eric Dumazet Cc: Jakub Kicinski Cc: Paolo Abeni Cc: Daniel Borkmann Cc: David Ahern Cc: Yajun Deng Cc: Roopa Prabhu Cc: Christian Brauner Cc: netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Alexey Kuznetsov Cc: Alexander Mikhalitsyn Cc: Konstantin Khorenko Cc: kernel@openvz.org Cc: devel@openvz.org Investigated-by: Alexander Mikhalitsyn Signed-off-by: Denis V. Lunev Signed-off-by: David S. Miller --- net/core/neighbour.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/net/core/neighbour.c b/net/core/neighbour.c index 6a8c2596ebab..0e38a05d5b23 100644 --- a/net/core/neighbour.c +++ b/net/core/neighbour.c @@ -307,14 +307,23 @@ static int neigh_del_timer(struct neighbour *n) return 0; } -static void pneigh_queue_purge(struct sk_buff_head *list) +static void pneigh_queue_purge(struct sk_buff_head *list, struct net *net) { + unsigned long flags; struct sk_buff *skb; - while ((skb = skb_dequeue(list)) != NULL) { - dev_put(skb->dev); - kfree_skb(skb); + spin_lock_irqsave(&list->lock, flags); + skb = skb_peek(list); + while (skb != NULL) { + struct sk_buff *skb_next = skb_peek_next(skb, list); + if (net == NULL || net_eq(dev_net(skb->dev), net)) { + __skb_unlink(skb, list); + dev_put(skb->dev); + kfree_skb(skb); + } + skb = skb_next; } + spin_unlock_irqrestore(&list->lock, flags); } static void neigh_flush_dev(struct neigh_table *tbl, struct net_device *dev, @@ -385,9 +394,9 @@ static int __neigh_ifdown(struct neigh_table *tbl, struct net_device *dev, write_lock_bh(&tbl->lock); neigh_flush_dev(tbl, dev, skip_perm); pneigh_ifdown_and_unlock(tbl, dev); - - del_timer_sync(&tbl->proxy_timer); - pneigh_queue_purge(&tbl->proxy_queue); + pneigh_queue_purge(&tbl->proxy_queue, dev_net(dev)); + if (skb_queue_empty_lockless(&tbl->proxy_queue)) + del_timer_sync(&tbl->proxy_timer); return 0; } @@ -1787,7 +1796,7 @@ int neigh_table_clear(int index, struct neigh_table *tbl) cancel_delayed_work_sync(&tbl->managed_work); cancel_delayed_work_sync(&tbl->gc_work); del_timer_sync(&tbl->proxy_timer); - pneigh_queue_purge(&tbl->proxy_queue); + pneigh_queue_purge(&tbl->proxy_queue, NULL); neigh_ifdown(tbl, NULL); if (atomic_read(&tbl->entries)) pr_crit("neighbour leakage\n"); -- cgit v1.2.3 From 0ff4eb3d5ebbf72a7fc355e6001a0a6740662bf9 Mon Sep 17 00:00:00 2001 From: Alexander Mikhalitsyn Date: Thu, 11 Aug 2022 18:20:12 +0300 Subject: neighbour: make proxy_queue.qlen limit per-device Right now we have a neigh_param PROXY_QLEN which specifies maximum length of neigh_table->proxy_queue. But in fact, this limitation doesn't work well because check condition looks like: tbl->proxy_queue.qlen > NEIGH_VAR(p, PROXY_QLEN) The problem is that p (struct neigh_parms) is a per-device thing, but tbl (struct neigh_table) is a system-wide global thing. It seems reasonable to make proxy_queue limit per-device based. v2: - nothing changed in this patch v3: - rebase to net tree Cc: "David S. Miller" Cc: Eric Dumazet Cc: Jakub Kicinski Cc: Paolo Abeni Cc: Daniel Borkmann Cc: David Ahern Cc: Yajun Deng Cc: Roopa Prabhu Cc: Christian Brauner Cc: netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Alexey Kuznetsov Cc: Alexander Mikhalitsyn Cc: Konstantin Khorenko Cc: kernel@openvz.org Cc: devel@openvz.org Suggested-by: Denis V. Lunev Signed-off-by: Alexander Mikhalitsyn Reviewed-by: Denis V. Lunev Signed-off-by: David S. Miller --- include/net/neighbour.h | 1 + net/core/neighbour.c | 25 ++++++++++++++++++++++--- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/include/net/neighbour.h b/include/net/neighbour.h index 9f0bab0589d9..3827a6b395fd 100644 --- a/include/net/neighbour.h +++ b/include/net/neighbour.h @@ -83,6 +83,7 @@ struct neigh_parms { struct rcu_head rcu_head; int reachable_time; + int qlen; int data[NEIGH_VAR_DATA_MAX]; DECLARE_BITMAP(data_state, NEIGH_VAR_DATA_MAX); }; diff --git a/net/core/neighbour.c b/net/core/neighbour.c index 0e38a05d5b23..5b669eb80270 100644 --- a/net/core/neighbour.c +++ b/net/core/neighbour.c @@ -316,9 +316,18 @@ static void pneigh_queue_purge(struct sk_buff_head *list, struct net *net) skb = skb_peek(list); while (skb != NULL) { struct sk_buff *skb_next = skb_peek_next(skb, list); - if (net == NULL || net_eq(dev_net(skb->dev), net)) { + struct net_device *dev = skb->dev; + if (net == NULL || net_eq(dev_net(dev), net)) { + struct in_device *in_dev; + + rcu_read_lock(); + in_dev = __in_dev_get_rcu(dev); + if (in_dev) + in_dev->arp_parms->qlen--; + rcu_read_unlock(); __skb_unlink(skb, list); - dev_put(skb->dev); + + dev_put(dev); kfree_skb(skb); } skb = skb_next; @@ -1606,8 +1615,15 @@ static void neigh_proxy_process(struct timer_list *t) if (tdif <= 0) { struct net_device *dev = skb->dev; + struct in_device *in_dev; + rcu_read_lock(); + in_dev = __in_dev_get_rcu(dev); + if (in_dev) + in_dev->arp_parms->qlen--; + rcu_read_unlock(); __skb_unlink(skb, &tbl->proxy_queue); + if (tbl->proxy_redo && netif_running(dev)) { rcu_read_lock(); tbl->proxy_redo(skb); @@ -1632,7 +1648,7 @@ void pneigh_enqueue(struct neigh_table *tbl, struct neigh_parms *p, unsigned long sched_next = jiffies + prandom_u32_max(NEIGH_VAR(p, PROXY_DELAY)); - if (tbl->proxy_queue.qlen > NEIGH_VAR(p, PROXY_QLEN)) { + if (p->qlen > NEIGH_VAR(p, PROXY_QLEN)) { kfree_skb(skb); return; } @@ -1648,6 +1664,7 @@ void pneigh_enqueue(struct neigh_table *tbl, struct neigh_parms *p, skb_dst_drop(skb); dev_hold(skb->dev); __skb_queue_tail(&tbl->proxy_queue, skb); + p->qlen++; mod_timer(&tbl->proxy_timer, sched_next); spin_unlock(&tbl->proxy_queue.lock); } @@ -1680,6 +1697,7 @@ struct neigh_parms *neigh_parms_alloc(struct net_device *dev, refcount_set(&p->refcnt, 1); p->reachable_time = neigh_rand_reach_time(NEIGH_VAR(p, BASE_REACHABLE_TIME)); + p->qlen = 0; netdev_hold(dev, &p->dev_tracker, GFP_KERNEL); p->dev = dev; write_pnet(&p->net, net); @@ -1745,6 +1763,7 @@ void neigh_table_init(int index, struct neigh_table *tbl) refcount_set(&tbl->parms.refcnt, 1); tbl->parms.reachable_time = neigh_rand_reach_time(NEIGH_VAR(&tbl->parms, BASE_REACHABLE_TIME)); + tbl->parms.qlen = 0; tbl->stats = alloc_percpu(struct neigh_statistics); if (!tbl->stats) -- cgit v1.2.3 From 7396ba87f1edf549284869451665c7c4e74ecd4f Mon Sep 17 00:00:00 2001 From: Xin Xiong Date: Sat, 13 Aug 2022 20:49:08 +0800 Subject: net: fix potential refcount leak in ndisc_router_discovery() The issue happens on specific paths in the function. After both the object `rt` and `neigh` are grabbed successfully, when `lifetime` is nonzero but the metric needs change, the function just deletes the route and set `rt` to NULL. Then, it may try grabbing `rt` and `neigh` again if above conditions hold. The function simply overwrite `neigh` if succeeds or returns if fails, without decreasing the reference count of previous `neigh`. This may result in memory leaks. Fix it by decrementing the reference count of `neigh` in place. Fixes: 6b2e04bc240f ("net: allow user to set metric on default route learned via Router Advertisement") Signed-off-by: Xin Xiong Signed-off-by: Xin Tan Signed-off-by: David S. Miller --- net/ipv6/ndisc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/net/ipv6/ndisc.c b/net/ipv6/ndisc.c index 98453693e400..3a553494ff16 100644 --- a/net/ipv6/ndisc.c +++ b/net/ipv6/ndisc.c @@ -1378,6 +1378,9 @@ static void ndisc_router_discovery(struct sk_buff *skb) if (!rt && lifetime) { ND_PRINTK(3, info, "RA: adding default router\n"); + if (neigh) + neigh_release(neigh); + rt = rt6_add_dflt_router(net, &ipv6_hdr(skb)->saddr, skb->dev, pref, defrtr_usr_metric); if (!rt) { -- cgit v1.2.3 From 02799571714dc5dd6948824b9d080b44a295f695 Mon Sep 17 00:00:00 2001 From: Jamal Hadi Salim Date: Sun, 14 Aug 2022 11:27:58 +0000 Subject: net_sched: cls_route: disallow handle of 0 Follows up on: https://lore.kernel.org/all/20220809170518.164662-1-cascardo@canonical.com/ handle of 0 implies from/to of universe realm which is not very sensible. Lets see what this patch will do: $sudo tc qdisc add dev $DEV root handle 1:0 prio //lets manufacture a way to insert handle of 0 $sudo tc filter add dev $DEV parent 1:0 protocol ip prio 100 \ route to 0 from 0 classid 1:10 action ok //gets rejected... Error: handle of 0 is not valid. We have an error talking to the kernel, -1 //lets create a legit entry.. sudo tc filter add dev $DEV parent 1:0 protocol ip prio 100 route from 10 \ classid 1:10 action ok //what did the kernel insert? $sudo tc filter ls dev $DEV parent 1:0 filter protocol ip pref 100 route chain 0 filter protocol ip pref 100 route chain 0 fh 0x000a8000 flowid 1:10 from 10 action order 1: gact action pass random type none pass val 0 index 1 ref 1 bind 1 //Lets try to replace that legit entry with a handle of 0 $ sudo tc filter replace dev $DEV parent 1:0 protocol ip prio 100 \ handle 0x000a8000 route to 0 from 0 classid 1:10 action drop Error: Replacing with handle of 0 is invalid. We have an error talking to the kernel, -1 And last, lets run Cascardo's POC: $ ./poc 0 0 -22 -22 -22 Signed-off-by: Jamal Hadi Salim Acked-by: Stephen Hemminger Signed-off-by: David S. Miller --- net/sched/cls_route.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/net/sched/cls_route.c b/net/sched/cls_route.c index 3f935cbbaff6..48712bc51bda 100644 --- a/net/sched/cls_route.c +++ b/net/sched/cls_route.c @@ -424,6 +424,11 @@ static int route4_set_parms(struct net *net, struct tcf_proto *tp, return -EINVAL; } + if (!nhandle) { + NL_SET_ERR_MSG(extack, "Replacing with handle of 0 is invalid"); + return -EINVAL; + } + h1 = to_hash(nhandle); b = rtnl_dereference(head->table[h1]); if (!b) { @@ -477,6 +482,11 @@ static int route4_change(struct net *net, struct sk_buff *in_skb, int err; bool new = true; + if (!handle) { + NL_SET_ERR_MSG(extack, "Creating with handle of 0 is invalid"); + return -EINVAL; + } + if (opt == NULL) return handle ? -EINVAL : 0; -- cgit v1.2.3 From 12e091389b29cddf26279fdf182b13b3a1583d0d Mon Sep 17 00:00:00 2001 From: Amit Cohen Date: Fri, 12 Aug 2022 17:32:00 +0200 Subject: mlxsw: spectrum_ptp: Fix compilation warnings In case that 'CONFIG_PTP_1588_CLOCK' is not enabled in the config file, there are implementations for the functions mlxsw_{sp,sp2}_ptp_txhdr_construct() as part of 'spectrum_ptp.h'. In this case, they should be defined as 'static' as they are not supposed to be used out of this file. Make the functions 'static', otherwise the following warnings are returned: "warning: no previous prototype for 'mlxsw_sp_ptp_txhdr_construct'" "warning: no previous prototype for 'mlxsw_sp2_ptp_txhdr_construct'" In addition, make the functions 'inline' for case that 'spectrum_ptp.h' will be included anywhere else and the functions would probably not be used, so compilation warnings about unused static will be returned. Fixes: 24157bc69f45 ("mlxsw: Send PTP packets as data packets to overcome a limitation") Reported-by: kernel test robot Signed-off-by: Amit Cohen Reviewed-by: Petr Machata Signed-off-by: Petr Machata Signed-off-by: David S. Miller --- drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.h | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.h b/drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.h index 2d1628fdefc1..a8b88230959a 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.h +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.h @@ -171,10 +171,11 @@ static inline void mlxsw_sp1_get_stats(struct mlxsw_sp_port *mlxsw_sp_port, { } -int mlxsw_sp_ptp_txhdr_construct(struct mlxsw_core *mlxsw_core, - struct mlxsw_sp_port *mlxsw_sp_port, - struct sk_buff *skb, - const struct mlxsw_tx_info *tx_info) +static inline int +mlxsw_sp_ptp_txhdr_construct(struct mlxsw_core *mlxsw_core, + struct mlxsw_sp_port *mlxsw_sp_port, + struct sk_buff *skb, + const struct mlxsw_tx_info *tx_info) { return -EOPNOTSUPP; } @@ -231,10 +232,11 @@ static inline int mlxsw_sp2_ptp_get_ts_info(struct mlxsw_sp *mlxsw_sp, return mlxsw_sp_ptp_get_ts_info_noptp(info); } -int mlxsw_sp2_ptp_txhdr_construct(struct mlxsw_core *mlxsw_core, - struct mlxsw_sp_port *mlxsw_sp_port, - struct sk_buff *skb, - const struct mlxsw_tx_info *tx_info) +static inline int +mlxsw_sp2_ptp_txhdr_construct(struct mlxsw_core *mlxsw_core, + struct mlxsw_sp_port *mlxsw_sp_port, + struct sk_buff *skb, + const struct mlxsw_tx_info *tx_info) { return -EOPNOTSUPP; } -- cgit v1.2.3 From a159e986ad26d3f35c0157ac92760ba5e44e6785 Mon Sep 17 00:00:00 2001 From: Amit Cohen Date: Fri, 12 Aug 2022 17:32:01 +0200 Subject: mlxsw: spectrum: Clear PTP configuration after unregistering the netdevice Currently as part of removing port, PTP API is called to clear the existing configuration and set the 'rx_filter' and 'tx_type' to zero. The clearing is done before unregistering the netdevice, which means that there is a window of time in which the user can reconfigure PTP in the port, and this configuration will not be cleared. Reorder the operations, clear PTP configuration after unregistering the netdevice. Fixes: 8748642751ede ("mlxsw: spectrum: PTP: Support SIOCGHWTSTAMP, SIOCSHWTSTAMP ioctls") Signed-off-by: Amit Cohen Signed-off-by: Ido Schimmel Signed-off-by: Petr Machata Signed-off-by: David S. Miller --- drivers/net/ethernet/mellanox/mlxsw/spectrum.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c index 1e240cdd9cbd..30c7b0e15721 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c @@ -1897,9 +1897,9 @@ static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u16 local_port) cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw); cancel_delayed_work_sync(&mlxsw_sp_port->ptp.shaper_dw); - mlxsw_sp_port_ptp_clear(mlxsw_sp_port); mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp); unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */ + mlxsw_sp_port_ptp_clear(mlxsw_sp_port); mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true); mlxsw_sp->ports[local_port] = NULL; mlxsw_sp_port_vlan_flush(mlxsw_sp_port, true); -- cgit v1.2.3 From d72fdef21f07540c6cbb8043cc93decd2a5d35dd Mon Sep 17 00:00:00 2001 From: Amit Cohen Date: Fri, 12 Aug 2022 17:32:02 +0200 Subject: mlxsw: spectrum_ptp: Protect PTP configuration with a mutex Currently the functions mlxsw_sp2_ptp_{configure, deconfigure}_port() assume that they are called when RTNL is locked and they warn otherwise. The deconfigure function can be called when port is removed, for example as part of device reload, then there is no locked RTNL and the function warns [1]. To avoid such case, do not assume that RTNL protects this code, add a dedicated mutex instead. The mutex protects 'ptp_state->config' which stores the existing global configuration in hardware. Use this mutex also to protect the code which configures the hardware. Then, there will be only one configuration in any time, which will be updated in 'ptp_state' and a race will be avoided. [1]: RTNL: assertion failed at drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c (1600) WARNING: CPU: 1 PID: 1583493 at drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c:1600 mlxsw_sp2_ptp_hwtstamp_set+0x2d3/0x300 [mlxsw_spectrum] [...] CPU: 1 PID: 1583493 Comm: devlink Not tainted5.19.0-rc8-custom-127022-gb371dffda095 #789 Hardware name: Mellanox Technologies Ltd.MSN3420/VMOD0005, BIOS 5.11 01/06/2019 RIP: 0010:mlxsw_sp2_ptp_hwtstamp_set+0x2d3/0x300[mlxsw_spectrum] [...] Call Trace: mlxsw_sp_port_remove+0x7e/0x190 [mlxsw_spectrum] mlxsw_sp_fini+0xd1/0x270 [mlxsw_spectrum] mlxsw_core_bus_device_unregister+0x55/0x280 [mlxsw_core] mlxsw_devlink_core_bus_device_reload_down+0x1c/0x30[mlxsw_core] devlink_reload+0x1ee/0x230 devlink_nl_cmd_reload+0x4de/0x580 genl_family_rcv_msg_doit+0xdc/0x140 genl_rcv_msg+0xd7/0x1d0 netlink_rcv_skb+0x49/0xf0 genl_rcv+0x1f/0x30 netlink_unicast+0x22f/0x350 netlink_sendmsg+0x208/0x440 __sys_sendto+0xf0/0x140 __x64_sys_sendto+0x1b/0x20 do_syscall_64+0x35/0x80 entry_SYSCALL_64_after_hwframe+0x63/0xcd Fixes: 08ef8bc825d96 ("mlxsw: spectrum_ptp: Support SIOCGHWTSTAMP, SIOCSHWTSTAMP ioctls") Reported-by: Ido Schimmel Signed-off-by: Amit Cohen Signed-off-by: Ido Schimmel Signed-off-by: Petr Machata Signed-off-by: David S. Miller --- drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c | 27 ++++++++++++++++------ 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c index 2e0b704b8a31..f32c83603b84 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c @@ -46,6 +46,7 @@ struct mlxsw_sp2_ptp_state { * enabled. */ struct hwtstamp_config config; + struct mutex lock; /* Protects 'config' and HW configuration. */ }; struct mlxsw_sp1_ptp_key { @@ -1374,6 +1375,7 @@ struct mlxsw_sp_ptp_state *mlxsw_sp2_ptp_init(struct mlxsw_sp *mlxsw_sp) goto err_ptp_traps_set; refcount_set(&ptp_state->ptp_port_enabled_ref, 0); + mutex_init(&ptp_state->lock); return &ptp_state->common; err_ptp_traps_set: @@ -1388,6 +1390,7 @@ void mlxsw_sp2_ptp_fini(struct mlxsw_sp_ptp_state *ptp_state_common) ptp_state = mlxsw_sp2_ptp_state(mlxsw_sp); + mutex_destroy(&ptp_state->lock); mlxsw_sp_ptp_traps_unset(mlxsw_sp); kfree(ptp_state); } @@ -1461,7 +1464,10 @@ int mlxsw_sp2_ptp_hwtstamp_get(struct mlxsw_sp_port *mlxsw_sp_port, ptp_state = mlxsw_sp2_ptp_state(mlxsw_sp_port->mlxsw_sp); + mutex_lock(&ptp_state->lock); *config = ptp_state->config; + mutex_unlock(&ptp_state->lock); + return 0; } @@ -1574,8 +1580,6 @@ static int mlxsw_sp2_ptp_configure_port(struct mlxsw_sp_port *mlxsw_sp_port, struct mlxsw_sp2_ptp_state *ptp_state; int err; - ASSERT_RTNL(); - ptp_state = mlxsw_sp2_ptp_state(mlxsw_sp_port->mlxsw_sp); if (refcount_inc_not_zero(&ptp_state->ptp_port_enabled_ref)) @@ -1597,8 +1601,6 @@ static int mlxsw_sp2_ptp_deconfigure_port(struct mlxsw_sp_port *mlxsw_sp_port, struct mlxsw_sp2_ptp_state *ptp_state; int err; - ASSERT_RTNL(); - ptp_state = mlxsw_sp2_ptp_state(mlxsw_sp_port->mlxsw_sp); if (!refcount_dec_and_test(&ptp_state->ptp_port_enabled_ref)) @@ -1618,16 +1620,20 @@ err_ptp_disable: int mlxsw_sp2_ptp_hwtstamp_set(struct mlxsw_sp_port *mlxsw_sp_port, struct hwtstamp_config *config) { + struct mlxsw_sp2_ptp_state *ptp_state; enum hwtstamp_rx_filters rx_filter; struct hwtstamp_config new_config; u16 new_ing_types, new_egr_types; bool ptp_enabled; int err; + ptp_state = mlxsw_sp2_ptp_state(mlxsw_sp_port->mlxsw_sp); + mutex_lock(&ptp_state->lock); + err = mlxsw_sp2_ptp_get_message_types(config, &new_ing_types, &new_egr_types, &rx_filter); if (err) - return err; + goto err_get_message_types; new_config.flags = config->flags; new_config.tx_type = config->tx_type; @@ -1640,11 +1646,11 @@ int mlxsw_sp2_ptp_hwtstamp_set(struct mlxsw_sp_port *mlxsw_sp_port, err = mlxsw_sp2_ptp_configure_port(mlxsw_sp_port, new_ing_types, new_egr_types, new_config); if (err) - return err; + goto err_configure_port; } else if (!new_ing_types && !new_egr_types && ptp_enabled) { err = mlxsw_sp2_ptp_deconfigure_port(mlxsw_sp_port, new_config); if (err) - return err; + goto err_deconfigure_port; } mlxsw_sp_port->ptp.ing_types = new_ing_types; @@ -1652,8 +1658,15 @@ int mlxsw_sp2_ptp_hwtstamp_set(struct mlxsw_sp_port *mlxsw_sp_port, /* Notify the ioctl caller what we are actually timestamping. */ config->rx_filter = rx_filter; + mutex_unlock(&ptp_state->lock); return 0; + +err_deconfigure_port: +err_configure_port: +err_get_message_types: + mutex_unlock(&ptp_state->lock); + return err; } int mlxsw_sp2_ptp_get_ts_info(struct mlxsw_sp *mlxsw_sp, -- cgit v1.2.3 From e01885c31bef7c2c5fcb79dc192039f25e300ded Mon Sep 17 00:00:00 2001 From: Amit Cohen Date: Fri, 12 Aug 2022 17:32:03 +0200 Subject: mlxsw: spectrum_ptp: Forbid PTP enablement only in RX or in TX Currently mlxsw driver configures one global PTP configuration for all ports. The reason is that the switch behaves like a transparent clock between CPU port and front-panel ports. When time stamp is enabled in any port, the hardware is configured to update the correction field. The fact that the configuration of CPU port affects all the ports, makes the correction field update to be global for all ports. Otherwise, user will see odd values in the correction field, as the switch will update the correction field in the CPU port, but not in all the front-panel ports. The CPU port is relevant in both RX and TX, so to avoid problematic configuration, forbid PTP enablement only in one direction, i.e., only in RX or TX. Without the change: $ hwstamp_ctl -i swp1 -r 12 -t 0 current settings: tx_type 0 rx_filter 0 new settings: tx_type 0 rx_filter 2 $ echo $? 0 With the change: $ hwstamp_ctl -i swp1 -r 12 -t 0 current settings: tx_type 1 rx_filter 2 SIOCSHWTSTAMP failed: Invalid argument Fixes: 08ef8bc825d96 ("mlxsw: spectrum_ptp: Support SIOCGHWTSTAMP, SIOCSHWTSTAMP ioctls") Signed-off-by: Amit Cohen Reviewed-by: Petr Machata Signed-off-by: Petr Machata Signed-off-by: David S. Miller --- drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c index f32c83603b84..7b01b9c20722 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c @@ -1529,6 +1529,9 @@ mlxsw_sp2_ptp_get_message_types(const struct hwtstamp_config *config, return -EINVAL; } + if ((ing_types && !egr_types) || (!ing_types && egr_types)) + return -EINVAL; + *p_ing_types = ing_types; *p_egr_types = egr_types; return 0; -- cgit v1.2.3 From 88cccd908d51397f9754f89a937cd13fa59dee37 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Fri, 12 Aug 2022 16:21:28 +0200 Subject: netfilter: nf_tables: NFTA_SET_ELEM_KEY_END requires concat and interval flags If the NFT_SET_CONCAT|NFT_SET_INTERVAL flags are set on, then the netlink attribute NFTA_SET_ELEM_KEY_END must be specified. Otherwise, NFTA_SET_ELEM_KEY_END should not be present. For catch-all element, NFTA_SET_ELEM_KEY_END should not be present. The NFT_SET_ELEM_INTERVAL_END is never used with this set flags combination. Fixes: 7b225d0b5c6d ("netfilter: nf_tables: add NFTA_SET_ELEM_KEY_END attribute") Signed-off-by: Pablo Neira Ayuso --- net/netfilter/nf_tables_api.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index bcfe8120e014..1d14d694f654 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -5844,6 +5844,24 @@ static void nft_setelem_remove(const struct net *net, set->ops->remove(net, set, elem); } +static bool nft_setelem_valid_key_end(const struct nft_set *set, + struct nlattr **nla, u32 flags) +{ + if ((set->flags & (NFT_SET_CONCAT | NFT_SET_INTERVAL)) == + (NFT_SET_CONCAT | NFT_SET_INTERVAL)) { + if (flags & NFT_SET_ELEM_INTERVAL_END) + return false; + if (!nla[NFTA_SET_ELEM_KEY_END] && + !(flags & NFT_SET_ELEM_CATCHALL)) + return false; + } else { + if (nla[NFTA_SET_ELEM_KEY_END]) + return false; + } + + return true; +} + static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, const struct nlattr *attr, u32 nlmsg_flags) { @@ -5903,6 +5921,9 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, return -EINVAL; } + if (!nft_setelem_valid_key_end(set, nla, flags)) + return -EINVAL; + if ((flags & NFT_SET_ELEM_INTERVAL_END) && (nla[NFTA_SET_ELEM_DATA] || nla[NFTA_SET_ELEM_OBJREF] || @@ -6333,6 +6354,9 @@ static int nft_del_setelem(struct nft_ctx *ctx, struct nft_set *set, if (!nla[NFTA_SET_ELEM_KEY] && !(flags & NFT_SET_ELEM_CATCHALL)) return -EINVAL; + if (!nft_setelem_valid_key_end(set, nla, flags)) + return -EINVAL; + nft_set_ext_prepare(&tmpl); if (flags != 0) { -- cgit v1.2.3 From fc0ae524b5fd2938c94d56da3f749f11eb3273d5 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Sat, 13 Aug 2022 15:22:05 +0200 Subject: netfilter: nf_tables: disallow NFT_SET_ELEM_CATCHALL and NFT_SET_ELEM_INTERVAL_END These flags are mutually exclusive, report EINVAL in this case. Fixes: aaa31047a6d2 ("netfilter: nftables: add catch-all set element support") Signed-off-by: Pablo Neira Ayuso --- net/netfilter/nf_tables_api.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index 1d14d694f654..b1b12e083abb 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -5198,6 +5198,9 @@ static int nft_setelem_parse_flags(const struct nft_set *set, if (!(set->flags & NFT_SET_INTERVAL) && *flags & NFT_SET_ELEM_INTERVAL_END) return -EINVAL; + if ((*flags & (NFT_SET_ELEM_INTERVAL_END | NFT_SET_ELEM_CATCHALL)) == + (NFT_SET_ELEM_INTERVAL_END | NFT_SET_ELEM_CATCHALL)) + return -EINVAL; return 0; } -- cgit v1.2.3 From 8535c239ac674f7ead0f2652932d35c52c4123b2 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Mon, 8 Aug 2022 16:06:04 +0100 Subject: nios2: page fault et.al. are *not* restartable syscalls... make sure that ->orig_r2 is negative for everything except the syscalls. Fixes: 82ed08dd1b0e ("nios2: Exception handling") Signed-off-by: Al Viro Signed-off-by: Dinh Nguyen --- arch/nios2/include/asm/entry.h | 3 ++- arch/nios2/kernel/entry.S | 4 +--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/nios2/include/asm/entry.h b/arch/nios2/include/asm/entry.h index cf37f55efbc2..bafb7b2ca59f 100644 --- a/arch/nios2/include/asm/entry.h +++ b/arch/nios2/include/asm/entry.h @@ -50,7 +50,8 @@ stw r13, PT_R13(sp) stw r14, PT_R14(sp) stw r15, PT_R15(sp) - stw r2, PT_ORIG_R2(sp) + movi r24, -1 + stw r24, PT_ORIG_R2(sp) stw r7, PT_ORIG_R7(sp) stw ra, PT_RA(sp) diff --git a/arch/nios2/kernel/entry.S b/arch/nios2/kernel/entry.S index 0794cd7803df..fbd348bf103f 100644 --- a/arch/nios2/kernel/entry.S +++ b/arch/nios2/kernel/entry.S @@ -185,6 +185,7 @@ ENTRY(handle_system_call) ldw r5, PT_R5(sp) local_restart: + stw r2, PT_ORIG_R2(sp) /* Check that the requested system call is within limits */ movui r1, __NR_syscalls bgeu r2, r1, ret_invsyscall @@ -336,9 +337,6 @@ external_interrupt: /* skip if no interrupt is pending */ beq r12, r0, ret_from_interrupt - movi r24, -1 - stw r24, PT_ORIG_R2(sp) - /* * Process an external hardware interrupt. */ -- cgit v1.2.3 From 45ec746c65097c25e77d24eae8fee0def5b6cc5d Mon Sep 17 00:00:00 2001 From: Al Viro Date: Mon, 8 Aug 2022 16:06:46 +0100 Subject: nios2: don't leave NULLs in sys_call_table[] fill the gaps in there with sys_ni_syscall, as everyone does... Fixes: 82ed08dd1b0e ("nios2: Exception handling") Signed-off-by: Al Viro Signed-off-by: Dinh Nguyen --- arch/nios2/kernel/entry.S | 1 - arch/nios2/kernel/syscall_table.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/nios2/kernel/entry.S b/arch/nios2/kernel/entry.S index fbd348bf103f..8f41ef5b0399 100644 --- a/arch/nios2/kernel/entry.S +++ b/arch/nios2/kernel/entry.S @@ -193,7 +193,6 @@ local_restart: movhi r11, %hiadj(sys_call_table) add r1, r1, r11 ldw r1, %lo(sys_call_table)(r1) - beq r1, r0, ret_invsyscall /* Check if we are being traced */ GET_THREAD_INFO r11 diff --git a/arch/nios2/kernel/syscall_table.c b/arch/nios2/kernel/syscall_table.c index 6176d63023c1..c2875a6dd5a4 100644 --- a/arch/nios2/kernel/syscall_table.c +++ b/arch/nios2/kernel/syscall_table.c @@ -13,5 +13,6 @@ #define __SYSCALL(nr, call) [nr] = (call), void *sys_call_table[__NR_syscalls] = { + [0 ... __NR_syscalls-1] = sys_ni_syscall, #include }; -- cgit v1.2.3 From 25ba820ef36bdbaf9884adeac69b6e1821a7df76 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Mon, 8 Aug 2022 16:07:21 +0100 Subject: nios2: traced syscall does need to check the syscall number all checks done before letting the tracer modify the register state are worthless... Fixes: 82ed08dd1b0e ("nios2: Exception handling") Signed-off-by: Al Viro Signed-off-by: Dinh Nguyen --- arch/nios2/kernel/entry.S | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/nios2/kernel/entry.S b/arch/nios2/kernel/entry.S index 8f41ef5b0399..fd2449031d08 100644 --- a/arch/nios2/kernel/entry.S +++ b/arch/nios2/kernel/entry.S @@ -255,9 +255,9 @@ traced_system_call: ldw r6, PT_R6(sp) ldw r7, PT_R7(sp) - /* Fetch the syscall function, we don't need to check the boundaries - * since this is already done. - */ + /* Fetch the syscall function. */ + movui r1, __NR_syscalls + bgeu r2, r1, traced_invsyscall slli r1, r2, 2 movhi r11,%hiadj(sys_call_table) add r1, r1, r11 @@ -287,6 +287,11 @@ end_translate_rc_and_ret2: RESTORE_SWITCH_STACK br ret_from_exception + /* If the syscall number was invalid return ENOSYS */ +traced_invsyscall: + movi r2, -ENOSYS + br translate_rc_and_ret2 + Luser_return: GET_THREAD_INFO r11 /* get thread_info pointer */ ldw r10, TI_FLAGS(r11) /* get thread_info->flags */ -- cgit v1.2.3 From 2d631bd58fe0ea3e3350212e23c9aba1fb606514 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Mon, 8 Aug 2022 16:08:48 +0100 Subject: nios2: fix syscall restart checks sys_foo() returns -512 (aka -ERESTARTSYS) => do_signal() sees 512 in r2 and 1 in r1. sys_foo() returns 512 => do_signal() sees 512 in r2 and 0 in r1. The former is restart-worthy; the latter obviously isn't. Fixes: b53e906d255d ("nios2: Signal handling support") Signed-off-by: Al Viro Signed-off-by: Dinh Nguyen --- arch/nios2/kernel/signal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/nios2/kernel/signal.c b/arch/nios2/kernel/signal.c index cb0b91589cf2..15e672d7150e 100644 --- a/arch/nios2/kernel/signal.c +++ b/arch/nios2/kernel/signal.c @@ -242,7 +242,7 @@ static int do_signal(struct pt_regs *regs) /* * If we were from a system call, check for system call restarting... */ - if (regs->orig_r2 >= 0) { + if (regs->orig_r2 >= 0 && regs->r1) { continue_addr = regs->ea; restart_addr = continue_addr - 4; retval = regs->r2; -- cgit v1.2.3 From 411a76b7219555c55867466c82d70ce928d6c9e1 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Mon, 8 Aug 2022 16:09:16 +0100 Subject: nios2: restarts apply only to the first sigframe we build... Fixes: b53e906d255d ("nios2: Signal handling support") Signed-off-by: Al Viro Signed-off-by: Dinh Nguyen --- arch/nios2/kernel/signal.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/nios2/kernel/signal.c b/arch/nios2/kernel/signal.c index 15e672d7150e..a5b93a30c6eb 100644 --- a/arch/nios2/kernel/signal.c +++ b/arch/nios2/kernel/signal.c @@ -264,6 +264,7 @@ static int do_signal(struct pt_regs *regs) regs->ea = restart_addr; break; } + regs->orig_r2 = -1; } if (get_signal(&ksig)) { -- cgit v1.2.3 From fd0c153daad135d0ec1a53c5dbe6936a724d6ae1 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Mon, 8 Aug 2022 16:09:45 +0100 Subject: nios2: add force_successful_syscall_return() If we use the ancient SysV syscall ABI, we'd better have tell the kernel how to claim that a negative return value is a success. Use ->orig_r2 for that - it's inaccessible via ptrace, so it's a fair game for changes and it's normally[*] non-negative on return from syscall. Set to -1; syscall is not going to be restart-worthy by definition, so we won't interfere with that use either. [*] the only exception is rt_sigreturn(), where we skip the entire messing with r1/r2 anyway. Fixes: 82ed08dd1b0e ("nios2: Exception handling") Signed-off-by: Al Viro Signed-off-by: Dinh Nguyen --- arch/nios2/include/asm/ptrace.h | 2 ++ arch/nios2/kernel/entry.S | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/arch/nios2/include/asm/ptrace.h b/arch/nios2/include/asm/ptrace.h index 642462144872..9da34c3022a2 100644 --- a/arch/nios2/include/asm/ptrace.h +++ b/arch/nios2/include/asm/ptrace.h @@ -74,6 +74,8 @@ extern void show_regs(struct pt_regs *); ((struct pt_regs *)((unsigned long)current_thread_info() + THREAD_SIZE)\ - 1) +#define force_successful_syscall_return() (current_pt_regs()->orig_r2 = -1) + int do_syscall_trace_enter(void); void do_syscall_trace_exit(void); #endif /* __ASSEMBLY__ */ diff --git a/arch/nios2/kernel/entry.S b/arch/nios2/kernel/entry.S index fd2449031d08..99f0a65e6234 100644 --- a/arch/nios2/kernel/entry.S +++ b/arch/nios2/kernel/entry.S @@ -213,6 +213,9 @@ local_restart: translate_rc_and_ret: movi r1, 0 bge r2, zero, 3f + ldw r1, PT_ORIG_R2(sp) + addi r1, r1, 1 + beq r1, zero, 3f sub r2, zero, r2 movi r1, 1 3: @@ -276,6 +279,9 @@ traced_system_call: translate_rc_and_ret2: movi r1, 0 bge r2, zero, 4f + ldw r1, PT_ORIG_R2(sp) + addi r1, r1, 1 + beq r1, zero, 4f sub r2, zero, r2 movi r1, 1 4: -- cgit v1.2.3 From 1b6345d4160ecd3d04bd8cd75df90c67811e8cc9 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Mon, 15 Aug 2022 17:55:07 +0200 Subject: netfilter: nf_tables: check NFT_SET_CONCAT flag if field_count is specified Since f3a2181e16f1 ("netfilter: nf_tables: Support for sets with multiple ranged fields"), it possible to combine intervals and concatenations. Later on, ef516e8625dd ("netfilter: nf_tables: reintroduce the NFT_SET_CONCAT flag") provides the NFT_SET_CONCAT flag for userspace to report that the set stores a concatenation. Make sure NFT_SET_CONCAT is set on if field_count is specified for consistency. Otherwise, if NFT_SET_CONCAT is specified with no field_count, bail out with EINVAL. Fixes: ef516e8625dd ("netfilter: nf_tables: reintroduce the NFT_SET_CONCAT flag") Signed-off-by: Pablo Neira Ayuso --- net/netfilter/nf_tables_api.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index b1b12e083abb..62cfb0e31c40 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -4451,6 +4451,11 @@ static int nf_tables_newset(struct sk_buff *skb, const struct nfnl_info *info, err = nf_tables_set_desc_parse(&desc, nla[NFTA_SET_DESC]); if (err < 0) return err; + + if (desc.field_count > 1 && !(flags & NFT_SET_CONCAT)) + return -EINVAL; + } else if (flags & NFT_SET_CONCAT) { + return -EINVAL; } if (nla[NFTA_SET_EXPR] || nla[NFTA_SET_EXPRESSIONS]) -- cgit v1.2.3 From f1227dc7d0411ee9a9faaa1e80cfd9d6e5d6d63e Mon Sep 17 00:00:00 2001 From: Guillaume Tucker Date: Wed, 3 Aug 2022 22:13:54 +0200 Subject: selftests/landlock: fix broken include of linux/landlock.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Revert part of the earlier changes to fix the kselftest build when using a sub-directory from the top of the tree as this broke the landlock test build as a side-effect when building with "make -C tools/testing/selftests/landlock". Reported-by: Mickaël Salaün Fixes: a917dd94b832 ("selftests/landlock: drop deprecated headers dependency") Fixes: f2745dc0ba3d ("selftests: stop using KSFT_KHDR_INSTALL") Signed-off-by: Guillaume Tucker Signed-off-by: Shuah Khan --- tools/testing/selftests/landlock/Makefile | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/landlock/Makefile b/tools/testing/selftests/landlock/Makefile index a6959df28eb0..02868ac3bc71 100644 --- a/tools/testing/selftests/landlock/Makefile +++ b/tools/testing/selftests/landlock/Makefile @@ -9,10 +9,13 @@ TEST_GEN_PROGS := $(src_test:.c=) TEST_GEN_PROGS_EXTENDED := true OVERRIDE_TARGETS := 1 +top_srcdir := ../../../.. include ../lib.mk +khdr_dir = $(top_srcdir)/usr/include + $(OUTPUT)/true: true.c $(LINK.c) $< $(LDLIBS) -o $@ -static -$(OUTPUT)/%_test: %_test.c ../kselftest_harness.h common.h - $(LINK.c) $< $(LDLIBS) -o $@ -lcap +$(OUTPUT)/%_test: %_test.c $(khdr_dir)/linux/landlock.h ../kselftest_harness.h common.h + $(LINK.c) $< $(LDLIBS) -o $@ -lcap -I$(khdr_dir) -- cgit v1.2.3 From 3a12df22a8f68954a4ba48435c06b3d1791c87c4 Mon Sep 17 00:00:00 2001 From: Sergei Antonov Date: Fri, 12 Aug 2022 20:13:39 +0300 Subject: net: moxa: pass pdev instead of ndev to DMA functions dma_map_single() calls fail in moxart_mac_setup_desc_ring() and moxart_mac_start_xmit() which leads to an incessant output of this: [ 16.043925] moxart-ethernet 92000000.mac eth0: DMA mapping error [ 16.050957] moxart-ethernet 92000000.mac eth0: DMA mapping error [ 16.058229] moxart-ethernet 92000000.mac eth0: DMA mapping error Passing pdev to DMA is a common approach among net drivers. Fixes: 6c821bd9edc9 ("net: Add MOXA ART SoCs ethernet driver") Signed-off-by: Sergei Antonov Suggested-by: Andrew Lunn Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/20220812171339.2271788-1-saproj@gmail.com Signed-off-by: Jakub Kicinski --- drivers/net/ethernet/moxa/moxart_ether.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/moxa/moxart_ether.c b/drivers/net/ethernet/moxa/moxart_ether.c index a3214a762e4b..f11f1cb92025 100644 --- a/drivers/net/ethernet/moxa/moxart_ether.c +++ b/drivers/net/ethernet/moxa/moxart_ether.c @@ -77,7 +77,7 @@ static void moxart_mac_free_memory(struct net_device *ndev) int i; for (i = 0; i < RX_DESC_NUM; i++) - dma_unmap_single(&ndev->dev, priv->rx_mapping[i], + dma_unmap_single(&priv->pdev->dev, priv->rx_mapping[i], priv->rx_buf_size, DMA_FROM_DEVICE); if (priv->tx_desc_base) @@ -147,11 +147,11 @@ static void moxart_mac_setup_desc_ring(struct net_device *ndev) desc + RX_REG_OFFSET_DESC1); priv->rx_buf[i] = priv->rx_buf_base + priv->rx_buf_size * i; - priv->rx_mapping[i] = dma_map_single(&ndev->dev, + priv->rx_mapping[i] = dma_map_single(&priv->pdev->dev, priv->rx_buf[i], priv->rx_buf_size, DMA_FROM_DEVICE); - if (dma_mapping_error(&ndev->dev, priv->rx_mapping[i])) + if (dma_mapping_error(&priv->pdev->dev, priv->rx_mapping[i])) netdev_err(ndev, "DMA mapping error\n"); moxart_desc_write(priv->rx_mapping[i], @@ -240,7 +240,7 @@ static int moxart_rx_poll(struct napi_struct *napi, int budget) if (len > RX_BUF_SIZE) len = RX_BUF_SIZE; - dma_sync_single_for_cpu(&ndev->dev, + dma_sync_single_for_cpu(&priv->pdev->dev, priv->rx_mapping[rx_head], priv->rx_buf_size, DMA_FROM_DEVICE); skb = netdev_alloc_skb_ip_align(ndev, len); @@ -294,7 +294,7 @@ static void moxart_tx_finished(struct net_device *ndev) unsigned int tx_tail = priv->tx_tail; while (tx_tail != tx_head) { - dma_unmap_single(&ndev->dev, priv->tx_mapping[tx_tail], + dma_unmap_single(&priv->pdev->dev, priv->tx_mapping[tx_tail], priv->tx_len[tx_tail], DMA_TO_DEVICE); ndev->stats.tx_packets++; @@ -358,9 +358,9 @@ static netdev_tx_t moxart_mac_start_xmit(struct sk_buff *skb, len = skb->len > TX_BUF_SIZE ? TX_BUF_SIZE : skb->len; - priv->tx_mapping[tx_head] = dma_map_single(&ndev->dev, skb->data, + priv->tx_mapping[tx_head] = dma_map_single(&priv->pdev->dev, skb->data, len, DMA_TO_DEVICE); - if (dma_mapping_error(&ndev->dev, priv->tx_mapping[tx_head])) { + if (dma_mapping_error(&priv->pdev->dev, priv->tx_mapping[tx_head])) { netdev_err(ndev, "DMA mapping error\n"); goto out_unlock; } @@ -379,7 +379,7 @@ static netdev_tx_t moxart_mac_start_xmit(struct sk_buff *skb, len = ETH_ZLEN; } - dma_sync_single_for_device(&ndev->dev, priv->tx_mapping[tx_head], + dma_sync_single_for_device(&priv->pdev->dev, priv->tx_mapping[tx_head], priv->tx_buf_size, DMA_TO_DEVICE); txdes1 = TX_DESC1_LTS | TX_DESC1_FTS | (len & TX_DESC1_BUF_SIZE_MASK); @@ -493,7 +493,7 @@ static int moxart_mac_probe(struct platform_device *pdev) priv->tx_buf_size = TX_BUF_SIZE; priv->rx_buf_size = RX_BUF_SIZE; - priv->tx_desc_base = dma_alloc_coherent(&pdev->dev, TX_REG_DESC_SIZE * + priv->tx_desc_base = dma_alloc_coherent(p_dev, TX_REG_DESC_SIZE * TX_DESC_NUM, &priv->tx_base, GFP_DMA | GFP_KERNEL); if (!priv->tx_desc_base) { @@ -501,7 +501,7 @@ static int moxart_mac_probe(struct platform_device *pdev) goto init_fail; } - priv->rx_desc_base = dma_alloc_coherent(&pdev->dev, RX_REG_DESC_SIZE * + priv->rx_desc_base = dma_alloc_coherent(p_dev, RX_REG_DESC_SIZE * RX_DESC_NUM, &priv->rx_base, GFP_DMA | GFP_KERNEL); if (!priv->rx_desc_base) { -- cgit v1.2.3 From 5b22f62724a0a09e00d301abf5b57b0c12be8a16 Mon Sep 17 00:00:00 2001 From: Zhengchao Shao Date: Mon, 15 Aug 2022 10:46:29 +0800 Subject: net: rtnetlink: fix module reference count leak issue in rtnetlink_rcv_msg When bulk delete command is received in the rtnetlink_rcv_msg function, if bulk delete is not supported, module_put is not called to release the reference counting. As a result, module reference count is leaked. Fixes: a6cec0bcd342 ("net: rtnetlink: add bulk delete support flag") Signed-off-by: Zhengchao Shao Acked-by: Nikolay Aleksandrov Link: https://lore.kernel.org/r/20220815024629.240367-1-shaozhengchao@huawei.com Signed-off-by: Jakub Kicinski --- net/core/rtnetlink.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c index ac45328607f7..4b5b15c684ed 100644 --- a/net/core/rtnetlink.c +++ b/net/core/rtnetlink.c @@ -6070,6 +6070,7 @@ static int rtnetlink_rcv_msg(struct sk_buff *skb, struct nlmsghdr *nlh, if (kind == RTNL_KIND_DEL && (nlh->nlmsg_flags & NLM_F_BULK) && !(flags & RTNL_FLAG_BULK_DEL_SUPPORTED)) { NL_SET_ERR_MSG(extack, "Bulk delete is not supported"); + module_put(owner); goto err_unlock; } -- cgit v1.2.3 From 2e9ca760c289e1f992eb2cd053e217db7934ab0a Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Tue, 16 Aug 2022 01:36:27 -0400 Subject: virtio_net: Revert "virtio_net: set the default max ring size by find_vqs()" This reverts commit 762faee5a2678559d3dc09d95f8f2c54cd0466a7. This has been reported to trip up guests on GCP (Google Cloud). The reason is that virtio_find_vqs_ctx_size is broken on legacy devices. We can in theory fix virtio_find_vqs_ctx_size but in fact the patch itself has several other issues: - It treats unknown speed as < 10G - It leaves userspace no way to find out the ring size set by hypervisor - It tests speed when link is down - It ignores the virtio spec advice: Both \field{speed} and \field{duplex} can change, thus the driver is expected to re-read these values after receiving a configuration change notification. - It is not clear the performance impact has been tested properly Revert the patch for now. Reported-by: Andres Freund Link: https://lore.kernel.org/r/20220814212610.GA3690074%40roeck-us.net Link: https://lore.kernel.org/r/20220815070203.plwjx7b3cyugpdt7%40awork3.anarazel.de Link: https://lore.kernel.org/r/3df6bb82-1951-455d-a768-e9e1513eb667%40www.fastmail.com Link: https://lore.kernel.org/r/FCDC5DDE-3CDD-4B8A-916F-CA7D87B547CE%40anarazel.de Fixes: 762faee5a267 ("virtio_net: set the default max ring size by find_vqs()") Cc: Xuan Zhuo Cc: Jason Wang Signed-off-by: Michael S. Tsirkin Tested-by: Andres Freund Tested-by: Guenter Roeck Message-Id: <20220816053602.173815-2-mst@redhat.com> --- drivers/net/virtio_net.c | 42 ++++-------------------------------------- 1 file changed, 4 insertions(+), 38 deletions(-) diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index d934774e9733..ece00b84e3a7 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c @@ -3432,29 +3432,6 @@ static unsigned int mergeable_min_buf_len(struct virtnet_info *vi, struct virtqu (unsigned int)GOOD_PACKET_LEN); } -static void virtnet_config_sizes(struct virtnet_info *vi, u32 *sizes) -{ - u32 i, rx_size, tx_size; - - if (vi->speed == SPEED_UNKNOWN || vi->speed < SPEED_10000) { - rx_size = 1024; - tx_size = 1024; - - } else if (vi->speed < SPEED_40000) { - rx_size = 1024 * 4; - tx_size = 1024 * 4; - - } else { - rx_size = 1024 * 8; - tx_size = 1024 * 8; - } - - for (i = 0; i < vi->max_queue_pairs; i++) { - sizes[rxq2vq(i)] = rx_size; - sizes[txq2vq(i)] = tx_size; - } -} - static int virtnet_find_vqs(struct virtnet_info *vi) { vq_callback_t **callbacks; @@ -3462,7 +3439,6 @@ static int virtnet_find_vqs(struct virtnet_info *vi) int ret = -ENOMEM; int i, total_vqs; const char **names; - u32 *sizes; bool *ctx; /* We expect 1 RX virtqueue followed by 1 TX virtqueue, followed by @@ -3490,15 +3466,10 @@ static int virtnet_find_vqs(struct virtnet_info *vi) ctx = NULL; } - sizes = kmalloc_array(total_vqs, sizeof(*sizes), GFP_KERNEL); - if (!sizes) - goto err_sizes; - /* Parameters for control virtqueue, if any */ if (vi->has_cvq) { callbacks[total_vqs - 1] = NULL; names[total_vqs - 1] = "control"; - sizes[total_vqs - 1] = 64; } /* Allocate/initialize parameters for send/receive virtqueues */ @@ -3513,10 +3484,8 @@ static int virtnet_find_vqs(struct virtnet_info *vi) ctx[rxq2vq(i)] = true; } - virtnet_config_sizes(vi, sizes); - - ret = virtio_find_vqs_ctx_size(vi->vdev, total_vqs, vqs, callbacks, - names, sizes, ctx, NULL); + ret = virtio_find_vqs_ctx(vi->vdev, total_vqs, vqs, callbacks, + names, ctx, NULL); if (ret) goto err_find; @@ -3536,8 +3505,6 @@ static int virtnet_find_vqs(struct virtnet_info *vi) err_find: - kfree(sizes); -err_sizes: kfree(ctx); err_ctx: kfree(names); @@ -3897,9 +3864,6 @@ static int virtnet_probe(struct virtio_device *vdev) vi->curr_queue_pairs = num_online_cpus(); vi->max_queue_pairs = max_queue_pairs; - virtnet_init_settings(dev); - virtnet_update_settings(vi); - /* Allocate/initialize the rx/tx queues, and invoke find_vqs */ err = init_vqs(vi); if (err) @@ -3912,6 +3876,8 @@ static int virtnet_probe(struct virtio_device *vdev) netif_set_real_num_tx_queues(dev, vi->curr_queue_pairs); netif_set_real_num_rx_queues(dev, vi->curr_queue_pairs); + virtnet_init_settings(dev); + if (virtio_has_feature(vdev, VIRTIO_NET_F_STANDBY)) { vi->failover = net_failover_create(vi->dev); if (IS_ERR(vi->failover)) { -- cgit v1.2.3 From 484b9fa4886bd9377969aad5e9ea17efda4ecda6 Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Tue, 16 Aug 2022 01:36:31 -0400 Subject: virtio: Revert "virtio: add helper virtio_find_vqs_ctx_size()" This reverts commit fe3dc04e31aa51f91dc7f741a5f76cc4817eb5b4: the API is now unused and in fact can't be implemented on top of a legacy device. Fixes: fe3dc04e31aa ("virtio: add helper virtio_find_vqs_ctx_size()") Cc: "Xuan Zhuo" Signed-off-by: Michael S. Tsirkin Message-Id: <20220816053602.173815-3-mst@redhat.com> --- include/linux/virtio_config.h | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/include/linux/virtio_config.h b/include/linux/virtio_config.h index 6adff09f7170..888f7e96f0c7 100644 --- a/include/linux/virtio_config.h +++ b/include/linux/virtio_config.h @@ -241,18 +241,6 @@ int virtio_find_vqs_ctx(struct virtio_device *vdev, unsigned nvqs, ctx, desc); } -static inline -int virtio_find_vqs_ctx_size(struct virtio_device *vdev, u32 nvqs, - struct virtqueue *vqs[], - vq_callback_t *callbacks[], - const char * const names[], - u32 sizes[], - const bool *ctx, struct irq_affinity *desc) -{ - return vdev->config->find_vqs(vdev, nvqs, vqs, callbacks, names, sizes, - ctx, desc); -} - /** * virtio_synchronize_cbs - synchronize with virtqueue callbacks * @vdev: the device -- cgit v1.2.3 From c62f61b58f6e41cab9c07557213b61d71e6b221c Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Tue, 16 Aug 2022 01:36:35 -0400 Subject: virtio-mmio: Revert "virtio_mmio: support the arg sizes of find_vqs()" This reverts commit fbed86abba6e0472d98079790e58060e4332608a. The API is now unused, let's not carry dead code around. Fixes: fbed86abba6e ("virtio_mmio: support the arg sizes of find_vqs()") Signed-off-by: Michael S. Tsirkin Message-Id: <20220816053602.173815-4-mst@redhat.com> --- drivers/virtio/virtio_mmio.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index c492a57531c6..dfcecfd7aba1 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -360,7 +360,7 @@ static void vm_synchronize_cbs(struct virtio_device *vdev) static struct virtqueue *vm_setup_vq(struct virtio_device *vdev, unsigned int index, void (*callback)(struct virtqueue *vq), - const char *name, u32 size, bool ctx) + const char *name, bool ctx) { struct virtio_mmio_device *vm_dev = to_virtio_mmio_device(vdev); struct virtio_mmio_vq_info *info; @@ -395,11 +395,8 @@ static struct virtqueue *vm_setup_vq(struct virtio_device *vdev, unsigned int in goto error_new_virtqueue; } - if (!size || size > num) - size = num; - /* Create the vring */ - vq = vring_create_virtqueue(index, size, VIRTIO_MMIO_VRING_ALIGN, vdev, + vq = vring_create_virtqueue(index, num, VIRTIO_MMIO_VRING_ALIGN, vdev, true, true, ctx, vm_notify, callback, name); if (!vq) { err = -ENOMEM; @@ -503,7 +500,6 @@ static int vm_find_vqs(struct virtio_device *vdev, unsigned int nvqs, } vqs[i] = vm_setup_vq(vdev, queue_idx++, callbacks[i], names[i], - sizes ? sizes[i] : 0, ctx ? ctx[i] : false); if (IS_ERR(vqs[i])) { vm_del_vqs(vdev); -- cgit v1.2.3 From 13aa8c6c37bd54eaf16f89e2e07019796fb9e681 Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Tue, 16 Aug 2022 01:36:40 -0400 Subject: virtio_pci: Revert "virtio_pci: support the arg sizes of find_vqs()" This reverts commit cdb44806fca2d0ad29ca644cbf1505433902ee0c: the legacy path is wrong and in fact can not support the proposed API since for a legacy device we never communicate the vq size to the hypervisor. Reported-by: Andres Freund Fixes: cdb44806fca2 ("virtio_pci: support the arg sizes of find_vqs()") Signed-off-by: Michael S. Tsirkin Message-Id: <20220816053602.173815-5-mst@redhat.com> --- drivers/virtio/virtio_pci_common.c | 18 ++++++++---------- drivers/virtio/virtio_pci_common.h | 1 - drivers/virtio/virtio_pci_legacy.c | 6 +----- drivers/virtio/virtio_pci_modern.c | 10 +++------- 4 files changed, 12 insertions(+), 23 deletions(-) diff --git a/drivers/virtio/virtio_pci_common.c b/drivers/virtio/virtio_pci_common.c index 00ad476a815d..7ad734584823 100644 --- a/drivers/virtio/virtio_pci_common.c +++ b/drivers/virtio/virtio_pci_common.c @@ -174,7 +174,6 @@ error: static struct virtqueue *vp_setup_vq(struct virtio_device *vdev, unsigned int index, void (*callback)(struct virtqueue *vq), const char *name, - u32 size, bool ctx, u16 msix_vec) { @@ -187,7 +186,7 @@ static struct virtqueue *vp_setup_vq(struct virtio_device *vdev, unsigned int in if (!info) return ERR_PTR(-ENOMEM); - vq = vp_dev->setup_vq(vp_dev, info, index, callback, name, size, ctx, + vq = vp_dev->setup_vq(vp_dev, info, index, callback, name, ctx, msix_vec); if (IS_ERR(vq)) goto out_info; @@ -284,7 +283,7 @@ void vp_del_vqs(struct virtio_device *vdev) static int vp_find_vqs_msix(struct virtio_device *vdev, unsigned int nvqs, struct virtqueue *vqs[], vq_callback_t *callbacks[], - const char * const names[], u32 sizes[], bool per_vq_vectors, + const char * const names[], bool per_vq_vectors, const bool *ctx, struct irq_affinity *desc) { @@ -327,8 +326,8 @@ static int vp_find_vqs_msix(struct virtio_device *vdev, unsigned int nvqs, else msix_vec = VP_MSIX_VQ_VECTOR; vqs[i] = vp_setup_vq(vdev, queue_idx++, callbacks[i], names[i], - sizes ? sizes[i] : 0, - ctx ? ctx[i] : false, msix_vec); + ctx ? ctx[i] : false, + msix_vec); if (IS_ERR(vqs[i])) { err = PTR_ERR(vqs[i]); goto error_find; @@ -358,7 +357,7 @@ error_find: static int vp_find_vqs_intx(struct virtio_device *vdev, unsigned int nvqs, struct virtqueue *vqs[], vq_callback_t *callbacks[], - const char * const names[], u32 sizes[], const bool *ctx) + const char * const names[], const bool *ctx) { struct virtio_pci_device *vp_dev = to_vp_device(vdev); int i, err, queue_idx = 0; @@ -380,7 +379,6 @@ static int vp_find_vqs_intx(struct virtio_device *vdev, unsigned int nvqs, continue; } vqs[i] = vp_setup_vq(vdev, queue_idx++, callbacks[i], names[i], - sizes ? sizes[i] : 0, ctx ? ctx[i] : false, VIRTIO_MSI_NO_VECTOR); if (IS_ERR(vqs[i])) { @@ -404,15 +402,15 @@ int vp_find_vqs(struct virtio_device *vdev, unsigned int nvqs, int err; /* Try MSI-X with one vector per queue. */ - err = vp_find_vqs_msix(vdev, nvqs, vqs, callbacks, names, sizes, true, ctx, desc); + err = vp_find_vqs_msix(vdev, nvqs, vqs, callbacks, names, true, ctx, desc); if (!err) return 0; /* Fallback: MSI-X with one vector for config, one shared for queues. */ - err = vp_find_vqs_msix(vdev, nvqs, vqs, callbacks, names, sizes, false, ctx, desc); + err = vp_find_vqs_msix(vdev, nvqs, vqs, callbacks, names, false, ctx, desc); if (!err) return 0; /* Finally fall back to regular interrupts. */ - return vp_find_vqs_intx(vdev, nvqs, vqs, callbacks, names, sizes, ctx); + return vp_find_vqs_intx(vdev, nvqs, vqs, callbacks, names, ctx); } const char *vp_bus_name(struct virtio_device *vdev) diff --git a/drivers/virtio/virtio_pci_common.h b/drivers/virtio/virtio_pci_common.h index c0448378b698..a5ff838b85a5 100644 --- a/drivers/virtio/virtio_pci_common.h +++ b/drivers/virtio/virtio_pci_common.h @@ -80,7 +80,6 @@ struct virtio_pci_device { unsigned int idx, void (*callback)(struct virtqueue *vq), const char *name, - u32 size, bool ctx, u16 msix_vec); void (*del_vq)(struct virtio_pci_vq_info *info); diff --git a/drivers/virtio/virtio_pci_legacy.c b/drivers/virtio/virtio_pci_legacy.c index d75e5c4e637f..2257f1b3d8ae 100644 --- a/drivers/virtio/virtio_pci_legacy.c +++ b/drivers/virtio/virtio_pci_legacy.c @@ -112,7 +112,6 @@ static struct virtqueue *setup_vq(struct virtio_pci_device *vp_dev, unsigned int index, void (*callback)(struct virtqueue *vq), const char *name, - u32 size, bool ctx, u16 msix_vec) { @@ -126,13 +125,10 @@ static struct virtqueue *setup_vq(struct virtio_pci_device *vp_dev, if (!num || vp_legacy_get_queue_enable(&vp_dev->ldev, index)) return ERR_PTR(-ENOENT); - if (!size || size > num) - size = num; - info->msix_vector = msix_vec; /* create the vring */ - vq = vring_create_virtqueue(index, size, + vq = vring_create_virtqueue(index, num, VIRTIO_PCI_VRING_ALIGN, &vp_dev->vdev, true, false, ctx, vp_notify, callback, name); diff --git a/drivers/virtio/virtio_pci_modern.c b/drivers/virtio/virtio_pci_modern.c index f7965c5dd36b..be51ec849252 100644 --- a/drivers/virtio/virtio_pci_modern.c +++ b/drivers/virtio/virtio_pci_modern.c @@ -293,7 +293,6 @@ static struct virtqueue *setup_vq(struct virtio_pci_device *vp_dev, unsigned int index, void (*callback)(struct virtqueue *vq), const char *name, - u32 size, bool ctx, u16 msix_vec) { @@ -311,18 +310,15 @@ static struct virtqueue *setup_vq(struct virtio_pci_device *vp_dev, if (!num || vp_modern_get_queue_enable(mdev, index)) return ERR_PTR(-ENOENT); - if (!size || size > num) - size = num; - - if (size & (size - 1)) { - dev_warn(&vp_dev->pci_dev->dev, "bad queue size %u", size); + if (num & (num - 1)) { + dev_warn(&vp_dev->pci_dev->dev, "bad queue size %u", num); return ERR_PTR(-EINVAL); } info->msix_vector = msix_vec; /* create the vring */ - vq = vring_create_virtqueue(index, size, + vq = vring_create_virtqueue(index, num, SMP_CACHE_BYTES, &vp_dev->vdev, true, true, ctx, vp_notify, callback, name); -- cgit v1.2.3 From 9e82eb574c5d90a175ae830916af8b8a1ccc31e7 Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Tue, 16 Aug 2022 01:36:45 -0400 Subject: virtio_vdpa: Revert "virtio_vdpa: support the arg sizes of find_vqs()" This reverts commit 99e8927d8a4da8eb8a8a5904dc13a3156be8e7c0: proposed API isn't supported on all transports but no effort was made to address this. It might not be hard to fix if we want to: maybe just rename size to size_hint and make sure legacy transports ignore the hint. But it's not sure what the benefit is in any case, so let's drop it. Fixes: 99e8927d8a4d ("virtio_vdpa: support the arg sizes of find_vqs()") Signed-off-by: Michael S. Tsirkin Message-Id: <20220816053602.173815-6-mst@redhat.com> --- drivers/virtio/virtio_vdpa.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/virtio/virtio_vdpa.c b/drivers/virtio/virtio_vdpa.c index 9bc4d110b800..832d2c5b1b19 100644 --- a/drivers/virtio/virtio_vdpa.c +++ b/drivers/virtio/virtio_vdpa.c @@ -131,7 +131,7 @@ static irqreturn_t virtio_vdpa_virtqueue_cb(void *private) static struct virtqueue * virtio_vdpa_setup_vq(struct virtio_device *vdev, unsigned int index, void (*callback)(struct virtqueue *vq), - const char *name, u32 size, bool ctx) + const char *name, bool ctx) { struct virtio_vdpa_device *vd_dev = to_virtio_vdpa_device(vdev); struct vdpa_device *vdpa = vd_get_vdpa(vdev); @@ -168,17 +168,14 @@ virtio_vdpa_setup_vq(struct virtio_device *vdev, unsigned int index, goto error_new_virtqueue; } - if (!size || size > max_num) - size = max_num; - if (ops->get_vq_num_min) min_num = ops->get_vq_num_min(vdpa); - may_reduce_num = (size == min_num) ? false : true; + may_reduce_num = (max_num == min_num) ? false : true; /* Create the vring */ align = ops->get_vq_align(vdpa); - vq = vring_create_virtqueue(index, size, align, vdev, + vq = vring_create_virtqueue(index, max_num, align, vdev, true, may_reduce_num, ctx, virtio_vdpa_notify, callback, name); if (!vq) { @@ -288,9 +285,9 @@ static int virtio_vdpa_find_vqs(struct virtio_device *vdev, unsigned int nvqs, continue; } - vqs[i] = virtio_vdpa_setup_vq(vdev, queue_idx++, callbacks[i], - names[i], sizes ? sizes[i] : 0, - ctx ? ctx[i] : false); + vqs[i] = virtio_vdpa_setup_vq(vdev, queue_idx++, + callbacks[i], names[i], ctx ? + ctx[i] : false); if (IS_ERR(vqs[i])) { err = PTR_ERR(vqs[i]); goto err_setup_vq; -- cgit v1.2.3 From 9993a4f989c7ca5e227329b2878f65d05c9fc20f Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Tue, 16 Aug 2022 01:36:58 -0400 Subject: virtio: Revert "virtio: find_vqs() add arg sizes" This reverts commit a10fba0377145fccefea4dc4dd5915b7ed87e546: the proposed API isn't supported on all transports but no effort was made to address this. It might not be hard to fix if we want to: maybe just rename size to size_hint and make sure legacy transports ignore the hint. But it's not sure what the benefit is in any case, so let's drop it. Fixes: a10fba037714 ("virtio: find_vqs() add arg sizes") Signed-off-by: Michael S. Tsirkin Message-Id: <20220816053602.173815-8-mst@redhat.com> --- arch/um/drivers/virtio_uml.c | 2 +- drivers/platform/mellanox/mlxbf-tmfifo.c | 1 - drivers/remoteproc/remoteproc_virtio.c | 1 - drivers/s390/virtio/virtio_ccw.c | 1 - drivers/virtio/virtio_mmio.c | 1 - drivers/virtio/virtio_pci_common.c | 2 +- drivers/virtio/virtio_pci_common.h | 2 +- drivers/virtio/virtio_pci_modern.c | 7 ++----- drivers/virtio/virtio_vdpa.c | 1 - include/linux/virtio_config.h | 14 +++++--------- 10 files changed, 10 insertions(+), 22 deletions(-) diff --git a/arch/um/drivers/virtio_uml.c b/arch/um/drivers/virtio_uml.c index 79e38afd4b91..e719af8bdf56 100644 --- a/arch/um/drivers/virtio_uml.c +++ b/arch/um/drivers/virtio_uml.c @@ -1011,7 +1011,7 @@ error_kzalloc: static int vu_find_vqs(struct virtio_device *vdev, unsigned nvqs, struct virtqueue *vqs[], vq_callback_t *callbacks[], - const char * const names[], u32 sizes[], const bool *ctx, + const char * const names[], const bool *ctx, struct irq_affinity *desc) { struct virtio_uml_device *vu_dev = to_virtio_uml_device(vdev); diff --git a/drivers/platform/mellanox/mlxbf-tmfifo.c b/drivers/platform/mellanox/mlxbf-tmfifo.c index 8be13d416f48..1ae3c56b66b0 100644 --- a/drivers/platform/mellanox/mlxbf-tmfifo.c +++ b/drivers/platform/mellanox/mlxbf-tmfifo.c @@ -928,7 +928,6 @@ static int mlxbf_tmfifo_virtio_find_vqs(struct virtio_device *vdev, struct virtqueue *vqs[], vq_callback_t *callbacks[], const char * const names[], - u32 sizes[], const bool *ctx, struct irq_affinity *desc) { diff --git a/drivers/remoteproc/remoteproc_virtio.c b/drivers/remoteproc/remoteproc_virtio.c index 81c4f5776109..0f7706e23eb9 100644 --- a/drivers/remoteproc/remoteproc_virtio.c +++ b/drivers/remoteproc/remoteproc_virtio.c @@ -158,7 +158,6 @@ static int rproc_virtio_find_vqs(struct virtio_device *vdev, unsigned int nvqs, struct virtqueue *vqs[], vq_callback_t *callbacks[], const char * const names[], - u32 sizes[], const bool * ctx, struct irq_affinity *desc) { diff --git a/drivers/s390/virtio/virtio_ccw.c b/drivers/s390/virtio/virtio_ccw.c index 896896e32664..a10dbe632ef9 100644 --- a/drivers/s390/virtio/virtio_ccw.c +++ b/drivers/s390/virtio/virtio_ccw.c @@ -637,7 +637,6 @@ static int virtio_ccw_find_vqs(struct virtio_device *vdev, unsigned nvqs, struct virtqueue *vqs[], vq_callback_t *callbacks[], const char * const names[], - u32 sizes[], const bool *ctx, struct irq_affinity *desc) { diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index dfcecfd7aba1..3ff746e3f24a 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -474,7 +474,6 @@ static int vm_find_vqs(struct virtio_device *vdev, unsigned int nvqs, struct virtqueue *vqs[], vq_callback_t *callbacks[], const char * const names[], - u32 sizes[], const bool *ctx, struct irq_affinity *desc) { diff --git a/drivers/virtio/virtio_pci_common.c b/drivers/virtio/virtio_pci_common.c index 7ad734584823..ad258a9d3b9f 100644 --- a/drivers/virtio/virtio_pci_common.c +++ b/drivers/virtio/virtio_pci_common.c @@ -396,7 +396,7 @@ out_del_vqs: /* the config->find_vqs() implementation */ int vp_find_vqs(struct virtio_device *vdev, unsigned int nvqs, struct virtqueue *vqs[], vq_callback_t *callbacks[], - const char * const names[], u32 sizes[], const bool *ctx, + const char * const names[], const bool *ctx, struct irq_affinity *desc) { int err; diff --git a/drivers/virtio/virtio_pci_common.h b/drivers/virtio/virtio_pci_common.h index a5ff838b85a5..23112d84218f 100644 --- a/drivers/virtio/virtio_pci_common.h +++ b/drivers/virtio/virtio_pci_common.h @@ -110,7 +110,7 @@ void vp_del_vqs(struct virtio_device *vdev); /* the config->find_vqs() implementation */ int vp_find_vqs(struct virtio_device *vdev, unsigned int nvqs, struct virtqueue *vqs[], vq_callback_t *callbacks[], - const char * const names[], u32 sizes[], const bool *ctx, + const char * const names[], const bool *ctx, struct irq_affinity *desc); const char *vp_bus_name(struct virtio_device *vdev); diff --git a/drivers/virtio/virtio_pci_modern.c b/drivers/virtio/virtio_pci_modern.c index be51ec849252..c3b9f2761849 100644 --- a/drivers/virtio/virtio_pci_modern.c +++ b/drivers/virtio/virtio_pci_modern.c @@ -347,15 +347,12 @@ err: static int vp_modern_find_vqs(struct virtio_device *vdev, unsigned int nvqs, struct virtqueue *vqs[], vq_callback_t *callbacks[], - const char * const names[], - u32 sizes[], - const bool *ctx, + const char * const names[], const bool *ctx, struct irq_affinity *desc) { struct virtio_pci_device *vp_dev = to_vp_device(vdev); struct virtqueue *vq; - int rc = vp_find_vqs(vdev, nvqs, vqs, callbacks, names, sizes, ctx, - desc); + int rc = vp_find_vqs(vdev, nvqs, vqs, callbacks, names, ctx, desc); if (rc) return rc; diff --git a/drivers/virtio/virtio_vdpa.c b/drivers/virtio/virtio_vdpa.c index 832d2c5b1b19..9670cc79371d 100644 --- a/drivers/virtio/virtio_vdpa.c +++ b/drivers/virtio/virtio_vdpa.c @@ -269,7 +269,6 @@ static int virtio_vdpa_find_vqs(struct virtio_device *vdev, unsigned int nvqs, struct virtqueue *vqs[], vq_callback_t *callbacks[], const char * const names[], - u32 sizes[], const bool *ctx, struct irq_affinity *desc) { diff --git a/include/linux/virtio_config.h b/include/linux/virtio_config.h index 888f7e96f0c7..36ec7be1f480 100644 --- a/include/linux/virtio_config.h +++ b/include/linux/virtio_config.h @@ -55,7 +55,6 @@ struct virtio_shm_region { * include a NULL entry for vqs that do not need a callback * names: array of virtqueue names (mainly for debugging) * include a NULL entry for vqs unused by driver - * sizes: array of virtqueue sizes * Returns 0 on success or error status * @del_vqs: free virtqueues found by find_vqs(). * @synchronize_cbs: synchronize with the virtqueue callbacks (optional) @@ -104,9 +103,7 @@ struct virtio_config_ops { void (*reset)(struct virtio_device *vdev); int (*find_vqs)(struct virtio_device *, unsigned nvqs, struct virtqueue *vqs[], vq_callback_t *callbacks[], - const char * const names[], - u32 sizes[], - const bool *ctx, + const char * const names[], const bool *ctx, struct irq_affinity *desc); void (*del_vqs)(struct virtio_device *); void (*synchronize_cbs)(struct virtio_device *); @@ -215,7 +212,7 @@ struct virtqueue *virtio_find_single_vq(struct virtio_device *vdev, const char *names[] = { n }; struct virtqueue *vq; int err = vdev->config->find_vqs(vdev, 1, &vq, callbacks, names, NULL, - NULL, NULL); + NULL); if (err < 0) return ERR_PTR(err); return vq; @@ -227,8 +224,7 @@ int virtio_find_vqs(struct virtio_device *vdev, unsigned nvqs, const char * const names[], struct irq_affinity *desc) { - return vdev->config->find_vqs(vdev, nvqs, vqs, callbacks, names, NULL, - NULL, desc); + return vdev->config->find_vqs(vdev, nvqs, vqs, callbacks, names, NULL, desc); } static inline @@ -237,8 +233,8 @@ int virtio_find_vqs_ctx(struct virtio_device *vdev, unsigned nvqs, const char * const names[], const bool *ctx, struct irq_affinity *desc) { - return vdev->config->find_vqs(vdev, nvqs, vqs, callbacks, names, NULL, - ctx, desc); + return vdev->config->find_vqs(vdev, nvqs, vqs, callbacks, names, ctx, + desc); } /** -- cgit v1.2.3 From 5c669c4a4c6aa0489848093c93b8029f5c5c75ec Mon Sep 17 00:00:00 2001 From: Ricardo Cañuelo Date: Wed, 10 Aug 2022 11:40:03 +0200 Subject: virtio: kerneldocs fixes and enhancements MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix variable names in some kerneldocs, naming in others. Add kerneldocs for struct vring_desc and vring_interrupt. Signed-off-by: Ricardo Cañuelo Message-Id: <20220810094004.1250-2-ricardo.canuelo@collabora.com> Signed-off-by: Michael S. Tsirkin Reviewed-by: Cornelia Huck --- drivers/virtio/virtio_ring.c | 8 ++++++++ include/linux/virtio.h | 6 +++--- include/linux/virtio_config.h | 6 +++--- include/uapi/linux/virtio_ring.h | 16 +++++++++++----- 4 files changed, 25 insertions(+), 11 deletions(-) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index d66c8e6d0ef3..4620e9d79dde 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -2426,6 +2426,14 @@ static inline bool more_used(const struct vring_virtqueue *vq) return vq->packed_ring ? more_used_packed(vq) : more_used_split(vq); } +/** + * vring_interrupt - notify a virtqueue on an interrupt + * @irq: the IRQ number (ignored) + * @_vq: the struct virtqueue to notify + * + * Calls the callback function of @_vq to process the virtqueue + * notification. + */ irqreturn_t vring_interrupt(int irq, void *_vq) { struct vring_virtqueue *vq = to_vvq(_vq); diff --git a/include/linux/virtio.h b/include/linux/virtio.h index a3f73bb6733e..dcab9c7e8784 100644 --- a/include/linux/virtio.h +++ b/include/linux/virtio.h @@ -11,7 +11,7 @@ #include /** - * virtqueue - a queue to register buffers for sending or receiving. + * struct virtqueue - a queue to register buffers for sending or receiving. * @list: the chain of virtqueues for this device * @callback: the function to call when buffers are consumed (can be NULL). * @name: the name of this virtqueue (mainly for debugging) @@ -97,7 +97,7 @@ int virtqueue_resize(struct virtqueue *vq, u32 num, void (*recycle)(struct virtqueue *vq, void *buf)); /** - * virtio_device - representation of a device using virtio + * struct virtio_device - representation of a device using virtio * @index: unique position on the virtio bus * @failed: saved value for VIRTIO_CONFIG_S_FAILED bit (for restore) * @config_enabled: configuration change reporting enabled @@ -156,7 +156,7 @@ size_t virtio_max_dma_size(struct virtio_device *vdev); list_for_each_entry(vq, &vdev->vqs, list) /** - * virtio_driver - operations for a virtio I/O driver + * struct virtio_driver - operations for a virtio I/O driver * @driver: underlying device driver (populate name and owner). * @id_table: the ids serviced by this driver. * @feature_table: an array of feature numbers supported by this driver. diff --git a/include/linux/virtio_config.h b/include/linux/virtio_config.h index 36ec7be1f480..4b517649cfe8 100644 --- a/include/linux/virtio_config.h +++ b/include/linux/virtio_config.h @@ -239,7 +239,7 @@ int virtio_find_vqs_ctx(struct virtio_device *vdev, unsigned nvqs, /** * virtio_synchronize_cbs - synchronize with virtqueue callbacks - * @vdev: the device + * @dev: the virtio device */ static inline void virtio_synchronize_cbs(struct virtio_device *dev) @@ -258,7 +258,7 @@ void virtio_synchronize_cbs(struct virtio_device *dev) /** * virtio_device_ready - enable vq use in probe function - * @vdev: the device + * @dev: the virtio device * * Driver must call this to use vqs in the probe function. * @@ -306,7 +306,7 @@ const char *virtio_bus_name(struct virtio_device *vdev) /** * virtqueue_set_affinity - setting affinity for a virtqueue * @vq: the virtqueue - * @cpu: the cpu no. + * @cpu_mask: the cpu mask * * Pay attention the function are best-effort: the affinity hint may not be set * due to config support, irq type and sharing. diff --git a/include/uapi/linux/virtio_ring.h b/include/uapi/linux/virtio_ring.h index 476d3e5c0fe7..f8c20d3de8da 100644 --- a/include/uapi/linux/virtio_ring.h +++ b/include/uapi/linux/virtio_ring.h @@ -93,15 +93,21 @@ #define VRING_USED_ALIGN_SIZE 4 #define VRING_DESC_ALIGN_SIZE 16 -/* Virtio ring descriptors: 16 bytes. These can chain together via "next". */ +/** + * struct vring_desc - Virtio ring descriptors, + * 16 bytes long. These can chain together via @next. + * + * @addr: buffer address (guest-physical) + * @len: buffer length + * @flags: descriptor flags + * @next: index of the next descriptor in the chain, + * if the VRING_DESC_F_NEXT flag is set. We chain unused + * descriptors via this, too. + */ struct vring_desc { - /* Address (guest-physical). */ __virtio64 addr; - /* Length. */ __virtio32 len; - /* The flags as indicated above. */ __virtio16 flags; - /* We chain unused descriptors via this, too */ __virtio16 next; }; -- cgit v1.2.3 From 2c6482091f01ba104cf8ee549aa5c717e80d43ea Mon Sep 17 00:00:00 2001 From: Przemyslaw Patynowski Date: Wed, 27 Jul 2022 11:19:40 +0200 Subject: i40e: Fix tunnel checksum offload with fragmented traffic Fix checksum offload on VXLAN tunnels. In case, when mpls protocol is not used, set l4 header to transport header of skb. This fixes case, when user tries to offload checksums of VXLAN tunneled traffic. Steps for reproduction (requires link partner with tunnels): ip l s enp130s0f0 up ip a f enp130s0f0 ip a a 10.10.110.2/24 dev enp130s0f0 ip l s enp130s0f0 mtu 1600 ip link add vxlan12_sut type vxlan id 12 group 238.168.100.100 dev \ enp130s0f0 dstport 4789 ip l s vxlan12_sut up ip a a 20.10.110.2/24 dev vxlan12_sut iperf3 -c 20.10.110.1 #should connect Without this patch, TX descriptor was using wrong data, due to l4 header pointing wrong address. NIC would then drop those packets internally, due to incorrect TX descriptor data, which increased GLV_TEPC register. Fixes: b4fb2d33514a ("i40e: Add support for MPLS + TSO") Signed-off-by: Przemyslaw Patynowski Signed-off-by: Mateusz Palczewski Tested-by: Marek Szlosek Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/i40e/i40e_txrx.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c index f6ba97a0166e..d4226161a3ef 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c +++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c @@ -3203,11 +3203,13 @@ static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags, protocol = vlan_get_protocol(skb); - if (eth_p_mpls(protocol)) + if (eth_p_mpls(protocol)) { ip.hdr = skb_inner_network_header(skb); - else + l4.hdr = skb_checksum_start(skb); + } else { ip.hdr = skb_network_header(skb); - l4.hdr = skb_checksum_start(skb); + l4.hdr = skb_transport_header(skb); + } /* set the tx_flags to indicate the IP protocol type. this is * required so that checksum header computation below is accurate. -- cgit v1.2.3 From 57c942bc3bef0970f0b21f8e0998e76a900ea80d Mon Sep 17 00:00:00 2001 From: Alan Brady Date: Tue, 2 Aug 2022 10:19:17 +0200 Subject: i40e: Fix to stop tx_timeout recovery if GLOBR fails When a tx_timeout fires, the PF attempts to recover by incrementally resetting. First we try a PFR, then CORER and finally a GLOBR. If the GLOBR fails, then we keep hitting the tx_timeout and incrementing the recovery level and issuing dmesgs, which is both annoying to the user and accomplishes nothing. If the GLOBR fails, then we're pretty much totally hosed, and there's not much else we can do to recover, so this makes it such that we just kill the VSI and stop hitting the tx_timeout in such a case. Fixes: 41c445ff0f48 ("i40e: main driver core") Signed-off-by: Alan Brady Signed-off-by: Mateusz Palczewski Tested-by: Gurucharan (A Contingent worker at Intel) Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/i40e/i40e_main.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c index b36bf9c3e1e4..9f1d5de7bf16 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_main.c +++ b/drivers/net/ethernet/intel/i40e/i40e_main.c @@ -384,7 +384,9 @@ static void i40e_tx_timeout(struct net_device *netdev, unsigned int txqueue) set_bit(__I40E_GLOBAL_RESET_REQUESTED, pf->state); break; default: - netdev_err(netdev, "tx_timeout recovery unsuccessful\n"); + netdev_err(netdev, "tx_timeout recovery unsuccessful, device is in non-recoverable state.\n"); + set_bit(__I40E_DOWN_REQUESTED, pf->state); + set_bit(__I40E_VSI_DOWN_REQUESTED, vsi->state); break; } -- cgit v1.2.3 From 415d832497098030241605c52ea83d4e2cfa7879 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Tue, 16 Aug 2022 16:03:11 +0900 Subject: locking/atomic: Make test_and_*_bit() ordered on failure These operations are documented as always ordered in include/asm-generic/bitops/instrumented-atomic.h, and producer-consumer type use cases where one side needs to ensure a flag is left pending after some shared data was updated rely on this ordering, even in the failure case. This is the case with the workqueue code, which currently suffers from a reproducible ordering violation on Apple M1 platforms (which are notoriously out-of-order) that ends up causing the TTY layer to fail to deliver data to userspace properly under the right conditions. This change fixes that bug. Change the documentation to restrict the "no order on failure" story to the _lock() variant (for which it makes sense), and remove the early-exit from the generic implementation, which is what causes the missing barrier semantics in that case. Without this, the remaining atomic op is fully ordered (including on ARM64 LSE, as of recent versions of the architecture spec). Suggested-by: Linus Torvalds Cc: stable@vger.kernel.org Fixes: e986a0d6cb36 ("locking/atomics, asm-generic/bitops/atomic.h: Rewrite using atomic_*() APIs") Fixes: 61e02392d3c7 ("locking/atomic/bitops: Document and clarify ordering semantics for failed test_and_{}_bit()") Signed-off-by: Hector Martin Acked-by: Will Deacon Reviewed-by: Arnd Bergmann Signed-off-by: Linus Torvalds --- Documentation/atomic_bitops.txt | 2 +- include/asm-generic/bitops/atomic.h | 6 ------ 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/Documentation/atomic_bitops.txt b/Documentation/atomic_bitops.txt index 093cdaefdb37..d8b101c97031 100644 --- a/Documentation/atomic_bitops.txt +++ b/Documentation/atomic_bitops.txt @@ -59,7 +59,7 @@ Like with atomic_t, the rule of thumb is: - RMW operations that have a return value are fully ordered. - RMW operations that are conditional are unordered on FAILURE, - otherwise the above rules apply. In the case of test_and_{}_bit() operations, + otherwise the above rules apply. In the case of test_and_set_bit_lock(), if the bit in memory is unchanged by the operation then it is deemed to have failed. diff --git a/include/asm-generic/bitops/atomic.h b/include/asm-generic/bitops/atomic.h index 3096f086b5a3..71ab4ba9c25d 100644 --- a/include/asm-generic/bitops/atomic.h +++ b/include/asm-generic/bitops/atomic.h @@ -39,9 +39,6 @@ arch_test_and_set_bit(unsigned int nr, volatile unsigned long *p) unsigned long mask = BIT_MASK(nr); p += BIT_WORD(nr); - if (READ_ONCE(*p) & mask) - return 1; - old = arch_atomic_long_fetch_or(mask, (atomic_long_t *)p); return !!(old & mask); } @@ -53,9 +50,6 @@ arch_test_and_clear_bit(unsigned int nr, volatile unsigned long *p) unsigned long mask = BIT_MASK(nr); p += BIT_WORD(nr); - if (!(READ_ONCE(*p) & mask)) - return 0; - old = arch_atomic_long_fetch_andnot(mask, (atomic_long_t *)p); return !!(old & mask); } -- cgit v1.2.3 From c4e34dd99f2e3fdfc63584078ce0fed20f4e7386 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Sun, 14 Aug 2022 14:16:13 -0700 Subject: x86: simplify load_unaligned_zeropad() implementation The exception for the "unaligned access at the end of the page, next page not mapped" never happens, but the fixup code ends up causing trouble for compilers to optimize well. clang in particular ends up seeing it being in the middle of a loop, and tries desperately to optimize the exception fixup code that is never really reached. The simple solution is to just move all the fixups into the exception handler itself, which moves it all out of the hot case code, and means that the compiler never sees it or needs to worry about it. Acked-by: Peter Zijlstra Signed-off-by: Linus Torvalds --- arch/x86/include/asm/extable_fixup_types.h | 2 ++ arch/x86/include/asm/word-at-a-time.h | 46 ++----------------------- arch/x86/mm/extable.c | 55 ++++++++++++++++++++++++++++++ 3 files changed, 60 insertions(+), 43 deletions(-) diff --git a/arch/x86/include/asm/extable_fixup_types.h b/arch/x86/include/asm/extable_fixup_types.h index 503622627400..991e31cfde94 100644 --- a/arch/x86/include/asm/extable_fixup_types.h +++ b/arch/x86/include/asm/extable_fixup_types.h @@ -64,4 +64,6 @@ #define EX_TYPE_UCOPY_LEN4 (EX_TYPE_UCOPY_LEN | EX_DATA_IMM(4)) #define EX_TYPE_UCOPY_LEN8 (EX_TYPE_UCOPY_LEN | EX_DATA_IMM(8)) +#define EX_TYPE_ZEROPAD 20 /* longword load with zeropad on fault */ + #endif diff --git a/arch/x86/include/asm/word-at-a-time.h b/arch/x86/include/asm/word-at-a-time.h index 8338b0432b50..46b4f1f7f354 100644 --- a/arch/x86/include/asm/word-at-a-time.h +++ b/arch/x86/include/asm/word-at-a-time.h @@ -77,58 +77,18 @@ static inline unsigned long find_zero(unsigned long mask) * and the next page not being mapped, take the exception and * return zeroes in the non-existing part. */ -#ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT - static inline unsigned long load_unaligned_zeropad(const void *addr) { - unsigned long offset, data; unsigned long ret; - asm_volatile_goto( + asm volatile( "1: mov %[mem], %[ret]\n" - - _ASM_EXTABLE(1b, %l[do_exception]) - - : [ret] "=r" (ret) - : [mem] "m" (*(unsigned long *)addr) - : : do_exception); - - return ret; - -do_exception: - offset = (unsigned long)addr & (sizeof(long) - 1); - addr = (void *)((unsigned long)addr & ~(sizeof(long) - 1)); - data = *(unsigned long *)addr; - ret = data >> offset * 8; - - return ret; -} - -#else /* !CONFIG_CC_HAS_ASM_GOTO_OUTPUT */ - -static inline unsigned long load_unaligned_zeropad(const void *addr) -{ - unsigned long offset, data; - unsigned long ret, err = 0; - - asm( "1: mov %[mem], %[ret]\n" "2:\n" - - _ASM_EXTABLE_FAULT(1b, 2b) - - : [ret] "=&r" (ret), "+a" (err) + _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_ZEROPAD) + : [ret] "=r" (ret) : [mem] "m" (*(unsigned long *)addr)); - if (unlikely(err)) { - offset = (unsigned long)addr & (sizeof(long) - 1); - addr = (void *)((unsigned long)addr & ~(sizeof(long) - 1)); - data = *(unsigned long *)addr; - ret = data >> offset * 8; - } - return ret; } -#endif /* CONFIG_CC_HAS_ASM_GOTO_OUTPUT */ - #endif /* _ASM_WORD_AT_A_TIME_H */ diff --git a/arch/x86/mm/extable.c b/arch/x86/mm/extable.c index 331310c29349..60814e110a54 100644 --- a/arch/x86/mm/extable.c +++ b/arch/x86/mm/extable.c @@ -41,6 +41,59 @@ static bool ex_handler_default(const struct exception_table_entry *e, return true; } +/* + * This is the *very* rare case where we do a "load_unaligned_zeropad()" + * and it's a page crosser into a non-existent page. + * + * This happens when we optimistically load a pathname a word-at-a-time + * and the name is less than the full word and the next page is not + * mapped. Typically that only happens for CONFIG_DEBUG_PAGEALLOC. + * + * NOTE! The faulting address is always a 'mov mem,reg' type instruction + * of size 'long', and the exception fixup must always point to right + * after the instruction. + */ +static bool ex_handler_zeropad(const struct exception_table_entry *e, + struct pt_regs *regs, + unsigned long fault_addr) +{ + struct insn insn; + const unsigned long mask = sizeof(long) - 1; + unsigned long offset, addr, next_ip, len; + unsigned long *reg; + + next_ip = ex_fixup_addr(e); + len = next_ip - regs->ip; + if (len > MAX_INSN_SIZE) + return false; + + if (insn_decode(&insn, (void *) regs->ip, len, INSN_MODE_KERN)) + return false; + if (insn.length != len) + return false; + + if (insn.opcode.bytes[0] != 0x8b) + return false; + if (insn.opnd_bytes != sizeof(long)) + return false; + + addr = (unsigned long) insn_get_addr_ref(&insn, regs); + if (addr == ~0ul) + return false; + + offset = addr & mask; + addr = addr & ~mask; + if (fault_addr != addr + sizeof(long)) + return false; + + reg = insn_get_modrm_reg_ptr(&insn, regs); + if (!reg) + return false; + + *reg = *(unsigned long *)addr >> (offset * 8); + return ex_handler_default(e, regs); +} + static bool ex_handler_fault(const struct exception_table_entry *fixup, struct pt_regs *regs, int trapnr) { @@ -217,6 +270,8 @@ int fixup_exception(struct pt_regs *regs, int trapnr, unsigned long error_code, return ex_handler_sgx(e, regs, trapnr); case EX_TYPE_UCOPY_LEN: return ex_handler_ucopy_len(e, regs, trapnr, reg, imm); + case EX_TYPE_ZEROPAD: + return ex_handler_zeropad(e, regs, fault_addr); } BUG(); } -- cgit v1.2.3 From de64b6b6fb6f369840d171b7c5a9baf31b8b2630 Mon Sep 17 00:00:00 2001 From: Zhengchao Shao Date: Mon, 15 Aug 2022 11:08:48 +0800 Subject: net: sched: fix misuse of qcpu->backlog in gnet_stats_add_queue_cpu In the gnet_stats_add_queue_cpu function, the qstats->qlen statistics are incorrectly set to qcpu->backlog. Fixes: 448e163f8b9b ("gen_stats: Add gnet_stats_add_queue()") Signed-off-by: Zhengchao Shao Link: https://lore.kernel.org/r/20220815030848.276746-1-shaozhengchao@huawei.com Signed-off-by: Jakub Kicinski --- net/core/gen_stats.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/core/gen_stats.c b/net/core/gen_stats.c index a10335b4ba2d..c8d137ef5980 100644 --- a/net/core/gen_stats.c +++ b/net/core/gen_stats.c @@ -345,7 +345,7 @@ static void gnet_stats_add_queue_cpu(struct gnet_stats_queue *qstats, for_each_possible_cpu(i) { const struct gnet_stats_queue *qcpu = per_cpu_ptr(q, i); - qstats->qlen += qcpu->backlog; + qstats->qlen += qcpu->qlen; qstats->backlog += qcpu->backlog; qstats->drops += qcpu->drops; qstats->requeues += qcpu->requeues; -- cgit v1.2.3 From aa5762c34213aba7a72dc58e70601370805fa794 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 15 Aug 2022 12:39:20 +0200 Subject: netfilter: conntrack: NF_CONNTRACK_PROCFS should no longer default to y NF_CONNTRACK_PROCFS was marked obsolete in commit 54b07dca68557b09 ("netfilter: provide config option to disable ancient procfs parts") in v3.3. Signed-off-by: Geert Uytterhoeven Signed-off-by: Florian Westphal --- net/netfilter/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/net/netfilter/Kconfig b/net/netfilter/Kconfig index 22f15ebf6045..4b8d04640ff3 100644 --- a/net/netfilter/Kconfig +++ b/net/netfilter/Kconfig @@ -144,7 +144,6 @@ config NF_CONNTRACK_ZONES config NF_CONNTRACK_PROCFS bool "Supply CT list in procfs (OBSOLETE)" - default y depends on PROC_FS help This option enables for the list of known conntrack entries -- cgit v1.2.3 From b71b7bfeac38c7a21c423ddafb29aa6258949df8 Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Tue, 16 Aug 2022 14:15:21 +0200 Subject: testing: selftests: nft_flowtable.sh: use random netns names "ns1" is a too generic name, use a random suffix to avoid errors when such a netns exists. Also allows to run multiple instances of the script in parallel. Signed-off-by: Florian Westphal --- tools/testing/selftests/netfilter/nft_flowtable.sh | 246 +++++++++++---------- 1 file changed, 128 insertions(+), 118 deletions(-) diff --git a/tools/testing/selftests/netfilter/nft_flowtable.sh b/tools/testing/selftests/netfilter/nft_flowtable.sh index d4ffebb989f8..c336e6c148d1 100755 --- a/tools/testing/selftests/netfilter/nft_flowtable.sh +++ b/tools/testing/selftests/netfilter/nft_flowtable.sh @@ -14,6 +14,11 @@ # nft_flowtable.sh -o8000 -l1500 -r2000 # +sfx=$(mktemp -u "XXXXXXXX") +ns1="ns1-$sfx" +ns2="ns2-$sfx" +nsr1="nsr1-$sfx" +nsr2="nsr2-$sfx" # Kselftest framework requirement - SKIP code is 4. ksft_skip=4 @@ -36,18 +41,17 @@ checktool (){ checktool "nft --version" "run test without nft tool" checktool "ip -Version" "run test without ip tool" checktool "which nc" "run test without nc (netcat)" -checktool "ip netns add nsr1" "create net namespace" +checktool "ip netns add $nsr1" "create net namespace $nsr1" -ip netns add ns1 -ip netns add ns2 - -ip netns add nsr2 +ip netns add $ns1 +ip netns add $ns2 +ip netns add $nsr2 cleanup() { - for i in 1 2; do - ip netns del ns$i - ip netns del nsr$i - done + ip netns del $ns1 + ip netns del $ns2 + ip netns del $nsr1 + ip netns del $nsr2 rm -f "$ns1in" "$ns1out" rm -f "$ns2in" "$ns2out" @@ -59,22 +63,21 @@ trap cleanup EXIT sysctl -q net.netfilter.nf_log_all_netns=1 -ip link add veth0 netns nsr1 type veth peer name eth0 netns ns1 -ip link add veth1 netns nsr1 type veth peer name veth0 netns nsr2 +ip link add veth0 netns $nsr1 type veth peer name eth0 netns $ns1 +ip link add veth1 netns $nsr1 type veth peer name veth0 netns $nsr2 -ip link add veth1 netns nsr2 type veth peer name eth0 netns ns2 +ip link add veth1 netns $nsr2 type veth peer name eth0 netns $ns2 for dev in lo veth0 veth1; do - for i in 1 2; do - ip -net nsr$i link set $dev up - done + ip -net $nsr1 link set $dev up + ip -net $nsr2 link set $dev up done -ip -net nsr1 addr add 10.0.1.1/24 dev veth0 -ip -net nsr1 addr add dead:1::1/64 dev veth0 +ip -net $nsr1 addr add 10.0.1.1/24 dev veth0 +ip -net $nsr1 addr add dead:1::1/64 dev veth0 -ip -net nsr2 addr add 10.0.2.1/24 dev veth1 -ip -net nsr2 addr add dead:2::1/64 dev veth1 +ip -net $nsr2 addr add 10.0.2.1/24 dev veth1 +ip -net $nsr2 addr add dead:2::1/64 dev veth1 # set different MTUs so we need to push packets coming from ns1 (large MTU) # to ns2 (smaller MTU) to stack either to perform fragmentation (ip_no_pmtu_disc=1), @@ -106,49 +109,56 @@ do esac done -if ! ip -net nsr1 link set veth0 mtu $omtu; then +if ! ip -net $nsr1 link set veth0 mtu $omtu; then exit 1 fi -ip -net ns1 link set eth0 mtu $omtu +ip -net $ns1 link set eth0 mtu $omtu -if ! ip -net nsr2 link set veth1 mtu $rmtu; then +if ! ip -net $nsr2 link set veth1 mtu $rmtu; then exit 1 fi -ip -net ns2 link set eth0 mtu $rmtu +ip -net $ns2 link set eth0 mtu $rmtu # transfer-net between nsr1 and nsr2. # these addresses are not used for connections. -ip -net nsr1 addr add 192.168.10.1/24 dev veth1 -ip -net nsr1 addr add fee1:2::1/64 dev veth1 - -ip -net nsr2 addr add 192.168.10.2/24 dev veth0 -ip -net nsr2 addr add fee1:2::2/64 dev veth0 - -for i in 1 2; do - ip netns exec nsr$i sysctl net.ipv4.conf.veth0.forwarding=1 > /dev/null - ip netns exec nsr$i sysctl net.ipv4.conf.veth1.forwarding=1 > /dev/null - - ip -net ns$i link set lo up - ip -net ns$i link set eth0 up - ip -net ns$i addr add 10.0.$i.99/24 dev eth0 - ip -net ns$i route add default via 10.0.$i.1 - ip -net ns$i addr add dead:$i::99/64 dev eth0 - ip -net ns$i route add default via dead:$i::1 - if ! ip netns exec ns$i sysctl net.ipv4.tcp_no_metrics_save=1 > /dev/null; then +ip -net $nsr1 addr add 192.168.10.1/24 dev veth1 +ip -net $nsr1 addr add fee1:2::1/64 dev veth1 + +ip -net $nsr2 addr add 192.168.10.2/24 dev veth0 +ip -net $nsr2 addr add fee1:2::2/64 dev veth0 + +for i in 0 1; do + ip netns exec $nsr1 sysctl net.ipv4.conf.veth$i.forwarding=1 > /dev/null + ip netns exec $nsr2 sysctl net.ipv4.conf.veth$i.forwarding=1 > /dev/null +done + +for ns in $ns1 $ns2;do + ip -net $ns link set lo up + ip -net $ns link set eth0 up + + if ! ip netns exec $ns sysctl net.ipv4.tcp_no_metrics_save=1 > /dev/null; then echo "ERROR: Check Originator/Responder values (problem during address addition)" exit 1 fi - # don't set ip DF bit for first two tests - ip netns exec ns$i sysctl net.ipv4.ip_no_pmtu_disc=1 > /dev/null + ip netns exec $ns sysctl net.ipv4.ip_no_pmtu_disc=1 > /dev/null done -ip -net nsr1 route add default via 192.168.10.2 -ip -net nsr2 route add default via 192.168.10.1 +ip -net $ns1 addr add 10.0.1.99/24 dev eth0 +ip -net $ns2 addr add 10.0.2.99/24 dev eth0 +ip -net $ns1 route add default via 10.0.1.1 +ip -net $ns2 route add default via 10.0.2.1 +ip -net $ns1 addr add dead:1::99/64 dev eth0 +ip -net $ns2 addr add dead:2::99/64 dev eth0 +ip -net $ns1 route add default via dead:1::1 +ip -net $ns2 route add default via dead:2::1 + +ip -net $nsr1 route add default via 192.168.10.2 +ip -net $nsr2 route add default via 192.168.10.1 -ip netns exec nsr1 nft -f - < /dev/null; then - echo "ERROR: ns1 cannot reach ns2" 1>&2 +if ! ip netns exec $ns1 ping -c 1 -q 10.0.2.99 > /dev/null; then + echo "ERROR: $ns1 cannot reach ns2" 1>&2 exit 1 fi -if ! ip netns exec ns2 ping -c 1 -q 10.0.1.99 > /dev/null; then - echo "ERROR: ns2 cannot reach ns1" 1>&2 +if ! ip netns exec $ns2 ping -c 1 -q 10.0.1.99 > /dev/null; then + echo "ERROR: $ns2 cannot reach $ns1" 1>&2 exit 1 fi if [ $ret -eq 0 ];then - echo "PASS: netns routing/connectivity: ns1 can reach ns2" + echo "PASS: netns routing/connectivity: $ns1 can reach $ns2" fi ns1in=$(mktemp) @@ -312,24 +322,24 @@ make_file "$ns2in" # First test: # No PMTU discovery, nsr1 is expected to fragment packets from ns1 to ns2 as needed. -if test_tcp_forwarding ns1 ns2; then +if test_tcp_forwarding $ns1 $ns2; then echo "PASS: flow offloaded for ns1/ns2" else echo "FAIL: flow offload for ns1/ns2:" 1>&2 - ip netns exec nsr1 nft list ruleset + ip netns exec $nsr1 nft list ruleset ret=1 fi # delete default route, i.e. ns2 won't be able to reach ns1 and # will depend on ns1 being masqueraded in nsr1. # expect ns1 has nsr1 address. -ip -net ns2 route del default via 10.0.2.1 -ip -net ns2 route del default via dead:2::1 -ip -net ns2 route add 192.168.10.1 via 10.0.2.1 +ip -net $ns2 route del default via 10.0.2.1 +ip -net $ns2 route del default via dead:2::1 +ip -net $ns2 route add 192.168.10.1 via 10.0.2.1 # Second test: # Same, but with NAT enabled. -ip netns exec nsr1 nft -f - <&2 - ip netns exec nsr1 nft list ruleset + ip netns exec $nsr1 nft list ruleset ret=1 fi # Third test: # Same as second test, but with PMTU discovery enabled. -handle=$(ip netns exec nsr1 nft -a list table inet filter | grep something-to-grep-for | cut -d \# -f 2) +handle=$(ip netns exec $nsr1 nft -a list table inet filter | grep something-to-grep-for | cut -d \# -f 2) -if ! ip netns exec nsr1 nft delete rule inet filter forward $handle; then +if ! ip netns exec $nsr1 nft delete rule inet filter forward $handle; then echo "FAIL: Could not delete large-packet accept rule" exit 1 fi -ip netns exec ns1 sysctl net.ipv4.ip_no_pmtu_disc=0 > /dev/null -ip netns exec ns2 sysctl net.ipv4.ip_no_pmtu_disc=0 > /dev/null +ip netns exec $ns1 sysctl net.ipv4.ip_no_pmtu_disc=0 > /dev/null +ip netns exec $ns2 sysctl net.ipv4.ip_no_pmtu_disc=0 > /dev/null -if test_tcp_forwarding_nat ns1 ns2; then +if test_tcp_forwarding_nat $ns1 $ns2; then echo "PASS: flow offloaded for ns1/ns2 with NAT and pmtu discovery" else echo "FAIL: flow offload for ns1/ns2 with NAT and pmtu discovery" 1>&2 - ip netns exec nsr1 nft list ruleset + ip netns exec $nsr1 nft list ruleset fi # Another test: # Add bridge interface br0 to Router1, with NAT enabled. -ip -net nsr1 link add name br0 type bridge -ip -net nsr1 addr flush dev veth0 -ip -net nsr1 link set up dev veth0 -ip -net nsr1 link set veth0 master br0 -ip -net nsr1 addr add 10.0.1.1/24 dev br0 -ip -net nsr1 addr add dead:1::1/64 dev br0 -ip -net nsr1 link set up dev br0 +ip -net $nsr1 link add name br0 type bridge +ip -net $nsr1 addr flush dev veth0 +ip -net $nsr1 link set up dev veth0 +ip -net $nsr1 link set veth0 master br0 +ip -net $nsr1 addr add 10.0.1.1/24 dev br0 +ip -net $nsr1 addr add dead:1::1/64 dev br0 +ip -net $nsr1 link set up dev br0 -ip netns exec nsr1 sysctl net.ipv4.conf.br0.forwarding=1 > /dev/null +ip netns exec $nsr1 sysctl net.ipv4.conf.br0.forwarding=1 > /dev/null # br0 with NAT enabled. -ip netns exec nsr1 nft -f - <&2 - ip netns exec nsr1 nft list ruleset + ip netns exec $nsr1 nft list ruleset ret=1 fi # Another test: # Add bridge interface br0 to Router1, with NAT and VLAN. -ip -net nsr1 link set veth0 nomaster -ip -net nsr1 link set down dev veth0 -ip -net nsr1 link add link veth0 name veth0.10 type vlan id 10 -ip -net nsr1 link set up dev veth0 -ip -net nsr1 link set up dev veth0.10 -ip -net nsr1 link set veth0.10 master br0 - -ip -net ns1 addr flush dev eth0 -ip -net ns1 link add link eth0 name eth0.10 type vlan id 10 -ip -net ns1 link set eth0 up -ip -net ns1 link set eth0.10 up -ip -net ns1 addr add 10.0.1.99/24 dev eth0.10 -ip -net ns1 route add default via 10.0.1.1 -ip -net ns1 addr add dead:1::99/64 dev eth0.10 - -if test_tcp_forwarding_nat ns1 ns2; then +ip -net $nsr1 link set veth0 nomaster +ip -net $nsr1 link set down dev veth0 +ip -net $nsr1 link add link veth0 name veth0.10 type vlan id 10 +ip -net $nsr1 link set up dev veth0 +ip -net $nsr1 link set up dev veth0.10 +ip -net $nsr1 link set veth0.10 master br0 + +ip -net $ns1 addr flush dev eth0 +ip -net $ns1 link add link eth0 name eth0.10 type vlan id 10 +ip -net $ns1 link set eth0 up +ip -net $ns1 link set eth0.10 up +ip -net $ns1 addr add 10.0.1.99/24 dev eth0.10 +ip -net $ns1 route add default via 10.0.1.1 +ip -net $ns1 addr add dead:1::99/64 dev eth0.10 + +if test_tcp_forwarding_nat $ns1 $ns2; then echo "PASS: flow offloaded for ns1/ns2 with bridge NAT and VLAN" else echo "FAIL: flow offload for ns1/ns2 with bridge NAT and VLAN" 1>&2 - ip netns exec nsr1 nft list ruleset + ip netns exec $nsr1 nft list ruleset ret=1 fi # restore test topology (remove bridge and VLAN) -ip -net nsr1 link set veth0 nomaster -ip -net nsr1 link set veth0 down -ip -net nsr1 link set veth0.10 down -ip -net nsr1 link delete veth0.10 type vlan -ip -net nsr1 link delete br0 type bridge -ip -net ns1 addr flush dev eth0.10 -ip -net ns1 link set eth0.10 down -ip -net ns1 link set eth0 down -ip -net ns1 link delete eth0.10 type vlan +ip -net $nsr1 link set veth0 nomaster +ip -net $nsr1 link set veth0 down +ip -net $nsr1 link set veth0.10 down +ip -net $nsr1 link delete veth0.10 type vlan +ip -net $nsr1 link delete br0 type bridge +ip -net $ns1 addr flush dev eth0.10 +ip -net $ns1 link set eth0.10 down +ip -net $ns1 link set eth0 down +ip -net $ns1 link delete eth0.10 type vlan # restore address in ns1 and nsr1 -ip -net ns1 link set eth0 up -ip -net ns1 addr add 10.0.1.99/24 dev eth0 -ip -net ns1 route add default via 10.0.1.1 -ip -net ns1 addr add dead:1::99/64 dev eth0 -ip -net ns1 route add default via dead:1::1 -ip -net nsr1 addr add 10.0.1.1/24 dev veth0 -ip -net nsr1 addr add dead:1::1/64 dev veth0 -ip -net nsr1 link set up dev veth0 +ip -net $ns1 link set eth0 up +ip -net $ns1 addr add 10.0.1.99/24 dev eth0 +ip -net $ns1 route add default via 10.0.1.1 +ip -net $ns1 addr add dead:1::99/64 dev eth0 +ip -net $ns1 route add default via dead:1::1 +ip -net $nsr1 addr add 10.0.1.1/24 dev veth0 +ip -net $nsr1 addr add dead:1::1/64 dev veth0 +ip -net $nsr1 link set up dev veth0 KEY_SHA="0x"$(ps -xaf | sha1sum | cut -d " " -f 1) KEY_AES="0x"$(ps -xaf | md5sum | cut -d " " -f 1) @@ -480,23 +490,23 @@ do_esp() { } -do_esp nsr1 192.168.10.1 192.168.10.2 10.0.1.0/24 10.0.2.0/24 $SPI1 $SPI2 +do_esp $nsr1 192.168.10.1 192.168.10.2 10.0.1.0/24 10.0.2.0/24 $SPI1 $SPI2 -do_esp nsr2 192.168.10.2 192.168.10.1 10.0.2.0/24 10.0.1.0/24 $SPI2 $SPI1 +do_esp $nsr2 192.168.10.2 192.168.10.1 10.0.2.0/24 10.0.1.0/24 $SPI2 $SPI1 -ip netns exec nsr1 nft delete table ip nat +ip netns exec $nsr1 nft delete table ip nat # restore default routes -ip -net ns2 route del 192.168.10.1 via 10.0.2.1 -ip -net ns2 route add default via 10.0.2.1 -ip -net ns2 route add default via dead:2::1 +ip -net $ns2 route del 192.168.10.1 via 10.0.2.1 +ip -net $ns2 route add default via 10.0.2.1 +ip -net $ns2 route add default via dead:2::1 -if test_tcp_forwarding ns1 ns2; then +if test_tcp_forwarding $ns1 $ns2; then echo "PASS: ipsec tunnel mode for ns1/ns2" else echo "FAIL: ipsec tunnel mode for ns1/ns2" - ip netns exec nsr1 nft list ruleset 1>&2 - ip netns exec nsr1 cat /proc/net/xfrm_stat 1>&2 + ip netns exec $nsr1 nft list ruleset 1>&2 + ip netns exec $nsr1 cat /proc/net/xfrm_stat 1>&2 fi exit $ret -- cgit v1.2.3 From 849f16bbfb686cf75e67c536d196027fa8bfc803 Mon Sep 17 00:00:00 2001 From: Jakub Kicinski Date: Mon, 15 Aug 2022 17:23:58 -0700 Subject: tls: rx: react to strparser initialization errors Even though the normal strparser's init function has a return value we got away with ignoring errors until now, as it only validates the parameters and we were passing correct parameters. tls_strp can fail to init on memory allocation errors, which syzbot duly induced and reported. Reported-by: syzbot+abd45eb849b05194b1b6@syzkaller.appspotmail.com Fixes: 84c61fe1a75b ("tls: rx: do not use the standard strparser") Signed-off-by: Jakub Kicinski Signed-off-by: David S. Miller --- net/tls/tls_sw.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/net/tls/tls_sw.c b/net/tls/tls_sw.c index f76119f62f1b..fe27241cd13f 100644 --- a/net/tls/tls_sw.c +++ b/net/tls/tls_sw.c @@ -2702,7 +2702,9 @@ int tls_set_sw_offload(struct sock *sk, struct tls_context *ctx, int tx) crypto_info->version != TLS_1_3_VERSION && !!(tfm->__crt_alg->cra_flags & CRYPTO_ALG_ASYNC); - tls_strp_init(&sw_ctx_rx->strp, sk); + rc = tls_strp_init(&sw_ctx_rx->strp, sk); + if (rc) + goto free_aead; } goto out; -- cgit v1.2.3 From c8550b9077d271b9b4fbe5a9a260eb021f371c4f Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Tue, 16 Aug 2022 14:15:22 +0200 Subject: testing: selftests: nft_flowtable.sh: rework test to detect offload failure This test fails on current kernel releases because the flotwable path now calls dst_check from packet path and will then remove the offload. Test script has two purposes: 1. check that file (random content) can be sent to other netns (and vv) 2. check that the flow is offloaded (rather than handled by classic forwarding path). Since dst_check is in place, 2) fails because the nftables ruleset in router namespace 1 intentionally blocks traffic under the assumption that packets are not passed via classic path at all. Rework this: Instead of blocking traffic, create two named counters, one for original and one for reverse direction. The first three test cases are handled by classic forwarding path (path mtu discovery is disabled and packets exceed MTU). But all other tests enable PMTUD, so the originator and responder are expected to lower packet size and flowtable is expected to do the packet forwarding. For those tests, check that the packet counters (which are only incremented for packets that are passed up to classic forward path) are significantly lower than the file size transferred. I've tested that the counter-checks fail as expected when the 'flow add' statement is removed from the ruleset. Signed-off-by: Florian Westphal --- tools/testing/selftests/netfilter/nft_flowtable.sh | 141 ++++++++++++--------- 1 file changed, 84 insertions(+), 57 deletions(-) diff --git a/tools/testing/selftests/netfilter/nft_flowtable.sh b/tools/testing/selftests/netfilter/nft_flowtable.sh index c336e6c148d1..7060bae04ec8 100755 --- a/tools/testing/selftests/netfilter/nft_flowtable.sh +++ b/tools/testing/selftests/netfilter/nft_flowtable.sh @@ -24,8 +24,7 @@ nsr2="nsr2-$sfx" ksft_skip=4 ret=0 -ns1in="" -ns2in="" +nsin="" ns1out="" ns2out="" @@ -53,8 +52,7 @@ cleanup() { ip netns del $nsr1 ip netns del $nsr2 - rm -f "$ns1in" "$ns1out" - rm -f "$ns2in" "$ns2out" + rm -f "$nsin" "$ns1out" "$ns2out" [ $log_netns -eq 0 ] && sysctl -q net.netfilter.nf_log_all_netns=$log_netns } @@ -165,36 +163,20 @@ table inet filter { devices = { veth0, veth1 } } + counter routed_orig { } + counter routed_repl { } + chain forward { type filter hook forward priority 0; policy drop; # flow offloaded? Tag ct with mark 1, so we can detect when it fails. - meta oif "veth1" tcp dport 12345 flow offload @f1 counter - - # use packet size to trigger 'should be offloaded by now'. - # otherwise, if 'flow offload' expression never offloads, the - # test will pass. - tcp dport 12345 meta length gt 200 ct mark set 1 counter - - # this turns off flow offloading internally, so expect packets again - tcp flags fin,rst ct mark set 0 accept - - # this allows large packets from responder, we need this as long - # as PMTUd is off. - # This rule is deleted for the last test, when we expect PMTUd - # to kick in and ensure all packets meet mtu requirements. - meta length gt $lmtu accept comment something-to-grep-for + meta oif "veth1" tcp dport 12345 ct mark set 1 flow add @f1 counter name routed_orig accept - # next line blocks connection w.o. working offload. - # we only do this for reverse dir, because we expect packets to - # enter slow path due to MTU mismatch of veth0 and veth1. - tcp sport 12345 ct mark 1 counter log prefix "mark failure " drop + # count packets supposedly offloaded as per direction. + ct mark 1 counter name ct direction map { original : routed_orig, reply : routed_repl } accept ct state established,related accept - # for packets that we can't offload yet, i.e. SYN (any ct that is not confirmed) - meta length lt 200 oif "veth1" tcp dport 12345 counter accept - meta nfproto ipv4 meta l4proto icmp accept meta nfproto ipv6 meta l4proto icmpv6 accept } @@ -221,16 +203,16 @@ if [ $ret -eq 0 ];then echo "PASS: netns routing/connectivity: $ns1 can reach $ns2" fi -ns1in=$(mktemp) +nsin=$(mktemp) ns1out=$(mktemp) -ns2in=$(mktemp) ns2out=$(mktemp) make_file() { name=$1 - SIZE=$((RANDOM % (1024 * 8))) + SIZE=$((RANDOM % (1024 * 128))) + SIZE=$((SIZE + (1024 * 8))) TSIZE=$((SIZE * 1024)) dd if=/dev/urandom of="$name" bs=1024 count=$SIZE 2> /dev/null @@ -241,6 +223,38 @@ make_file() dd if=/dev/urandom conf=notrunc of="$name" bs=1 count=$SIZE 2> /dev/null } +check_counters() +{ + local what=$1 + local ok=1 + + local orig=$(ip netns exec $nsr1 nft reset counter inet filter routed_orig | grep packets) + local repl=$(ip netns exec $nsr1 nft reset counter inet filter routed_repl | grep packets) + + local orig_cnt=${orig#*bytes} + local repl_cnt=${repl#*bytes} + + local fs=$(du -sb $nsin) + local max_orig=${fs%%/*} + local max_repl=$((max_orig/4)) + + if [ $orig_cnt -gt $max_orig ];then + echo "FAIL: $what: original counter $orig_cnt exceeds expected value $max_orig" 1>&2 + ret=1 + ok=0 + fi + + if [ $repl_cnt -gt $max_repl ];then + echo "FAIL: $what: reply counter $repl_cnt exceeds expected value $max_repl" 1>&2 + ret=1 + ok=0 + fi + + if [ $ok -eq 1 ]; then + echo "PASS: $what" + fi +} + check_transfer() { in=$1 @@ -265,11 +279,11 @@ test_tcp_forwarding_ip() local dstport=$4 local lret=0 - ip netns exec $nsb nc -w 5 -l -p 12345 < "$ns2in" > "$ns2out" & + ip netns exec $nsb nc -w 5 -l -p 12345 < "$nsin" > "$ns2out" & lpid=$! sleep 1 - ip netns exec $nsa nc -w 4 "$dstip" "$dstport" < "$ns1in" > "$ns1out" & + ip netns exec $nsa nc -w 4 "$dstip" "$dstport" < "$nsin" > "$ns1out" & cpid=$! sleep 3 @@ -284,11 +298,11 @@ test_tcp_forwarding_ip() wait - if ! check_transfer "$ns1in" "$ns2out" "ns1 -> ns2"; then + if ! check_transfer "$nsin" "$ns2out" "ns1 -> ns2"; then lret=1 fi - if ! check_transfer "$ns2in" "$ns1out" "ns1 <- ns2"; then + if ! check_transfer "$nsin" "$ns1out" "ns1 <- ns2"; then lret=1 fi @@ -305,23 +319,40 @@ test_tcp_forwarding() test_tcp_forwarding_nat() { local lret + local pmtu test_tcp_forwarding_ip "$1" "$2" 10.0.2.99 12345 lret=$? + pmtu=$3 + what=$4 + if [ $lret -eq 0 ] ; then + if [ $pmtu -eq 1 ] ;then + check_counters "flow offload for ns1/ns2 with masquerade and pmtu discovery $what" + else + echo "PASS: flow offload for ns1/ns2 with masquerade $what" + fi + test_tcp_forwarding_ip "$1" "$2" 10.6.6.6 1666 lret=$? + if [ $pmtu -eq 1 ] ;then + check_counters "flow offload for ns1/ns2 with dnat and pmtu discovery $what" + elif [ $lret -eq 0 ] ; then + echo "PASS: flow offload for ns1/ns2 with dnat $what" + fi fi return $lret } -make_file "$ns1in" -make_file "$ns2in" +make_file "$nsin" # First test: # No PMTU discovery, nsr1 is expected to fragment packets from ns1 to ns2 as needed. +# Due to MTU mismatch in both directions, all packets (except small packets like pure +# acks) have to be handled by normal forwarding path. Therefore, packet counters +# are not checked. if test_tcp_forwarding $ns1 $ns2; then echo "PASS: flow offloaded for ns1/ns2" else @@ -338,7 +369,8 @@ ip -net $ns2 route del default via dead:2::1 ip -net $ns2 route add 192.168.10.1 via 10.0.2.1 # Second test: -# Same, but with NAT enabled. +# Same, but with NAT enabled. Same as in first test: we expect normal forward path +# to handle most packets. ip netns exec $nsr1 nft -f - <&2 ip netns exec $nsr1 nft list ruleset ret=1 fi # Third test: -# Same as second test, but with PMTU discovery enabled. -handle=$(ip netns exec $nsr1 nft -a list table inet filter | grep something-to-grep-for | cut -d \# -f 2) - -if ! ip netns exec $nsr1 nft delete rule inet filter forward $handle; then - echo "FAIL: Could not delete large-packet accept rule" - exit 1 -fi - +# Same as second test, but with PMTU discovery enabled. This +# means that we expect the fastpath to handle packets as soon +# as the endpoints adjust the packet size. ip netns exec $ns1 sysctl net.ipv4.ip_no_pmtu_disc=0 > /dev/null ip netns exec $ns2 sysctl net.ipv4.ip_no_pmtu_disc=0 > /dev/null -if test_tcp_forwarding_nat $ns1 $ns2; then - echo "PASS: flow offloaded for ns1/ns2 with NAT and pmtu discovery" -else +# reset counters. +# With pmtu in-place we'll also check that nft counters +# are lower than file size and packets were forwarded via flowtable layer. +# For earlier tests (large mtus), packets cannot be handled via flowtable +# (except pure acks and other small packets). +ip netns exec $nsr1 nft reset counters table inet filter >/dev/null + +if ! test_tcp_forwarding_nat $ns1 $ns2 1 ""; then echo "FAIL: flow offload for ns1/ns2 with NAT and pmtu discovery" 1>&2 ip netns exec $nsr1 nft list ruleset fi @@ -408,14 +438,13 @@ table ip nat { } EOF -if test_tcp_forwarding_nat $ns1 $ns2; then - echo "PASS: flow offloaded for ns1/ns2 with bridge NAT" -else +if ! test_tcp_forwarding_nat $ns1 $ns2 1 "on bridge"; then echo "FAIL: flow offload for ns1/ns2 with bridge NAT" 1>&2 ip netns exec $nsr1 nft list ruleset ret=1 fi + # Another test: # Add bridge interface br0 to Router1, with NAT and VLAN. ip -net $nsr1 link set veth0 nomaster @@ -433,9 +462,7 @@ ip -net $ns1 addr add 10.0.1.99/24 dev eth0.10 ip -net $ns1 route add default via 10.0.1.1 ip -net $ns1 addr add dead:1::99/64 dev eth0.10 -if test_tcp_forwarding_nat $ns1 $ns2; then - echo "PASS: flow offloaded for ns1/ns2 with bridge NAT and VLAN" -else +if ! test_tcp_forwarding_nat $ns1 $ns2 1 "bridge and VLAN"; then echo "FAIL: flow offload for ns1/ns2 with bridge NAT and VLAN" 1>&2 ip netns exec $nsr1 nft list ruleset ret=1 @@ -502,7 +529,7 @@ ip -net $ns2 route add default via 10.0.2.1 ip -net $ns2 route add default via dead:2::1 if test_tcp_forwarding $ns1 $ns2; then - echo "PASS: ipsec tunnel mode for ns1/ns2" + check_counters "ipsec tunnel mode for ns1/ns2" else echo "FAIL: ipsec tunnel mode for ns1/ns2" ip netns exec $nsr1 nft list ruleset 1>&2 -- cgit v1.2.3 From ffa9ed86522f1c08d4face4e0a4ebf366037bf19 Mon Sep 17 00:00:00 2001 From: Grzegorz Siwik Date: Fri, 12 Aug 2022 15:25:47 +0200 Subject: ice: Fix double VLAN error when entering promisc mode Avoid enabling or disabling VLAN 0 when trying to set promiscuous VLAN mode if double VLAN mode is enabled. This fix is needed because the driver tries to add the VLAN 0 filter twice (once for inner and once for outer) when double VLAN mode is enabled. The filter program is rejected by the firmware when double VLAN is enabled, because the promiscuous filter only needs to be set once. This issue was missed in the initial implementation of double VLAN mode. Fixes: 5eda8afd6bcc ("ice: Add support for PF/VF promiscuous mode") Signed-off-by: Grzegorz Siwik Link: https://lore.kernel.org/all/CAK8fFZ7m-KR57M_rYX6xZN39K89O=LGooYkKsu6HKt0Bs+x6xQ@mail.gmail.com/ Tested-by: Jaroslav Pulchart Tested-by: Igor Raits Tested-by: Gurucharan (A Contingent worker at Intel) Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/ice/ice_switch.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/ethernet/intel/ice/ice_switch.c b/drivers/net/ethernet/intel/ice/ice_switch.c index 262e553e3b58..0c265739cce2 100644 --- a/drivers/net/ethernet/intel/ice/ice_switch.c +++ b/drivers/net/ethernet/intel/ice/ice_switch.c @@ -4445,6 +4445,13 @@ ice_set_vlan_vsi_promisc(struct ice_hw *hw, u16 vsi_handle, u8 promisc_mask, goto free_fltr_list; list_for_each_entry(list_itr, &vsi_list_head, list_entry) { + /* Avoid enabling or disabling VLAN zero twice when in double + * VLAN mode + */ + if (ice_is_dvm_ena(hw) && + list_itr->fltr_info.l_data.vlan.tpid == 0) + continue; + vlan_id = list_itr->fltr_info.l_data.vlan.vlan_id; if (rm_vlan_promisc) status = ice_clear_vsi_promisc(hw, vsi_handle, -- cgit v1.2.3 From 11e551a2efa4481bd4f616ab75374a2710b480e9 Mon Sep 17 00:00:00 2001 From: Grzegorz Siwik Date: Fri, 12 Aug 2022 15:25:48 +0200 Subject: ice: Ignore EEXIST when setting promisc mode Ignore EEXIST error when setting promiscuous mode. This fix is needed because the driver could set promiscuous mode when it still has not cleared properly. Promiscuous mode could be set only once, so setting it second time will be rejected. Fixes: 5eda8afd6bcc ("ice: Add support for PF/VF promiscuous mode") Signed-off-by: Grzegorz Siwik Link: https://lore.kernel.org/all/CAK8fFZ7m-KR57M_rYX6xZN39K89O=LGooYkKsu6HKt0Bs+x6xQ@mail.gmail.com/ Tested-by: Jaroslav Pulchart Tested-by: Igor Raits Tested-by: Gurucharan (A Contingent worker at Intel) Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/ice/ice_switch.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/ice/ice_switch.c b/drivers/net/ethernet/intel/ice/ice_switch.c index 0c265739cce2..3808034f7e7e 100644 --- a/drivers/net/ethernet/intel/ice/ice_switch.c +++ b/drivers/net/ethernet/intel/ice/ice_switch.c @@ -4459,7 +4459,7 @@ ice_set_vlan_vsi_promisc(struct ice_hw *hw, u16 vsi_handle, u8 promisc_mask, else status = ice_set_vsi_promisc(hw, vsi_handle, promisc_mask, vlan_id); - if (status) + if (status && status != -EEXIST) break; } -- cgit v1.2.3 From abddafd4585cc825d454da3cf308ad1226f6c554 Mon Sep 17 00:00:00 2001 From: Grzegorz Siwik Date: Fri, 12 Aug 2022 15:25:49 +0200 Subject: ice: Fix clearing of promisc mode with bridge over bond When at least two interfaces are bonded and a bridge is enabled on the bond, an error can occur when the bridge is removed and re-added. The reason for the error is because promiscuous mode was not fully cleared from the VLAN VSI in the hardware. With this change, promiscuous mode is properly removed when the bridge disconnects from bonding. [ 1033.676359] bond1: link status definitely down for interface enp95s0f0, disabling it [ 1033.676366] bond1: making interface enp175s0f0 the new active one [ 1033.676369] device enp95s0f0 left promiscuous mode [ 1033.676522] device enp175s0f0 entered promiscuous mode [ 1033.676901] ice 0000:af:00.0 enp175s0f0: Error setting Multicast promiscuous mode on VSI 6 [ 1041.795662] ice 0000:af:00.0 enp175s0f0: Error setting Multicast promiscuous mode on VSI 6 [ 1041.944826] bond1: link status definitely down for interface enp175s0f0, disabling it [ 1041.944874] device enp175s0f0 left promiscuous mode [ 1041.944918] bond1: now running without any active interface! Fixes: c31af68a1b94 ("ice: Add outer_vlan_ops and VSI specific VLAN ops implementations") Co-developed-by: Jesse Brandeburg Signed-off-by: Jesse Brandeburg Signed-off-by: Grzegorz Siwik Link: https://lore.kernel.org/all/CAK8fFZ7m-KR57M_rYX6xZN39K89O=LGooYkKsu6HKt0Bs+x6xQ@mail.gmail.com/ Tested-by: Jaroslav Pulchart Tested-by: Igor Raits Tested-by: Gurucharan (A Contingent worker at Intel) Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/ice/ice_lib.c | 6 +++++- drivers/net/ethernet/intel/ice/ice_main.c | 12 +++++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_lib.c b/drivers/net/ethernet/intel/ice/ice_lib.c index 0d4dbca88964..733c455f6574 100644 --- a/drivers/net/ethernet/intel/ice/ice_lib.c +++ b/drivers/net/ethernet/intel/ice/ice_lib.c @@ -4062,7 +4062,11 @@ int ice_vsi_del_vlan_zero(struct ice_vsi *vsi) if (err && err != -EEXIST) return err; - return 0; + /* when deleting the last VLAN filter, make sure to disable the VLAN + * promisc mode so the filter isn't left by accident + */ + return ice_clear_vsi_promisc(&vsi->back->hw, vsi->idx, + ICE_MCAST_VLAN_PROMISC_BITS, 0); } /** diff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c index eb40526ee179..4ecaf40cf946 100644 --- a/drivers/net/ethernet/intel/ice/ice_main.c +++ b/drivers/net/ethernet/intel/ice/ice_main.c @@ -267,8 +267,10 @@ static int ice_set_promisc(struct ice_vsi *vsi, u8 promisc_m) status = ice_fltr_set_vsi_promisc(&vsi->back->hw, vsi->idx, promisc_m, 0); } + if (status && status != -EEXIST) + return status; - return status; + return 0; } /** @@ -3573,6 +3575,14 @@ ice_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid) while (test_and_set_bit(ICE_CFG_BUSY, vsi->state)) usleep_range(1000, 2000); + ret = ice_clear_vsi_promisc(&vsi->back->hw, vsi->idx, + ICE_MCAST_VLAN_PROMISC_BITS, vid); + if (ret) { + netdev_err(netdev, "Error clearing multicast promiscuous mode on VSI %i\n", + vsi->vsi_num); + vsi->current_netdev_flags |= IFF_ALLMULTI; + } + vlan_ops = ice_get_compat_vsi_vlan_ops(vsi); /* Make sure VLAN delete is successful before updating VLAN -- cgit v1.2.3 From 79956b83ed4281c35561c39254558092d96a9ed1 Mon Sep 17 00:00:00 2001 From: Benjamin Mikailenko Date: Fri, 12 Aug 2022 15:25:50 +0200 Subject: ice: Ignore error message when setting same promiscuous mode Commit 1273f89578f2 ("ice: Fix broken IFF_ALLMULTI handling") introduced new checks when setting/clearing promiscuous mode. But if the requested promiscuous mode setting already exists, an -EEXIST error message would be printed. This is incorrect because promiscuous mode is either on/off and shouldn't print an error when the requested configuration is already set. This can happen when removing a bridge with two bonded interfaces and promiscuous most isn't fully cleared from VLAN VSI in hardware. Fix this by ignoring cases where requested promiscuous mode exists. Fixes: 1273f89578f2 ("ice: Fix broken IFF_ALLMULTI handling") Signed-off-by: Benjamin Mikailenko Signed-off-by: Grzegorz Siwik Link: https://lore.kernel.org/all/CAK8fFZ7m-KR57M_rYX6xZN39K89O=LGooYkKsu6HKt0Bs+x6xQ@mail.gmail.com/ Tested-by: Gurucharan (A Contingent worker at Intel) Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/ice/ice_fltr.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_fltr.c b/drivers/net/ethernet/intel/ice/ice_fltr.c index 85a94483c2ed..40e678cfb507 100644 --- a/drivers/net/ethernet/intel/ice/ice_fltr.c +++ b/drivers/net/ethernet/intel/ice/ice_fltr.c @@ -62,7 +62,7 @@ ice_fltr_set_vlan_vsi_promisc(struct ice_hw *hw, struct ice_vsi *vsi, int result; result = ice_set_vlan_vsi_promisc(hw, vsi->idx, promisc_mask, false); - if (result) + if (result && result != -EEXIST) dev_err(ice_pf_to_dev(pf), "Error setting promisc mode on VSI %i (rc=%d)\n", vsi->vsi_num, result); @@ -86,7 +86,7 @@ ice_fltr_clear_vlan_vsi_promisc(struct ice_hw *hw, struct ice_vsi *vsi, int result; result = ice_set_vlan_vsi_promisc(hw, vsi->idx, promisc_mask, true); - if (result) + if (result && result != -EEXIST) dev_err(ice_pf_to_dev(pf), "Error clearing promisc mode on VSI %i (rc=%d)\n", vsi->vsi_num, result); @@ -109,7 +109,7 @@ ice_fltr_clear_vsi_promisc(struct ice_hw *hw, u16 vsi_handle, u8 promisc_mask, int result; result = ice_clear_vsi_promisc(hw, vsi_handle, promisc_mask, vid); - if (result) + if (result && result != -EEXIST) dev_err(ice_pf_to_dev(pf), "Error clearing promisc mode on VSI %i for VID %u (rc=%d)\n", ice_get_hw_vsi_num(hw, vsi_handle), vid, result); @@ -132,7 +132,7 @@ ice_fltr_set_vsi_promisc(struct ice_hw *hw, u16 vsi_handle, u8 promisc_mask, int result; result = ice_set_vsi_promisc(hw, vsi_handle, promisc_mask, vid); - if (result) + if (result && result != -EEXIST) dev_err(ice_pf_to_dev(pf), "Error setting promisc mode on VSI %i for VID %u (rc=%d)\n", ice_get_hw_vsi_num(hw, vsi_handle), vid, result); -- cgit v1.2.3 From 664d4646184ed986f8195df684cc4660563fb02a Mon Sep 17 00:00:00 2001 From: Sylwester Dziedziuch Date: Wed, 3 Aug 2022 10:42:46 +0200 Subject: ice: Fix VF not able to send tagged traffic with no VLAN filters VF was not able to send tagged traffic when it didn't have any VLAN interfaces and VLAN anti-spoofing was enabled. Fix this by allowing VFs with no VLAN filters to send tagged traffic. After VF adds a VLAN interface it will be able to send tagged traffic matching VLAN filters only. Testing hints: 1. Spawn VF 2. Send tagged packet from a VF 3. The packet should be sent out and not dropped 4. Add a VLAN interface on VF 5. Send tagged packet on that VLAN interface 6. Packet should be sent out and not dropped 7. Send tagged packet with id different than VLAN interface 8. Packet should be dropped Fixes: daf4dd16438b ("ice: Refactor spoofcheck configuration functions") Signed-off-by: Sylwester Dziedziuch Signed-off-by: Mateusz Palczewski Tested-by: Konrad Jankowski Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/ice/ice_vf_lib.c | 11 ++++-- drivers/net/ethernet/intel/ice/ice_virtchnl.c | 57 +++++++++++++++++++++++---- 2 files changed, 57 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_vf_lib.c b/drivers/net/ethernet/intel/ice/ice_vf_lib.c index 76f70fe1d998..0abeed092de1 100644 --- a/drivers/net/ethernet/intel/ice/ice_vf_lib.c +++ b/drivers/net/ethernet/intel/ice/ice_vf_lib.c @@ -764,13 +764,16 @@ static int ice_cfg_mac_antispoof(struct ice_vsi *vsi, bool enable) static int ice_vsi_ena_spoofchk(struct ice_vsi *vsi) { struct ice_vsi_vlan_ops *vlan_ops; - int err; + int err = 0; vlan_ops = ice_get_compat_vsi_vlan_ops(vsi); - err = vlan_ops->ena_tx_filtering(vsi); - if (err) - return err; + /* Allow VF with VLAN 0 only to send all tagged traffic */ + if (vsi->type != ICE_VSI_VF || ice_vsi_has_non_zero_vlans(vsi)) { + err = vlan_ops->ena_tx_filtering(vsi); + if (err) + return err; + } return ice_cfg_mac_antispoof(vsi, true); } diff --git a/drivers/net/ethernet/intel/ice/ice_virtchnl.c b/drivers/net/ethernet/intel/ice/ice_virtchnl.c index 094e3c97a1ea..2b4c791b6cba 100644 --- a/drivers/net/ethernet/intel/ice/ice_virtchnl.c +++ b/drivers/net/ethernet/intel/ice/ice_virtchnl.c @@ -2288,6 +2288,15 @@ static int ice_vc_process_vlan_msg(struct ice_vf *vf, u8 *msg, bool add_v) /* Enable VLAN filtering on first non-zero VLAN */ if (!vlan_promisc && vid && !ice_is_dvm_ena(&pf->hw)) { + if (vf->spoofchk) { + status = vsi->inner_vlan_ops.ena_tx_filtering(vsi); + if (status) { + v_ret = VIRTCHNL_STATUS_ERR_PARAM; + dev_err(dev, "Enable VLAN anti-spoofing on VLAN ID: %d failed error-%d\n", + vid, status); + goto error_param; + } + } if (vsi->inner_vlan_ops.ena_rx_filtering(vsi)) { v_ret = VIRTCHNL_STATUS_ERR_PARAM; dev_err(dev, "Enable VLAN pruning on VLAN ID: %d failed error-%d\n", @@ -2333,8 +2342,10 @@ static int ice_vc_process_vlan_msg(struct ice_vf *vf, u8 *msg, bool add_v) } /* Disable VLAN filtering when only VLAN 0 is left */ - if (!ice_vsi_has_non_zero_vlans(vsi)) + if (!ice_vsi_has_non_zero_vlans(vsi)) { + vsi->inner_vlan_ops.dis_tx_filtering(vsi); vsi->inner_vlan_ops.dis_rx_filtering(vsi); + } if (vlan_promisc) ice_vf_dis_vlan_promisc(vsi, &vlan); @@ -2838,6 +2849,13 @@ ice_vc_del_vlans(struct ice_vf *vf, struct ice_vsi *vsi, if (vlan_promisc) ice_vf_dis_vlan_promisc(vsi, &vlan); + + /* Disable VLAN filtering when only VLAN 0 is left */ + if (!ice_vsi_has_non_zero_vlans(vsi) && ice_is_dvm_ena(&vsi->back->hw)) { + err = vsi->outer_vlan_ops.dis_tx_filtering(vsi); + if (err) + return err; + } } vc_vlan = &vlan_fltr->inner; @@ -2853,8 +2871,17 @@ ice_vc_del_vlans(struct ice_vf *vf, struct ice_vsi *vsi, /* no support for VLAN promiscuous on inner VLAN unless * we are in Single VLAN Mode (SVM) */ - if (!ice_is_dvm_ena(&vsi->back->hw) && vlan_promisc) - ice_vf_dis_vlan_promisc(vsi, &vlan); + if (!ice_is_dvm_ena(&vsi->back->hw)) { + if (vlan_promisc) + ice_vf_dis_vlan_promisc(vsi, &vlan); + + /* Disable VLAN filtering when only VLAN 0 is left */ + if (!ice_vsi_has_non_zero_vlans(vsi)) { + err = vsi->inner_vlan_ops.dis_tx_filtering(vsi); + if (err) + return err; + } + } } } @@ -2931,6 +2958,13 @@ ice_vc_add_vlans(struct ice_vf *vf, struct ice_vsi *vsi, if (err) return err; } + + /* Enable VLAN filtering on first non-zero VLAN */ + if (vf->spoofchk && vlan.vid && ice_is_dvm_ena(&vsi->back->hw)) { + err = vsi->outer_vlan_ops.ena_tx_filtering(vsi); + if (err) + return err; + } } vc_vlan = &vlan_fltr->inner; @@ -2946,10 +2980,19 @@ ice_vc_add_vlans(struct ice_vf *vf, struct ice_vsi *vsi, /* no support for VLAN promiscuous on inner VLAN unless * we are in Single VLAN Mode (SVM) */ - if (!ice_is_dvm_ena(&vsi->back->hw) && vlan_promisc) { - err = ice_vf_ena_vlan_promisc(vsi, &vlan); - if (err) - return err; + if (!ice_is_dvm_ena(&vsi->back->hw)) { + if (vlan_promisc) { + err = ice_vf_ena_vlan_promisc(vsi, &vlan); + if (err) + return err; + } + + /* Enable VLAN filtering on first non-zero VLAN */ + if (vf->spoofchk && vlan.vid) { + err = vsi->inner_vlan_ops.ena_tx_filtering(vsi); + if (err) + return err; + } } } } -- cgit v1.2.3 From 36c0d935015766bf20d621c18313f17691bda5e3 Mon Sep 17 00:00:00 2001 From: Arun Ramadoss Date: Tue, 16 Aug 2022 16:25:16 +0530 Subject: net: dsa: microchip: ksz9477: fix fdb_dump last invalid entry In the ksz9477_fdb_dump function it reads the ALU control register and exit from the timeout loop if there is valid entry or search is complete. After exiting the loop, it reads the alu entry and report to the user space irrespective of entry is valid. It works till the valid entry. If the loop exited when search is complete, it reads the alu table. The table returns all ones and it is reported to user space. So bridge fdb show gives ff:ff:ff:ff:ff:ff as last entry for every port. To fix it, after exiting the loop the entry is reported only if it is valid one. Fixes: b987e98e50ab ("dsa: add DSA switch driver for Microchip KSZ9477") Signed-off-by: Arun Ramadoss Reviewed-by: Vladimir Oltean Link: https://lore.kernel.org/r/20220816105516.18350-1-arun.ramadoss@microchip.com Signed-off-by: Jakub Kicinski --- drivers/net/dsa/microchip/ksz9477.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/dsa/microchip/ksz9477.c b/drivers/net/dsa/microchip/ksz9477.c index 4b14d80d27ed..e4f446db0ca1 100644 --- a/drivers/net/dsa/microchip/ksz9477.c +++ b/drivers/net/dsa/microchip/ksz9477.c @@ -613,6 +613,9 @@ int ksz9477_fdb_dump(struct ksz_device *dev, int port, goto exit; } + if (!(ksz_data & ALU_VALID)) + continue; + /* read ALU table */ ksz9477_read_table(dev, alu_table); -- cgit v1.2.3 From ae2a823643d71f40751259266f7c2e7d90909662 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Thu, 11 Aug 2022 15:29:46 -0700 Subject: dcache: move the DCACHE_OP_COMPARE case out of the __d_lookup_rcu loop __d_lookup_rcu() is one of the hottest functions in the kernel on certain loads, and it is complicated by filesystems that might want to have their own name compare function. We can improve code generation by moving the test of DCACHE_OP_COMPARE outside the loop, which makes the loop itself much simpler, at the cost of some code duplication. But both cases end up being simpler, and the "native" direct case-sensitive compare particularly so. Cc: Al Viro Signed-off-by: Linus Torvalds --- fs/dcache.c | 72 +++++++++++++++++++++++++++++++++++++++++-------------------- 1 file changed, 49 insertions(+), 23 deletions(-) diff --git a/fs/dcache.c b/fs/dcache.c index c5dc32a59c76..bb0c4d0038db 100644 --- a/fs/dcache.c +++ b/fs/dcache.c @@ -2270,6 +2270,48 @@ bool d_same_name(const struct dentry *dentry, const struct dentry *parent, } EXPORT_SYMBOL_GPL(d_same_name); +/* + * This is __d_lookup_rcu() when the parent dentry has + * DCACHE_OP_COMPARE, which makes things much nastier. + */ +static noinline struct dentry *__d_lookup_rcu_op_compare( + const struct dentry *parent, + const struct qstr *name, + unsigned *seqp) +{ + u64 hashlen = name->hash_len; + struct hlist_bl_head *b = d_hash(hashlen_hash(hashlen)); + struct hlist_bl_node *node; + struct dentry *dentry; + + hlist_bl_for_each_entry_rcu(dentry, node, b, d_hash) { + int tlen; + const char *tname; + unsigned seq; + +seqretry: + seq = raw_seqcount_begin(&dentry->d_seq); + if (dentry->d_parent != parent) + continue; + if (d_unhashed(dentry)) + continue; + if (dentry->d_name.hash != hashlen_hash(hashlen)) + continue; + tlen = dentry->d_name.len; + tname = dentry->d_name.name; + /* we want a consistent (name,len) pair */ + if (read_seqcount_retry(&dentry->d_seq, seq)) { + cpu_relax(); + goto seqretry; + } + if (parent->d_op->d_compare(dentry, tlen, tname, name) != 0) + continue; + *seqp = seq; + return dentry; + } + return NULL; +} + /** * __d_lookup_rcu - search for a dentry (racy, store-free) * @parent: parent dentry @@ -2316,6 +2358,9 @@ struct dentry *__d_lookup_rcu(const struct dentry *parent, * Keep the two functions in sync. */ + if (unlikely(parent->d_flags & DCACHE_OP_COMPARE)) + return __d_lookup_rcu_op_compare(parent, name, seqp); + /* * The hash list is protected using RCU. * @@ -2332,7 +2377,6 @@ struct dentry *__d_lookup_rcu(const struct dentry *parent, hlist_bl_for_each_entry_rcu(dentry, node, b, d_hash) { unsigned seq; -seqretry: /* * The dentry sequence count protects us from concurrent * renames, and thus protects parent and name fields. @@ -2355,28 +2399,10 @@ seqretry: continue; if (d_unhashed(dentry)) continue; - - if (unlikely(parent->d_flags & DCACHE_OP_COMPARE)) { - int tlen; - const char *tname; - if (dentry->d_name.hash != hashlen_hash(hashlen)) - continue; - tlen = dentry->d_name.len; - tname = dentry->d_name.name; - /* we want a consistent (name,len) pair */ - if (read_seqcount_retry(&dentry->d_seq, seq)) { - cpu_relax(); - goto seqretry; - } - if (parent->d_op->d_compare(dentry, - tlen, tname, name) != 0) - continue; - } else { - if (dentry->d_name.hash_len != hashlen) - continue; - if (dentry_cmp(dentry, str, hashlen_len(hashlen)) != 0) - continue; - } + if (dentry->d_name.hash_len != hashlen) + continue; + if (dentry_cmp(dentry, str, hashlen_len(hashlen)) != 0) + continue; *seqp = seq; return dentry; } -- cgit v1.2.3 From fc4aaf9fb3c99bcb326d52f9d320ed5680bd1cee Mon Sep 17 00:00:00 2001 From: David Howells Date: Tue, 16 Aug 2022 10:34:40 +0100 Subject: net: Fix suspicious RCU usage in bpf_sk_reuseport_detach() bpf_sk_reuseport_detach() calls __rcu_dereference_sk_user_data_with_flags() to obtain the value of sk->sk_user_data, but that function is only usable if the RCU read lock is held, and neither that function nor any of its callers hold it. Fix this by adding a new helper, __locked_read_sk_user_data_with_flags() that checks to see if sk->sk_callback_lock() is held and use that here instead. Alternatively, making __rcu_dereference_sk_user_data_with_flags() use rcu_dereference_checked() might suffice. Without this, the following warning can be occasionally observed: ============================= WARNING: suspicious RCU usage 6.0.0-rc1-build2+ #563 Not tainted ----------------------------- include/net/sock.h:592 suspicious rcu_dereference_check() usage! other info that might help us debug this: rcu_scheduler_active = 2, debug_locks = 1 5 locks held by locktest/29873: #0: ffff88812734b550 (&sb->s_type->i_mutex_key#9){+.+.}-{3:3}, at: __sock_release+0x77/0x121 #1: ffff88812f5621b0 (sk_lock-AF_INET){+.+.}-{0:0}, at: tcp_close+0x1c/0x70 #2: ffff88810312f5c8 (&h->lhash2[i].lock){+.+.}-{2:2}, at: inet_unhash+0x76/0x1c0 #3: ffffffff83768bb8 (reuseport_lock){+...}-{2:2}, at: reuseport_detach_sock+0x18/0xdd #4: ffff88812f562438 (clock-AF_INET){++..}-{2:2}, at: bpf_sk_reuseport_detach+0x24/0xa4 stack backtrace: CPU: 1 PID: 29873 Comm: locktest Not tainted 6.0.0-rc1-build2+ #563 Hardware name: ASUS All Series/H97-PLUS, BIOS 2306 10/09/2014 Call Trace: dump_stack_lvl+0x4c/0x5f bpf_sk_reuseport_detach+0x6d/0xa4 reuseport_detach_sock+0x75/0xdd inet_unhash+0xa5/0x1c0 tcp_set_state+0x169/0x20f ? lockdep_sock_is_held+0x3a/0x3a ? __lock_release.isra.0+0x13e/0x220 ? reacquire_held_locks+0x1bb/0x1bb ? hlock_class+0x31/0x96 ? mark_lock+0x9e/0x1af __tcp_close+0x50/0x4b6 tcp_close+0x28/0x70 inet_release+0x8e/0xa7 __sock_release+0x95/0x121 sock_close+0x14/0x17 __fput+0x20f/0x36a task_work_run+0xa3/0xcc exit_to_user_mode_prepare+0x9c/0x14d syscall_exit_to_user_mode+0x18/0x44 entry_SYSCALL_64_after_hwframe+0x63/0xcd Fixes: cf8c1e967224 ("net: refactor bpf_sk_reuseport_detach()") Signed-off-by: David Howells cc: Hawkins Jiawei Link: https://lore.kernel.org/r/166064248071.3502205.10036394558814861778.stgit@warthog.procyon.org.uk Signed-off-by: Jakub Kicinski --- include/net/sock.h | 25 +++++++++++++++++++++++++ kernel/bpf/reuseport_array.c | 2 +- 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/include/net/sock.h b/include/net/sock.h index 05a1bbdf5805..d08cfe190a78 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -577,6 +577,31 @@ static inline bool sk_user_data_is_nocopy(const struct sock *sk) #define __sk_user_data(sk) ((*((void __rcu **)&(sk)->sk_user_data))) +/** + * __locked_read_sk_user_data_with_flags - return the pointer + * only if argument flags all has been set in sk_user_data. Otherwise + * return NULL + * + * @sk: socket + * @flags: flag bits + * + * The caller must be holding sk->sk_callback_lock. + */ +static inline void * +__locked_read_sk_user_data_with_flags(const struct sock *sk, + uintptr_t flags) +{ + uintptr_t sk_user_data = + (uintptr_t)rcu_dereference_check(__sk_user_data(sk), + lockdep_is_held(&sk->sk_callback_lock)); + + WARN_ON_ONCE(flags & SK_USER_DATA_PTRMASK); + + if ((sk_user_data & flags) == flags) + return (void *)(sk_user_data & SK_USER_DATA_PTRMASK); + return NULL; +} + /** * __rcu_dereference_sk_user_data_with_flags - return the pointer * only if argument flags all has been set in sk_user_data. Otherwise diff --git a/kernel/bpf/reuseport_array.c b/kernel/bpf/reuseport_array.c index 85fa9dbfa8bf..82c61612f382 100644 --- a/kernel/bpf/reuseport_array.c +++ b/kernel/bpf/reuseport_array.c @@ -24,7 +24,7 @@ void bpf_sk_reuseport_detach(struct sock *sk) struct sock __rcu **socks; write_lock_bh(&sk->sk_callback_lock); - socks = __rcu_dereference_sk_user_data_with_flags(sk, SK_USER_DATA_BPF); + socks = __locked_read_sk_user_data_with_flags(sk, SK_USER_DATA_BPF); if (socks) { WRITE_ONCE(sk->sk_user_data, NULL); /* -- cgit v1.2.3 From fd8e899cdb5ecaf8e8ee73854a99e10807eef1de Mon Sep 17 00:00:00 2001 From: Rustam Subkhankulov Date: Wed, 17 Aug 2022 03:38:45 +0300 Subject: net: dsa: sja1105: fix buffer overflow in sja1105_setup_devlink_regions() If an error occurs in dsa_devlink_region_create(), then 'priv->regions' array will be accessed by negative index '-1'. Found by Linux Verification Center (linuxtesting.org) with SVACE. Signed-off-by: Rustam Subkhankulov Fixes: bf425b82059e ("net: dsa: sja1105: expose static config as devlink region") Link: https://lore.kernel.org/r/20220817003845.389644-1-subkhankulov@ispras.ru Signed-off-by: Jakub Kicinski --- drivers/net/dsa/sja1105/sja1105_devlink.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/sja1105/sja1105_devlink.c b/drivers/net/dsa/sja1105/sja1105_devlink.c index 0569ff066634..10c6fea1227f 100644 --- a/drivers/net/dsa/sja1105/sja1105_devlink.c +++ b/drivers/net/dsa/sja1105/sja1105_devlink.c @@ -93,7 +93,7 @@ static int sja1105_setup_devlink_regions(struct dsa_switch *ds) region = dsa_devlink_region_create(ds, ops, 1, size); if (IS_ERR(region)) { - while (i-- >= 0) + while (--i >= 0) dsa_devlink_region_destroy(priv->regions[i]); return PTR_ERR(region); } -- cgit v1.2.3 From 211987f3ac734000ea1548784b2a4539a974fbc8 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Tue, 16 Aug 2022 23:14:45 +0300 Subject: net: dsa: don't warn in dsa_port_set_state_now() when driver doesn't support it ds->ops->port_stp_state_set() is, like most DSA methods, optional, and if absent, the port is supposed to remain in the forwarding state (as standalone). Such is the case with the mv88e6060 driver, which does not offload the bridge layer. DSA warns that the STP state can't be changed to FORWARDING as part of dsa_port_enable_rt(), when in fact it should not. The error message is also not up to modern standards, so take the opportunity to make it more descriptive. Fixes: fd3645413197 ("net: dsa: change scope of STP state setter") Reported-by: Sergei Antonov Signed-off-by: Vladimir Oltean Reviewed-by: Sergei Antonov Link: https://lore.kernel.org/r/20220816201445.1809483-1-vladimir.oltean@nxp.com Signed-off-by: Jakub Kicinski --- net/dsa/port.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/net/dsa/port.c b/net/dsa/port.c index 2dd76eb1621c..a8895ee3cd60 100644 --- a/net/dsa/port.c +++ b/net/dsa/port.c @@ -145,11 +145,14 @@ int dsa_port_set_state(struct dsa_port *dp, u8 state, bool do_fast_age) static void dsa_port_set_state_now(struct dsa_port *dp, u8 state, bool do_fast_age) { + struct dsa_switch *ds = dp->ds; int err; err = dsa_port_set_state(dp, state, do_fast_age); - if (err) - pr_err("DSA: failed to set STP state %u (%d)\n", state, err); + if (err && err != -EOPNOTSUPP) { + dev_err(ds->dev, "port %d failed to set STP state %u: %pe\n", + dp->index, state, ERR_PTR(err)); + } } int dsa_port_set_mst_state(struct dsa_port *dp, -- cgit v1.2.3 From 40d21c4565bce064c73a03b79a157a3493c518b9 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Tue, 16 Aug 2022 16:53:45 +0300 Subject: net: dsa: felix: fix ethtool 256-511 and 512-1023 TX packet counters What the driver actually reports as 256-511 is in fact 512-1023, and the TX packets in the 256-511 bucket are not reported. Fix that. Fixes: 56051948773e ("net: dsa: ocelot: add driver for Felix switch family") Signed-off-by: Vladimir Oltean Signed-off-by: Jakub Kicinski --- drivers/net/dsa/ocelot/felix_vsc9959.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/ocelot/felix_vsc9959.c b/drivers/net/dsa/ocelot/felix_vsc9959.c index b4034b78c0ca..5859ef3b242c 100644 --- a/drivers/net/dsa/ocelot/felix_vsc9959.c +++ b/drivers/net/dsa/ocelot/felix_vsc9959.c @@ -602,7 +602,8 @@ static const struct ocelot_stat_layout vsc9959_stats_layout[] = { { .offset = 0x87, .name = "tx_frames_below_65_octets", }, { .offset = 0x88, .name = "tx_frames_65_to_127_octets", }, { .offset = 0x89, .name = "tx_frames_128_255_octets", }, - { .offset = 0x8B, .name = "tx_frames_256_511_octets", }, + { .offset = 0x8A, .name = "tx_frames_256_511_octets", }, + { .offset = 0x8B, .name = "tx_frames_512_1023_octets", }, { .offset = 0x8C, .name = "tx_frames_1024_1526_octets", }, { .offset = 0x8D, .name = "tx_frames_over_1526_octets", }, { .offset = 0x8E, .name = "tx_yellow_prio_0", }, -- cgit v1.2.3 From 5152de7b79ab0be150f5966481b0c8f996192531 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Tue, 16 Aug 2022 16:53:46 +0300 Subject: net: mscc: ocelot: fix incorrect ndo_get_stats64 packet counters Reading stats using the SYS_COUNT_* register definitions is only used by ocelot_get_stats64() from the ocelot switchdev driver, however, currently the bucket definitions are incorrect. Separately, on both RX and TX, we have the following problems: - a 256-1023 bucket which actually tracks the 256-511 packets - the 1024-1526 bucket actually tracks the 512-1023 packets - the 1527-max bucket actually tracks the 1024-1526 packets => nobody tracks the packets from the real 1527-max bucket Additionally, the RX_PAUSE, RX_CONTROL, RX_LONGS and RX_CLASSIFIED_DROPS all track the wrong thing. However this doesn't seem to have any consequence, since ocelot_get_stats64() doesn't use these. Even though this problem only manifests itself for the switchdev driver, we cannot split the fix for ocelot and for DSA, since it requires fixing the bucket definitions from enum ocelot_reg, which makes us necessarily adapt the structures from felix and seville as well. Fixes: 84705fc16552 ("net: dsa: felix: introduce support for Seville VSC9953 switch") Fixes: 56051948773e ("net: dsa: ocelot: add driver for Felix switch family") Fixes: a556c76adc05 ("net: mscc: Add initial Ocelot switch support") Signed-off-by: Vladimir Oltean Signed-off-by: Jakub Kicinski --- drivers/net/dsa/ocelot/felix_vsc9959.c | 20 ++++++++++++-------- drivers/net/dsa/ocelot/seville_vsc9953.c | 16 +++++++++------- drivers/net/ethernet/mscc/ocelot_net.c | 6 ++++-- drivers/net/ethernet/mscc/vsc7514_regs.c | 24 +++++++++++++----------- include/soc/mscc/ocelot.h | 6 ++++-- 5 files changed, 42 insertions(+), 30 deletions(-) diff --git a/drivers/net/dsa/ocelot/felix_vsc9959.c b/drivers/net/dsa/ocelot/felix_vsc9959.c index 5859ef3b242c..e1ebe21cad00 100644 --- a/drivers/net/dsa/ocelot/felix_vsc9959.c +++ b/drivers/net/dsa/ocelot/felix_vsc9959.c @@ -281,19 +281,23 @@ static const u32 vsc9959_sys_regmap[] = { REG(SYS_COUNT_RX_64, 0x000024), REG(SYS_COUNT_RX_65_127, 0x000028), REG(SYS_COUNT_RX_128_255, 0x00002c), - REG(SYS_COUNT_RX_256_1023, 0x000030), - REG(SYS_COUNT_RX_1024_1526, 0x000034), - REG(SYS_COUNT_RX_1527_MAX, 0x000038), - REG(SYS_COUNT_RX_LONGS, 0x000044), + REG(SYS_COUNT_RX_256_511, 0x000030), + REG(SYS_COUNT_RX_512_1023, 0x000034), + REG(SYS_COUNT_RX_1024_1526, 0x000038), + REG(SYS_COUNT_RX_1527_MAX, 0x00003c), + REG(SYS_COUNT_RX_PAUSE, 0x000040), + REG(SYS_COUNT_RX_CONTROL, 0x000044), + REG(SYS_COUNT_RX_LONGS, 0x000048), REG(SYS_COUNT_TX_OCTETS, 0x000200), REG(SYS_COUNT_TX_COLLISION, 0x000210), REG(SYS_COUNT_TX_DROPS, 0x000214), REG(SYS_COUNT_TX_64, 0x00021c), REG(SYS_COUNT_TX_65_127, 0x000220), - REG(SYS_COUNT_TX_128_511, 0x000224), - REG(SYS_COUNT_TX_512_1023, 0x000228), - REG(SYS_COUNT_TX_1024_1526, 0x00022c), - REG(SYS_COUNT_TX_1527_MAX, 0x000230), + REG(SYS_COUNT_TX_128_255, 0x000224), + REG(SYS_COUNT_TX_256_511, 0x000228), + REG(SYS_COUNT_TX_512_1023, 0x00022c), + REG(SYS_COUNT_TX_1024_1526, 0x000230), + REG(SYS_COUNT_TX_1527_MAX, 0x000234), REG(SYS_COUNT_TX_AGING, 0x000278), REG(SYS_RESET_CFG, 0x000e00), REG(SYS_SR_ETYPE_CFG, 0x000e04), diff --git a/drivers/net/dsa/ocelot/seville_vsc9953.c b/drivers/net/dsa/ocelot/seville_vsc9953.c index ea0649211356..ebe9ddbbe2b7 100644 --- a/drivers/net/dsa/ocelot/seville_vsc9953.c +++ b/drivers/net/dsa/ocelot/seville_vsc9953.c @@ -277,19 +277,21 @@ static const u32 vsc9953_sys_regmap[] = { REG(SYS_COUNT_RX_64, 0x000024), REG(SYS_COUNT_RX_65_127, 0x000028), REG(SYS_COUNT_RX_128_255, 0x00002c), - REG(SYS_COUNT_RX_256_1023, 0x000030), - REG(SYS_COUNT_RX_1024_1526, 0x000034), - REG(SYS_COUNT_RX_1527_MAX, 0x000038), + REG(SYS_COUNT_RX_256_511, 0x000030), + REG(SYS_COUNT_RX_512_1023, 0x000034), + REG(SYS_COUNT_RX_1024_1526, 0x000038), + REG(SYS_COUNT_RX_1527_MAX, 0x00003c), REG(SYS_COUNT_RX_LONGS, 0x000048), REG(SYS_COUNT_TX_OCTETS, 0x000100), REG(SYS_COUNT_TX_COLLISION, 0x000110), REG(SYS_COUNT_TX_DROPS, 0x000114), REG(SYS_COUNT_TX_64, 0x00011c), REG(SYS_COUNT_TX_65_127, 0x000120), - REG(SYS_COUNT_TX_128_511, 0x000124), - REG(SYS_COUNT_TX_512_1023, 0x000128), - REG(SYS_COUNT_TX_1024_1526, 0x00012c), - REG(SYS_COUNT_TX_1527_MAX, 0x000130), + REG(SYS_COUNT_TX_128_255, 0x000124), + REG(SYS_COUNT_TX_256_511, 0x000128), + REG(SYS_COUNT_TX_512_1023, 0x00012c), + REG(SYS_COUNT_TX_1024_1526, 0x000130), + REG(SYS_COUNT_TX_1527_MAX, 0x000134), REG(SYS_COUNT_TX_AGING, 0x000178), REG(SYS_RESET_CFG, 0x000318), REG_RESERVED(SYS_SR_ETYPE_CFG), diff --git a/drivers/net/ethernet/mscc/ocelot_net.c b/drivers/net/ethernet/mscc/ocelot_net.c index 5e6136e80282..9d8cea16245e 100644 --- a/drivers/net/ethernet/mscc/ocelot_net.c +++ b/drivers/net/ethernet/mscc/ocelot_net.c @@ -739,7 +739,8 @@ static void ocelot_get_stats64(struct net_device *dev, ocelot_read(ocelot, SYS_COUNT_RX_64) + ocelot_read(ocelot, SYS_COUNT_RX_65_127) + ocelot_read(ocelot, SYS_COUNT_RX_128_255) + - ocelot_read(ocelot, SYS_COUNT_RX_256_1023) + + ocelot_read(ocelot, SYS_COUNT_RX_256_511) + + ocelot_read(ocelot, SYS_COUNT_RX_512_1023) + ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) + ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX); stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST); @@ -749,7 +750,8 @@ static void ocelot_get_stats64(struct net_device *dev, stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS); stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) + ocelot_read(ocelot, SYS_COUNT_TX_65_127) + - ocelot_read(ocelot, SYS_COUNT_TX_128_511) + + ocelot_read(ocelot, SYS_COUNT_TX_128_255) + + ocelot_read(ocelot, SYS_COUNT_TX_256_511) + ocelot_read(ocelot, SYS_COUNT_TX_512_1023) + ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) + ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX); diff --git a/drivers/net/ethernet/mscc/vsc7514_regs.c b/drivers/net/ethernet/mscc/vsc7514_regs.c index c2af4eb8ca5d..38ab20b48cd4 100644 --- a/drivers/net/ethernet/mscc/vsc7514_regs.c +++ b/drivers/net/ethernet/mscc/vsc7514_regs.c @@ -180,13 +180,14 @@ const u32 vsc7514_sys_regmap[] = { REG(SYS_COUNT_RX_64, 0x000024), REG(SYS_COUNT_RX_65_127, 0x000028), REG(SYS_COUNT_RX_128_255, 0x00002c), - REG(SYS_COUNT_RX_256_1023, 0x000030), - REG(SYS_COUNT_RX_1024_1526, 0x000034), - REG(SYS_COUNT_RX_1527_MAX, 0x000038), - REG(SYS_COUNT_RX_PAUSE, 0x00003c), - REG(SYS_COUNT_RX_CONTROL, 0x000040), - REG(SYS_COUNT_RX_LONGS, 0x000044), - REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x000048), + REG(SYS_COUNT_RX_256_511, 0x000030), + REG(SYS_COUNT_RX_512_1023, 0x000034), + REG(SYS_COUNT_RX_1024_1526, 0x000038), + REG(SYS_COUNT_RX_1527_MAX, 0x00003c), + REG(SYS_COUNT_RX_PAUSE, 0x000040), + REG(SYS_COUNT_RX_CONTROL, 0x000044), + REG(SYS_COUNT_RX_LONGS, 0x000048), + REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x00004c), REG(SYS_COUNT_TX_OCTETS, 0x000100), REG(SYS_COUNT_TX_UNICAST, 0x000104), REG(SYS_COUNT_TX_MULTICAST, 0x000108), @@ -196,10 +197,11 @@ const u32 vsc7514_sys_regmap[] = { REG(SYS_COUNT_TX_PAUSE, 0x000118), REG(SYS_COUNT_TX_64, 0x00011c), REG(SYS_COUNT_TX_65_127, 0x000120), - REG(SYS_COUNT_TX_128_511, 0x000124), - REG(SYS_COUNT_TX_512_1023, 0x000128), - REG(SYS_COUNT_TX_1024_1526, 0x00012c), - REG(SYS_COUNT_TX_1527_MAX, 0x000130), + REG(SYS_COUNT_TX_128_255, 0x000124), + REG(SYS_COUNT_TX_256_511, 0x000128), + REG(SYS_COUNT_TX_512_1023, 0x00012c), + REG(SYS_COUNT_TX_1024_1526, 0x000130), + REG(SYS_COUNT_TX_1527_MAX, 0x000134), REG(SYS_COUNT_TX_AGING, 0x000170), REG(SYS_RESET_CFG, 0x000508), REG(SYS_CMID, 0x00050c), diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h index ac151ecc7f19..e7e5b06deb2d 100644 --- a/include/soc/mscc/ocelot.h +++ b/include/soc/mscc/ocelot.h @@ -335,7 +335,8 @@ enum ocelot_reg { SYS_COUNT_RX_64, SYS_COUNT_RX_65_127, SYS_COUNT_RX_128_255, - SYS_COUNT_RX_256_1023, + SYS_COUNT_RX_256_511, + SYS_COUNT_RX_512_1023, SYS_COUNT_RX_1024_1526, SYS_COUNT_RX_1527_MAX, SYS_COUNT_RX_PAUSE, @@ -351,7 +352,8 @@ enum ocelot_reg { SYS_COUNT_TX_PAUSE, SYS_COUNT_TX_64, SYS_COUNT_TX_65_127, - SYS_COUNT_TX_128_511, + SYS_COUNT_TX_128_255, + SYS_COUNT_TX_256_511, SYS_COUNT_TX_512_1023, SYS_COUNT_TX_1024_1526, SYS_COUNT_TX_1527_MAX, -- cgit v1.2.3 From 173ca86618d751bd183456c9cdbb69952ba283c8 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Tue, 16 Aug 2022 16:53:47 +0300 Subject: net: mscc: ocelot: fix address of SYS_COUNT_TX_AGING counter This register, used as part of stats->tx_dropped in ocelot_get_stats64(), has a wrong address. At the address currently given, there is actually the c_tx_green_prio_6 counter. Fixes: a556c76adc05 ("net: mscc: Add initial Ocelot switch support") Signed-off-by: Vladimir Oltean Signed-off-by: Jakub Kicinski --- drivers/net/ethernet/mscc/vsc7514_regs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mscc/vsc7514_regs.c b/drivers/net/ethernet/mscc/vsc7514_regs.c index 38ab20b48cd4..8ff935f7f150 100644 --- a/drivers/net/ethernet/mscc/vsc7514_regs.c +++ b/drivers/net/ethernet/mscc/vsc7514_regs.c @@ -202,7 +202,7 @@ const u32 vsc7514_sys_regmap[] = { REG(SYS_COUNT_TX_512_1023, 0x00012c), REG(SYS_COUNT_TX_1024_1526, 0x000130), REG(SYS_COUNT_TX_1527_MAX, 0x000134), - REG(SYS_COUNT_TX_AGING, 0x000170), + REG(SYS_COUNT_TX_AGING, 0x000178), REG(SYS_RESET_CFG, 0x000508), REG(SYS_CMID, 0x00050c), REG(SYS_VLAN_ETYPE_CFG, 0x000510), -- cgit v1.2.3 From 22d842e3efe56402c33b5e6e303bb71ce9bf9334 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Tue, 16 Aug 2022 16:53:48 +0300 Subject: net: mscc: ocelot: turn stats_lock into a spinlock ocelot_get_stats64() currently runs unlocked and therefore may collide with ocelot_port_update_stats() which indirectly accesses the same counters. However, ocelot_get_stats64() runs in atomic context, and we cannot simply take the sleepable ocelot->stats_lock mutex. We need to convert it to an atomic spinlock first. Do that as a preparatory change. Signed-off-by: Vladimir Oltean Signed-off-by: Jakub Kicinski --- drivers/net/dsa/ocelot/felix_vsc9959.c | 4 ++-- drivers/net/ethernet/mscc/ocelot.c | 11 +++++------ include/soc/mscc/ocelot.h | 2 +- 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/net/dsa/ocelot/felix_vsc9959.c b/drivers/net/dsa/ocelot/felix_vsc9959.c index e1ebe21cad00..46fd6cd0d8f3 100644 --- a/drivers/net/dsa/ocelot/felix_vsc9959.c +++ b/drivers/net/dsa/ocelot/felix_vsc9959.c @@ -2171,7 +2171,7 @@ static void vsc9959_psfp_sgi_table_del(struct ocelot *ocelot, static void vsc9959_psfp_counters_get(struct ocelot *ocelot, u32 index, struct felix_stream_filter_counters *counters) { - mutex_lock(&ocelot->stats_lock); + spin_lock(&ocelot->stats_lock); ocelot_rmw(ocelot, SYS_STAT_CFG_STAT_VIEW(index), SYS_STAT_CFG_STAT_VIEW_M, @@ -2188,7 +2188,7 @@ static void vsc9959_psfp_counters_get(struct ocelot *ocelot, u32 index, SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10), SYS_STAT_CFG); - mutex_unlock(&ocelot->stats_lock); + spin_unlock(&ocelot->stats_lock); } static int vsc9959_psfp_filter_add(struct ocelot *ocelot, int port, diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c index d4649e4ee0e7..c67f162f8ab5 100644 --- a/drivers/net/ethernet/mscc/ocelot.c +++ b/drivers/net/ethernet/mscc/ocelot.c @@ -1906,13 +1906,13 @@ static void ocelot_check_stats_work(struct work_struct *work) stats_work); int i, err; - mutex_lock(&ocelot->stats_lock); + spin_lock(&ocelot->stats_lock); for (i = 0; i < ocelot->num_phys_ports; i++) { err = ocelot_port_update_stats(ocelot, i); if (err) break; } - mutex_unlock(&ocelot->stats_lock); + spin_unlock(&ocelot->stats_lock); if (err) dev_err(ocelot->dev, "Error %d updating ethtool stats\n", err); @@ -1925,7 +1925,7 @@ void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) { int i, err; - mutex_lock(&ocelot->stats_lock); + spin_lock(&ocelot->stats_lock); /* check and update now */ err = ocelot_port_update_stats(ocelot, port); @@ -1934,7 +1934,7 @@ void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) for (i = 0; i < ocelot->num_stats; i++) *data++ = ocelot->stats[port * ocelot->num_stats + i]; - mutex_unlock(&ocelot->stats_lock); + spin_unlock(&ocelot->stats_lock); if (err) dev_err(ocelot->dev, "Error %d updating ethtool stats\n", err); @@ -3363,7 +3363,7 @@ int ocelot_init(struct ocelot *ocelot) if (!ocelot->stats) return -ENOMEM; - mutex_init(&ocelot->stats_lock); + spin_lock_init(&ocelot->stats_lock); mutex_init(&ocelot->ptp_lock); mutex_init(&ocelot->mact_lock); mutex_init(&ocelot->fwd_domain_lock); @@ -3511,7 +3511,6 @@ void ocelot_deinit(struct ocelot *ocelot) cancel_delayed_work(&ocelot->stats_work); destroy_workqueue(ocelot->stats_queue); destroy_workqueue(ocelot->owq); - mutex_destroy(&ocelot->stats_lock); } EXPORT_SYMBOL(ocelot_deinit); diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h index e7e5b06deb2d..72b9474391da 100644 --- a/include/soc/mscc/ocelot.h +++ b/include/soc/mscc/ocelot.h @@ -752,7 +752,7 @@ struct ocelot { struct ocelot_psfp_list psfp; /* Workqueue to check statistics for overflow with its lock */ - struct mutex stats_lock; + spinlock_t stats_lock; u64 *stats; struct delayed_work stats_work; struct workqueue_struct *stats_queue; -- cgit v1.2.3 From 18d8e67df184081bc6ce6220a2dd965cfd3d7e6b Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Tue, 16 Aug 2022 16:53:49 +0300 Subject: net: mscc: ocelot: fix race between ndo_get_stats64 and ocelot_check_stats_work The 2 methods can run concurrently, and one will change the window of counters (SYS_STAT_CFG_STAT_VIEW) that the other sees. The fix is similar to what commit 7fbf6795d127 ("net: mscc: ocelot: fix mutex lock error during ethtool stats read") has done for ethtool -S. Fixes: a556c76adc05 ("net: mscc: Add initial Ocelot switch support") Signed-off-by: Vladimir Oltean Signed-off-by: Jakub Kicinski --- drivers/net/ethernet/mscc/ocelot_net.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/ethernet/mscc/ocelot_net.c b/drivers/net/ethernet/mscc/ocelot_net.c index 9d8cea16245e..6b9d37138844 100644 --- a/drivers/net/ethernet/mscc/ocelot_net.c +++ b/drivers/net/ethernet/mscc/ocelot_net.c @@ -726,6 +726,8 @@ static void ocelot_get_stats64(struct net_device *dev, struct ocelot *ocelot = priv->port.ocelot; int port = priv->port.index; + spin_lock(&ocelot->stats_lock); + /* Configure the port to read the stats from */ ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port), SYS_STAT_CFG); @@ -758,6 +760,8 @@ static void ocelot_get_stats64(struct net_device *dev, stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) + ocelot_read(ocelot, SYS_COUNT_TX_AGING); stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION); + + spin_unlock(&ocelot->stats_lock); } static int ocelot_port_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], -- cgit v1.2.3 From 9190460084ddd0e9235f55eab0fdd5456b5f2fd5 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Tue, 16 Aug 2022 16:53:50 +0300 Subject: net: mscc: ocelot: make struct ocelot_stat_layout array indexable The ocelot counters are 32-bit and require periodic reading, every 2 seconds, by ocelot_port_update_stats(), so that wraparounds are detected. Currently, the counters reported by ocelot_get_stats64() come from the 32-bit hardware counters directly, rather than from the 64-bit accumulated ocelot->stats, and this is a problem for their integrity. The strategy is to make ocelot_get_stats64() able to cherry-pick individual stats from ocelot->stats the way in which it currently reads them out from SYS_COUNT_* registers. But currently it can't, because ocelot->stats is an opaque u64 array that's used only to feed data into ethtool -S. To solve that problem, we need to make ocelot->stats indexable, and associate each element with an element of struct ocelot_stat_layout used by ethtool -S. This makes ocelot_stat_layout a fat (and possibly sparse) array, so we need to change the way in which we access it. We no longer need OCELOT_STAT_END as a sentinel, because we know the array's size (OCELOT_NUM_STATS). We just need to skip the array elements that were left unpopulated for the switch revision (ocelot, felix, seville). Signed-off-by: Vladimir Oltean Signed-off-by: Jakub Kicinski --- drivers/net/dsa/ocelot/felix_vsc9959.c | 468 +++++++++++++++++++++++------ drivers/net/dsa/ocelot/seville_vsc9953.c | 468 +++++++++++++++++++++++------ drivers/net/ethernet/mscc/ocelot.c | 40 ++- drivers/net/ethernet/mscc/ocelot_vsc7514.c | 468 +++++++++++++++++++++++------ include/soc/mscc/ocelot.h | 105 ++++++- 5 files changed, 1243 insertions(+), 306 deletions(-) diff --git a/drivers/net/dsa/ocelot/felix_vsc9959.c b/drivers/net/dsa/ocelot/felix_vsc9959.c index 46fd6cd0d8f3..c9f270f24b1c 100644 --- a/drivers/net/dsa/ocelot/felix_vsc9959.c +++ b/drivers/net/dsa/ocelot/felix_vsc9959.c @@ -551,101 +551,379 @@ static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = { [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4), }; -static const struct ocelot_stat_layout vsc9959_stats_layout[] = { - { .offset = 0x00, .name = "rx_octets", }, - { .offset = 0x01, .name = "rx_unicast", }, - { .offset = 0x02, .name = "rx_multicast", }, - { .offset = 0x03, .name = "rx_broadcast", }, - { .offset = 0x04, .name = "rx_shorts", }, - { .offset = 0x05, .name = "rx_fragments", }, - { .offset = 0x06, .name = "rx_jabbers", }, - { .offset = 0x07, .name = "rx_crc_align_errs", }, - { .offset = 0x08, .name = "rx_sym_errs", }, - { .offset = 0x09, .name = "rx_frames_below_65_octets", }, - { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", }, - { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", }, - { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", }, - { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", }, - { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", }, - { .offset = 0x0F, .name = "rx_frames_over_1526_octets", }, - { .offset = 0x10, .name = "rx_pause", }, - { .offset = 0x11, .name = "rx_control", }, - { .offset = 0x12, .name = "rx_longs", }, - { .offset = 0x13, .name = "rx_classified_drops", }, - { .offset = 0x14, .name = "rx_red_prio_0", }, - { .offset = 0x15, .name = "rx_red_prio_1", }, - { .offset = 0x16, .name = "rx_red_prio_2", }, - { .offset = 0x17, .name = "rx_red_prio_3", }, - { .offset = 0x18, .name = "rx_red_prio_4", }, - { .offset = 0x19, .name = "rx_red_prio_5", }, - { .offset = 0x1A, .name = "rx_red_prio_6", }, - { .offset = 0x1B, .name = "rx_red_prio_7", }, - { .offset = 0x1C, .name = "rx_yellow_prio_0", }, - { .offset = 0x1D, .name = "rx_yellow_prio_1", }, - { .offset = 0x1E, .name = "rx_yellow_prio_2", }, - { .offset = 0x1F, .name = "rx_yellow_prio_3", }, - { .offset = 0x20, .name = "rx_yellow_prio_4", }, - { .offset = 0x21, .name = "rx_yellow_prio_5", }, - { .offset = 0x22, .name = "rx_yellow_prio_6", }, - { .offset = 0x23, .name = "rx_yellow_prio_7", }, - { .offset = 0x24, .name = "rx_green_prio_0", }, - { .offset = 0x25, .name = "rx_green_prio_1", }, - { .offset = 0x26, .name = "rx_green_prio_2", }, - { .offset = 0x27, .name = "rx_green_prio_3", }, - { .offset = 0x28, .name = "rx_green_prio_4", }, - { .offset = 0x29, .name = "rx_green_prio_5", }, - { .offset = 0x2A, .name = "rx_green_prio_6", }, - { .offset = 0x2B, .name = "rx_green_prio_7", }, - { .offset = 0x80, .name = "tx_octets", }, - { .offset = 0x81, .name = "tx_unicast", }, - { .offset = 0x82, .name = "tx_multicast", }, - { .offset = 0x83, .name = "tx_broadcast", }, - { .offset = 0x84, .name = "tx_collision", }, - { .offset = 0x85, .name = "tx_drops", }, - { .offset = 0x86, .name = "tx_pause", }, - { .offset = 0x87, .name = "tx_frames_below_65_octets", }, - { .offset = 0x88, .name = "tx_frames_65_to_127_octets", }, - { .offset = 0x89, .name = "tx_frames_128_255_octets", }, - { .offset = 0x8A, .name = "tx_frames_256_511_octets", }, - { .offset = 0x8B, .name = "tx_frames_512_1023_octets", }, - { .offset = 0x8C, .name = "tx_frames_1024_1526_octets", }, - { .offset = 0x8D, .name = "tx_frames_over_1526_octets", }, - { .offset = 0x8E, .name = "tx_yellow_prio_0", }, - { .offset = 0x8F, .name = "tx_yellow_prio_1", }, - { .offset = 0x90, .name = "tx_yellow_prio_2", }, - { .offset = 0x91, .name = "tx_yellow_prio_3", }, - { .offset = 0x92, .name = "tx_yellow_prio_4", }, - { .offset = 0x93, .name = "tx_yellow_prio_5", }, - { .offset = 0x94, .name = "tx_yellow_prio_6", }, - { .offset = 0x95, .name = "tx_yellow_prio_7", }, - { .offset = 0x96, .name = "tx_green_prio_0", }, - { .offset = 0x97, .name = "tx_green_prio_1", }, - { .offset = 0x98, .name = "tx_green_prio_2", }, - { .offset = 0x99, .name = "tx_green_prio_3", }, - { .offset = 0x9A, .name = "tx_green_prio_4", }, - { .offset = 0x9B, .name = "tx_green_prio_5", }, - { .offset = 0x9C, .name = "tx_green_prio_6", }, - { .offset = 0x9D, .name = "tx_green_prio_7", }, - { .offset = 0x9E, .name = "tx_aged", }, - { .offset = 0x100, .name = "drop_local", }, - { .offset = 0x101, .name = "drop_tail", }, - { .offset = 0x102, .name = "drop_yellow_prio_0", }, - { .offset = 0x103, .name = "drop_yellow_prio_1", }, - { .offset = 0x104, .name = "drop_yellow_prio_2", }, - { .offset = 0x105, .name = "drop_yellow_prio_3", }, - { .offset = 0x106, .name = "drop_yellow_prio_4", }, - { .offset = 0x107, .name = "drop_yellow_prio_5", }, - { .offset = 0x108, .name = "drop_yellow_prio_6", }, - { .offset = 0x109, .name = "drop_yellow_prio_7", }, - { .offset = 0x10A, .name = "drop_green_prio_0", }, - { .offset = 0x10B, .name = "drop_green_prio_1", }, - { .offset = 0x10C, .name = "drop_green_prio_2", }, - { .offset = 0x10D, .name = "drop_green_prio_3", }, - { .offset = 0x10E, .name = "drop_green_prio_4", }, - { .offset = 0x10F, .name = "drop_green_prio_5", }, - { .offset = 0x110, .name = "drop_green_prio_6", }, - { .offset = 0x111, .name = "drop_green_prio_7", }, - OCELOT_STAT_END +static const struct ocelot_stat_layout vsc9959_stats_layout[OCELOT_NUM_STATS] = { + [OCELOT_STAT_RX_OCTETS] = { + .name = "rx_octets", + .offset = 0x00, + }, + [OCELOT_STAT_RX_UNICAST] = { + .name = "rx_unicast", + .offset = 0x01, + }, + [OCELOT_STAT_RX_MULTICAST] = { + .name = "rx_multicast", + .offset = 0x02, + }, + [OCELOT_STAT_RX_BROADCAST] = { + .name = "rx_broadcast", + .offset = 0x03, + }, + [OCELOT_STAT_RX_SHORTS] = { + .name = "rx_shorts", + .offset = 0x04, + }, + [OCELOT_STAT_RX_FRAGMENTS] = { + .name = "rx_fragments", + .offset = 0x05, + }, + [OCELOT_STAT_RX_JABBERS] = { + .name = "rx_jabbers", + .offset = 0x06, + }, + [OCELOT_STAT_RX_CRC_ALIGN_ERRS] = { + .name = "rx_crc_align_errs", + .offset = 0x07, + }, + [OCELOT_STAT_RX_SYM_ERRS] = { + .name = "rx_sym_errs", + .offset = 0x08, + }, + [OCELOT_STAT_RX_64] = { + .name = "rx_frames_below_65_octets", + .offset = 0x09, + }, + [OCELOT_STAT_RX_65_127] = { + .name = "rx_frames_65_to_127_octets", + .offset = 0x0A, + }, + [OCELOT_STAT_RX_128_255] = { + .name = "rx_frames_128_to_255_octets", + .offset = 0x0B, + }, + [OCELOT_STAT_RX_256_511] = { + .name = "rx_frames_256_to_511_octets", + .offset = 0x0C, + }, + [OCELOT_STAT_RX_512_1023] = { + .name = "rx_frames_512_to_1023_octets", + .offset = 0x0D, + }, + [OCELOT_STAT_RX_1024_1526] = { + .name = "rx_frames_1024_to_1526_octets", + .offset = 0x0E, + }, + [OCELOT_STAT_RX_1527_MAX] = { + .name = "rx_frames_over_1526_octets", + .offset = 0x0F, + }, + [OCELOT_STAT_RX_PAUSE] = { + .name = "rx_pause", + .offset = 0x10, + }, + [OCELOT_STAT_RX_CONTROL] = { + .name = "rx_control", + .offset = 0x11, + }, + [OCELOT_STAT_RX_LONGS] = { + .name = "rx_longs", + .offset = 0x12, + }, + [OCELOT_STAT_RX_CLASSIFIED_DROPS] = { + .name = "rx_classified_drops", + .offset = 0x13, + }, + [OCELOT_STAT_RX_RED_PRIO_0] = { + .name = "rx_red_prio_0", + .offset = 0x14, + }, + [OCELOT_STAT_RX_RED_PRIO_1] = { + .name = "rx_red_prio_1", + .offset = 0x15, + }, + [OCELOT_STAT_RX_RED_PRIO_2] = { + .name = "rx_red_prio_2", + .offset = 0x16, + }, + [OCELOT_STAT_RX_RED_PRIO_3] = { + .name = "rx_red_prio_3", + .offset = 0x17, + }, + [OCELOT_STAT_RX_RED_PRIO_4] = { + .name = "rx_red_prio_4", + .offset = 0x18, + }, + [OCELOT_STAT_RX_RED_PRIO_5] = { + .name = "rx_red_prio_5", + .offset = 0x19, + }, + [OCELOT_STAT_RX_RED_PRIO_6] = { + .name = "rx_red_prio_6", + .offset = 0x1A, + }, + [OCELOT_STAT_RX_RED_PRIO_7] = { + .name = "rx_red_prio_7", + .offset = 0x1B, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_0] = { + .name = "rx_yellow_prio_0", + .offset = 0x1C, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_1] = { + .name = "rx_yellow_prio_1", + .offset = 0x1D, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_2] = { + .name = "rx_yellow_prio_2", + .offset = 0x1E, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_3] = { + .name = "rx_yellow_prio_3", + .offset = 0x1F, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_4] = { + .name = "rx_yellow_prio_4", + .offset = 0x20, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_5] = { + .name = "rx_yellow_prio_5", + .offset = 0x21, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_6] = { + .name = "rx_yellow_prio_6", + .offset = 0x22, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_7] = { + .name = "rx_yellow_prio_7", + .offset = 0x23, + }, + [OCELOT_STAT_RX_GREEN_PRIO_0] = { + .name = "rx_green_prio_0", + .offset = 0x24, + }, + [OCELOT_STAT_RX_GREEN_PRIO_1] = { + .name = "rx_green_prio_1", + .offset = 0x25, + }, + [OCELOT_STAT_RX_GREEN_PRIO_2] = { + .name = "rx_green_prio_2", + .offset = 0x26, + }, + [OCELOT_STAT_RX_GREEN_PRIO_3] = { + .name = "rx_green_prio_3", + .offset = 0x27, + }, + [OCELOT_STAT_RX_GREEN_PRIO_4] = { + .name = "rx_green_prio_4", + .offset = 0x28, + }, + [OCELOT_STAT_RX_GREEN_PRIO_5] = { + .name = "rx_green_prio_5", + .offset = 0x29, + }, + [OCELOT_STAT_RX_GREEN_PRIO_6] = { + .name = "rx_green_prio_6", + .offset = 0x2A, + }, + [OCELOT_STAT_RX_GREEN_PRIO_7] = { + .name = "rx_green_prio_7", + .offset = 0x2B, + }, + [OCELOT_STAT_TX_OCTETS] = { + .name = "tx_octets", + .offset = 0x80, + }, + [OCELOT_STAT_TX_UNICAST] = { + .name = "tx_unicast", + .offset = 0x81, + }, + [OCELOT_STAT_TX_MULTICAST] = { + .name = "tx_multicast", + .offset = 0x82, + }, + [OCELOT_STAT_TX_BROADCAST] = { + .name = "tx_broadcast", + .offset = 0x83, + }, + [OCELOT_STAT_TX_COLLISION] = { + .name = "tx_collision", + .offset = 0x84, + }, + [OCELOT_STAT_TX_DROPS] = { + .name = "tx_drops", + .offset = 0x85, + }, + [OCELOT_STAT_TX_PAUSE] = { + .name = "tx_pause", + .offset = 0x86, + }, + [OCELOT_STAT_TX_64] = { + .name = "tx_frames_below_65_octets", + .offset = 0x87, + }, + [OCELOT_STAT_TX_65_127] = { + .name = "tx_frames_65_to_127_octets", + .offset = 0x88, + }, + [OCELOT_STAT_TX_128_255] = { + .name = "tx_frames_128_255_octets", + .offset = 0x89, + }, + [OCELOT_STAT_TX_256_511] = { + .name = "tx_frames_256_511_octets", + .offset = 0x8A, + }, + [OCELOT_STAT_TX_512_1023] = { + .name = "tx_frames_512_1023_octets", + .offset = 0x8B, + }, + [OCELOT_STAT_TX_1024_1526] = { + .name = "tx_frames_1024_1526_octets", + .offset = 0x8C, + }, + [OCELOT_STAT_TX_1527_MAX] = { + .name = "tx_frames_over_1526_octets", + .offset = 0x8D, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_0] = { + .name = "tx_yellow_prio_0", + .offset = 0x8E, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_1] = { + .name = "tx_yellow_prio_1", + .offset = 0x8F, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_2] = { + .name = "tx_yellow_prio_2", + .offset = 0x90, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_3] = { + .name = "tx_yellow_prio_3", + .offset = 0x91, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_4] = { + .name = "tx_yellow_prio_4", + .offset = 0x92, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_5] = { + .name = "tx_yellow_prio_5", + .offset = 0x93, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_6] = { + .name = "tx_yellow_prio_6", + .offset = 0x94, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_7] = { + .name = "tx_yellow_prio_7", + .offset = 0x95, + }, + [OCELOT_STAT_TX_GREEN_PRIO_0] = { + .name = "tx_green_prio_0", + .offset = 0x96, + }, + [OCELOT_STAT_TX_GREEN_PRIO_1] = { + .name = "tx_green_prio_1", + .offset = 0x97, + }, + [OCELOT_STAT_TX_GREEN_PRIO_2] = { + .name = "tx_green_prio_2", + .offset = 0x98, + }, + [OCELOT_STAT_TX_GREEN_PRIO_3] = { + .name = "tx_green_prio_3", + .offset = 0x99, + }, + [OCELOT_STAT_TX_GREEN_PRIO_4] = { + .name = "tx_green_prio_4", + .offset = 0x9A, + }, + [OCELOT_STAT_TX_GREEN_PRIO_5] = { + .name = "tx_green_prio_5", + .offset = 0x9B, + }, + [OCELOT_STAT_TX_GREEN_PRIO_6] = { + .name = "tx_green_prio_6", + .offset = 0x9C, + }, + [OCELOT_STAT_TX_GREEN_PRIO_7] = { + .name = "tx_green_prio_7", + .offset = 0x9D, + }, + [OCELOT_STAT_TX_AGED] = { + .name = "tx_aged", + .offset = 0x9E, + }, + [OCELOT_STAT_DROP_LOCAL] = { + .name = "drop_local", + .offset = 0x100, + }, + [OCELOT_STAT_DROP_TAIL] = { + .name = "drop_tail", + .offset = 0x101, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_0] = { + .name = "drop_yellow_prio_0", + .offset = 0x102, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_1] = { + .name = "drop_yellow_prio_1", + .offset = 0x103, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_2] = { + .name = "drop_yellow_prio_2", + .offset = 0x104, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_3] = { + .name = "drop_yellow_prio_3", + .offset = 0x105, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_4] = { + .name = "drop_yellow_prio_4", + .offset = 0x106, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_5] = { + .name = "drop_yellow_prio_5", + .offset = 0x107, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_6] = { + .name = "drop_yellow_prio_6", + .offset = 0x108, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_7] = { + .name = "drop_yellow_prio_7", + .offset = 0x109, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_0] = { + .name = "drop_green_prio_0", + .offset = 0x10A, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_1] = { + .name = "drop_green_prio_1", + .offset = 0x10B, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_2] = { + .name = "drop_green_prio_2", + .offset = 0x10C, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_3] = { + .name = "drop_green_prio_3", + .offset = 0x10D, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_4] = { + .name = "drop_green_prio_4", + .offset = 0x10E, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_5] = { + .name = "drop_green_prio_5", + .offset = 0x10F, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_6] = { + .name = "drop_green_prio_6", + .offset = 0x110, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_7] = { + .name = "drop_green_prio_7", + .offset = 0x111, + }, }; static const struct vcap_field vsc9959_vcap_es0_keys[] = { diff --git a/drivers/net/dsa/ocelot/seville_vsc9953.c b/drivers/net/dsa/ocelot/seville_vsc9953.c index ebe9ddbbe2b7..fe5d4642d0bc 100644 --- a/drivers/net/dsa/ocelot/seville_vsc9953.c +++ b/drivers/net/dsa/ocelot/seville_vsc9953.c @@ -545,101 +545,379 @@ static const struct reg_field vsc9953_regfields[REGFIELD_MAX] = { [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 11, 4), }; -static const struct ocelot_stat_layout vsc9953_stats_layout[] = { - { .offset = 0x00, .name = "rx_octets", }, - { .offset = 0x01, .name = "rx_unicast", }, - { .offset = 0x02, .name = "rx_multicast", }, - { .offset = 0x03, .name = "rx_broadcast", }, - { .offset = 0x04, .name = "rx_shorts", }, - { .offset = 0x05, .name = "rx_fragments", }, - { .offset = 0x06, .name = "rx_jabbers", }, - { .offset = 0x07, .name = "rx_crc_align_errs", }, - { .offset = 0x08, .name = "rx_sym_errs", }, - { .offset = 0x09, .name = "rx_frames_below_65_octets", }, - { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", }, - { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", }, - { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", }, - { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", }, - { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", }, - { .offset = 0x0F, .name = "rx_frames_over_1526_octets", }, - { .offset = 0x10, .name = "rx_pause", }, - { .offset = 0x11, .name = "rx_control", }, - { .offset = 0x12, .name = "rx_longs", }, - { .offset = 0x13, .name = "rx_classified_drops", }, - { .offset = 0x14, .name = "rx_red_prio_0", }, - { .offset = 0x15, .name = "rx_red_prio_1", }, - { .offset = 0x16, .name = "rx_red_prio_2", }, - { .offset = 0x17, .name = "rx_red_prio_3", }, - { .offset = 0x18, .name = "rx_red_prio_4", }, - { .offset = 0x19, .name = "rx_red_prio_5", }, - { .offset = 0x1A, .name = "rx_red_prio_6", }, - { .offset = 0x1B, .name = "rx_red_prio_7", }, - { .offset = 0x1C, .name = "rx_yellow_prio_0", }, - { .offset = 0x1D, .name = "rx_yellow_prio_1", }, - { .offset = 0x1E, .name = "rx_yellow_prio_2", }, - { .offset = 0x1F, .name = "rx_yellow_prio_3", }, - { .offset = 0x20, .name = "rx_yellow_prio_4", }, - { .offset = 0x21, .name = "rx_yellow_prio_5", }, - { .offset = 0x22, .name = "rx_yellow_prio_6", }, - { .offset = 0x23, .name = "rx_yellow_prio_7", }, - { .offset = 0x24, .name = "rx_green_prio_0", }, - { .offset = 0x25, .name = "rx_green_prio_1", }, - { .offset = 0x26, .name = "rx_green_prio_2", }, - { .offset = 0x27, .name = "rx_green_prio_3", }, - { .offset = 0x28, .name = "rx_green_prio_4", }, - { .offset = 0x29, .name = "rx_green_prio_5", }, - { .offset = 0x2A, .name = "rx_green_prio_6", }, - { .offset = 0x2B, .name = "rx_green_prio_7", }, - { .offset = 0x40, .name = "tx_octets", }, - { .offset = 0x41, .name = "tx_unicast", }, - { .offset = 0x42, .name = "tx_multicast", }, - { .offset = 0x43, .name = "tx_broadcast", }, - { .offset = 0x44, .name = "tx_collision", }, - { .offset = 0x45, .name = "tx_drops", }, - { .offset = 0x46, .name = "tx_pause", }, - { .offset = 0x47, .name = "tx_frames_below_65_octets", }, - { .offset = 0x48, .name = "tx_frames_65_to_127_octets", }, - { .offset = 0x49, .name = "tx_frames_128_255_octets", }, - { .offset = 0x4A, .name = "tx_frames_256_511_octets", }, - { .offset = 0x4B, .name = "tx_frames_512_1023_octets", }, - { .offset = 0x4C, .name = "tx_frames_1024_1526_octets", }, - { .offset = 0x4D, .name = "tx_frames_over_1526_octets", }, - { .offset = 0x4E, .name = "tx_yellow_prio_0", }, - { .offset = 0x4F, .name = "tx_yellow_prio_1", }, - { .offset = 0x50, .name = "tx_yellow_prio_2", }, - { .offset = 0x51, .name = "tx_yellow_prio_3", }, - { .offset = 0x52, .name = "tx_yellow_prio_4", }, - { .offset = 0x53, .name = "tx_yellow_prio_5", }, - { .offset = 0x54, .name = "tx_yellow_prio_6", }, - { .offset = 0x55, .name = "tx_yellow_prio_7", }, - { .offset = 0x56, .name = "tx_green_prio_0", }, - { .offset = 0x57, .name = "tx_green_prio_1", }, - { .offset = 0x58, .name = "tx_green_prio_2", }, - { .offset = 0x59, .name = "tx_green_prio_3", }, - { .offset = 0x5A, .name = "tx_green_prio_4", }, - { .offset = 0x5B, .name = "tx_green_prio_5", }, - { .offset = 0x5C, .name = "tx_green_prio_6", }, - { .offset = 0x5D, .name = "tx_green_prio_7", }, - { .offset = 0x5E, .name = "tx_aged", }, - { .offset = 0x80, .name = "drop_local", }, - { .offset = 0x81, .name = "drop_tail", }, - { .offset = 0x82, .name = "drop_yellow_prio_0", }, - { .offset = 0x83, .name = "drop_yellow_prio_1", }, - { .offset = 0x84, .name = "drop_yellow_prio_2", }, - { .offset = 0x85, .name = "drop_yellow_prio_3", }, - { .offset = 0x86, .name = "drop_yellow_prio_4", }, - { .offset = 0x87, .name = "drop_yellow_prio_5", }, - { .offset = 0x88, .name = "drop_yellow_prio_6", }, - { .offset = 0x89, .name = "drop_yellow_prio_7", }, - { .offset = 0x8A, .name = "drop_green_prio_0", }, - { .offset = 0x8B, .name = "drop_green_prio_1", }, - { .offset = 0x8C, .name = "drop_green_prio_2", }, - { .offset = 0x8D, .name = "drop_green_prio_3", }, - { .offset = 0x8E, .name = "drop_green_prio_4", }, - { .offset = 0x8F, .name = "drop_green_prio_5", }, - { .offset = 0x90, .name = "drop_green_prio_6", }, - { .offset = 0x91, .name = "drop_green_prio_7", }, - OCELOT_STAT_END +static const struct ocelot_stat_layout vsc9953_stats_layout[OCELOT_NUM_STATS] = { + [OCELOT_STAT_RX_OCTETS] = { + .name = "rx_octets", + .offset = 0x00, + }, + [OCELOT_STAT_RX_UNICAST] = { + .name = "rx_unicast", + .offset = 0x01, + }, + [OCELOT_STAT_RX_MULTICAST] = { + .name = "rx_multicast", + .offset = 0x02, + }, + [OCELOT_STAT_RX_BROADCAST] = { + .name = "rx_broadcast", + .offset = 0x03, + }, + [OCELOT_STAT_RX_SHORTS] = { + .name = "rx_shorts", + .offset = 0x04, + }, + [OCELOT_STAT_RX_FRAGMENTS] = { + .name = "rx_fragments", + .offset = 0x05, + }, + [OCELOT_STAT_RX_JABBERS] = { + .name = "rx_jabbers", + .offset = 0x06, + }, + [OCELOT_STAT_RX_CRC_ALIGN_ERRS] = { + .name = "rx_crc_align_errs", + .offset = 0x07, + }, + [OCELOT_STAT_RX_SYM_ERRS] = { + .name = "rx_sym_errs", + .offset = 0x08, + }, + [OCELOT_STAT_RX_64] = { + .name = "rx_frames_below_65_octets", + .offset = 0x09, + }, + [OCELOT_STAT_RX_65_127] = { + .name = "rx_frames_65_to_127_octets", + .offset = 0x0A, + }, + [OCELOT_STAT_RX_128_255] = { + .name = "rx_frames_128_to_255_octets", + .offset = 0x0B, + }, + [OCELOT_STAT_RX_256_511] = { + .name = "rx_frames_256_to_511_octets", + .offset = 0x0C, + }, + [OCELOT_STAT_RX_512_1023] = { + .name = "rx_frames_512_to_1023_octets", + .offset = 0x0D, + }, + [OCELOT_STAT_RX_1024_1526] = { + .name = "rx_frames_1024_to_1526_octets", + .offset = 0x0E, + }, + [OCELOT_STAT_RX_1527_MAX] = { + .name = "rx_frames_over_1526_octets", + .offset = 0x0F, + }, + [OCELOT_STAT_RX_PAUSE] = { + .name = "rx_pause", + .offset = 0x10, + }, + [OCELOT_STAT_RX_CONTROL] = { + .name = "rx_control", + .offset = 0x11, + }, + [OCELOT_STAT_RX_LONGS] = { + .name = "rx_longs", + .offset = 0x12, + }, + [OCELOT_STAT_RX_CLASSIFIED_DROPS] = { + .name = "rx_classified_drops", + .offset = 0x13, + }, + [OCELOT_STAT_RX_RED_PRIO_0] = { + .name = "rx_red_prio_0", + .offset = 0x14, + }, + [OCELOT_STAT_RX_RED_PRIO_1] = { + .name = "rx_red_prio_1", + .offset = 0x15, + }, + [OCELOT_STAT_RX_RED_PRIO_2] = { + .name = "rx_red_prio_2", + .offset = 0x16, + }, + [OCELOT_STAT_RX_RED_PRIO_3] = { + .name = "rx_red_prio_3", + .offset = 0x17, + }, + [OCELOT_STAT_RX_RED_PRIO_4] = { + .name = "rx_red_prio_4", + .offset = 0x18, + }, + [OCELOT_STAT_RX_RED_PRIO_5] = { + .name = "rx_red_prio_5", + .offset = 0x19, + }, + [OCELOT_STAT_RX_RED_PRIO_6] = { + .name = "rx_red_prio_6", + .offset = 0x1A, + }, + [OCELOT_STAT_RX_RED_PRIO_7] = { + .name = "rx_red_prio_7", + .offset = 0x1B, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_0] = { + .name = "rx_yellow_prio_0", + .offset = 0x1C, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_1] = { + .name = "rx_yellow_prio_1", + .offset = 0x1D, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_2] = { + .name = "rx_yellow_prio_2", + .offset = 0x1E, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_3] = { + .name = "rx_yellow_prio_3", + .offset = 0x1F, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_4] = { + .name = "rx_yellow_prio_4", + .offset = 0x20, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_5] = { + .name = "rx_yellow_prio_5", + .offset = 0x21, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_6] = { + .name = "rx_yellow_prio_6", + .offset = 0x22, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_7] = { + .name = "rx_yellow_prio_7", + .offset = 0x23, + }, + [OCELOT_STAT_RX_GREEN_PRIO_0] = { + .name = "rx_green_prio_0", + .offset = 0x24, + }, + [OCELOT_STAT_RX_GREEN_PRIO_1] = { + .name = "rx_green_prio_1", + .offset = 0x25, + }, + [OCELOT_STAT_RX_GREEN_PRIO_2] = { + .name = "rx_green_prio_2", + .offset = 0x26, + }, + [OCELOT_STAT_RX_GREEN_PRIO_3] = { + .name = "rx_green_prio_3", + .offset = 0x27, + }, + [OCELOT_STAT_RX_GREEN_PRIO_4] = { + .name = "rx_green_prio_4", + .offset = 0x28, + }, + [OCELOT_STAT_RX_GREEN_PRIO_5] = { + .name = "rx_green_prio_5", + .offset = 0x29, + }, + [OCELOT_STAT_RX_GREEN_PRIO_6] = { + .name = "rx_green_prio_6", + .offset = 0x2A, + }, + [OCELOT_STAT_RX_GREEN_PRIO_7] = { + .name = "rx_green_prio_7", + .offset = 0x2B, + }, + [OCELOT_STAT_TX_OCTETS] = { + .name = "tx_octets", + .offset = 0x40, + }, + [OCELOT_STAT_TX_UNICAST] = { + .name = "tx_unicast", + .offset = 0x41, + }, + [OCELOT_STAT_TX_MULTICAST] = { + .name = "tx_multicast", + .offset = 0x42, + }, + [OCELOT_STAT_TX_BROADCAST] = { + .name = "tx_broadcast", + .offset = 0x43, + }, + [OCELOT_STAT_TX_COLLISION] = { + .name = "tx_collision", + .offset = 0x44, + }, + [OCELOT_STAT_TX_DROPS] = { + .name = "tx_drops", + .offset = 0x45, + }, + [OCELOT_STAT_TX_PAUSE] = { + .name = "tx_pause", + .offset = 0x46, + }, + [OCELOT_STAT_TX_64] = { + .name = "tx_frames_below_65_octets", + .offset = 0x47, + }, + [OCELOT_STAT_TX_65_127] = { + .name = "tx_frames_65_to_127_octets", + .offset = 0x48, + }, + [OCELOT_STAT_TX_128_255] = { + .name = "tx_frames_128_255_octets", + .offset = 0x49, + }, + [OCELOT_STAT_TX_256_511] = { + .name = "tx_frames_256_511_octets", + .offset = 0x4A, + }, + [OCELOT_STAT_TX_512_1023] = { + .name = "tx_frames_512_1023_octets", + .offset = 0x4B, + }, + [OCELOT_STAT_TX_1024_1526] = { + .name = "tx_frames_1024_1526_octets", + .offset = 0x4C, + }, + [OCELOT_STAT_TX_1527_MAX] = { + .name = "tx_frames_over_1526_octets", + .offset = 0x4D, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_0] = { + .name = "tx_yellow_prio_0", + .offset = 0x4E, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_1] = { + .name = "tx_yellow_prio_1", + .offset = 0x4F, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_2] = { + .name = "tx_yellow_prio_2", + .offset = 0x50, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_3] = { + .name = "tx_yellow_prio_3", + .offset = 0x51, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_4] = { + .name = "tx_yellow_prio_4", + .offset = 0x52, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_5] = { + .name = "tx_yellow_prio_5", + .offset = 0x53, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_6] = { + .name = "tx_yellow_prio_6", + .offset = 0x54, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_7] = { + .name = "tx_yellow_prio_7", + .offset = 0x55, + }, + [OCELOT_STAT_TX_GREEN_PRIO_0] = { + .name = "tx_green_prio_0", + .offset = 0x56, + }, + [OCELOT_STAT_TX_GREEN_PRIO_1] = { + .name = "tx_green_prio_1", + .offset = 0x57, + }, + [OCELOT_STAT_TX_GREEN_PRIO_2] = { + .name = "tx_green_prio_2", + .offset = 0x58, + }, + [OCELOT_STAT_TX_GREEN_PRIO_3] = { + .name = "tx_green_prio_3", + .offset = 0x59, + }, + [OCELOT_STAT_TX_GREEN_PRIO_4] = { + .name = "tx_green_prio_4", + .offset = 0x5A, + }, + [OCELOT_STAT_TX_GREEN_PRIO_5] = { + .name = "tx_green_prio_5", + .offset = 0x5B, + }, + [OCELOT_STAT_TX_GREEN_PRIO_6] = { + .name = "tx_green_prio_6", + .offset = 0x5C, + }, + [OCELOT_STAT_TX_GREEN_PRIO_7] = { + .name = "tx_green_prio_7", + .offset = 0x5D, + }, + [OCELOT_STAT_TX_AGED] = { + .name = "tx_aged", + .offset = 0x5E, + }, + [OCELOT_STAT_DROP_LOCAL] = { + .name = "drop_local", + .offset = 0x80, + }, + [OCELOT_STAT_DROP_TAIL] = { + .name = "drop_tail", + .offset = 0x81, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_0] = { + .name = "drop_yellow_prio_0", + .offset = 0x82, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_1] = { + .name = "drop_yellow_prio_1", + .offset = 0x83, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_2] = { + .name = "drop_yellow_prio_2", + .offset = 0x84, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_3] = { + .name = "drop_yellow_prio_3", + .offset = 0x85, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_4] = { + .name = "drop_yellow_prio_4", + .offset = 0x86, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_5] = { + .name = "drop_yellow_prio_5", + .offset = 0x87, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_6] = { + .name = "drop_yellow_prio_6", + .offset = 0x88, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_7] = { + .name = "drop_yellow_prio_7", + .offset = 0x89, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_0] = { + .name = "drop_green_prio_0", + .offset = 0x8A, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_1] = { + .name = "drop_green_prio_1", + .offset = 0x8B, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_2] = { + .name = "drop_green_prio_2", + .offset = 0x8C, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_3] = { + .name = "drop_green_prio_3", + .offset = 0x8D, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_4] = { + .name = "drop_green_prio_4", + .offset = 0x8E, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_5] = { + .name = "drop_green_prio_5", + .offset = 0x8F, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_6] = { + .name = "drop_green_prio_6", + .offset = 0x90, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_7] = { + .name = "drop_green_prio_7", + .offset = 0x91, + }, }; static const struct vcap_field vsc9953_vcap_es0_keys[] = { diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c index c67f162f8ab5..68991b021c56 100644 --- a/drivers/net/ethernet/mscc/ocelot.c +++ b/drivers/net/ethernet/mscc/ocelot.c @@ -1860,16 +1860,20 @@ void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) if (sset != ETH_SS_STATS) return; - for (i = 0; i < ocelot->num_stats; i++) + for (i = 0; i < OCELOT_NUM_STATS; i++) { + if (ocelot->stats_layout[i].name[0] == '\0') + continue; + memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, ETH_GSTRING_LEN); + } } EXPORT_SYMBOL(ocelot_get_strings); /* Caller must hold &ocelot->stats_lock */ static int ocelot_port_update_stats(struct ocelot *ocelot, int port) { - unsigned int idx = port * ocelot->num_stats; + unsigned int idx = port * OCELOT_NUM_STATS; struct ocelot_stats_region *region; int err, j; @@ -1930,9 +1934,15 @@ void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) /* check and update now */ err = ocelot_port_update_stats(ocelot, port); - /* Copy all counters */ - for (i = 0; i < ocelot->num_stats; i++) - *data++ = ocelot->stats[port * ocelot->num_stats + i]; + /* Copy all supported counters */ + for (i = 0; i < OCELOT_NUM_STATS; i++) { + int index = port * OCELOT_NUM_STATS + i; + + if (ocelot->stats_layout[i].name[0] == '\0') + continue; + + *data++ = ocelot->stats[index]; + } spin_unlock(&ocelot->stats_lock); @@ -1943,10 +1953,16 @@ EXPORT_SYMBOL(ocelot_get_ethtool_stats); int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) { + int i, num_stats = 0; + if (sset != ETH_SS_STATS) return -EOPNOTSUPP; - return ocelot->num_stats; + for (i = 0; i < OCELOT_NUM_STATS; i++) + if (ocelot->stats_layout[i].name[0] != '\0') + num_stats++; + + return num_stats; } EXPORT_SYMBOL(ocelot_get_sset_count); @@ -1958,7 +1974,10 @@ static int ocelot_prepare_stats_regions(struct ocelot *ocelot) INIT_LIST_HEAD(&ocelot->stats_regions); - for (i = 0; i < ocelot->num_stats; i++) { + for (i = 0; i < OCELOT_NUM_STATS; i++) { + if (ocelot->stats_layout[i].name[0] == '\0') + continue; + if (region && ocelot->stats_layout[i].offset == last + 1) { region->count++; } else { @@ -3340,7 +3359,6 @@ static void ocelot_detect_features(struct ocelot *ocelot) int ocelot_init(struct ocelot *ocelot) { - const struct ocelot_stat_layout *stat; char queue_name[32]; int i, ret; u32 port; @@ -3353,12 +3371,8 @@ int ocelot_init(struct ocelot *ocelot) } } - ocelot->num_stats = 0; - for_each_stat(ocelot, stat) - ocelot->num_stats++; - ocelot->stats = devm_kcalloc(ocelot->dev, - ocelot->num_phys_ports * ocelot->num_stats, + ocelot->num_phys_ports * OCELOT_NUM_STATS, sizeof(u64), GFP_KERNEL); if (!ocelot->stats) return -ENOMEM; diff --git a/drivers/net/ethernet/mscc/ocelot_vsc7514.c b/drivers/net/ethernet/mscc/ocelot_vsc7514.c index 961f803aca19..9ff910560043 100644 --- a/drivers/net/ethernet/mscc/ocelot_vsc7514.c +++ b/drivers/net/ethernet/mscc/ocelot_vsc7514.c @@ -96,101 +96,379 @@ static const struct reg_field ocelot_regfields[REGFIELD_MAX] = { [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 12, 4), }; -static const struct ocelot_stat_layout ocelot_stats_layout[] = { - { .name = "rx_octets", .offset = 0x00, }, - { .name = "rx_unicast", .offset = 0x01, }, - { .name = "rx_multicast", .offset = 0x02, }, - { .name = "rx_broadcast", .offset = 0x03, }, - { .name = "rx_shorts", .offset = 0x04, }, - { .name = "rx_fragments", .offset = 0x05, }, - { .name = "rx_jabbers", .offset = 0x06, }, - { .name = "rx_crc_align_errs", .offset = 0x07, }, - { .name = "rx_sym_errs", .offset = 0x08, }, - { .name = "rx_frames_below_65_octets", .offset = 0x09, }, - { .name = "rx_frames_65_to_127_octets", .offset = 0x0A, }, - { .name = "rx_frames_128_to_255_octets", .offset = 0x0B, }, - { .name = "rx_frames_256_to_511_octets", .offset = 0x0C, }, - { .name = "rx_frames_512_to_1023_octets", .offset = 0x0D, }, - { .name = "rx_frames_1024_to_1526_octets", .offset = 0x0E, }, - { .name = "rx_frames_over_1526_octets", .offset = 0x0F, }, - { .name = "rx_pause", .offset = 0x10, }, - { .name = "rx_control", .offset = 0x11, }, - { .name = "rx_longs", .offset = 0x12, }, - { .name = "rx_classified_drops", .offset = 0x13, }, - { .name = "rx_red_prio_0", .offset = 0x14, }, - { .name = "rx_red_prio_1", .offset = 0x15, }, - { .name = "rx_red_prio_2", .offset = 0x16, }, - { .name = "rx_red_prio_3", .offset = 0x17, }, - { .name = "rx_red_prio_4", .offset = 0x18, }, - { .name = "rx_red_prio_5", .offset = 0x19, }, - { .name = "rx_red_prio_6", .offset = 0x1A, }, - { .name = "rx_red_prio_7", .offset = 0x1B, }, - { .name = "rx_yellow_prio_0", .offset = 0x1C, }, - { .name = "rx_yellow_prio_1", .offset = 0x1D, }, - { .name = "rx_yellow_prio_2", .offset = 0x1E, }, - { .name = "rx_yellow_prio_3", .offset = 0x1F, }, - { .name = "rx_yellow_prio_4", .offset = 0x20, }, - { .name = "rx_yellow_prio_5", .offset = 0x21, }, - { .name = "rx_yellow_prio_6", .offset = 0x22, }, - { .name = "rx_yellow_prio_7", .offset = 0x23, }, - { .name = "rx_green_prio_0", .offset = 0x24, }, - { .name = "rx_green_prio_1", .offset = 0x25, }, - { .name = "rx_green_prio_2", .offset = 0x26, }, - { .name = "rx_green_prio_3", .offset = 0x27, }, - { .name = "rx_green_prio_4", .offset = 0x28, }, - { .name = "rx_green_prio_5", .offset = 0x29, }, - { .name = "rx_green_prio_6", .offset = 0x2A, }, - { .name = "rx_green_prio_7", .offset = 0x2B, }, - { .name = "tx_octets", .offset = 0x40, }, - { .name = "tx_unicast", .offset = 0x41, }, - { .name = "tx_multicast", .offset = 0x42, }, - { .name = "tx_broadcast", .offset = 0x43, }, - { .name = "tx_collision", .offset = 0x44, }, - { .name = "tx_drops", .offset = 0x45, }, - { .name = "tx_pause", .offset = 0x46, }, - { .name = "tx_frames_below_65_octets", .offset = 0x47, }, - { .name = "tx_frames_65_to_127_octets", .offset = 0x48, }, - { .name = "tx_frames_128_255_octets", .offset = 0x49, }, - { .name = "tx_frames_256_511_octets", .offset = 0x4A, }, - { .name = "tx_frames_512_1023_octets", .offset = 0x4B, }, - { .name = "tx_frames_1024_1526_octets", .offset = 0x4C, }, - { .name = "tx_frames_over_1526_octets", .offset = 0x4D, }, - { .name = "tx_yellow_prio_0", .offset = 0x4E, }, - { .name = "tx_yellow_prio_1", .offset = 0x4F, }, - { .name = "tx_yellow_prio_2", .offset = 0x50, }, - { .name = "tx_yellow_prio_3", .offset = 0x51, }, - { .name = "tx_yellow_prio_4", .offset = 0x52, }, - { .name = "tx_yellow_prio_5", .offset = 0x53, }, - { .name = "tx_yellow_prio_6", .offset = 0x54, }, - { .name = "tx_yellow_prio_7", .offset = 0x55, }, - { .name = "tx_green_prio_0", .offset = 0x56, }, - { .name = "tx_green_prio_1", .offset = 0x57, }, - { .name = "tx_green_prio_2", .offset = 0x58, }, - { .name = "tx_green_prio_3", .offset = 0x59, }, - { .name = "tx_green_prio_4", .offset = 0x5A, }, - { .name = "tx_green_prio_5", .offset = 0x5B, }, - { .name = "tx_green_prio_6", .offset = 0x5C, }, - { .name = "tx_green_prio_7", .offset = 0x5D, }, - { .name = "tx_aged", .offset = 0x5E, }, - { .name = "drop_local", .offset = 0x80, }, - { .name = "drop_tail", .offset = 0x81, }, - { .name = "drop_yellow_prio_0", .offset = 0x82, }, - { .name = "drop_yellow_prio_1", .offset = 0x83, }, - { .name = "drop_yellow_prio_2", .offset = 0x84, }, - { .name = "drop_yellow_prio_3", .offset = 0x85, }, - { .name = "drop_yellow_prio_4", .offset = 0x86, }, - { .name = "drop_yellow_prio_5", .offset = 0x87, }, - { .name = "drop_yellow_prio_6", .offset = 0x88, }, - { .name = "drop_yellow_prio_7", .offset = 0x89, }, - { .name = "drop_green_prio_0", .offset = 0x8A, }, - { .name = "drop_green_prio_1", .offset = 0x8B, }, - { .name = "drop_green_prio_2", .offset = 0x8C, }, - { .name = "drop_green_prio_3", .offset = 0x8D, }, - { .name = "drop_green_prio_4", .offset = 0x8E, }, - { .name = "drop_green_prio_5", .offset = 0x8F, }, - { .name = "drop_green_prio_6", .offset = 0x90, }, - { .name = "drop_green_prio_7", .offset = 0x91, }, - OCELOT_STAT_END +static const struct ocelot_stat_layout ocelot_stats_layout[OCELOT_NUM_STATS] = { + [OCELOT_STAT_RX_OCTETS] = { + .name = "rx_octets", + .offset = 0x00, + }, + [OCELOT_STAT_RX_UNICAST] = { + .name = "rx_unicast", + .offset = 0x01, + }, + [OCELOT_STAT_RX_MULTICAST] = { + .name = "rx_multicast", + .offset = 0x02, + }, + [OCELOT_STAT_RX_BROADCAST] = { + .name = "rx_broadcast", + .offset = 0x03, + }, + [OCELOT_STAT_RX_SHORTS] = { + .name = "rx_shorts", + .offset = 0x04, + }, + [OCELOT_STAT_RX_FRAGMENTS] = { + .name = "rx_fragments", + .offset = 0x05, + }, + [OCELOT_STAT_RX_JABBERS] = { + .name = "rx_jabbers", + .offset = 0x06, + }, + [OCELOT_STAT_RX_CRC_ALIGN_ERRS] = { + .name = "rx_crc_align_errs", + .offset = 0x07, + }, + [OCELOT_STAT_RX_SYM_ERRS] = { + .name = "rx_sym_errs", + .offset = 0x08, + }, + [OCELOT_STAT_RX_64] = { + .name = "rx_frames_below_65_octets", + .offset = 0x09, + }, + [OCELOT_STAT_RX_65_127] = { + .name = "rx_frames_65_to_127_octets", + .offset = 0x0A, + }, + [OCELOT_STAT_RX_128_255] = { + .name = "rx_frames_128_to_255_octets", + .offset = 0x0B, + }, + [OCELOT_STAT_RX_256_511] = { + .name = "rx_frames_256_to_511_octets", + .offset = 0x0C, + }, + [OCELOT_STAT_RX_512_1023] = { + .name = "rx_frames_512_to_1023_octets", + .offset = 0x0D, + }, + [OCELOT_STAT_RX_1024_1526] = { + .name = "rx_frames_1024_to_1526_octets", + .offset = 0x0E, + }, + [OCELOT_STAT_RX_1527_MAX] = { + .name = "rx_frames_over_1526_octets", + .offset = 0x0F, + }, + [OCELOT_STAT_RX_PAUSE] = { + .name = "rx_pause", + .offset = 0x10, + }, + [OCELOT_STAT_RX_CONTROL] = { + .name = "rx_control", + .offset = 0x11, + }, + [OCELOT_STAT_RX_LONGS] = { + .name = "rx_longs", + .offset = 0x12, + }, + [OCELOT_STAT_RX_CLASSIFIED_DROPS] = { + .name = "rx_classified_drops", + .offset = 0x13, + }, + [OCELOT_STAT_RX_RED_PRIO_0] = { + .name = "rx_red_prio_0", + .offset = 0x14, + }, + [OCELOT_STAT_RX_RED_PRIO_1] = { + .name = "rx_red_prio_1", + .offset = 0x15, + }, + [OCELOT_STAT_RX_RED_PRIO_2] = { + .name = "rx_red_prio_2", + .offset = 0x16, + }, + [OCELOT_STAT_RX_RED_PRIO_3] = { + .name = "rx_red_prio_3", + .offset = 0x17, + }, + [OCELOT_STAT_RX_RED_PRIO_4] = { + .name = "rx_red_prio_4", + .offset = 0x18, + }, + [OCELOT_STAT_RX_RED_PRIO_5] = { + .name = "rx_red_prio_5", + .offset = 0x19, + }, + [OCELOT_STAT_RX_RED_PRIO_6] = { + .name = "rx_red_prio_6", + .offset = 0x1A, + }, + [OCELOT_STAT_RX_RED_PRIO_7] = { + .name = "rx_red_prio_7", + .offset = 0x1B, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_0] = { + .name = "rx_yellow_prio_0", + .offset = 0x1C, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_1] = { + .name = "rx_yellow_prio_1", + .offset = 0x1D, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_2] = { + .name = "rx_yellow_prio_2", + .offset = 0x1E, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_3] = { + .name = "rx_yellow_prio_3", + .offset = 0x1F, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_4] = { + .name = "rx_yellow_prio_4", + .offset = 0x20, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_5] = { + .name = "rx_yellow_prio_5", + .offset = 0x21, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_6] = { + .name = "rx_yellow_prio_6", + .offset = 0x22, + }, + [OCELOT_STAT_RX_YELLOW_PRIO_7] = { + .name = "rx_yellow_prio_7", + .offset = 0x23, + }, + [OCELOT_STAT_RX_GREEN_PRIO_0] = { + .name = "rx_green_prio_0", + .offset = 0x24, + }, + [OCELOT_STAT_RX_GREEN_PRIO_1] = { + .name = "rx_green_prio_1", + .offset = 0x25, + }, + [OCELOT_STAT_RX_GREEN_PRIO_2] = { + .name = "rx_green_prio_2", + .offset = 0x26, + }, + [OCELOT_STAT_RX_GREEN_PRIO_3] = { + .name = "rx_green_prio_3", + .offset = 0x27, + }, + [OCELOT_STAT_RX_GREEN_PRIO_4] = { + .name = "rx_green_prio_4", + .offset = 0x28, + }, + [OCELOT_STAT_RX_GREEN_PRIO_5] = { + .name = "rx_green_prio_5", + .offset = 0x29, + }, + [OCELOT_STAT_RX_GREEN_PRIO_6] = { + .name = "rx_green_prio_6", + .offset = 0x2A, + }, + [OCELOT_STAT_RX_GREEN_PRIO_7] = { + .name = "rx_green_prio_7", + .offset = 0x2B, + }, + [OCELOT_STAT_TX_OCTETS] = { + .name = "tx_octets", + .offset = 0x40, + }, + [OCELOT_STAT_TX_UNICAST] = { + .name = "tx_unicast", + .offset = 0x41, + }, + [OCELOT_STAT_TX_MULTICAST] = { + .name = "tx_multicast", + .offset = 0x42, + }, + [OCELOT_STAT_TX_BROADCAST] = { + .name = "tx_broadcast", + .offset = 0x43, + }, + [OCELOT_STAT_TX_COLLISION] = { + .name = "tx_collision", + .offset = 0x44, + }, + [OCELOT_STAT_TX_DROPS] = { + .name = "tx_drops", + .offset = 0x45, + }, + [OCELOT_STAT_TX_PAUSE] = { + .name = "tx_pause", + .offset = 0x46, + }, + [OCELOT_STAT_TX_64] = { + .name = "tx_frames_below_65_octets", + .offset = 0x47, + }, + [OCELOT_STAT_TX_65_127] = { + .name = "tx_frames_65_to_127_octets", + .offset = 0x48, + }, + [OCELOT_STAT_TX_128_255] = { + .name = "tx_frames_128_255_octets", + .offset = 0x49, + }, + [OCELOT_STAT_TX_256_511] = { + .name = "tx_frames_256_511_octets", + .offset = 0x4A, + }, + [OCELOT_STAT_TX_512_1023] = { + .name = "tx_frames_512_1023_octets", + .offset = 0x4B, + }, + [OCELOT_STAT_TX_1024_1526] = { + .name = "tx_frames_1024_1526_octets", + .offset = 0x4C, + }, + [OCELOT_STAT_TX_1527_MAX] = { + .name = "tx_frames_over_1526_octets", + .offset = 0x4D, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_0] = { + .name = "tx_yellow_prio_0", + .offset = 0x4E, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_1] = { + .name = "tx_yellow_prio_1", + .offset = 0x4F, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_2] = { + .name = "tx_yellow_prio_2", + .offset = 0x50, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_3] = { + .name = "tx_yellow_prio_3", + .offset = 0x51, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_4] = { + .name = "tx_yellow_prio_4", + .offset = 0x52, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_5] = { + .name = "tx_yellow_prio_5", + .offset = 0x53, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_6] = { + .name = "tx_yellow_prio_6", + .offset = 0x54, + }, + [OCELOT_STAT_TX_YELLOW_PRIO_7] = { + .name = "tx_yellow_prio_7", + .offset = 0x55, + }, + [OCELOT_STAT_TX_GREEN_PRIO_0] = { + .name = "tx_green_prio_0", + .offset = 0x56, + }, + [OCELOT_STAT_TX_GREEN_PRIO_1] = { + .name = "tx_green_prio_1", + .offset = 0x57, + }, + [OCELOT_STAT_TX_GREEN_PRIO_2] = { + .name = "tx_green_prio_2", + .offset = 0x58, + }, + [OCELOT_STAT_TX_GREEN_PRIO_3] = { + .name = "tx_green_prio_3", + .offset = 0x59, + }, + [OCELOT_STAT_TX_GREEN_PRIO_4] = { + .name = "tx_green_prio_4", + .offset = 0x5A, + }, + [OCELOT_STAT_TX_GREEN_PRIO_5] = { + .name = "tx_green_prio_5", + .offset = 0x5B, + }, + [OCELOT_STAT_TX_GREEN_PRIO_6] = { + .name = "tx_green_prio_6", + .offset = 0x5C, + }, + [OCELOT_STAT_TX_GREEN_PRIO_7] = { + .name = "tx_green_prio_7", + .offset = 0x5D, + }, + [OCELOT_STAT_TX_AGED] = { + .name = "tx_aged", + .offset = 0x5E, + }, + [OCELOT_STAT_DROP_LOCAL] = { + .name = "drop_local", + .offset = 0x80, + }, + [OCELOT_STAT_DROP_TAIL] = { + .name = "drop_tail", + .offset = 0x81, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_0] = { + .name = "drop_yellow_prio_0", + .offset = 0x82, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_1] = { + .name = "drop_yellow_prio_1", + .offset = 0x83, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_2] = { + .name = "drop_yellow_prio_2", + .offset = 0x84, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_3] = { + .name = "drop_yellow_prio_3", + .offset = 0x85, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_4] = { + .name = "drop_yellow_prio_4", + .offset = 0x86, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_5] = { + .name = "drop_yellow_prio_5", + .offset = 0x87, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_6] = { + .name = "drop_yellow_prio_6", + .offset = 0x88, + }, + [OCELOT_STAT_DROP_YELLOW_PRIO_7] = { + .name = "drop_yellow_prio_7", + .offset = 0x89, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_0] = { + .name = "drop_green_prio_0", + .offset = 0x8A, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_1] = { + .name = "drop_green_prio_1", + .offset = 0x8B, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_2] = { + .name = "drop_green_prio_2", + .offset = 0x8C, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_3] = { + .name = "drop_green_prio_3", + .offset = 0x8D, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_4] = { + .name = "drop_green_prio_4", + .offset = 0x8E, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_5] = { + .name = "drop_green_prio_5", + .offset = 0x8F, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_6] = { + .name = "drop_green_prio_6", + .offset = 0x90, + }, + [OCELOT_STAT_DROP_GREEN_PRIO_7] = { + .name = "drop_green_prio_7", + .offset = 0x91, + }, }; static void ocelot_pll5_init(struct ocelot *ocelot) diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h index 72b9474391da..2428bc64cb1d 100644 --- a/include/soc/mscc/ocelot.h +++ b/include/soc/mscc/ocelot.h @@ -105,11 +105,6 @@ #define REG_RESERVED_ADDR 0xffffffff #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR) -#define for_each_stat(ocelot, stat) \ - for ((stat) = (ocelot)->stats_layout; \ - ((stat)->name[0] != '\0'); \ - (stat)++) - enum ocelot_target { ANA = 1, QS, @@ -540,13 +535,108 @@ enum ocelot_ptp_pins { TOD_ACC_PIN }; +enum ocelot_stat { + OCELOT_STAT_RX_OCTETS, + OCELOT_STAT_RX_UNICAST, + OCELOT_STAT_RX_MULTICAST, + OCELOT_STAT_RX_BROADCAST, + OCELOT_STAT_RX_SHORTS, + OCELOT_STAT_RX_FRAGMENTS, + OCELOT_STAT_RX_JABBERS, + OCELOT_STAT_RX_CRC_ALIGN_ERRS, + OCELOT_STAT_RX_SYM_ERRS, + OCELOT_STAT_RX_64, + OCELOT_STAT_RX_65_127, + OCELOT_STAT_RX_128_255, + OCELOT_STAT_RX_256_511, + OCELOT_STAT_RX_512_1023, + OCELOT_STAT_RX_1024_1526, + OCELOT_STAT_RX_1527_MAX, + OCELOT_STAT_RX_PAUSE, + OCELOT_STAT_RX_CONTROL, + OCELOT_STAT_RX_LONGS, + OCELOT_STAT_RX_CLASSIFIED_DROPS, + OCELOT_STAT_RX_RED_PRIO_0, + OCELOT_STAT_RX_RED_PRIO_1, + OCELOT_STAT_RX_RED_PRIO_2, + OCELOT_STAT_RX_RED_PRIO_3, + OCELOT_STAT_RX_RED_PRIO_4, + OCELOT_STAT_RX_RED_PRIO_5, + OCELOT_STAT_RX_RED_PRIO_6, + OCELOT_STAT_RX_RED_PRIO_7, + OCELOT_STAT_RX_YELLOW_PRIO_0, + OCELOT_STAT_RX_YELLOW_PRIO_1, + OCELOT_STAT_RX_YELLOW_PRIO_2, + OCELOT_STAT_RX_YELLOW_PRIO_3, + OCELOT_STAT_RX_YELLOW_PRIO_4, + OCELOT_STAT_RX_YELLOW_PRIO_5, + OCELOT_STAT_RX_YELLOW_PRIO_6, + OCELOT_STAT_RX_YELLOW_PRIO_7, + OCELOT_STAT_RX_GREEN_PRIO_0, + OCELOT_STAT_RX_GREEN_PRIO_1, + OCELOT_STAT_RX_GREEN_PRIO_2, + OCELOT_STAT_RX_GREEN_PRIO_3, + OCELOT_STAT_RX_GREEN_PRIO_4, + OCELOT_STAT_RX_GREEN_PRIO_5, + OCELOT_STAT_RX_GREEN_PRIO_6, + OCELOT_STAT_RX_GREEN_PRIO_7, + OCELOT_STAT_TX_OCTETS, + OCELOT_STAT_TX_UNICAST, + OCELOT_STAT_TX_MULTICAST, + OCELOT_STAT_TX_BROADCAST, + OCELOT_STAT_TX_COLLISION, + OCELOT_STAT_TX_DROPS, + OCELOT_STAT_TX_PAUSE, + OCELOT_STAT_TX_64, + OCELOT_STAT_TX_65_127, + OCELOT_STAT_TX_128_255, + OCELOT_STAT_TX_256_511, + OCELOT_STAT_TX_512_1023, + OCELOT_STAT_TX_1024_1526, + OCELOT_STAT_TX_1527_MAX, + OCELOT_STAT_TX_YELLOW_PRIO_0, + OCELOT_STAT_TX_YELLOW_PRIO_1, + OCELOT_STAT_TX_YELLOW_PRIO_2, + OCELOT_STAT_TX_YELLOW_PRIO_3, + OCELOT_STAT_TX_YELLOW_PRIO_4, + OCELOT_STAT_TX_YELLOW_PRIO_5, + OCELOT_STAT_TX_YELLOW_PRIO_6, + OCELOT_STAT_TX_YELLOW_PRIO_7, + OCELOT_STAT_TX_GREEN_PRIO_0, + OCELOT_STAT_TX_GREEN_PRIO_1, + OCELOT_STAT_TX_GREEN_PRIO_2, + OCELOT_STAT_TX_GREEN_PRIO_3, + OCELOT_STAT_TX_GREEN_PRIO_4, + OCELOT_STAT_TX_GREEN_PRIO_5, + OCELOT_STAT_TX_GREEN_PRIO_6, + OCELOT_STAT_TX_GREEN_PRIO_7, + OCELOT_STAT_TX_AGED, + OCELOT_STAT_DROP_LOCAL, + OCELOT_STAT_DROP_TAIL, + OCELOT_STAT_DROP_YELLOW_PRIO_0, + OCELOT_STAT_DROP_YELLOW_PRIO_1, + OCELOT_STAT_DROP_YELLOW_PRIO_2, + OCELOT_STAT_DROP_YELLOW_PRIO_3, + OCELOT_STAT_DROP_YELLOW_PRIO_4, + OCELOT_STAT_DROP_YELLOW_PRIO_5, + OCELOT_STAT_DROP_YELLOW_PRIO_6, + OCELOT_STAT_DROP_YELLOW_PRIO_7, + OCELOT_STAT_DROP_GREEN_PRIO_0, + OCELOT_STAT_DROP_GREEN_PRIO_1, + OCELOT_STAT_DROP_GREEN_PRIO_2, + OCELOT_STAT_DROP_GREEN_PRIO_3, + OCELOT_STAT_DROP_GREEN_PRIO_4, + OCELOT_STAT_DROP_GREEN_PRIO_5, + OCELOT_STAT_DROP_GREEN_PRIO_6, + OCELOT_STAT_DROP_GREEN_PRIO_7, + OCELOT_NUM_STATS, +}; + struct ocelot_stat_layout { u32 offset; char name[ETH_GSTRING_LEN]; }; -#define OCELOT_STAT_END { .name = "" } - struct ocelot_stats_region { struct list_head node; u32 offset; @@ -709,7 +799,6 @@ struct ocelot { const u32 *const *map; const struct ocelot_stat_layout *stats_layout; struct list_head stats_regions; - unsigned int num_stats; u32 pool_size[OCELOT_SB_NUM][OCELOT_SB_POOL_NUM]; int packet_buffer_size; -- cgit v1.2.3 From d4c367650704de091d4c1f6bb379c0a5c389c73a Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Tue, 16 Aug 2022 16:53:51 +0300 Subject: net: mscc: ocelot: keep ocelot_stat_layout by reg address, not offset With so many counter addresses recently discovered as being wrong, it is desirable to at least have a central database of information, rather than two: one through the SYS_COUNT_* registers (used for ndo_get_stats64), and the other through the offset field of struct ocelot_stat_layout elements (used for ethtool -S). The strategy will be to keep the SYS_COUNT_* definitions as the single source of truth, but for that we need to expand our current definitions to cover all registers. Then we need to convert the ocelot region creation logic, and stats worker, to the read semantics imposed by going through SYS_COUNT_* absolute register addresses, rather than offsets of 32-bit words relative to SYS_COUNT_RX_OCTETS (which should have been SYS_CNT, by the way). Signed-off-by: Vladimir Oltean Signed-off-by: Jakub Kicinski --- drivers/net/dsa/ocelot/felix_vsc9959.c | 253 +++++++++++++++++----------- drivers/net/dsa/ocelot/seville_vsc9953.c | 255 ++++++++++++++++++----------- drivers/net/ethernet/mscc/ocelot.c | 11 +- drivers/net/ethernet/mscc/ocelot_vsc7514.c | 186 ++++++++++----------- drivers/net/ethernet/mscc/vsc7514_regs.c | 58 +++++++ include/soc/mscc/ocelot.h | 66 +++++++- 6 files changed, 540 insertions(+), 289 deletions(-) diff --git a/drivers/net/dsa/ocelot/felix_vsc9959.c b/drivers/net/dsa/ocelot/felix_vsc9959.c index c9f270f24b1c..1cdce8a98d1d 100644 --- a/drivers/net/dsa/ocelot/felix_vsc9959.c +++ b/drivers/net/dsa/ocelot/felix_vsc9959.c @@ -274,10 +274,14 @@ static const u32 vsc9959_rew_regmap[] = { static const u32 vsc9959_sys_regmap[] = { REG(SYS_COUNT_RX_OCTETS, 0x000000), + REG(SYS_COUNT_RX_UNICAST, 0x000004), REG(SYS_COUNT_RX_MULTICAST, 0x000008), + REG(SYS_COUNT_RX_BROADCAST, 0x00000c), REG(SYS_COUNT_RX_SHORTS, 0x000010), REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), REG(SYS_COUNT_RX_JABBERS, 0x000018), + REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c), + REG(SYS_COUNT_RX_SYM_ERRS, 0x000020), REG(SYS_COUNT_RX_64, 0x000024), REG(SYS_COUNT_RX_65_127, 0x000028), REG(SYS_COUNT_RX_128_255, 0x00002c), @@ -288,9 +292,38 @@ static const u32 vsc9959_sys_regmap[] = { REG(SYS_COUNT_RX_PAUSE, 0x000040), REG(SYS_COUNT_RX_CONTROL, 0x000044), REG(SYS_COUNT_RX_LONGS, 0x000048), + REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x00004c), + REG(SYS_COUNT_RX_RED_PRIO_0, 0x000050), + REG(SYS_COUNT_RX_RED_PRIO_1, 0x000054), + REG(SYS_COUNT_RX_RED_PRIO_2, 0x000058), + REG(SYS_COUNT_RX_RED_PRIO_3, 0x00005c), + REG(SYS_COUNT_RX_RED_PRIO_4, 0x000060), + REG(SYS_COUNT_RX_RED_PRIO_5, 0x000064), + REG(SYS_COUNT_RX_RED_PRIO_6, 0x000068), + REG(SYS_COUNT_RX_RED_PRIO_7, 0x00006c), + REG(SYS_COUNT_RX_YELLOW_PRIO_0, 0x000070), + REG(SYS_COUNT_RX_YELLOW_PRIO_1, 0x000074), + REG(SYS_COUNT_RX_YELLOW_PRIO_2, 0x000078), + REG(SYS_COUNT_RX_YELLOW_PRIO_3, 0x00007c), + REG(SYS_COUNT_RX_YELLOW_PRIO_4, 0x000080), + REG(SYS_COUNT_RX_YELLOW_PRIO_5, 0x000084), + REG(SYS_COUNT_RX_YELLOW_PRIO_6, 0x000088), + REG(SYS_COUNT_RX_YELLOW_PRIO_7, 0x00008c), + REG(SYS_COUNT_RX_GREEN_PRIO_0, 0x000090), + REG(SYS_COUNT_RX_GREEN_PRIO_1, 0x000094), + REG(SYS_COUNT_RX_GREEN_PRIO_2, 0x000098), + REG(SYS_COUNT_RX_GREEN_PRIO_3, 0x00009c), + REG(SYS_COUNT_RX_GREEN_PRIO_4, 0x0000a0), + REG(SYS_COUNT_RX_GREEN_PRIO_5, 0x0000a4), + REG(SYS_COUNT_RX_GREEN_PRIO_6, 0x0000a8), + REG(SYS_COUNT_RX_GREEN_PRIO_7, 0x0000ac), REG(SYS_COUNT_TX_OCTETS, 0x000200), + REG(SYS_COUNT_TX_UNICAST, 0x000204), + REG(SYS_COUNT_TX_MULTICAST, 0x000208), + REG(SYS_COUNT_TX_BROADCAST, 0x00020c), REG(SYS_COUNT_TX_COLLISION, 0x000210), REG(SYS_COUNT_TX_DROPS, 0x000214), + REG(SYS_COUNT_TX_PAUSE, 0x000218), REG(SYS_COUNT_TX_64, 0x00021c), REG(SYS_COUNT_TX_65_127, 0x000220), REG(SYS_COUNT_TX_128_255, 0x000224), @@ -298,7 +331,41 @@ static const u32 vsc9959_sys_regmap[] = { REG(SYS_COUNT_TX_512_1023, 0x00022c), REG(SYS_COUNT_TX_1024_1526, 0x000230), REG(SYS_COUNT_TX_1527_MAX, 0x000234), + REG(SYS_COUNT_TX_YELLOW_PRIO_0, 0x000238), + REG(SYS_COUNT_TX_YELLOW_PRIO_1, 0x00023c), + REG(SYS_COUNT_TX_YELLOW_PRIO_2, 0x000240), + REG(SYS_COUNT_TX_YELLOW_PRIO_3, 0x000244), + REG(SYS_COUNT_TX_YELLOW_PRIO_4, 0x000248), + REG(SYS_COUNT_TX_YELLOW_PRIO_5, 0x00024c), + REG(SYS_COUNT_TX_YELLOW_PRIO_6, 0x000250), + REG(SYS_COUNT_TX_YELLOW_PRIO_7, 0x000254), + REG(SYS_COUNT_TX_GREEN_PRIO_0, 0x000258), + REG(SYS_COUNT_TX_GREEN_PRIO_1, 0x00025c), + REG(SYS_COUNT_TX_GREEN_PRIO_2, 0x000260), + REG(SYS_COUNT_TX_GREEN_PRIO_3, 0x000264), + REG(SYS_COUNT_TX_GREEN_PRIO_4, 0x000268), + REG(SYS_COUNT_TX_GREEN_PRIO_5, 0x00026c), + REG(SYS_COUNT_TX_GREEN_PRIO_6, 0x000270), + REG(SYS_COUNT_TX_GREEN_PRIO_7, 0x000274), REG(SYS_COUNT_TX_AGING, 0x000278), + REG(SYS_COUNT_DROP_LOCAL, 0x000400), + REG(SYS_COUNT_DROP_TAIL, 0x000404), + REG(SYS_COUNT_DROP_YELLOW_PRIO_0, 0x000408), + REG(SYS_COUNT_DROP_YELLOW_PRIO_1, 0x00040c), + REG(SYS_COUNT_DROP_YELLOW_PRIO_2, 0x000410), + REG(SYS_COUNT_DROP_YELLOW_PRIO_3, 0x000414), + REG(SYS_COUNT_DROP_YELLOW_PRIO_4, 0x000418), + REG(SYS_COUNT_DROP_YELLOW_PRIO_5, 0x00041c), + REG(SYS_COUNT_DROP_YELLOW_PRIO_6, 0x000420), + REG(SYS_COUNT_DROP_YELLOW_PRIO_7, 0x000424), + REG(SYS_COUNT_DROP_GREEN_PRIO_0, 0x000428), + REG(SYS_COUNT_DROP_GREEN_PRIO_1, 0x00042c), + REG(SYS_COUNT_DROP_GREEN_PRIO_2, 0x000430), + REG(SYS_COUNT_DROP_GREEN_PRIO_3, 0x000434), + REG(SYS_COUNT_DROP_GREEN_PRIO_4, 0x000438), + REG(SYS_COUNT_DROP_GREEN_PRIO_5, 0x00043c), + REG(SYS_COUNT_DROP_GREEN_PRIO_6, 0x000440), + REG(SYS_COUNT_DROP_GREEN_PRIO_7, 0x000444), REG(SYS_RESET_CFG, 0x000e00), REG(SYS_SR_ETYPE_CFG, 0x000e04), REG(SYS_VLAN_ETYPE_CFG, 0x000e08), @@ -554,375 +621,375 @@ static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = { static const struct ocelot_stat_layout vsc9959_stats_layout[OCELOT_NUM_STATS] = { [OCELOT_STAT_RX_OCTETS] = { .name = "rx_octets", - .offset = 0x00, + .reg = SYS_COUNT_RX_OCTETS, }, [OCELOT_STAT_RX_UNICAST] = { .name = "rx_unicast", - .offset = 0x01, + .reg = SYS_COUNT_RX_UNICAST, }, [OCELOT_STAT_RX_MULTICAST] = { .name = "rx_multicast", - .offset = 0x02, + .reg = SYS_COUNT_RX_MULTICAST, }, [OCELOT_STAT_RX_BROADCAST] = { .name = "rx_broadcast", - .offset = 0x03, + .reg = SYS_COUNT_RX_BROADCAST, }, [OCELOT_STAT_RX_SHORTS] = { .name = "rx_shorts", - .offset = 0x04, + .reg = SYS_COUNT_RX_SHORTS, }, [OCELOT_STAT_RX_FRAGMENTS] = { .name = "rx_fragments", - .offset = 0x05, + .reg = SYS_COUNT_RX_FRAGMENTS, }, [OCELOT_STAT_RX_JABBERS] = { .name = "rx_jabbers", - .offset = 0x06, + .reg = SYS_COUNT_RX_JABBERS, }, [OCELOT_STAT_RX_CRC_ALIGN_ERRS] = { .name = "rx_crc_align_errs", - .offset = 0x07, + .reg = SYS_COUNT_RX_CRC_ALIGN_ERRS, }, [OCELOT_STAT_RX_SYM_ERRS] = { .name = "rx_sym_errs", - .offset = 0x08, + .reg = SYS_COUNT_RX_SYM_ERRS, }, [OCELOT_STAT_RX_64] = { .name = "rx_frames_below_65_octets", - .offset = 0x09, + .reg = SYS_COUNT_RX_64, }, [OCELOT_STAT_RX_65_127] = { .name = "rx_frames_65_to_127_octets", - .offset = 0x0A, + .reg = SYS_COUNT_RX_65_127, }, [OCELOT_STAT_RX_128_255] = { .name = "rx_frames_128_to_255_octets", - .offset = 0x0B, + .reg = SYS_COUNT_RX_128_255, }, [OCELOT_STAT_RX_256_511] = { .name = "rx_frames_256_to_511_octets", - .offset = 0x0C, + .reg = SYS_COUNT_RX_256_511, }, [OCELOT_STAT_RX_512_1023] = { .name = "rx_frames_512_to_1023_octets", - .offset = 0x0D, + .reg = SYS_COUNT_RX_512_1023, }, [OCELOT_STAT_RX_1024_1526] = { .name = "rx_frames_1024_to_1526_octets", - .offset = 0x0E, + .reg = SYS_COUNT_RX_1024_1526, }, [OCELOT_STAT_RX_1527_MAX] = { .name = "rx_frames_over_1526_octets", - .offset = 0x0F, + .reg = SYS_COUNT_RX_1527_MAX, }, [OCELOT_STAT_RX_PAUSE] = { .name = "rx_pause", - .offset = 0x10, + .reg = SYS_COUNT_RX_PAUSE, }, [OCELOT_STAT_RX_CONTROL] = { .name = "rx_control", - .offset = 0x11, + .reg = SYS_COUNT_RX_CONTROL, }, [OCELOT_STAT_RX_LONGS] = { .name = "rx_longs", - .offset = 0x12, + .reg = SYS_COUNT_RX_LONGS, }, [OCELOT_STAT_RX_CLASSIFIED_DROPS] = { .name = "rx_classified_drops", - .offset = 0x13, + .reg = SYS_COUNT_RX_CLASSIFIED_DROPS, }, [OCELOT_STAT_RX_RED_PRIO_0] = { .name = "rx_red_prio_0", - .offset = 0x14, + .reg = SYS_COUNT_RX_RED_PRIO_0, }, [OCELOT_STAT_RX_RED_PRIO_1] = { .name = "rx_red_prio_1", - .offset = 0x15, + .reg = SYS_COUNT_RX_RED_PRIO_1, }, [OCELOT_STAT_RX_RED_PRIO_2] = { .name = "rx_red_prio_2", - .offset = 0x16, + .reg = SYS_COUNT_RX_RED_PRIO_2, }, [OCELOT_STAT_RX_RED_PRIO_3] = { .name = "rx_red_prio_3", - .offset = 0x17, + .reg = SYS_COUNT_RX_RED_PRIO_3, }, [OCELOT_STAT_RX_RED_PRIO_4] = { .name = "rx_red_prio_4", - .offset = 0x18, + .reg = SYS_COUNT_RX_RED_PRIO_4, }, [OCELOT_STAT_RX_RED_PRIO_5] = { .name = "rx_red_prio_5", - .offset = 0x19, + .reg = SYS_COUNT_RX_RED_PRIO_5, }, [OCELOT_STAT_RX_RED_PRIO_6] = { .name = "rx_red_prio_6", - .offset = 0x1A, + .reg = SYS_COUNT_RX_RED_PRIO_6, }, [OCELOT_STAT_RX_RED_PRIO_7] = { .name = "rx_red_prio_7", - .offset = 0x1B, + .reg = SYS_COUNT_RX_RED_PRIO_7, }, [OCELOT_STAT_RX_YELLOW_PRIO_0] = { .name = "rx_yellow_prio_0", - .offset = 0x1C, + .reg = SYS_COUNT_RX_YELLOW_PRIO_0, }, [OCELOT_STAT_RX_YELLOW_PRIO_1] = { .name = "rx_yellow_prio_1", - .offset = 0x1D, + .reg = SYS_COUNT_RX_YELLOW_PRIO_1, }, [OCELOT_STAT_RX_YELLOW_PRIO_2] = { .name = "rx_yellow_prio_2", - .offset = 0x1E, + .reg = SYS_COUNT_RX_YELLOW_PRIO_2, }, [OCELOT_STAT_RX_YELLOW_PRIO_3] = { .name = "rx_yellow_prio_3", - .offset = 0x1F, + .reg = SYS_COUNT_RX_YELLOW_PRIO_3, }, [OCELOT_STAT_RX_YELLOW_PRIO_4] = { .name = "rx_yellow_prio_4", - .offset = 0x20, + .reg = SYS_COUNT_RX_YELLOW_PRIO_4, }, [OCELOT_STAT_RX_YELLOW_PRIO_5] = { .name = "rx_yellow_prio_5", - .offset = 0x21, + .reg = SYS_COUNT_RX_YELLOW_PRIO_5, }, [OCELOT_STAT_RX_YELLOW_PRIO_6] = { .name = "rx_yellow_prio_6", - .offset = 0x22, + .reg = SYS_COUNT_RX_YELLOW_PRIO_6, }, [OCELOT_STAT_RX_YELLOW_PRIO_7] = { .name = "rx_yellow_prio_7", - .offset = 0x23, + .reg = SYS_COUNT_RX_YELLOW_PRIO_7, }, [OCELOT_STAT_RX_GREEN_PRIO_0] = { .name = "rx_green_prio_0", - .offset = 0x24, + .reg = SYS_COUNT_RX_GREEN_PRIO_0, }, [OCELOT_STAT_RX_GREEN_PRIO_1] = { .name = "rx_green_prio_1", - .offset = 0x25, + .reg = SYS_COUNT_RX_GREEN_PRIO_1, }, [OCELOT_STAT_RX_GREEN_PRIO_2] = { .name = "rx_green_prio_2", - .offset = 0x26, + .reg = SYS_COUNT_RX_GREEN_PRIO_2, }, [OCELOT_STAT_RX_GREEN_PRIO_3] = { .name = "rx_green_prio_3", - .offset = 0x27, + .reg = SYS_COUNT_RX_GREEN_PRIO_3, }, [OCELOT_STAT_RX_GREEN_PRIO_4] = { .name = "rx_green_prio_4", - .offset = 0x28, + .reg = SYS_COUNT_RX_GREEN_PRIO_4, }, [OCELOT_STAT_RX_GREEN_PRIO_5] = { .name = "rx_green_prio_5", - .offset = 0x29, + .reg = SYS_COUNT_RX_GREEN_PRIO_5, }, [OCELOT_STAT_RX_GREEN_PRIO_6] = { .name = "rx_green_prio_6", - .offset = 0x2A, + .reg = SYS_COUNT_RX_GREEN_PRIO_6, }, [OCELOT_STAT_RX_GREEN_PRIO_7] = { .name = "rx_green_prio_7", - .offset = 0x2B, + .reg = SYS_COUNT_RX_GREEN_PRIO_7, }, [OCELOT_STAT_TX_OCTETS] = { .name = "tx_octets", - .offset = 0x80, + .reg = SYS_COUNT_TX_OCTETS, }, [OCELOT_STAT_TX_UNICAST] = { .name = "tx_unicast", - .offset = 0x81, + .reg = SYS_COUNT_TX_UNICAST, }, [OCELOT_STAT_TX_MULTICAST] = { .name = "tx_multicast", - .offset = 0x82, + .reg = SYS_COUNT_TX_MULTICAST, }, [OCELOT_STAT_TX_BROADCAST] = { .name = "tx_broadcast", - .offset = 0x83, + .reg = SYS_COUNT_TX_BROADCAST, }, [OCELOT_STAT_TX_COLLISION] = { .name = "tx_collision", - .offset = 0x84, + .reg = SYS_COUNT_TX_COLLISION, }, [OCELOT_STAT_TX_DROPS] = { .name = "tx_drops", - .offset = 0x85, + .reg = SYS_COUNT_TX_DROPS, }, [OCELOT_STAT_TX_PAUSE] = { .name = "tx_pause", - .offset = 0x86, + .reg = SYS_COUNT_TX_PAUSE, }, [OCELOT_STAT_TX_64] = { .name = "tx_frames_below_65_octets", - .offset = 0x87, + .reg = SYS_COUNT_TX_64, }, [OCELOT_STAT_TX_65_127] = { .name = "tx_frames_65_to_127_octets", - .offset = 0x88, + .reg = SYS_COUNT_TX_65_127, }, [OCELOT_STAT_TX_128_255] = { .name = "tx_frames_128_255_octets", - .offset = 0x89, + .reg = SYS_COUNT_TX_128_255, }, [OCELOT_STAT_TX_256_511] = { .name = "tx_frames_256_511_octets", - .offset = 0x8A, + .reg = SYS_COUNT_TX_256_511, }, [OCELOT_STAT_TX_512_1023] = { .name = "tx_frames_512_1023_octets", - .offset = 0x8B, + .reg = SYS_COUNT_TX_512_1023, }, [OCELOT_STAT_TX_1024_1526] = { .name = "tx_frames_1024_1526_octets", - .offset = 0x8C, + .reg = SYS_COUNT_TX_1024_1526, }, [OCELOT_STAT_TX_1527_MAX] = { .name = "tx_frames_over_1526_octets", - .offset = 0x8D, + .reg = SYS_COUNT_TX_1527_MAX, }, [OCELOT_STAT_TX_YELLOW_PRIO_0] = { .name = "tx_yellow_prio_0", - .offset = 0x8E, + .reg = SYS_COUNT_TX_YELLOW_PRIO_0, }, [OCELOT_STAT_TX_YELLOW_PRIO_1] = { .name = "tx_yellow_prio_1", - .offset = 0x8F, + .reg = SYS_COUNT_TX_YELLOW_PRIO_1, }, [OCELOT_STAT_TX_YELLOW_PRIO_2] = { .name = "tx_yellow_prio_2", - .offset = 0x90, + .reg = SYS_COUNT_TX_YELLOW_PRIO_2, }, [OCELOT_STAT_TX_YELLOW_PRIO_3] = { .name = "tx_yellow_prio_3", - .offset = 0x91, + .reg = SYS_COUNT_TX_YELLOW_PRIO_3, }, [OCELOT_STAT_TX_YELLOW_PRIO_4] = { .name = "tx_yellow_prio_4", - .offset = 0x92, + .reg = SYS_COUNT_TX_YELLOW_PRIO_4, }, [OCELOT_STAT_TX_YELLOW_PRIO_5] = { .name = "tx_yellow_prio_5", - .offset = 0x93, + .reg = SYS_COUNT_TX_YELLOW_PRIO_5, }, [OCELOT_STAT_TX_YELLOW_PRIO_6] = { .name = "tx_yellow_prio_6", - .offset = 0x94, + .reg = SYS_COUNT_TX_YELLOW_PRIO_6, }, [OCELOT_STAT_TX_YELLOW_PRIO_7] = { .name = "tx_yellow_prio_7", - .offset = 0x95, + .reg = SYS_COUNT_TX_YELLOW_PRIO_7, }, [OCELOT_STAT_TX_GREEN_PRIO_0] = { .name = "tx_green_prio_0", - .offset = 0x96, + .reg = SYS_COUNT_TX_GREEN_PRIO_0, }, [OCELOT_STAT_TX_GREEN_PRIO_1] = { .name = "tx_green_prio_1", - .offset = 0x97, + .reg = SYS_COUNT_TX_GREEN_PRIO_1, }, [OCELOT_STAT_TX_GREEN_PRIO_2] = { .name = "tx_green_prio_2", - .offset = 0x98, + .reg = SYS_COUNT_TX_GREEN_PRIO_2, }, [OCELOT_STAT_TX_GREEN_PRIO_3] = { .name = "tx_green_prio_3", - .offset = 0x99, + .reg = SYS_COUNT_TX_GREEN_PRIO_3, }, [OCELOT_STAT_TX_GREEN_PRIO_4] = { .name = "tx_green_prio_4", - .offset = 0x9A, + .reg = SYS_COUNT_TX_GREEN_PRIO_4, }, [OCELOT_STAT_TX_GREEN_PRIO_5] = { .name = "tx_green_prio_5", - .offset = 0x9B, + .reg = SYS_COUNT_TX_GREEN_PRIO_5, }, [OCELOT_STAT_TX_GREEN_PRIO_6] = { .name = "tx_green_prio_6", - .offset = 0x9C, + .reg = SYS_COUNT_TX_GREEN_PRIO_6, }, [OCELOT_STAT_TX_GREEN_PRIO_7] = { .name = "tx_green_prio_7", - .offset = 0x9D, + .reg = SYS_COUNT_TX_GREEN_PRIO_7, }, [OCELOT_STAT_TX_AGED] = { .name = "tx_aged", - .offset = 0x9E, + .reg = SYS_COUNT_TX_AGING, }, [OCELOT_STAT_DROP_LOCAL] = { .name = "drop_local", - .offset = 0x100, + .reg = SYS_COUNT_DROP_LOCAL, }, [OCELOT_STAT_DROP_TAIL] = { .name = "drop_tail", - .offset = 0x101, + .reg = SYS_COUNT_DROP_TAIL, }, [OCELOT_STAT_DROP_YELLOW_PRIO_0] = { .name = "drop_yellow_prio_0", - .offset = 0x102, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_0, }, [OCELOT_STAT_DROP_YELLOW_PRIO_1] = { .name = "drop_yellow_prio_1", - .offset = 0x103, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_1, }, [OCELOT_STAT_DROP_YELLOW_PRIO_2] = { .name = "drop_yellow_prio_2", - .offset = 0x104, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_2, }, [OCELOT_STAT_DROP_YELLOW_PRIO_3] = { .name = "drop_yellow_prio_3", - .offset = 0x105, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_3, }, [OCELOT_STAT_DROP_YELLOW_PRIO_4] = { .name = "drop_yellow_prio_4", - .offset = 0x106, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_4, }, [OCELOT_STAT_DROP_YELLOW_PRIO_5] = { .name = "drop_yellow_prio_5", - .offset = 0x107, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_5, }, [OCELOT_STAT_DROP_YELLOW_PRIO_6] = { .name = "drop_yellow_prio_6", - .offset = 0x108, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_6, }, [OCELOT_STAT_DROP_YELLOW_PRIO_7] = { .name = "drop_yellow_prio_7", - .offset = 0x109, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_7, }, [OCELOT_STAT_DROP_GREEN_PRIO_0] = { .name = "drop_green_prio_0", - .offset = 0x10A, + .reg = SYS_COUNT_DROP_GREEN_PRIO_0, }, [OCELOT_STAT_DROP_GREEN_PRIO_1] = { .name = "drop_green_prio_1", - .offset = 0x10B, + .reg = SYS_COUNT_DROP_GREEN_PRIO_1, }, [OCELOT_STAT_DROP_GREEN_PRIO_2] = { .name = "drop_green_prio_2", - .offset = 0x10C, + .reg = SYS_COUNT_DROP_GREEN_PRIO_2, }, [OCELOT_STAT_DROP_GREEN_PRIO_3] = { .name = "drop_green_prio_3", - .offset = 0x10D, + .reg = SYS_COUNT_DROP_GREEN_PRIO_3, }, [OCELOT_STAT_DROP_GREEN_PRIO_4] = { .name = "drop_green_prio_4", - .offset = 0x10E, + .reg = SYS_COUNT_DROP_GREEN_PRIO_4, }, [OCELOT_STAT_DROP_GREEN_PRIO_5] = { .name = "drop_green_prio_5", - .offset = 0x10F, + .reg = SYS_COUNT_DROP_GREEN_PRIO_5, }, [OCELOT_STAT_DROP_GREEN_PRIO_6] = { .name = "drop_green_prio_6", - .offset = 0x110, + .reg = SYS_COUNT_DROP_GREEN_PRIO_6, }, [OCELOT_STAT_DROP_GREEN_PRIO_7] = { .name = "drop_green_prio_7", - .offset = 0x111, + .reg = SYS_COUNT_DROP_GREEN_PRIO_7, }, }; diff --git a/drivers/net/dsa/ocelot/seville_vsc9953.c b/drivers/net/dsa/ocelot/seville_vsc9953.c index fe5d4642d0bc..b34f4cdfe814 100644 --- a/drivers/net/dsa/ocelot/seville_vsc9953.c +++ b/drivers/net/dsa/ocelot/seville_vsc9953.c @@ -270,10 +270,14 @@ static const u32 vsc9953_rew_regmap[] = { static const u32 vsc9953_sys_regmap[] = { REG(SYS_COUNT_RX_OCTETS, 0x000000), + REG(SYS_COUNT_RX_UNICAST, 0x000004), REG(SYS_COUNT_RX_MULTICAST, 0x000008), + REG(SYS_COUNT_RX_BROADCAST, 0x00000c), REG(SYS_COUNT_RX_SHORTS, 0x000010), REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), REG(SYS_COUNT_RX_JABBERS, 0x000018), + REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c), + REG(SYS_COUNT_RX_SYM_ERRS, 0x000020), REG(SYS_COUNT_RX_64, 0x000024), REG(SYS_COUNT_RX_65_127, 0x000028), REG(SYS_COUNT_RX_128_255, 0x00002c), @@ -281,10 +285,41 @@ static const u32 vsc9953_sys_regmap[] = { REG(SYS_COUNT_RX_512_1023, 0x000034), REG(SYS_COUNT_RX_1024_1526, 0x000038), REG(SYS_COUNT_RX_1527_MAX, 0x00003c), + REG(SYS_COUNT_RX_PAUSE, 0x000040), + REG(SYS_COUNT_RX_CONTROL, 0x000044), REG(SYS_COUNT_RX_LONGS, 0x000048), + REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x00004c), + REG(SYS_COUNT_RX_RED_PRIO_0, 0x000050), + REG(SYS_COUNT_RX_RED_PRIO_1, 0x000054), + REG(SYS_COUNT_RX_RED_PRIO_2, 0x000058), + REG(SYS_COUNT_RX_RED_PRIO_3, 0x00005c), + REG(SYS_COUNT_RX_RED_PRIO_4, 0x000060), + REG(SYS_COUNT_RX_RED_PRIO_5, 0x000064), + REG(SYS_COUNT_RX_RED_PRIO_6, 0x000068), + REG(SYS_COUNT_RX_RED_PRIO_7, 0x00006c), + REG(SYS_COUNT_RX_YELLOW_PRIO_0, 0x000070), + REG(SYS_COUNT_RX_YELLOW_PRIO_1, 0x000074), + REG(SYS_COUNT_RX_YELLOW_PRIO_2, 0x000078), + REG(SYS_COUNT_RX_YELLOW_PRIO_3, 0x00007c), + REG(SYS_COUNT_RX_YELLOW_PRIO_4, 0x000080), + REG(SYS_COUNT_RX_YELLOW_PRIO_5, 0x000084), + REG(SYS_COUNT_RX_YELLOW_PRIO_6, 0x000088), + REG(SYS_COUNT_RX_YELLOW_PRIO_7, 0x00008c), + REG(SYS_COUNT_RX_GREEN_PRIO_0, 0x000090), + REG(SYS_COUNT_RX_GREEN_PRIO_1, 0x000094), + REG(SYS_COUNT_RX_GREEN_PRIO_2, 0x000098), + REG(SYS_COUNT_RX_GREEN_PRIO_3, 0x00009c), + REG(SYS_COUNT_RX_GREEN_PRIO_4, 0x0000a0), + REG(SYS_COUNT_RX_GREEN_PRIO_5, 0x0000a4), + REG(SYS_COUNT_RX_GREEN_PRIO_6, 0x0000a8), + REG(SYS_COUNT_RX_GREEN_PRIO_7, 0x0000ac), REG(SYS_COUNT_TX_OCTETS, 0x000100), + REG(SYS_COUNT_TX_UNICAST, 0x000104), + REG(SYS_COUNT_TX_MULTICAST, 0x000108), + REG(SYS_COUNT_TX_BROADCAST, 0x00010c), REG(SYS_COUNT_TX_COLLISION, 0x000110), REG(SYS_COUNT_TX_DROPS, 0x000114), + REG(SYS_COUNT_TX_PAUSE, 0x000118), REG(SYS_COUNT_TX_64, 0x00011c), REG(SYS_COUNT_TX_65_127, 0x000120), REG(SYS_COUNT_TX_128_255, 0x000124), @@ -292,7 +327,41 @@ static const u32 vsc9953_sys_regmap[] = { REG(SYS_COUNT_TX_512_1023, 0x00012c), REG(SYS_COUNT_TX_1024_1526, 0x000130), REG(SYS_COUNT_TX_1527_MAX, 0x000134), + REG(SYS_COUNT_TX_YELLOW_PRIO_0, 0x000138), + REG(SYS_COUNT_TX_YELLOW_PRIO_1, 0x00013c), + REG(SYS_COUNT_TX_YELLOW_PRIO_2, 0x000140), + REG(SYS_COUNT_TX_YELLOW_PRIO_3, 0x000144), + REG(SYS_COUNT_TX_YELLOW_PRIO_4, 0x000148), + REG(SYS_COUNT_TX_YELLOW_PRIO_5, 0x00014c), + REG(SYS_COUNT_TX_YELLOW_PRIO_6, 0x000150), + REG(SYS_COUNT_TX_YELLOW_PRIO_7, 0x000154), + REG(SYS_COUNT_TX_GREEN_PRIO_0, 0x000158), + REG(SYS_COUNT_TX_GREEN_PRIO_1, 0x00015c), + REG(SYS_COUNT_TX_GREEN_PRIO_2, 0x000160), + REG(SYS_COUNT_TX_GREEN_PRIO_3, 0x000164), + REG(SYS_COUNT_TX_GREEN_PRIO_4, 0x000168), + REG(SYS_COUNT_TX_GREEN_PRIO_5, 0x00016c), + REG(SYS_COUNT_TX_GREEN_PRIO_6, 0x000170), + REG(SYS_COUNT_TX_GREEN_PRIO_7, 0x000174), REG(SYS_COUNT_TX_AGING, 0x000178), + REG(SYS_COUNT_DROP_LOCAL, 0x000200), + REG(SYS_COUNT_DROP_TAIL, 0x000204), + REG(SYS_COUNT_DROP_YELLOW_PRIO_0, 0x000208), + REG(SYS_COUNT_DROP_YELLOW_PRIO_1, 0x00020c), + REG(SYS_COUNT_DROP_YELLOW_PRIO_2, 0x000210), + REG(SYS_COUNT_DROP_YELLOW_PRIO_3, 0x000214), + REG(SYS_COUNT_DROP_YELLOW_PRIO_4, 0x000218), + REG(SYS_COUNT_DROP_YELLOW_PRIO_5, 0x00021c), + REG(SYS_COUNT_DROP_YELLOW_PRIO_6, 0x000220), + REG(SYS_COUNT_DROP_YELLOW_PRIO_7, 0x000224), + REG(SYS_COUNT_DROP_GREEN_PRIO_0, 0x000228), + REG(SYS_COUNT_DROP_GREEN_PRIO_1, 0x00022c), + REG(SYS_COUNT_DROP_GREEN_PRIO_2, 0x000230), + REG(SYS_COUNT_DROP_GREEN_PRIO_3, 0x000234), + REG(SYS_COUNT_DROP_GREEN_PRIO_4, 0x000238), + REG(SYS_COUNT_DROP_GREEN_PRIO_5, 0x00023c), + REG(SYS_COUNT_DROP_GREEN_PRIO_6, 0x000240), + REG(SYS_COUNT_DROP_GREEN_PRIO_7, 0x000244), REG(SYS_RESET_CFG, 0x000318), REG_RESERVED(SYS_SR_ETYPE_CFG), REG(SYS_VLAN_ETYPE_CFG, 0x000320), @@ -548,375 +617,375 @@ static const struct reg_field vsc9953_regfields[REGFIELD_MAX] = { static const struct ocelot_stat_layout vsc9953_stats_layout[OCELOT_NUM_STATS] = { [OCELOT_STAT_RX_OCTETS] = { .name = "rx_octets", - .offset = 0x00, + .reg = SYS_COUNT_RX_OCTETS, }, [OCELOT_STAT_RX_UNICAST] = { .name = "rx_unicast", - .offset = 0x01, + .reg = SYS_COUNT_RX_UNICAST, }, [OCELOT_STAT_RX_MULTICAST] = { .name = "rx_multicast", - .offset = 0x02, + .reg = SYS_COUNT_RX_MULTICAST, }, [OCELOT_STAT_RX_BROADCAST] = { .name = "rx_broadcast", - .offset = 0x03, + .reg = SYS_COUNT_RX_BROADCAST, }, [OCELOT_STAT_RX_SHORTS] = { .name = "rx_shorts", - .offset = 0x04, + .reg = SYS_COUNT_RX_SHORTS, }, [OCELOT_STAT_RX_FRAGMENTS] = { .name = "rx_fragments", - .offset = 0x05, + .reg = SYS_COUNT_RX_FRAGMENTS, }, [OCELOT_STAT_RX_JABBERS] = { .name = "rx_jabbers", - .offset = 0x06, + .reg = SYS_COUNT_RX_JABBERS, }, [OCELOT_STAT_RX_CRC_ALIGN_ERRS] = { .name = "rx_crc_align_errs", - .offset = 0x07, + .reg = SYS_COUNT_RX_CRC_ALIGN_ERRS, }, [OCELOT_STAT_RX_SYM_ERRS] = { .name = "rx_sym_errs", - .offset = 0x08, + .reg = SYS_COUNT_RX_SYM_ERRS, }, [OCELOT_STAT_RX_64] = { .name = "rx_frames_below_65_octets", - .offset = 0x09, + .reg = SYS_COUNT_RX_64, }, [OCELOT_STAT_RX_65_127] = { .name = "rx_frames_65_to_127_octets", - .offset = 0x0A, + .reg = SYS_COUNT_RX_65_127, }, [OCELOT_STAT_RX_128_255] = { .name = "rx_frames_128_to_255_octets", - .offset = 0x0B, + .reg = SYS_COUNT_RX_128_255, }, [OCELOT_STAT_RX_256_511] = { .name = "rx_frames_256_to_511_octets", - .offset = 0x0C, + .reg = SYS_COUNT_RX_256_511, }, [OCELOT_STAT_RX_512_1023] = { .name = "rx_frames_512_to_1023_octets", - .offset = 0x0D, + .reg = SYS_COUNT_RX_512_1023, }, [OCELOT_STAT_RX_1024_1526] = { .name = "rx_frames_1024_to_1526_octets", - .offset = 0x0E, + .reg = SYS_COUNT_RX_1024_1526, }, [OCELOT_STAT_RX_1527_MAX] = { .name = "rx_frames_over_1526_octets", - .offset = 0x0F, + .reg = SYS_COUNT_RX_1527_MAX, }, [OCELOT_STAT_RX_PAUSE] = { .name = "rx_pause", - .offset = 0x10, + .reg = SYS_COUNT_RX_PAUSE, }, [OCELOT_STAT_RX_CONTROL] = { .name = "rx_control", - .offset = 0x11, + .reg = SYS_COUNT_RX_CONTROL, }, [OCELOT_STAT_RX_LONGS] = { .name = "rx_longs", - .offset = 0x12, + .reg = SYS_COUNT_RX_LONGS, }, [OCELOT_STAT_RX_CLASSIFIED_DROPS] = { .name = "rx_classified_drops", - .offset = 0x13, + .reg = SYS_COUNT_RX_CLASSIFIED_DROPS, }, [OCELOT_STAT_RX_RED_PRIO_0] = { .name = "rx_red_prio_0", - .offset = 0x14, + .reg = SYS_COUNT_RX_RED_PRIO_0, }, [OCELOT_STAT_RX_RED_PRIO_1] = { .name = "rx_red_prio_1", - .offset = 0x15, + .reg = SYS_COUNT_RX_RED_PRIO_1, }, [OCELOT_STAT_RX_RED_PRIO_2] = { .name = "rx_red_prio_2", - .offset = 0x16, + .reg = SYS_COUNT_RX_RED_PRIO_2, }, [OCELOT_STAT_RX_RED_PRIO_3] = { .name = "rx_red_prio_3", - .offset = 0x17, + .reg = SYS_COUNT_RX_RED_PRIO_3, }, [OCELOT_STAT_RX_RED_PRIO_4] = { .name = "rx_red_prio_4", - .offset = 0x18, + .reg = SYS_COUNT_RX_RED_PRIO_4, }, [OCELOT_STAT_RX_RED_PRIO_5] = { .name = "rx_red_prio_5", - .offset = 0x19, + .reg = SYS_COUNT_RX_RED_PRIO_5, }, [OCELOT_STAT_RX_RED_PRIO_6] = { .name = "rx_red_prio_6", - .offset = 0x1A, + .reg = SYS_COUNT_RX_RED_PRIO_6, }, [OCELOT_STAT_RX_RED_PRIO_7] = { .name = "rx_red_prio_7", - .offset = 0x1B, + .reg = SYS_COUNT_RX_RED_PRIO_7, }, [OCELOT_STAT_RX_YELLOW_PRIO_0] = { .name = "rx_yellow_prio_0", - .offset = 0x1C, + .reg = SYS_COUNT_RX_YELLOW_PRIO_0, }, [OCELOT_STAT_RX_YELLOW_PRIO_1] = { .name = "rx_yellow_prio_1", - .offset = 0x1D, + .reg = SYS_COUNT_RX_YELLOW_PRIO_1, }, [OCELOT_STAT_RX_YELLOW_PRIO_2] = { .name = "rx_yellow_prio_2", - .offset = 0x1E, + .reg = SYS_COUNT_RX_YELLOW_PRIO_2, }, [OCELOT_STAT_RX_YELLOW_PRIO_3] = { .name = "rx_yellow_prio_3", - .offset = 0x1F, + .reg = SYS_COUNT_RX_YELLOW_PRIO_3, }, [OCELOT_STAT_RX_YELLOW_PRIO_4] = { .name = "rx_yellow_prio_4", - .offset = 0x20, + .reg = SYS_COUNT_RX_YELLOW_PRIO_4, }, [OCELOT_STAT_RX_YELLOW_PRIO_5] = { .name = "rx_yellow_prio_5", - .offset = 0x21, + .reg = SYS_COUNT_RX_YELLOW_PRIO_5, }, [OCELOT_STAT_RX_YELLOW_PRIO_6] = { .name = "rx_yellow_prio_6", - .offset = 0x22, + .reg = SYS_COUNT_RX_YELLOW_PRIO_6, }, [OCELOT_STAT_RX_YELLOW_PRIO_7] = { .name = "rx_yellow_prio_7", - .offset = 0x23, + .reg = SYS_COUNT_RX_YELLOW_PRIO_7, }, [OCELOT_STAT_RX_GREEN_PRIO_0] = { .name = "rx_green_prio_0", - .offset = 0x24, + .reg = SYS_COUNT_RX_GREEN_PRIO_0, }, [OCELOT_STAT_RX_GREEN_PRIO_1] = { .name = "rx_green_prio_1", - .offset = 0x25, + .reg = SYS_COUNT_RX_GREEN_PRIO_1, }, [OCELOT_STAT_RX_GREEN_PRIO_2] = { .name = "rx_green_prio_2", - .offset = 0x26, + .reg = SYS_COUNT_RX_GREEN_PRIO_2, }, [OCELOT_STAT_RX_GREEN_PRIO_3] = { .name = "rx_green_prio_3", - .offset = 0x27, + .reg = SYS_COUNT_RX_GREEN_PRIO_3, }, [OCELOT_STAT_RX_GREEN_PRIO_4] = { .name = "rx_green_prio_4", - .offset = 0x28, + .reg = SYS_COUNT_RX_GREEN_PRIO_4, }, [OCELOT_STAT_RX_GREEN_PRIO_5] = { .name = "rx_green_prio_5", - .offset = 0x29, + .reg = SYS_COUNT_RX_GREEN_PRIO_5, }, [OCELOT_STAT_RX_GREEN_PRIO_6] = { .name = "rx_green_prio_6", - .offset = 0x2A, + .reg = SYS_COUNT_RX_GREEN_PRIO_6, }, [OCELOT_STAT_RX_GREEN_PRIO_7] = { .name = "rx_green_prio_7", - .offset = 0x2B, + .reg = SYS_COUNT_RX_GREEN_PRIO_7, }, [OCELOT_STAT_TX_OCTETS] = { .name = "tx_octets", - .offset = 0x40, + .reg = SYS_COUNT_TX_OCTETS, }, [OCELOT_STAT_TX_UNICAST] = { .name = "tx_unicast", - .offset = 0x41, + .reg = SYS_COUNT_TX_UNICAST, }, [OCELOT_STAT_TX_MULTICAST] = { .name = "tx_multicast", - .offset = 0x42, + .reg = SYS_COUNT_TX_MULTICAST, }, [OCELOT_STAT_TX_BROADCAST] = { .name = "tx_broadcast", - .offset = 0x43, + .reg = SYS_COUNT_TX_BROADCAST, }, [OCELOT_STAT_TX_COLLISION] = { .name = "tx_collision", - .offset = 0x44, + .reg = SYS_COUNT_TX_COLLISION, }, [OCELOT_STAT_TX_DROPS] = { .name = "tx_drops", - .offset = 0x45, + .reg = SYS_COUNT_TX_DROPS, }, [OCELOT_STAT_TX_PAUSE] = { .name = "tx_pause", - .offset = 0x46, + .reg = SYS_COUNT_TX_PAUSE, }, [OCELOT_STAT_TX_64] = { .name = "tx_frames_below_65_octets", - .offset = 0x47, + .reg = SYS_COUNT_TX_64, }, [OCELOT_STAT_TX_65_127] = { .name = "tx_frames_65_to_127_octets", - .offset = 0x48, + .reg = SYS_COUNT_TX_65_127, }, [OCELOT_STAT_TX_128_255] = { .name = "tx_frames_128_255_octets", - .offset = 0x49, + .reg = SYS_COUNT_TX_128_255, }, [OCELOT_STAT_TX_256_511] = { .name = "tx_frames_256_511_octets", - .offset = 0x4A, + .reg = SYS_COUNT_TX_256_511, }, [OCELOT_STAT_TX_512_1023] = { .name = "tx_frames_512_1023_octets", - .offset = 0x4B, + .reg = SYS_COUNT_TX_512_1023, }, [OCELOT_STAT_TX_1024_1526] = { .name = "tx_frames_1024_1526_octets", - .offset = 0x4C, + .reg = SYS_COUNT_TX_1024_1526, }, [OCELOT_STAT_TX_1527_MAX] = { .name = "tx_frames_over_1526_octets", - .offset = 0x4D, + .reg = SYS_COUNT_TX_1527_MAX, }, [OCELOT_STAT_TX_YELLOW_PRIO_0] = { .name = "tx_yellow_prio_0", - .offset = 0x4E, + .reg = SYS_COUNT_TX_YELLOW_PRIO_0, }, [OCELOT_STAT_TX_YELLOW_PRIO_1] = { .name = "tx_yellow_prio_1", - .offset = 0x4F, + .reg = SYS_COUNT_TX_YELLOW_PRIO_1, }, [OCELOT_STAT_TX_YELLOW_PRIO_2] = { .name = "tx_yellow_prio_2", - .offset = 0x50, + .reg = SYS_COUNT_TX_YELLOW_PRIO_2, }, [OCELOT_STAT_TX_YELLOW_PRIO_3] = { .name = "tx_yellow_prio_3", - .offset = 0x51, + .reg = SYS_COUNT_TX_YELLOW_PRIO_3, }, [OCELOT_STAT_TX_YELLOW_PRIO_4] = { .name = "tx_yellow_prio_4", - .offset = 0x52, + .reg = SYS_COUNT_TX_YELLOW_PRIO_4, }, [OCELOT_STAT_TX_YELLOW_PRIO_5] = { .name = "tx_yellow_prio_5", - .offset = 0x53, + .reg = SYS_COUNT_TX_YELLOW_PRIO_5, }, [OCELOT_STAT_TX_YELLOW_PRIO_6] = { .name = "tx_yellow_prio_6", - .offset = 0x54, + .reg = SYS_COUNT_TX_YELLOW_PRIO_6, }, [OCELOT_STAT_TX_YELLOW_PRIO_7] = { .name = "tx_yellow_prio_7", - .offset = 0x55, + .reg = SYS_COUNT_TX_YELLOW_PRIO_7, }, [OCELOT_STAT_TX_GREEN_PRIO_0] = { .name = "tx_green_prio_0", - .offset = 0x56, + .reg = SYS_COUNT_TX_GREEN_PRIO_0, }, [OCELOT_STAT_TX_GREEN_PRIO_1] = { .name = "tx_green_prio_1", - .offset = 0x57, + .reg = SYS_COUNT_TX_GREEN_PRIO_1, }, [OCELOT_STAT_TX_GREEN_PRIO_2] = { .name = "tx_green_prio_2", - .offset = 0x58, + .reg = SYS_COUNT_TX_GREEN_PRIO_2, }, [OCELOT_STAT_TX_GREEN_PRIO_3] = { .name = "tx_green_prio_3", - .offset = 0x59, + .reg = SYS_COUNT_TX_GREEN_PRIO_3, }, [OCELOT_STAT_TX_GREEN_PRIO_4] = { .name = "tx_green_prio_4", - .offset = 0x5A, + .reg = SYS_COUNT_TX_GREEN_PRIO_4, }, [OCELOT_STAT_TX_GREEN_PRIO_5] = { .name = "tx_green_prio_5", - .offset = 0x5B, + .reg = SYS_COUNT_TX_GREEN_PRIO_5, }, [OCELOT_STAT_TX_GREEN_PRIO_6] = { .name = "tx_green_prio_6", - .offset = 0x5C, + .reg = SYS_COUNT_TX_GREEN_PRIO_6, }, [OCELOT_STAT_TX_GREEN_PRIO_7] = { .name = "tx_green_prio_7", - .offset = 0x5D, + .reg = SYS_COUNT_TX_GREEN_PRIO_7, }, [OCELOT_STAT_TX_AGED] = { .name = "tx_aged", - .offset = 0x5E, + .reg = SYS_COUNT_TX_AGING, }, [OCELOT_STAT_DROP_LOCAL] = { .name = "drop_local", - .offset = 0x80, + .reg = SYS_COUNT_DROP_LOCAL, }, [OCELOT_STAT_DROP_TAIL] = { .name = "drop_tail", - .offset = 0x81, + .reg = SYS_COUNT_DROP_TAIL, }, [OCELOT_STAT_DROP_YELLOW_PRIO_0] = { .name = "drop_yellow_prio_0", - .offset = 0x82, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_0, }, [OCELOT_STAT_DROP_YELLOW_PRIO_1] = { .name = "drop_yellow_prio_1", - .offset = 0x83, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_1, }, [OCELOT_STAT_DROP_YELLOW_PRIO_2] = { .name = "drop_yellow_prio_2", - .offset = 0x84, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_2, }, [OCELOT_STAT_DROP_YELLOW_PRIO_3] = { .name = "drop_yellow_prio_3", - .offset = 0x85, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_3, }, [OCELOT_STAT_DROP_YELLOW_PRIO_4] = { .name = "drop_yellow_prio_4", - .offset = 0x86, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_4, }, [OCELOT_STAT_DROP_YELLOW_PRIO_5] = { .name = "drop_yellow_prio_5", - .offset = 0x87, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_5, }, [OCELOT_STAT_DROP_YELLOW_PRIO_6] = { .name = "drop_yellow_prio_6", - .offset = 0x88, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_6, }, [OCELOT_STAT_DROP_YELLOW_PRIO_7] = { .name = "drop_yellow_prio_7", - .offset = 0x89, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_7, }, [OCELOT_STAT_DROP_GREEN_PRIO_0] = { .name = "drop_green_prio_0", - .offset = 0x8A, + .reg = SYS_COUNT_DROP_GREEN_PRIO_0, }, [OCELOT_STAT_DROP_GREEN_PRIO_1] = { .name = "drop_green_prio_1", - .offset = 0x8B, + .reg = SYS_COUNT_DROP_GREEN_PRIO_1, }, [OCELOT_STAT_DROP_GREEN_PRIO_2] = { .name = "drop_green_prio_2", - .offset = 0x8C, + .reg = SYS_COUNT_DROP_GREEN_PRIO_2, }, [OCELOT_STAT_DROP_GREEN_PRIO_3] = { .name = "drop_green_prio_3", - .offset = 0x8D, + .reg = SYS_COUNT_DROP_GREEN_PRIO_3, }, [OCELOT_STAT_DROP_GREEN_PRIO_4] = { .name = "drop_green_prio_4", - .offset = 0x8E, + .reg = SYS_COUNT_DROP_GREEN_PRIO_4, }, [OCELOT_STAT_DROP_GREEN_PRIO_5] = { .name = "drop_green_prio_5", - .offset = 0x8F, + .reg = SYS_COUNT_DROP_GREEN_PRIO_5, }, [OCELOT_STAT_DROP_GREEN_PRIO_6] = { .name = "drop_green_prio_6", - .offset = 0x90, + .reg = SYS_COUNT_DROP_GREEN_PRIO_6, }, [OCELOT_STAT_DROP_GREEN_PRIO_7] = { .name = "drop_green_prio_7", - .offset = 0x91, + .reg = SYS_COUNT_DROP_GREEN_PRIO_7, }, }; diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c index 68991b021c56..306026e6aa11 100644 --- a/drivers/net/ethernet/mscc/ocelot.c +++ b/drivers/net/ethernet/mscc/ocelot.c @@ -1881,9 +1881,8 @@ static int ocelot_port_update_stats(struct ocelot *ocelot, int port) ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port), SYS_STAT_CFG); list_for_each_entry(region, &ocelot->stats_regions, node) { - err = ocelot_bulk_read_rix(ocelot, SYS_COUNT_RX_OCTETS, - region->offset, region->buf, - region->count); + err = ocelot_bulk_read(ocelot, region->base, region->buf, + region->count); if (err) return err; @@ -1978,7 +1977,7 @@ static int ocelot_prepare_stats_regions(struct ocelot *ocelot) if (ocelot->stats_layout[i].name[0] == '\0') continue; - if (region && ocelot->stats_layout[i].offset == last + 1) { + if (region && ocelot->stats_layout[i].reg == last + 4) { region->count++; } else { region = devm_kzalloc(ocelot->dev, sizeof(*region), @@ -1986,12 +1985,12 @@ static int ocelot_prepare_stats_regions(struct ocelot *ocelot) if (!region) return -ENOMEM; - region->offset = ocelot->stats_layout[i].offset; + region->base = ocelot->stats_layout[i].reg; region->count = 1; list_add_tail(®ion->node, &ocelot->stats_regions); } - last = ocelot->stats_layout[i].offset; + last = ocelot->stats_layout[i].reg; } list_for_each_entry(region, &ocelot->stats_regions, node) { diff --git a/drivers/net/ethernet/mscc/ocelot_vsc7514.c b/drivers/net/ethernet/mscc/ocelot_vsc7514.c index 9ff910560043..9c488953f541 100644 --- a/drivers/net/ethernet/mscc/ocelot_vsc7514.c +++ b/drivers/net/ethernet/mscc/ocelot_vsc7514.c @@ -99,375 +99,375 @@ static const struct reg_field ocelot_regfields[REGFIELD_MAX] = { static const struct ocelot_stat_layout ocelot_stats_layout[OCELOT_NUM_STATS] = { [OCELOT_STAT_RX_OCTETS] = { .name = "rx_octets", - .offset = 0x00, + .reg = SYS_COUNT_RX_OCTETS, }, [OCELOT_STAT_RX_UNICAST] = { .name = "rx_unicast", - .offset = 0x01, + .reg = SYS_COUNT_RX_UNICAST, }, [OCELOT_STAT_RX_MULTICAST] = { .name = "rx_multicast", - .offset = 0x02, + .reg = SYS_COUNT_RX_MULTICAST, }, [OCELOT_STAT_RX_BROADCAST] = { .name = "rx_broadcast", - .offset = 0x03, + .reg = SYS_COUNT_RX_BROADCAST, }, [OCELOT_STAT_RX_SHORTS] = { .name = "rx_shorts", - .offset = 0x04, + .reg = SYS_COUNT_RX_SHORTS, }, [OCELOT_STAT_RX_FRAGMENTS] = { .name = "rx_fragments", - .offset = 0x05, + .reg = SYS_COUNT_RX_FRAGMENTS, }, [OCELOT_STAT_RX_JABBERS] = { .name = "rx_jabbers", - .offset = 0x06, + .reg = SYS_COUNT_RX_JABBERS, }, [OCELOT_STAT_RX_CRC_ALIGN_ERRS] = { .name = "rx_crc_align_errs", - .offset = 0x07, + .reg = SYS_COUNT_RX_CRC_ALIGN_ERRS, }, [OCELOT_STAT_RX_SYM_ERRS] = { .name = "rx_sym_errs", - .offset = 0x08, + .reg = SYS_COUNT_RX_SYM_ERRS, }, [OCELOT_STAT_RX_64] = { .name = "rx_frames_below_65_octets", - .offset = 0x09, + .reg = SYS_COUNT_RX_64, }, [OCELOT_STAT_RX_65_127] = { .name = "rx_frames_65_to_127_octets", - .offset = 0x0A, + .reg = SYS_COUNT_RX_65_127, }, [OCELOT_STAT_RX_128_255] = { .name = "rx_frames_128_to_255_octets", - .offset = 0x0B, + .reg = SYS_COUNT_RX_128_255, }, [OCELOT_STAT_RX_256_511] = { .name = "rx_frames_256_to_511_octets", - .offset = 0x0C, + .reg = SYS_COUNT_RX_256_511, }, [OCELOT_STAT_RX_512_1023] = { .name = "rx_frames_512_to_1023_octets", - .offset = 0x0D, + .reg = SYS_COUNT_RX_512_1023, }, [OCELOT_STAT_RX_1024_1526] = { .name = "rx_frames_1024_to_1526_octets", - .offset = 0x0E, + .reg = SYS_COUNT_RX_1024_1526, }, [OCELOT_STAT_RX_1527_MAX] = { .name = "rx_frames_over_1526_octets", - .offset = 0x0F, + .reg = SYS_COUNT_RX_1527_MAX, }, [OCELOT_STAT_RX_PAUSE] = { .name = "rx_pause", - .offset = 0x10, + .reg = SYS_COUNT_RX_PAUSE, }, [OCELOT_STAT_RX_CONTROL] = { .name = "rx_control", - .offset = 0x11, + .reg = SYS_COUNT_RX_CONTROL, }, [OCELOT_STAT_RX_LONGS] = { .name = "rx_longs", - .offset = 0x12, + .reg = SYS_COUNT_RX_LONGS, }, [OCELOT_STAT_RX_CLASSIFIED_DROPS] = { .name = "rx_classified_drops", - .offset = 0x13, + .reg = SYS_COUNT_RX_CLASSIFIED_DROPS, }, [OCELOT_STAT_RX_RED_PRIO_0] = { .name = "rx_red_prio_0", - .offset = 0x14, + .reg = SYS_COUNT_RX_RED_PRIO_0, }, [OCELOT_STAT_RX_RED_PRIO_1] = { .name = "rx_red_prio_1", - .offset = 0x15, + .reg = SYS_COUNT_RX_RED_PRIO_1, }, [OCELOT_STAT_RX_RED_PRIO_2] = { .name = "rx_red_prio_2", - .offset = 0x16, + .reg = SYS_COUNT_RX_RED_PRIO_2, }, [OCELOT_STAT_RX_RED_PRIO_3] = { .name = "rx_red_prio_3", - .offset = 0x17, + .reg = SYS_COUNT_RX_RED_PRIO_3, }, [OCELOT_STAT_RX_RED_PRIO_4] = { .name = "rx_red_prio_4", - .offset = 0x18, + .reg = SYS_COUNT_RX_RED_PRIO_4, }, [OCELOT_STAT_RX_RED_PRIO_5] = { .name = "rx_red_prio_5", - .offset = 0x19, + .reg = SYS_COUNT_RX_RED_PRIO_5, }, [OCELOT_STAT_RX_RED_PRIO_6] = { .name = "rx_red_prio_6", - .offset = 0x1A, + .reg = SYS_COUNT_RX_RED_PRIO_6, }, [OCELOT_STAT_RX_RED_PRIO_7] = { .name = "rx_red_prio_7", - .offset = 0x1B, + .reg = SYS_COUNT_RX_RED_PRIO_7, }, [OCELOT_STAT_RX_YELLOW_PRIO_0] = { .name = "rx_yellow_prio_0", - .offset = 0x1C, + .reg = SYS_COUNT_RX_YELLOW_PRIO_0, }, [OCELOT_STAT_RX_YELLOW_PRIO_1] = { .name = "rx_yellow_prio_1", - .offset = 0x1D, + .reg = SYS_COUNT_RX_YELLOW_PRIO_1, }, [OCELOT_STAT_RX_YELLOW_PRIO_2] = { .name = "rx_yellow_prio_2", - .offset = 0x1E, + .reg = SYS_COUNT_RX_YELLOW_PRIO_2, }, [OCELOT_STAT_RX_YELLOW_PRIO_3] = { .name = "rx_yellow_prio_3", - .offset = 0x1F, + .reg = SYS_COUNT_RX_YELLOW_PRIO_3, }, [OCELOT_STAT_RX_YELLOW_PRIO_4] = { .name = "rx_yellow_prio_4", - .offset = 0x20, + .reg = SYS_COUNT_RX_YELLOW_PRIO_4, }, [OCELOT_STAT_RX_YELLOW_PRIO_5] = { .name = "rx_yellow_prio_5", - .offset = 0x21, + .reg = SYS_COUNT_RX_YELLOW_PRIO_5, }, [OCELOT_STAT_RX_YELLOW_PRIO_6] = { .name = "rx_yellow_prio_6", - .offset = 0x22, + .reg = SYS_COUNT_RX_YELLOW_PRIO_6, }, [OCELOT_STAT_RX_YELLOW_PRIO_7] = { .name = "rx_yellow_prio_7", - .offset = 0x23, + .reg = SYS_COUNT_RX_YELLOW_PRIO_7, }, [OCELOT_STAT_RX_GREEN_PRIO_0] = { .name = "rx_green_prio_0", - .offset = 0x24, + .reg = SYS_COUNT_RX_GREEN_PRIO_0, }, [OCELOT_STAT_RX_GREEN_PRIO_1] = { .name = "rx_green_prio_1", - .offset = 0x25, + .reg = SYS_COUNT_RX_GREEN_PRIO_1, }, [OCELOT_STAT_RX_GREEN_PRIO_2] = { .name = "rx_green_prio_2", - .offset = 0x26, + .reg = SYS_COUNT_RX_GREEN_PRIO_2, }, [OCELOT_STAT_RX_GREEN_PRIO_3] = { .name = "rx_green_prio_3", - .offset = 0x27, + .reg = SYS_COUNT_RX_GREEN_PRIO_3, }, [OCELOT_STAT_RX_GREEN_PRIO_4] = { .name = "rx_green_prio_4", - .offset = 0x28, + .reg = SYS_COUNT_RX_GREEN_PRIO_4, }, [OCELOT_STAT_RX_GREEN_PRIO_5] = { .name = "rx_green_prio_5", - .offset = 0x29, + .reg = SYS_COUNT_RX_GREEN_PRIO_5, }, [OCELOT_STAT_RX_GREEN_PRIO_6] = { .name = "rx_green_prio_6", - .offset = 0x2A, + .reg = SYS_COUNT_RX_GREEN_PRIO_6, }, [OCELOT_STAT_RX_GREEN_PRIO_7] = { .name = "rx_green_prio_7", - .offset = 0x2B, + .reg = SYS_COUNT_RX_GREEN_PRIO_7, }, [OCELOT_STAT_TX_OCTETS] = { .name = "tx_octets", - .offset = 0x40, + .reg = SYS_COUNT_TX_OCTETS, }, [OCELOT_STAT_TX_UNICAST] = { .name = "tx_unicast", - .offset = 0x41, + .reg = SYS_COUNT_TX_UNICAST, }, [OCELOT_STAT_TX_MULTICAST] = { .name = "tx_multicast", - .offset = 0x42, + .reg = SYS_COUNT_TX_MULTICAST, }, [OCELOT_STAT_TX_BROADCAST] = { .name = "tx_broadcast", - .offset = 0x43, + .reg = SYS_COUNT_TX_BROADCAST, }, [OCELOT_STAT_TX_COLLISION] = { .name = "tx_collision", - .offset = 0x44, + .reg = SYS_COUNT_TX_COLLISION, }, [OCELOT_STAT_TX_DROPS] = { .name = "tx_drops", - .offset = 0x45, + .reg = SYS_COUNT_TX_DROPS, }, [OCELOT_STAT_TX_PAUSE] = { .name = "tx_pause", - .offset = 0x46, + .reg = SYS_COUNT_TX_PAUSE, }, [OCELOT_STAT_TX_64] = { .name = "tx_frames_below_65_octets", - .offset = 0x47, + .reg = SYS_COUNT_TX_64, }, [OCELOT_STAT_TX_65_127] = { .name = "tx_frames_65_to_127_octets", - .offset = 0x48, + .reg = SYS_COUNT_TX_65_127, }, [OCELOT_STAT_TX_128_255] = { .name = "tx_frames_128_255_octets", - .offset = 0x49, + .reg = SYS_COUNT_TX_128_255, }, [OCELOT_STAT_TX_256_511] = { .name = "tx_frames_256_511_octets", - .offset = 0x4A, + .reg = SYS_COUNT_TX_256_511, }, [OCELOT_STAT_TX_512_1023] = { .name = "tx_frames_512_1023_octets", - .offset = 0x4B, + .reg = SYS_COUNT_TX_512_1023, }, [OCELOT_STAT_TX_1024_1526] = { .name = "tx_frames_1024_1526_octets", - .offset = 0x4C, + .reg = SYS_COUNT_TX_1024_1526, }, [OCELOT_STAT_TX_1527_MAX] = { .name = "tx_frames_over_1526_octets", - .offset = 0x4D, + .reg = SYS_COUNT_TX_1527_MAX, }, [OCELOT_STAT_TX_YELLOW_PRIO_0] = { .name = "tx_yellow_prio_0", - .offset = 0x4E, + .reg = SYS_COUNT_TX_YELLOW_PRIO_0, }, [OCELOT_STAT_TX_YELLOW_PRIO_1] = { .name = "tx_yellow_prio_1", - .offset = 0x4F, + .reg = SYS_COUNT_TX_YELLOW_PRIO_1, }, [OCELOT_STAT_TX_YELLOW_PRIO_2] = { .name = "tx_yellow_prio_2", - .offset = 0x50, + .reg = SYS_COUNT_TX_YELLOW_PRIO_2, }, [OCELOT_STAT_TX_YELLOW_PRIO_3] = { .name = "tx_yellow_prio_3", - .offset = 0x51, + .reg = SYS_COUNT_TX_YELLOW_PRIO_3, }, [OCELOT_STAT_TX_YELLOW_PRIO_4] = { .name = "tx_yellow_prio_4", - .offset = 0x52, + .reg = SYS_COUNT_TX_YELLOW_PRIO_4, }, [OCELOT_STAT_TX_YELLOW_PRIO_5] = { .name = "tx_yellow_prio_5", - .offset = 0x53, + .reg = SYS_COUNT_TX_YELLOW_PRIO_5, }, [OCELOT_STAT_TX_YELLOW_PRIO_6] = { .name = "tx_yellow_prio_6", - .offset = 0x54, + .reg = SYS_COUNT_TX_YELLOW_PRIO_6, }, [OCELOT_STAT_TX_YELLOW_PRIO_7] = { .name = "tx_yellow_prio_7", - .offset = 0x55, + .reg = SYS_COUNT_TX_YELLOW_PRIO_7, }, [OCELOT_STAT_TX_GREEN_PRIO_0] = { .name = "tx_green_prio_0", - .offset = 0x56, + .reg = SYS_COUNT_TX_GREEN_PRIO_0, }, [OCELOT_STAT_TX_GREEN_PRIO_1] = { .name = "tx_green_prio_1", - .offset = 0x57, + .reg = SYS_COUNT_TX_GREEN_PRIO_1, }, [OCELOT_STAT_TX_GREEN_PRIO_2] = { .name = "tx_green_prio_2", - .offset = 0x58, + .reg = SYS_COUNT_TX_GREEN_PRIO_2, }, [OCELOT_STAT_TX_GREEN_PRIO_3] = { .name = "tx_green_prio_3", - .offset = 0x59, + .reg = SYS_COUNT_TX_GREEN_PRIO_3, }, [OCELOT_STAT_TX_GREEN_PRIO_4] = { .name = "tx_green_prio_4", - .offset = 0x5A, + .reg = SYS_COUNT_TX_GREEN_PRIO_4, }, [OCELOT_STAT_TX_GREEN_PRIO_5] = { .name = "tx_green_prio_5", - .offset = 0x5B, + .reg = SYS_COUNT_TX_GREEN_PRIO_5, }, [OCELOT_STAT_TX_GREEN_PRIO_6] = { .name = "tx_green_prio_6", - .offset = 0x5C, + .reg = SYS_COUNT_TX_GREEN_PRIO_6, }, [OCELOT_STAT_TX_GREEN_PRIO_7] = { .name = "tx_green_prio_7", - .offset = 0x5D, + .reg = SYS_COUNT_TX_GREEN_PRIO_7, }, [OCELOT_STAT_TX_AGED] = { .name = "tx_aged", - .offset = 0x5E, + .reg = SYS_COUNT_TX_AGING, }, [OCELOT_STAT_DROP_LOCAL] = { .name = "drop_local", - .offset = 0x80, + .reg = SYS_COUNT_DROP_LOCAL, }, [OCELOT_STAT_DROP_TAIL] = { .name = "drop_tail", - .offset = 0x81, + .reg = SYS_COUNT_DROP_TAIL, }, [OCELOT_STAT_DROP_YELLOW_PRIO_0] = { .name = "drop_yellow_prio_0", - .offset = 0x82, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_0, }, [OCELOT_STAT_DROP_YELLOW_PRIO_1] = { .name = "drop_yellow_prio_1", - .offset = 0x83, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_1, }, [OCELOT_STAT_DROP_YELLOW_PRIO_2] = { .name = "drop_yellow_prio_2", - .offset = 0x84, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_2, }, [OCELOT_STAT_DROP_YELLOW_PRIO_3] = { .name = "drop_yellow_prio_3", - .offset = 0x85, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_3, }, [OCELOT_STAT_DROP_YELLOW_PRIO_4] = { .name = "drop_yellow_prio_4", - .offset = 0x86, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_4, }, [OCELOT_STAT_DROP_YELLOW_PRIO_5] = { .name = "drop_yellow_prio_5", - .offset = 0x87, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_5, }, [OCELOT_STAT_DROP_YELLOW_PRIO_6] = { .name = "drop_yellow_prio_6", - .offset = 0x88, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_6, }, [OCELOT_STAT_DROP_YELLOW_PRIO_7] = { .name = "drop_yellow_prio_7", - .offset = 0x89, + .reg = SYS_COUNT_DROP_YELLOW_PRIO_7, }, [OCELOT_STAT_DROP_GREEN_PRIO_0] = { .name = "drop_green_prio_0", - .offset = 0x8A, + .reg = SYS_COUNT_DROP_GREEN_PRIO_0, }, [OCELOT_STAT_DROP_GREEN_PRIO_1] = { .name = "drop_green_prio_1", - .offset = 0x8B, + .reg = SYS_COUNT_DROP_GREEN_PRIO_1, }, [OCELOT_STAT_DROP_GREEN_PRIO_2] = { .name = "drop_green_prio_2", - .offset = 0x8C, + .reg = SYS_COUNT_DROP_GREEN_PRIO_2, }, [OCELOT_STAT_DROP_GREEN_PRIO_3] = { .name = "drop_green_prio_3", - .offset = 0x8D, + .reg = SYS_COUNT_DROP_GREEN_PRIO_3, }, [OCELOT_STAT_DROP_GREEN_PRIO_4] = { .name = "drop_green_prio_4", - .offset = 0x8E, + .reg = SYS_COUNT_DROP_GREEN_PRIO_4, }, [OCELOT_STAT_DROP_GREEN_PRIO_5] = { .name = "drop_green_prio_5", - .offset = 0x8F, + .reg = SYS_COUNT_DROP_GREEN_PRIO_5, }, [OCELOT_STAT_DROP_GREEN_PRIO_6] = { .name = "drop_green_prio_6", - .offset = 0x90, + .reg = SYS_COUNT_DROP_GREEN_PRIO_6, }, [OCELOT_STAT_DROP_GREEN_PRIO_7] = { .name = "drop_green_prio_7", - .offset = 0x91, + .reg = SYS_COUNT_DROP_GREEN_PRIO_7, }, }; diff --git a/drivers/net/ethernet/mscc/vsc7514_regs.c b/drivers/net/ethernet/mscc/vsc7514_regs.c index 8ff935f7f150..9cf82ecf191c 100644 --- a/drivers/net/ethernet/mscc/vsc7514_regs.c +++ b/drivers/net/ethernet/mscc/vsc7514_regs.c @@ -188,6 +188,30 @@ const u32 vsc7514_sys_regmap[] = { REG(SYS_COUNT_RX_CONTROL, 0x000044), REG(SYS_COUNT_RX_LONGS, 0x000048), REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x00004c), + REG(SYS_COUNT_RX_RED_PRIO_0, 0x000050), + REG(SYS_COUNT_RX_RED_PRIO_1, 0x000054), + REG(SYS_COUNT_RX_RED_PRIO_2, 0x000058), + REG(SYS_COUNT_RX_RED_PRIO_3, 0x00005c), + REG(SYS_COUNT_RX_RED_PRIO_4, 0x000060), + REG(SYS_COUNT_RX_RED_PRIO_5, 0x000064), + REG(SYS_COUNT_RX_RED_PRIO_6, 0x000068), + REG(SYS_COUNT_RX_RED_PRIO_7, 0x00006c), + REG(SYS_COUNT_RX_YELLOW_PRIO_0, 0x000070), + REG(SYS_COUNT_RX_YELLOW_PRIO_1, 0x000074), + REG(SYS_COUNT_RX_YELLOW_PRIO_2, 0x000078), + REG(SYS_COUNT_RX_YELLOW_PRIO_3, 0x00007c), + REG(SYS_COUNT_RX_YELLOW_PRIO_4, 0x000080), + REG(SYS_COUNT_RX_YELLOW_PRIO_5, 0x000084), + REG(SYS_COUNT_RX_YELLOW_PRIO_6, 0x000088), + REG(SYS_COUNT_RX_YELLOW_PRIO_7, 0x00008c), + REG(SYS_COUNT_RX_GREEN_PRIO_0, 0x000090), + REG(SYS_COUNT_RX_GREEN_PRIO_1, 0x000094), + REG(SYS_COUNT_RX_GREEN_PRIO_2, 0x000098), + REG(SYS_COUNT_RX_GREEN_PRIO_3, 0x00009c), + REG(SYS_COUNT_RX_GREEN_PRIO_4, 0x0000a0), + REG(SYS_COUNT_RX_GREEN_PRIO_5, 0x0000a4), + REG(SYS_COUNT_RX_GREEN_PRIO_6, 0x0000a8), + REG(SYS_COUNT_RX_GREEN_PRIO_7, 0x0000ac), REG(SYS_COUNT_TX_OCTETS, 0x000100), REG(SYS_COUNT_TX_UNICAST, 0x000104), REG(SYS_COUNT_TX_MULTICAST, 0x000108), @@ -202,7 +226,41 @@ const u32 vsc7514_sys_regmap[] = { REG(SYS_COUNT_TX_512_1023, 0x00012c), REG(SYS_COUNT_TX_1024_1526, 0x000130), REG(SYS_COUNT_TX_1527_MAX, 0x000134), + REG(SYS_COUNT_TX_YELLOW_PRIO_0, 0x000138), + REG(SYS_COUNT_TX_YELLOW_PRIO_1, 0x00013c), + REG(SYS_COUNT_TX_YELLOW_PRIO_2, 0x000140), + REG(SYS_COUNT_TX_YELLOW_PRIO_3, 0x000144), + REG(SYS_COUNT_TX_YELLOW_PRIO_4, 0x000148), + REG(SYS_COUNT_TX_YELLOW_PRIO_5, 0x00014c), + REG(SYS_COUNT_TX_YELLOW_PRIO_6, 0x000150), + REG(SYS_COUNT_TX_YELLOW_PRIO_7, 0x000154), + REG(SYS_COUNT_TX_GREEN_PRIO_0, 0x000158), + REG(SYS_COUNT_TX_GREEN_PRIO_1, 0x00015c), + REG(SYS_COUNT_TX_GREEN_PRIO_2, 0x000160), + REG(SYS_COUNT_TX_GREEN_PRIO_3, 0x000164), + REG(SYS_COUNT_TX_GREEN_PRIO_4, 0x000168), + REG(SYS_COUNT_TX_GREEN_PRIO_5, 0x00016c), + REG(SYS_COUNT_TX_GREEN_PRIO_6, 0x000170), + REG(SYS_COUNT_TX_GREEN_PRIO_7, 0x000174), REG(SYS_COUNT_TX_AGING, 0x000178), + REG(SYS_COUNT_DROP_LOCAL, 0x000200), + REG(SYS_COUNT_DROP_TAIL, 0x000204), + REG(SYS_COUNT_DROP_YELLOW_PRIO_0, 0x000208), + REG(SYS_COUNT_DROP_YELLOW_PRIO_1, 0x00020c), + REG(SYS_COUNT_DROP_YELLOW_PRIO_2, 0x000210), + REG(SYS_COUNT_DROP_YELLOW_PRIO_3, 0x000214), + REG(SYS_COUNT_DROP_YELLOW_PRIO_4, 0x000218), + REG(SYS_COUNT_DROP_YELLOW_PRIO_5, 0x00021c), + REG(SYS_COUNT_DROP_YELLOW_PRIO_6, 0x000220), + REG(SYS_COUNT_DROP_YELLOW_PRIO_7, 0x000214), + REG(SYS_COUNT_DROP_GREEN_PRIO_0, 0x000218), + REG(SYS_COUNT_DROP_GREEN_PRIO_1, 0x00021c), + REG(SYS_COUNT_DROP_GREEN_PRIO_2, 0x000220), + REG(SYS_COUNT_DROP_GREEN_PRIO_3, 0x000224), + REG(SYS_COUNT_DROP_GREEN_PRIO_4, 0x000228), + REG(SYS_COUNT_DROP_GREEN_PRIO_5, 0x00022c), + REG(SYS_COUNT_DROP_GREEN_PRIO_6, 0x000230), + REG(SYS_COUNT_DROP_GREEN_PRIO_7, 0x000234), REG(SYS_RESET_CFG, 0x000508), REG(SYS_CMID, 0x00050c), REG(SYS_VLAN_ETYPE_CFG, 0x000510), diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h index 2428bc64cb1d..2edea901bbd5 100644 --- a/include/soc/mscc/ocelot.h +++ b/include/soc/mscc/ocelot.h @@ -338,6 +338,30 @@ enum ocelot_reg { SYS_COUNT_RX_CONTROL, SYS_COUNT_RX_LONGS, SYS_COUNT_RX_CLASSIFIED_DROPS, + SYS_COUNT_RX_RED_PRIO_0, + SYS_COUNT_RX_RED_PRIO_1, + SYS_COUNT_RX_RED_PRIO_2, + SYS_COUNT_RX_RED_PRIO_3, + SYS_COUNT_RX_RED_PRIO_4, + SYS_COUNT_RX_RED_PRIO_5, + SYS_COUNT_RX_RED_PRIO_6, + SYS_COUNT_RX_RED_PRIO_7, + SYS_COUNT_RX_YELLOW_PRIO_0, + SYS_COUNT_RX_YELLOW_PRIO_1, + SYS_COUNT_RX_YELLOW_PRIO_2, + SYS_COUNT_RX_YELLOW_PRIO_3, + SYS_COUNT_RX_YELLOW_PRIO_4, + SYS_COUNT_RX_YELLOW_PRIO_5, + SYS_COUNT_RX_YELLOW_PRIO_6, + SYS_COUNT_RX_YELLOW_PRIO_7, + SYS_COUNT_RX_GREEN_PRIO_0, + SYS_COUNT_RX_GREEN_PRIO_1, + SYS_COUNT_RX_GREEN_PRIO_2, + SYS_COUNT_RX_GREEN_PRIO_3, + SYS_COUNT_RX_GREEN_PRIO_4, + SYS_COUNT_RX_GREEN_PRIO_5, + SYS_COUNT_RX_GREEN_PRIO_6, + SYS_COUNT_RX_GREEN_PRIO_7, SYS_COUNT_TX_OCTETS, SYS_COUNT_TX_UNICAST, SYS_COUNT_TX_MULTICAST, @@ -352,7 +376,41 @@ enum ocelot_reg { SYS_COUNT_TX_512_1023, SYS_COUNT_TX_1024_1526, SYS_COUNT_TX_1527_MAX, + SYS_COUNT_TX_YELLOW_PRIO_0, + SYS_COUNT_TX_YELLOW_PRIO_1, + SYS_COUNT_TX_YELLOW_PRIO_2, + SYS_COUNT_TX_YELLOW_PRIO_3, + SYS_COUNT_TX_YELLOW_PRIO_4, + SYS_COUNT_TX_YELLOW_PRIO_5, + SYS_COUNT_TX_YELLOW_PRIO_6, + SYS_COUNT_TX_YELLOW_PRIO_7, + SYS_COUNT_TX_GREEN_PRIO_0, + SYS_COUNT_TX_GREEN_PRIO_1, + SYS_COUNT_TX_GREEN_PRIO_2, + SYS_COUNT_TX_GREEN_PRIO_3, + SYS_COUNT_TX_GREEN_PRIO_4, + SYS_COUNT_TX_GREEN_PRIO_5, + SYS_COUNT_TX_GREEN_PRIO_6, + SYS_COUNT_TX_GREEN_PRIO_7, SYS_COUNT_TX_AGING, + SYS_COUNT_DROP_LOCAL, + SYS_COUNT_DROP_TAIL, + SYS_COUNT_DROP_YELLOW_PRIO_0, + SYS_COUNT_DROP_YELLOW_PRIO_1, + SYS_COUNT_DROP_YELLOW_PRIO_2, + SYS_COUNT_DROP_YELLOW_PRIO_3, + SYS_COUNT_DROP_YELLOW_PRIO_4, + SYS_COUNT_DROP_YELLOW_PRIO_5, + SYS_COUNT_DROP_YELLOW_PRIO_6, + SYS_COUNT_DROP_YELLOW_PRIO_7, + SYS_COUNT_DROP_GREEN_PRIO_0, + SYS_COUNT_DROP_GREEN_PRIO_1, + SYS_COUNT_DROP_GREEN_PRIO_2, + SYS_COUNT_DROP_GREEN_PRIO_3, + SYS_COUNT_DROP_GREEN_PRIO_4, + SYS_COUNT_DROP_GREEN_PRIO_5, + SYS_COUNT_DROP_GREEN_PRIO_6, + SYS_COUNT_DROP_GREEN_PRIO_7, SYS_RESET_CFG, SYS_SR_ETYPE_CFG, SYS_VLAN_ETYPE_CFG, @@ -633,13 +691,13 @@ enum ocelot_stat { }; struct ocelot_stat_layout { - u32 offset; + u32 reg; char name[ETH_GSTRING_LEN]; }; struct ocelot_stats_region { struct list_head node; - u32 offset; + u32 base; int count; u32 *buf; }; @@ -877,8 +935,8 @@ struct ocelot_policer { u32 burst; /* bytes */ }; -#define ocelot_bulk_read_rix(ocelot, reg, ri, buf, count) \ - __ocelot_bulk_read_ix(ocelot, reg, reg##_RSZ * (ri), buf, count) +#define ocelot_bulk_read(ocelot, reg, buf, count) \ + __ocelot_bulk_read_ix(ocelot, reg, 0, buf, count) #define ocelot_read_ix(ocelot, reg, gi, ri) \ __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) -- cgit v1.2.3 From e780e3193e889fd8358b862f7cd18ec5a4901caf Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Tue, 16 Aug 2022 16:53:52 +0300 Subject: net: mscc: ocelot: report ndo_get_stats64 from the wraparound-resistant ocelot->stats Rather than reading the stats64 counters directly from the 32-bit hardware, it's better to rely on the output produced by the periodic ocelot_port_update_stats(). It would be even better to call ocelot_port_update_stats() right from ocelot_get_stats64() to make sure we report the current values rather than the ones from 2 seconds ago. But we need to export ocelot_port_update_stats() from the switch lib towards the switchdev driver for that, and future work will largely undo that. There are more ocelot-based drivers waiting to be introduced, an example of which is the SPI-controlled VSC7512. In that driver's case, it will be impossible to call ocelot_port_update_stats() from ndo_get_stats64 context, since the latter is atomic, and reading the stats over SPI is sleepable. So the compromise taken here, which will also hold going forward, is to report 64-bit counters to stats64, which are not 100% up to date. Fixes: a556c76adc05 ("net: mscc: Add initial Ocelot switch support") Signed-off-by: Vladimir Oltean Signed-off-by: Jakub Kicinski --- drivers/net/ethernet/mscc/ocelot_net.c | 53 +++++++++++++++++----------------- 1 file changed, 26 insertions(+), 27 deletions(-) diff --git a/drivers/net/ethernet/mscc/ocelot_net.c b/drivers/net/ethernet/mscc/ocelot_net.c index 6b9d37138844..330d30841cdc 100644 --- a/drivers/net/ethernet/mscc/ocelot_net.c +++ b/drivers/net/ethernet/mscc/ocelot_net.c @@ -725,41 +725,40 @@ static void ocelot_get_stats64(struct net_device *dev, struct ocelot_port_private *priv = netdev_priv(dev); struct ocelot *ocelot = priv->port.ocelot; int port = priv->port.index; + u64 *s; spin_lock(&ocelot->stats_lock); - /* Configure the port to read the stats from */ - ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port), - SYS_STAT_CFG); + s = &ocelot->stats[port * OCELOT_NUM_STATS]; /* Get Rx stats */ - stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS); - stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) + - ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) + - ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) + - ocelot_read(ocelot, SYS_COUNT_RX_LONGS) + - ocelot_read(ocelot, SYS_COUNT_RX_64) + - ocelot_read(ocelot, SYS_COUNT_RX_65_127) + - ocelot_read(ocelot, SYS_COUNT_RX_128_255) + - ocelot_read(ocelot, SYS_COUNT_RX_256_511) + - ocelot_read(ocelot, SYS_COUNT_RX_512_1023) + - ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) + - ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX); - stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST); + stats->rx_bytes = s[OCELOT_STAT_RX_OCTETS]; + stats->rx_packets = s[OCELOT_STAT_RX_SHORTS] + + s[OCELOT_STAT_RX_FRAGMENTS] + + s[OCELOT_STAT_RX_JABBERS] + + s[OCELOT_STAT_RX_LONGS] + + s[OCELOT_STAT_RX_64] + + s[OCELOT_STAT_RX_65_127] + + s[OCELOT_STAT_RX_128_255] + + s[OCELOT_STAT_RX_256_511] + + s[OCELOT_STAT_RX_512_1023] + + s[OCELOT_STAT_RX_1024_1526] + + s[OCELOT_STAT_RX_1527_MAX]; + stats->multicast = s[OCELOT_STAT_RX_MULTICAST]; stats->rx_dropped = dev->stats.rx_dropped; /* Get Tx stats */ - stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS); - stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) + - ocelot_read(ocelot, SYS_COUNT_TX_65_127) + - ocelot_read(ocelot, SYS_COUNT_TX_128_255) + - ocelot_read(ocelot, SYS_COUNT_TX_256_511) + - ocelot_read(ocelot, SYS_COUNT_TX_512_1023) + - ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) + - ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX); - stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) + - ocelot_read(ocelot, SYS_COUNT_TX_AGING); - stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION); + stats->tx_bytes = s[OCELOT_STAT_TX_OCTETS]; + stats->tx_packets = s[OCELOT_STAT_TX_64] + + s[OCELOT_STAT_TX_65_127] + + s[OCELOT_STAT_TX_128_255] + + s[OCELOT_STAT_TX_256_511] + + s[OCELOT_STAT_TX_512_1023] + + s[OCELOT_STAT_TX_1024_1526] + + s[OCELOT_STAT_TX_1527_MAX]; + stats->tx_dropped = s[OCELOT_STAT_TX_DROPS] + + s[OCELOT_STAT_TX_AGED]; + stats->collisions = s[OCELOT_STAT_TX_COLLISION]; spin_unlock(&ocelot->stats_lock); } -- cgit v1.2.3 From d515f38c1e6dac42db145a778bd87a241f89590c Mon Sep 17 00:00:00 2001 From: Leon Romanovsky Date: Tue, 16 Aug 2022 11:47:23 +0300 Subject: net/mlx5e: Allocate flow steering storage during uplink initialization IPsec code relies on valid priv->fs pointer that is the case in NIC flow, but not correct in uplink. Before commit that mentioned in the Fixes line, that pointer was valid in all flows as it was allocated together with priv struct. In addition, the cleanup representors routine called to that not-initialized priv->fs pointer and its internals which caused NULL deference. So, move FS allocation to be as early as possible. Fixes: af8bbf730068 ("net/mlx5e: Convert mlx5e_flow_steering member of mlx5e_priv to pointer") Signed-off-by: Leon Romanovsky Link: https://lore.kernel.org/r/ae46fa5bed3c67f937bfdfc0370101278f5422f1.1660639564.git.leonro@nvidia.com Signed-off-by: Jakub Kicinski --- drivers/net/ethernet/mellanox/mlx5/core/en_rep.c | 25 ++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c index 4c1599de652c..0c66774a1720 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c @@ -696,6 +696,13 @@ static int mlx5e_init_rep(struct mlx5_core_dev *mdev, { struct mlx5e_priv *priv = netdev_priv(netdev); + priv->fs = mlx5e_fs_init(priv->profile, mdev, + !test_bit(MLX5E_STATE_DESTROYING, &priv->state)); + if (!priv->fs) { + netdev_err(priv->netdev, "FS allocation failed\n"); + return -ENOMEM; + } + mlx5e_build_rep_params(netdev); mlx5e_timestamp_init(priv); @@ -708,12 +715,21 @@ static int mlx5e_init_ul_rep(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv = netdev_priv(netdev); int err; + priv->fs = mlx5e_fs_init(priv->profile, mdev, + !test_bit(MLX5E_STATE_DESTROYING, &priv->state)); + if (!priv->fs) { + netdev_err(priv->netdev, "FS allocation failed\n"); + return -ENOMEM; + } + err = mlx5e_ipsec_init(priv); if (err) mlx5_core_err(mdev, "Uplink rep IPsec initialization failed, %d\n", err); mlx5e_vxlan_set_netdev_info(priv); - return mlx5e_init_rep(mdev, netdev); + mlx5e_build_rep_params(netdev); + mlx5e_timestamp_init(priv); + return 0; } static void mlx5e_cleanup_rep(struct mlx5e_priv *priv) @@ -836,13 +852,6 @@ static int mlx5e_init_rep_rx(struct mlx5e_priv *priv) struct mlx5_core_dev *mdev = priv->mdev; int err; - priv->fs = mlx5e_fs_init(priv->profile, mdev, - !test_bit(MLX5E_STATE_DESTROYING, &priv->state)); - if (!priv->fs) { - netdev_err(priv->netdev, "FS allocation failed\n"); - return -ENOMEM; - } - priv->rx_res = mlx5e_rx_res_alloc(); if (!priv->rx_res) { err = -ENOMEM; -- cgit v1.2.3 From a617ccc01608c3f422c65da1b6c7a31057f46f62 Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi Date: Tue, 16 Aug 2022 16:16:15 +0200 Subject: net: ethernet: mtk_eth_soc: fix possible NULL pointer dereference in mtk_xdp_run Fix possible NULL pointer dereference in mtk_xdp_run() if the ebpf program returns XDP_TX and xdp_convert_buff_to_frame routine fails returning NULL. Fixes: 5886d26fd25bb ("net: ethernet: mtk_eth_soc: add xmit XDP support") Signed-off-by: Lorenzo Bianconi Link: https://lore.kernel.org/r/627a07d759020356b64473e09f0855960e02db28.1660659112.git.lorenzo@kernel.org Signed-off-by: Jakub Kicinski --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index d9426b01f462..8aff4c0c28bd 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -1732,7 +1732,7 @@ static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring, case XDP_TX: { struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); - if (mtk_xdp_submit_frame(eth, xdpf, dev, false)) { + if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) { count = &hw_stats->xdp_stats.rx_xdp_tx_errors; act = XDP_DROP; break; -- cgit v1.2.3 From 573ae4f13f630d6660008f1974c0a8a29c30e18a Mon Sep 17 00:00:00 2001 From: Jens Wiklander Date: Thu, 18 Aug 2022 13:08:59 +0200 Subject: tee: add overflow check in register_shm_helper() With special lengths supplied by user space, register_shm_helper() has an integer overflow when calculating the number of pages covered by a supplied user space memory region. This causes internal_get_user_pages_fast() a helper function of pin_user_pages_fast() to do a NULL pointer dereference: Unable to handle kernel NULL pointer dereference at virtual address 0000000000000010 Modules linked in: CPU: 1 PID: 173 Comm: optee_example_a Not tainted 5.19.0 #11 Hardware name: QEMU QEMU Virtual Machine, BIOS 0.0.0 02/06/2015 pc : internal_get_user_pages_fast+0x474/0xa80 Call trace: internal_get_user_pages_fast+0x474/0xa80 pin_user_pages_fast+0x24/0x4c register_shm_helper+0x194/0x330 tee_shm_register_user_buf+0x78/0x120 tee_ioctl+0xd0/0x11a0 __arm64_sys_ioctl+0xa8/0xec invoke_syscall+0x48/0x114 Fix this by adding an an explicit call to access_ok() in tee_shm_register_user_buf() to catch an invalid user space address early. Fixes: 033ddf12bcf5 ("tee: add register user memory") Cc: stable@vger.kernel.org Reported-by: Nimish Mishra Reported-by: Anirban Chakraborty Reported-by: Debdeep Mukhopadhyay Suggested-by: Jerome Forissier Signed-off-by: Jens Wiklander Signed-off-by: Linus Torvalds --- drivers/tee/tee_shm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/tee/tee_shm.c b/drivers/tee/tee_shm.c index f2b1bcefcadd..1175f3a46859 100644 --- a/drivers/tee/tee_shm.c +++ b/drivers/tee/tee_shm.c @@ -326,6 +326,9 @@ struct tee_shm *tee_shm_register_user_buf(struct tee_context *ctx, void *ret; int id; + if (!access_ok((void __user *)addr, length)) + return ERR_PTR(-EFAULT); + mutex_lock(&teedev->mutex); id = idr_alloc(&teedev->idr, NULL, 1, 0, GFP_KERNEL); mutex_unlock(&teedev->mutex); -- cgit v1.2.3 From 5c23d6b717e4e956376f3852b90f58e262946b50 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Tue, 16 Aug 2022 16:23:57 +0200 Subject: stmmac: intel: Add a missing clk_disable_unprepare() call in intel_eth_pci_remove() Commit 09f012e64e4b ("stmmac: intel: Fix clock handling on error and remove paths") removed this clk_disable_unprepare() This was partly revert by commit ac322f86b56c ("net: stmmac: Fix clock handling on remove path") which removed this clk_disable_unprepare() because: " While unloading the dwmac-intel driver, clk_disable_unprepare() is being called twice in stmmac_dvr_remove() and intel_eth_pci_remove(). This causes kernel panic on the second call. " However later on, commit 5ec55823438e8 ("net: stmmac: add clocks management for gmac driver") has updated stmmac_dvr_remove() which do not call clk_disable_unprepare() anymore. So this call should now be called from intel_eth_pci_remove(). Fixes: 5ec55823438e8 ("net: stmmac: add clocks management for gmac driver") Signed-off-by: Christophe JAILLET Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/d7c8c1dadf40df3a7c9e643f76ffadd0ccc1ad1b.1660659689.git.christophe.jaillet@wanadoo.fr Signed-off-by: Jakub Kicinski --- drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c index 52f9ed8db9c9..4f2b82a884b9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -1134,6 +1134,7 @@ static void intel_eth_pci_remove(struct pci_dev *pdev) stmmac_dvr_remove(&pdev->dev); + clk_disable_unprepare(priv->plat->stmmac_clk); clk_unregister_fixed_rate(priv->plat->stmmac_clk); pcim_iounmap_regions(pdev, BIT(0)); -- cgit v1.2.3 From 249801360db3dec4f73768c502192020bfddeacc Mon Sep 17 00:00:00 2001 From: Jakub Kicinski Date: Tue, 16 Aug 2022 09:19:39 -0700 Subject: net: genl: fix error path memory leak in policy dumping If construction of the array of policies fails when recording non-first policy we need to unwind. netlink_policy_dump_add_policy() itself also needs fixing as it currently gives up on error without recording the allocated pointer in the pstate pointer. Reported-by: syzbot+dc54d9ba8153b216cae0@syzkaller.appspotmail.com Fixes: 50a896cf2d6f ("genetlink: properly support per-op policy dumping") Link: https://lore.kernel.org/r/20220816161939.577583-1-kuba@kernel.org Signed-off-by: Jakub Kicinski --- net/netlink/genetlink.c | 6 +++++- net/netlink/policy.c | 14 ++++++++++++-- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/net/netlink/genetlink.c b/net/netlink/genetlink.c index 1afca2a6c2ac..57010927e20a 100644 --- a/net/netlink/genetlink.c +++ b/net/netlink/genetlink.c @@ -1174,13 +1174,17 @@ static int ctrl_dumppolicy_start(struct netlink_callback *cb) op.policy, op.maxattr); if (err) - return err; + goto err_free_state; } } if (!ctx->state) return -ENODATA; return 0; + +err_free_state: + netlink_policy_dump_free(ctx->state); + return err; } static void *ctrl_dumppolicy_prep(struct sk_buff *skb, diff --git a/net/netlink/policy.c b/net/netlink/policy.c index 8d7c900e27f4..87e3de0fde89 100644 --- a/net/netlink/policy.c +++ b/net/netlink/policy.c @@ -144,7 +144,7 @@ int netlink_policy_dump_add_policy(struct netlink_policy_dump_state **pstate, err = add_policy(&state, policy, maxtype); if (err) - return err; + goto err_try_undo; for (policy_idx = 0; policy_idx < state->n_alloc && state->policies[policy_idx].policy; @@ -164,7 +164,7 @@ int netlink_policy_dump_add_policy(struct netlink_policy_dump_state **pstate, policy[type].nested_policy, policy[type].len); if (err) - return err; + goto err_try_undo; break; default: break; @@ -174,6 +174,16 @@ int netlink_policy_dump_add_policy(struct netlink_policy_dump_state **pstate, *pstate = state; return 0; + +err_try_undo: + /* Try to preserve reasonable unwind semantics - if we're starting from + * scratch clean up fully, otherwise record what we got and caller will. + */ + if (!*pstate) + netlink_policy_dump_free(state); + else + *pstate = state; + return err; } static bool -- cgit v1.2.3 From 8aa48ade7db4738bcc57447dccbf21db6618f64e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 17 Aug 2022 18:54:51 +0200 Subject: dt-bindings: Fix incorrect "the the" corrections Lots of double occurrences of "the" were replaced by single occurrences, but some of them should become "to the" instead. Fixes: 12e5bde18d7f6ca4 ("dt-bindings: Fix typo in comment") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/c5743c0a1a24b3a8893797b52fed88b99e56b04b.1660755148.git.geert+renesas@glider.be Signed-off-by: Jakub Kicinski --- Documentation/devicetree/bindings/net/qcom-emac.txt | 2 +- Documentation/devicetree/bindings/thermal/rcar-thermal.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/qcom-emac.txt b/Documentation/devicetree/bindings/net/qcom-emac.txt index e6cb2291471c..7ae8aa148634 100644 --- a/Documentation/devicetree/bindings/net/qcom-emac.txt +++ b/Documentation/devicetree/bindings/net/qcom-emac.txt @@ -14,7 +14,7 @@ MAC node: - mac-address : The 6-byte MAC address. If present, it is the default MAC address. - internal-phy : phandle to the internal PHY node -- phy-handle : phandle the external PHY node +- phy-handle : phandle to the external PHY node Internal PHY node: - compatible : Should be "qcom,fsm9900-emac-sgmii" or "qcom,qdf2432-emac-sgmii". diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.yaml b/Documentation/devicetree/bindings/thermal/rcar-thermal.yaml index 00dcbdd36144..119998d10ff4 100644 --- a/Documentation/devicetree/bindings/thermal/rcar-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.yaml @@ -42,7 +42,7 @@ properties: description: Address ranges of the thermal registers. If more then one range is given the first one must be the common registers followed by each sensor - according the datasheet. + according to the datasheet. minItems: 1 maxItems: 4 -- cgit v1.2.3 From 6faee3d4ee8be0f0367d0c3d826afb3571b7a5e0 Mon Sep 17 00:00:00 2001 From: Lin Ma Date: Wed, 17 Aug 2022 11:49:21 -0700 Subject: igb: Add lock to avoid data race The commit c23d92b80e0b ("igb: Teardown SR-IOV before unregister_netdev()") places the unregister_netdev() call after the igb_disable_sriov() call to avoid functionality issue. However, it introduces several race conditions when detaching a device. For example, when .remove() is called, the below interleaving leads to use-after-free. (FREE from device detaching) | (USE from netdev core) igb_remove | igb_ndo_get_vf_config igb_disable_sriov | vf >= adapter->vfs_allocated_count? kfree(adapter->vf_data) | adapter->vfs_allocated_count = 0 | | memcpy(... adapter->vf_data[vf] Moreover, the igb_disable_sriov() also suffers from data race with the requests from VF driver. (FREE from device detaching) | (USE from requests) igb_remove | igb_msix_other igb_disable_sriov | igb_msg_task kfree(adapter->vf_data) | vf < adapter->vfs_allocated_count adapter->vfs_allocated_count = 0 | To this end, this commit first eliminates the data races from netdev core by using rtnl_lock (similar to commit 719479230893 ("dpaa2-eth: add MAC/PHY support through phylink")). And then adds a spinlock to eliminate races from driver requests. (similar to commit 1e53834ce541 ("ixgbe: Add locking to prevent panic when setting sriov_numvfs to zero") Fixes: c23d92b80e0b ("igb: Teardown SR-IOV before unregister_netdev()") Signed-off-by: Lin Ma Tested-by: Konrad Jankowski Signed-off-by: Tony Nguyen Link: https://lore.kernel.org/r/20220817184921.735244-1-anthony.l.nguyen@intel.com Signed-off-by: Jakub Kicinski --- drivers/net/ethernet/intel/igb/igb.h | 2 ++ drivers/net/ethernet/intel/igb/igb_main.c | 12 +++++++++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/igb/igb.h b/drivers/net/ethernet/intel/igb/igb.h index 2d3daf022651..015b78144114 100644 --- a/drivers/net/ethernet/intel/igb/igb.h +++ b/drivers/net/ethernet/intel/igb/igb.h @@ -664,6 +664,8 @@ struct igb_adapter { struct igb_mac_addr *mac_table; struct vf_mac_filter vf_macs; struct vf_mac_filter *vf_mac_list; + /* lock for VF resources */ + spinlock_t vfs_lock; }; /* flags controlling PTP/1588 function */ diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c index d8b836a85cc3..2796e81d2726 100644 --- a/drivers/net/ethernet/intel/igb/igb_main.c +++ b/drivers/net/ethernet/intel/igb/igb_main.c @@ -3637,6 +3637,7 @@ static int igb_disable_sriov(struct pci_dev *pdev) struct net_device *netdev = pci_get_drvdata(pdev); struct igb_adapter *adapter = netdev_priv(netdev); struct e1000_hw *hw = &adapter->hw; + unsigned long flags; /* reclaim resources allocated to VFs */ if (adapter->vf_data) { @@ -3649,12 +3650,13 @@ static int igb_disable_sriov(struct pci_dev *pdev) pci_disable_sriov(pdev); msleep(500); } - + spin_lock_irqsave(&adapter->vfs_lock, flags); kfree(adapter->vf_mac_list); adapter->vf_mac_list = NULL; kfree(adapter->vf_data); adapter->vf_data = NULL; adapter->vfs_allocated_count = 0; + spin_unlock_irqrestore(&adapter->vfs_lock, flags); wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); wrfl(); msleep(100); @@ -3814,7 +3816,9 @@ static void igb_remove(struct pci_dev *pdev) igb_release_hw_control(adapter); #ifdef CONFIG_PCI_IOV + rtnl_lock(); igb_disable_sriov(pdev); + rtnl_unlock(); #endif unregister_netdev(netdev); @@ -3974,6 +3978,9 @@ static int igb_sw_init(struct igb_adapter *adapter) spin_lock_init(&adapter->nfc_lock); spin_lock_init(&adapter->stats64_lock); + + /* init spinlock to avoid concurrency of VF resources */ + spin_lock_init(&adapter->vfs_lock); #ifdef CONFIG_PCI_IOV switch (hw->mac.type) { case e1000_82576: @@ -7958,8 +7965,10 @@ unlock: static void igb_msg_task(struct igb_adapter *adapter) { struct e1000_hw *hw = &adapter->hw; + unsigned long flags; u32 vf; + spin_lock_irqsave(&adapter->vfs_lock, flags); for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { /* process any reset requests */ if (!igb_check_for_rst(hw, vf)) @@ -7973,6 +7982,7 @@ static void igb_msg_task(struct igb_adapter *adapter) if (!igb_check_for_ack(hw, vf)) igb_rcv_ack_from_vf(adapter, vf); } + spin_unlock_irqrestore(&adapter->vfs_lock, flags); } /** -- cgit v1.2.3 From e9c6e79760265f019cde39d3f2c443dfbc1395b0 Mon Sep 17 00:00:00 2001 From: Cong Wang Date: Wed, 17 Aug 2022 12:54:42 -0700 Subject: tcp: fix sock skb accounting in tcp_read_skb() Before commit 965b57b469a5 ("net: Introduce a new proto_ops ->read_skb()"), skb was not dequeued from receive queue hence when we close TCP socket skb can be just flushed synchronously. After this commit, we have to uncharge skb immediately after being dequeued, otherwise it is still charged in the original sock. And we still need to retain skb->sk, as eBPF programs may extract sock information from skb->sk. Therefore, we have to call skb_set_owner_sk_safe() here. Fixes: 965b57b469a5 ("net: Introduce a new proto_ops ->read_skb()") Reported-and-tested-by: syzbot+a0e6f8738b58f7654417@syzkaller.appspotmail.com Tested-by: Stanislav Fomichev Cc: Eric Dumazet Cc: John Fastabend Cc: Jakub Sitnicki Signed-off-by: Cong Wang Signed-off-by: Jakub Kicinski --- net/ipv4/tcp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index 970e9a2cca4a..05da5cac080b 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -1760,6 +1760,7 @@ int tcp_read_skb(struct sock *sk, skb_read_actor_t recv_actor) int used; __skb_unlink(skb, &sk->sk_receive_queue); + WARN_ON(!skb_set_owner_sk_safe(skb, sk)); used = recv_actor(sk, skb); if (used <= 0) { if (!copied) -- cgit v1.2.3 From c457985aaa92e1fda2ce837cabf90bf687b92dcb Mon Sep 17 00:00:00 2001 From: Cong Wang Date: Wed, 17 Aug 2022 12:54:43 -0700 Subject: tcp: fix tcp_cleanup_rbuf() for tcp_read_skb() tcp_cleanup_rbuf() retrieves the skb from sk_receive_queue, it assumes the skb is not yet dequeued. This is no longer true for tcp_read_skb() case where we dequeue the skb first. Fix this by introducing a helper __tcp_cleanup_rbuf() which does not require any skb and calling it in tcp_read_skb(). Fixes: 04919bed948d ("tcp: Introduce tcp_read_skb()") Cc: Eric Dumazet Cc: John Fastabend Cc: Jakub Sitnicki Signed-off-by: Cong Wang Signed-off-by: Jakub Kicinski --- net/ipv4/tcp.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index 05da5cac080b..181a0d350123 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -1567,17 +1567,11 @@ static int tcp_peek_sndq(struct sock *sk, struct msghdr *msg, int len) * calculation of whether or not we must ACK for the sake of * a window update. */ -void tcp_cleanup_rbuf(struct sock *sk, int copied) +static void __tcp_cleanup_rbuf(struct sock *sk, int copied) { struct tcp_sock *tp = tcp_sk(sk); bool time_to_ack = false; - struct sk_buff *skb = skb_peek(&sk->sk_receive_queue); - - WARN(skb && !before(tp->copied_seq, TCP_SKB_CB(skb)->end_seq), - "cleanup rbuf bug: copied %X seq %X rcvnxt %X\n", - tp->copied_seq, TCP_SKB_CB(skb)->end_seq, tp->rcv_nxt); - if (inet_csk_ack_scheduled(sk)) { const struct inet_connection_sock *icsk = inet_csk(sk); @@ -1623,6 +1617,17 @@ void tcp_cleanup_rbuf(struct sock *sk, int copied) tcp_send_ack(sk); } +void tcp_cleanup_rbuf(struct sock *sk, int copied) +{ + struct sk_buff *skb = skb_peek(&sk->sk_receive_queue); + struct tcp_sock *tp = tcp_sk(sk); + + WARN(skb && !before(tp->copied_seq, TCP_SKB_CB(skb)->end_seq), + "cleanup rbuf bug: copied %X seq %X rcvnxt %X\n", + tp->copied_seq, TCP_SKB_CB(skb)->end_seq, tp->rcv_nxt); + __tcp_cleanup_rbuf(sk, copied); +} + static void tcp_eat_recv_skb(struct sock *sk, struct sk_buff *skb) { __skb_unlink(skb, &sk->sk_receive_queue); @@ -1771,20 +1776,19 @@ int tcp_read_skb(struct sock *sk, skb_read_actor_t recv_actor) copied += used; if (TCP_SKB_CB(skb)->tcp_flags & TCPHDR_FIN) { - consume_skb(skb); ++seq; break; } - consume_skb(skb); break; } + consume_skb(skb); WRITE_ONCE(tp->copied_seq, seq); tcp_rcv_space_adjust(sk); /* Clean up data we have read: This will do ACK frames. */ if (copied > 0) - tcp_cleanup_rbuf(sk, copied); + __tcp_cleanup_rbuf(sk, copied); return copied; } -- cgit v1.2.3 From a8688821f3854f37fe0198b8945f9cfc051ab2cf Mon Sep 17 00:00:00 2001 From: Cong Wang Date: Wed, 17 Aug 2022 12:54:44 -0700 Subject: tcp: refactor tcp_read_skb() a bit As tcp_read_skb() only reads one skb at a time, the while loop is unnecessary, we can turn it into an if. This also simplifies the code logic. Cc: Eric Dumazet Cc: John Fastabend Cc: Jakub Sitnicki Signed-off-by: Cong Wang Signed-off-by: Jakub Kicinski --- net/ipv4/tcp.c | 26 +++++++++----------------- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index 181a0d350123..56a554b49caa 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -1761,25 +1761,17 @@ int tcp_read_skb(struct sock *sk, skb_read_actor_t recv_actor) if (sk->sk_state == TCP_LISTEN) return -ENOTCONN; - while ((skb = tcp_recv_skb(sk, seq, &offset)) != NULL) { - int used; - - __skb_unlink(skb, &sk->sk_receive_queue); - WARN_ON(!skb_set_owner_sk_safe(skb, sk)); - used = recv_actor(sk, skb); - if (used <= 0) { - if (!copied) - copied = used; - break; - } - seq += used; - copied += used; + skb = tcp_recv_skb(sk, seq, &offset); + if (!skb) + return 0; - if (TCP_SKB_CB(skb)->tcp_flags & TCPHDR_FIN) { + __skb_unlink(skb, &sk->sk_receive_queue); + WARN_ON(!skb_set_owner_sk_safe(skb, sk)); + copied = recv_actor(sk, skb); + if (copied > 0) { + seq += copied; + if (TCP_SKB_CB(skb)->tcp_flags & TCPHDR_FIN) ++seq; - break; - } - break; } consume_skb(skb); WRITE_ONCE(tp->copied_seq, seq); -- cgit v1.2.3 From 2e23acd99efacfd2a63cb9725afbc65e4e964fb7 Mon Sep 17 00:00:00 2001 From: Cong Wang Date: Wed, 17 Aug 2022 12:54:45 -0700 Subject: tcp: handle pure FIN case correctly When skb->len==0, the recv_actor() returns 0 too, but we also use 0 for error conditions. This patch amends this by propagating the errors to tcp_read_skb() so that we can distinguish skb->len==0 case from error cases. Fixes: 04919bed948d ("tcp: Introduce tcp_read_skb()") Reported-by: Eric Dumazet Cc: John Fastabend Cc: Jakub Sitnicki Signed-off-by: Cong Wang Signed-off-by: Jakub Kicinski --- net/core/skmsg.c | 5 +++-- net/ipv4/tcp.c | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/net/core/skmsg.c b/net/core/skmsg.c index f47338d89d5d..59e75ffcc1f4 100644 --- a/net/core/skmsg.c +++ b/net/core/skmsg.c @@ -1194,8 +1194,9 @@ static int sk_psock_verdict_recv(struct sock *sk, struct sk_buff *skb) ret = bpf_prog_run_pin_on_cpu(prog, skb); ret = sk_psock_map_verd(ret, skb_bpf_redirect_fetch(skb)); } - if (sk_psock_verdict_apply(psock, skb, ret) < 0) - len = 0; + ret = sk_psock_verdict_apply(psock, skb, ret); + if (ret < 0) + len = ret; out: rcu_read_unlock(); return len; diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index 56a554b49caa..bbe218753662 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -1768,7 +1768,7 @@ int tcp_read_skb(struct sock *sk, skb_read_actor_t recv_actor) __skb_unlink(skb, &sk->sk_receive_queue); WARN_ON(!skb_set_owner_sk_safe(skb, sk)); copied = recv_actor(sk, skb); - if (copied > 0) { + if (copied >= 0) { seq += copied; if (TCP_SKB_CB(skb)->tcp_flags & TCPHDR_FIN) ++seq; -- cgit v1.2.3 From f4693b81ea3802d2c28c868e1639e580d0da2d1f Mon Sep 17 00:00:00 2001 From: Sergei Antonov Date: Thu, 18 Aug 2022 12:23:17 +0300 Subject: net: moxa: MAC address reading, generating, validity checking This device does not remember its MAC address, so add a possibility to get it from the platform. If it fails, generate a random address. This will provide a MAC address early during boot without user space being involved. Also remove extra calls to is_valid_ether_addr(). Made after suggestions by Andrew Lunn: 1) Use eth_hw_addr_random() to assign a random MAC address during probe. 2) Remove is_valid_ether_addr() from moxart_mac_open() 3) Add a call to platform_get_ethdev_address() during probe 4) Remove is_valid_ether_addr() from moxart_set_mac_address(). The core does this v1 -> v2: Handle EPROBE_DEFER returned from platform_get_ethdev_address(). Move MAC reading code to the beginning of the probe function. Signed-off-by: Sergei Antonov Suggested-by: Andrew Lunn CC: Yang Yingliang CC: Pavel Skripkin CC: Guobin Huang CC: Yang Wei CC: Christophe JAILLET Reviewed-by: Andrew Lunn Reviewed-by: Vladimir Oltean Link: https://lore.kernel.org/r/20220818092317.529557-1-saproj@gmail.com Signed-off-by: Jakub Kicinski --- drivers/net/ethernet/moxa/moxart_ether.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/moxa/moxart_ether.c b/drivers/net/ethernet/moxa/moxart_ether.c index f11f1cb92025..19009a6bd33a 100644 --- a/drivers/net/ethernet/moxa/moxart_ether.c +++ b/drivers/net/ethernet/moxa/moxart_ether.c @@ -62,9 +62,6 @@ static int moxart_set_mac_address(struct net_device *ndev, void *addr) { struct sockaddr *address = addr; - if (!is_valid_ether_addr(address->sa_data)) - return -EADDRNOTAVAIL; - eth_hw_addr_set(ndev, address->sa_data); moxart_update_mac_address(ndev); @@ -172,9 +169,6 @@ static int moxart_mac_open(struct net_device *ndev) { struct moxart_mac_priv_t *priv = netdev_priv(ndev); - if (!is_valid_ether_addr(ndev->dev_addr)) - return -EADDRNOTAVAIL; - napi_enable(&priv->napi); moxart_mac_reset(ndev); @@ -488,6 +482,13 @@ static int moxart_mac_probe(struct platform_device *pdev) } ndev->base_addr = res->start; + ret = platform_get_ethdev_address(p_dev, ndev); + if (ret == -EPROBE_DEFER) + goto init_fail; + if (ret) + eth_hw_addr_random(ndev); + moxart_update_mac_address(ndev); + spin_lock_init(&priv->txlock); priv->tx_buf_size = TX_BUF_SIZE; -- cgit v1.2.3