From f28d7de6bd4d41774744e011141945affa127da4 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Thu, 16 Jan 2014 09:10:31 +0100 Subject: ARM: orion: provide C-style interrupt handler for MULTI_IRQ_HANDLER DT-enabled Marvell Kirkwood and Dove SoCs make use of an irqchip driver. As expected for irqchip drivers, it uses a C-style interrupt handler and therefore selects MULTI_IRQ_HANDLER. Now, compiling a kernel with both non-DT and DT support enabled, selecting MULTI_IRQ_HANDLER will break ASM irq handler used by non-DT boards. Therefore, we provide a C-style irq handler even for non-DT boards, if MULTI_IRQ_HANDLER is set. By installing the C-style irq handler in orion_irq_init this is transparent to all non-DT board files. While the regression report was filed on Marvell Kirkwood, also Marvell Dove non-DT boards are affected and fixed by this patch. Signed-off-by: Sebastian Hesselbarth Tested-by: Ian Campbell Reported-by: Ian Campbell Cc: # v3.12+ Fixes: 2326f04321a9 ("ARM: kirkwood: convert to DT irqchip and clocksource") Fixes: f07d73e33d0e ("ARM: dove: convert to DT irqchip and clocksource") Acked-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/plat-orion/irq.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c index c492e1b3dfdb..807df142444b 100644 --- a/arch/arm/plat-orion/irq.c +++ b/arch/arm/plat-orion/irq.c @@ -15,8 +15,51 @@ #include #include #include +#include #include #include +#include + +#ifdef CONFIG_MULTI_IRQ_HANDLER +/* + * Compiling with both non-DT and DT support enabled, will + * break asm irq handler used by non-DT boards. Therefore, + * we provide a C-style irq handler even for non-DT boards, + * if MULTI_IRQ_HANDLER is set. + * + * Notes: + * - this is prepared for Kirkwood and Dove only, update + * accordingly if you add Orion5x or MV78x00. + * - Orion5x uses different macro names and has only one + * set of CAUSE/MASK registers. + * - MV78x00 uses the same macro names but has a third + * set of CAUSE/MASK registers. + * + */ + +static void __iomem *orion_irq_base = IRQ_VIRT_BASE; + +asmlinkage void +__exception_irq_entry orion_legacy_handle_irq(struct pt_regs *regs) +{ + u32 stat; + + stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_LOW_OFF); + stat &= readl_relaxed(orion_irq_base + IRQ_MASK_LOW_OFF); + if (stat) { + unsigned int hwirq = __fls(stat); + handle_IRQ(hwirq, regs); + return; + } + stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_HIGH_OFF); + stat &= readl_relaxed(orion_irq_base + IRQ_MASK_HIGH_OFF); + if (stat) { + unsigned int hwirq = 32 + __fls(stat); + handle_IRQ(hwirq, regs); + return; + } +} +#endif void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) { @@ -35,6 +78,10 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) ct->chip.irq_unmask = irq_gc_mask_set_bit; irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); + +#ifdef CONFIG_MULTI_IRQ_HANDLER + set_handle_irq(orion_legacy_handle_irq); +#endif } #ifdef CONFIG_OF -- cgit v1.2.3 From 77dfdeb41125b6468790fa4c620da262c910cbc9 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Fri, 17 Jan 2014 15:52:11 -0300 Subject: ARM: kirkwood: kirkwood_pm_init() should return void This function was originally meant to return void as declared in the common.h header. Fix it and include the header to catch these errors in the future. [jac] removed 'return 0;' to clear this warning: arch/arm/mach-kirkwood/pm.c: In function 'kirkwood_pm_init': arch/arm/mach-kirkwood/pm.c:73:2: warning: 'return' with a value, in function returning void [enabled by default] Reported-by: Andrew Lunn Signed-off-by: Ezequiel Garcia Acked-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-kirkwood/pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-kirkwood/pm.c b/arch/arm/mach-kirkwood/pm.c index 8783a7184e73..c6ab8d9303a5 100644 --- a/arch/arm/mach-kirkwood/pm.c +++ b/arch/arm/mach-kirkwood/pm.c @@ -18,6 +18,7 @@ #include #include #include +#include "common.h" static void __iomem *ddr_operation_base; @@ -65,9 +66,8 @@ static const struct platform_suspend_ops kirkwood_suspend_ops = { .valid = kirkwood_pm_valid_standby, }; -int __init kirkwood_pm_init(void) +void __init kirkwood_pm_init(void) { ddr_operation_base = ioremap(DDR_OPERATION_BASE, 4); suspend_set_ops(&kirkwood_suspend_ops); - return 0; } -- cgit v1.2.3 From dc4910d9e93f8cc56b190dd8fc9e789135978216 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 20 Jan 2014 15:59:50 +0100 Subject: ARM: mvebu: Fix kernel hang in mvebu_soc_id_init() when of_iomap failed When pci_base is accessed whereas it has not been properly mapped by of_iomap() the kernel hang. The check of this pointer made an improper use of IS_ERR() instead of comparing to NULL. This patch fix this issue. Signed-off-by: Gregory CLEMENT Reported-by: Ezequiel Garcia Cc: stable@vger.kernel.org # v3.12+: af8d1c63afcb: ARM: mvebu: Add support to get the ID and the revision of a SoC Cc: stable@vger.kernel.org # v3.12+: 85e618a1be2b: ARM: mvebu: Add quirk for i2c for the OpenBlocks AX3-4 board Cc: stable@vger.kernel.org # v3.12+: 6cf70ae928ba: i2c: mv64xxx: Fix bus hang on A0 version of the Armada XP SoCs Cc: stable@vger.kernel.org # v3.12+: f8b94beb7e6a: i2c: mv64xxx: Document the newly introduced Armada XP A0 compatible Cc: stable@vger.kernel.org # v3.12+ Fixes: 930ab3d403ae (i2c: mv64xxx: Add I2C Transaction Generator support) Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/mvebu-soc-id.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.c b/arch/arm/mach-mvebu/mvebu-soc-id.c index fe4fc1cbdfaf..f3b325f6cbd4 100644 --- a/arch/arm/mach-mvebu/mvebu-soc-id.c +++ b/arch/arm/mach-mvebu/mvebu-soc-id.c @@ -88,7 +88,7 @@ static int __init mvebu_soc_id_init(void) } pci_base = of_iomap(child, 0); - if (IS_ERR(pci_base)) { + if (pci_base == NULL) { pr_err("cannot map registers\n"); ret = -ENOMEM; goto res_ioremap; -- cgit v1.2.3 From 19e61d41404fe4094c2d54943dbf883d9bbca864 Mon Sep 17 00:00:00 2001 From: Arnaud Ebalard Date: Mon, 20 Jan 2014 22:52:05 +0100 Subject: ARM: mvebu: fix compilation warning on Armada 370 (i.e. non-SMP) The following appears during compilation for an Armada 370 target because 'irq_controller_lock' is used only when CONFIG_SMP is enabled: drivers/irqchip/irq-armada-370-xp.c:62:8: warning: 'irq_controller_lock' defined but not used [-Wunused-variable] Fix that warning by moving declaration of 'irq_controller_lock' inside existing #ifdef. Signed-off-by: Arnaud Ebalard Signed-off-by: Jason Cooper --- drivers/irqchip/irq-armada-370-xp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index 433cc8568dec..9300bc32784e 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -59,8 +59,6 @@ #define PCI_MSI_DOORBELL_END (32) #define PCI_MSI_DOORBELL_MASK 0xFFFF0000 -static DEFINE_RAW_SPINLOCK(irq_controller_lock); - static void __iomem *per_cpu_int_base; static void __iomem *main_int_base; static struct irq_domain *armada_370_xp_mpic_domain; @@ -239,6 +237,8 @@ static inline int armada_370_xp_msi_init(struct device_node *node, #endif #ifdef CONFIG_SMP +static DEFINE_RAW_SPINLOCK(irq_controller_lock); + static int armada_xp_set_affinity(struct irq_data *d, const struct cpumask *mask_val, bool force) { -- cgit v1.2.3