From 016f9663156fe7e1402ef5ebaaca55d67f639966 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 11 Sep 2018 11:12:49 +0100 Subject: clk: renesas: r8a7743: Add r8a7744 support Add RZ/G1N (R8A7744) Clock Pulse Generator / Module Standby and Software Reset support. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Simon Horman Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/Kconfig | 2 +- drivers/clk/renesas/r8a7743-cpg-mssr.c | 13 ++++++++++++- drivers/clk/renesas/renesas-cpg-mssr.c | 5 +++++ 3 files changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 2edcb1bdb487..7a6ceecc213e 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -6,7 +6,7 @@ config CLK_RENESAS select CLK_R7S9210 if ARCH_R7S9210 select CLK_R8A73A4 if ARCH_R8A73A4 select CLK_R8A7740 if ARCH_R8A7740 - select CLK_R8A7743 if ARCH_R8A7743 + select CLK_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744 select CLK_R8A7745 if ARCH_R8A7745 select CLK_R8A77470 if ARCH_R8A77470 select CLK_R8A774A1 if ARCH_R8A774A1 diff --git a/drivers/clk/renesas/r8a7743-cpg-mssr.c b/drivers/clk/renesas/r8a7743-cpg-mssr.c index 011c170ec3f9..ab994f4c1ec8 100644 --- a/drivers/clk/renesas/r8a7743-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7743-cpg-mssr.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -37,7 +38,7 @@ enum clk_ids { MOD_CLK_BASE }; -static const struct cpg_core_clk r8a7743_core_clks[] __initconst = { +static struct cpg_core_clk r8a7743_core_clks[] __initdata = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("usb_extal", CLK_USB_EXTAL), @@ -238,6 +239,8 @@ static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = { static int __init r8a7743_cpg_mssr_init(struct device *dev) { const struct rcar_gen2_cpg_pll_config *cpg_pll_config; + struct device_node *np = dev->of_node; + unsigned int i; u32 cpg_mode; int error; @@ -247,6 +250,14 @@ static int __init r8a7743_cpg_mssr_init(struct device *dev) cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; + if (of_device_is_compatible(np, "renesas,r8a7744-cpg-mssr")) { + /* RZ/G1N uses a 1/5 divider for ZG */ + for (i = 0; i < ARRAY_SIZE(r8a7743_core_clks); i++) + if (r8a7743_core_clks[i].id == R8A7743_CLK_ZG) { + r8a7743_core_clks[i].div = 5; + break; + } + } return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode); } diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index b97e0e3ff0b1..c4beec7b563f 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -693,6 +693,11 @@ static const struct of_device_id cpg_mssr_match[] = { .compatible = "renesas,r8a7743-cpg-mssr", .data = &r8a7743_cpg_mssr_info, }, + /* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */ + { + .compatible = "renesas,r8a7744-cpg-mssr", + .data = &r8a7743_cpg_mssr_info, + }, #endif #ifdef CONFIG_CLK_R8A7745 { -- cgit v1.2.3