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2021-01-26drm/i915: Introduce intel_dbuf_slice_size()Ville Syrjälä2-16/+21
2021-01-26drm/i915: Pass the crtc to skl_compute_dbuf_slices()Ville Syrjälä1-12/+10
2021-01-26drm/i915: Extract intel_crtc_ddb_weight()Ville Syrjälä1-18/+27
2021-01-25drm/i915: Fix vblank evasion with vrrVille Syrjälä1-1/+4
2021-01-25drm/i915: Fix vblank timestamps with VRRVille Syrjälä4-6/+34
2021-01-25drm/i915: Add vrr state dumpVille Syrjälä1-0/+7
2021-01-25drm/i915/display: Helpers for VRR vblank min and max startVille Syrjälä2-0/+38
2021-01-25drm/i915/display: Add HW state readout for VRRManasi Navare3-0/+26
2021-01-25drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP SinkManasi Navare2-1/+20
2021-01-25drm/i915/display/vrr: Disable VRR in modeset disable pathManasi Navare3-0/+16
2021-01-25drm/i915/display/vrr: Send VRR push to flip the frameManasi Navare3-0/+18
2021-01-25drm/i915/display/vrr: Configure and enable VRR in modeset enableManasi Navare3-0/+28
2021-01-25drm/i915: Rename VRR_CTL reg fieldsVille Syrjälä1-7/+7
2021-01-25drm/i915/display: VRR + DRRS cannot be enabled togetherVille Syrjälä1-0/+3
2021-01-25drm/i915/display/dp: Do not enable PSR if VRR is enabledManasi Navare1-0/+7
2021-01-25drm/i915/display/dp: Compute VRR state in atomic_checkManasi Navare5-0/+95
2021-01-25drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp()Ville Syrjälä1-14/+24
2021-01-25drm/i915: Extract intel_mode_vblank_start()Ville Syrjälä1-3/+11
2021-01-25drm/i915: Store framestart_delay in dev_privVille Syrjälä2-11/+14
2021-01-25drm/i915/display/dp: Attach and set drm connector VRR propertyAditya Swarup2-2/+10
2021-01-25drm/i915/display/vrr: Create VRR file and add VRR capability checkManasi Navare4-0/+49
2021-01-22drm/i915/tgl: Add Clear Color support for TGL Render DecompressionRadhakrishna Sripada4-5/+116
2021-01-22drm/i915/gem: Add a helper to read data from a GEM object pageImre Deak2-0/+73
2021-01-22drm/i915/hdcp: Fix uninitialized symbolAnshuman Gupta1-10/+10
2021-01-22drm/i915/hdcp: Fix WARN_ON(data->k > INTEL_NUM_PIPES)Anshuman Gupta1-0/+2
2021-01-21drm/i915/dp: Don't use DPCD backlights that need PWM enable/disableLyude Paul1-1/+6
2021-01-21drm/i915: Unify the sanity checks for the buf trans tablesVille Syrjälä1-13/+10
2021-01-21drm/i915: Fix ICL MG PHY vswing handlingVille Syrjälä1-4/+3
2021-01-21drm/msm/dp: fix build after dp quirk helper changeJani Nikula1-4/+2
2021-01-21drm/i915/dp: split out aux functionality to intel_dp_aux.cJani Nikula6-681/+714
2021-01-21drm/i915/dp: abstract struct intel_dp pps members to a sub-structJani Nikula4-135/+140
2021-01-21drm/i915/pps: move pps code over from intel_display.c and refactorJani Nikula5-38/+42
2021-01-21drm/i915/pps: refactor init abstractionsJani Nikula1-25/+12
2021-01-19drm/dp: Revert "drm/dp: Introduce EDID-based quirks"Lyude Paul6-95/+6
2021-01-19drm/i915/dp: Allow forcing specific interfaces through enable_dpcd_backlightLyude Paul2-4/+43
2021-01-19drm/i915/dp: Enable Intel's HDR backlight interface (only SDR for now)Lyude Paul4-31/+269
2021-01-19drm/i915: Keep track of pwm-related backlight hooks separatelyLyude Paul2-150/+186
2021-01-19drm/i915: Reuse the async_flip() hook for the async flip disable w/aVille Syrjälä4-37/+35
2021-01-19drm/i915: Move the async_flip bit setup into the .async_flip() hookVille Syrjälä2-3/+2
2021-01-19drm/i915: Add plane vfuncs to enable/disable flip_done interruptVille Syrjälä5-33/+67
2021-01-19drm/i915: Generalize the async flip capability checkVille Syrjälä2-2/+4
2021-01-19drm/i915: Drop redundant parensVille Syrjälä1-1/+1
2021-01-19drm/i915: Fix the PHY compliance test vs. hotplug mishapVille Syrjälä3-1/+10
2021-01-19drm/i915: Fix the training pattern debug printVille Syrjälä1-5/+22
2021-01-19drm/i915: Disable TRAINING_PATTERN_SET before stopping the TPS transmissionVille Syrjälä1-6/+5
2021-01-18drm/i915: support two CSC module on gen11 and laterLee Shawn C2-13/+16
2021-01-15Merge drm/drm-next into drm-intel-nextRodrigo Vivi228-12802/+18878
2021-01-16drm/i915: split fdi code out from intel_display.cDave Airlie5-682/+718
2021-01-16drm/i915: refactor pll code out into intel_dpll.cDave Airlie6-1391/+1414
2021-01-16drm/i915: refactor some crtc code out of intel display. (v2)Dave Airlie4-304/+349
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