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2019-04-26dmaengine: imx-sdma: Only check ratio on parts that support 1:1Angus Ainslie (Purism)1-1/+14
On imx8mq B0 chip, AHB/SDMA clock ratio 2:1 can't be supported, since SDMA clock ratio has to be increased to 250Mhz, AHB can't reach to 500Mhz, so use 1:1 instead. To limit this change to the imx8mq for now this patch also adds an im8mq-sdma compatible string. Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca> Acked-by: Robin Gong <yibin.gong@nxp.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-03-14Merge tag 'dmaengine-5.1-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds1-12/+37
Pull dmaengine updates from Vinod Koul: - dmatest updates for modularizing common struct and code - remove SG support for VDMA xilinx IP and updates to driver - Update to dw driver to support Intel iDMA controllers multi-block support - tegra updates for proper reporting of residue - Add Snow Ridge ioatdma device id and support for IOATDMA v3.4 - struct_size() usage and useless LIST_HEAD cleanups in subsystem. - qDMA controller driver for Layerscape SoCs - stm32-dma PM Runtime support - And usual updates to imx-sdma, sprd, Documentation, fsl-edma, bcm2835, qcom_hidma etc * tag 'dmaengine-5.1-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (81 commits) dmaengine: imx-sdma: fix consistent dma test failures dmaengine: imx-sdma: add a test for imx8mq multi sdma devices dmaengine: imx-sdma: add clock ratio 1:1 check dmaengine: dmatest: move test data alloc & free into functions dmaengine: dmatest: add short-hand `buf_size` var in dmatest_func() dmaengine: dmatest: wrap src & dst data into a struct dmaengine: ioatdma: support latency tolerance report (LTR) for v3.4 dmaengine: ioatdma: add descriptor pre-fetch support for v3.4 dmaengine: ioatdma: disable DCA enabling on IOATDMA v3.4 dmaengine: ioatdma: Add Snow Ridge ioatdma device id dmaengine: sprd: Change channel id to slave id for DMA cell specifier dt-bindings: dmaengine: sprd: Change channel id to slave id for DMA cell specifier dmaengine: mv_xor: Use correct device for DMA API Documentation :dmaengine: clarify DMA desc. pointer after submission Documentation: dmaengine: fix dmatest.rst warning dmaengine: k3dma: Add support for dma-channel-mask dmaengine: k3dma: Delete axi_config dmaengine: k3dma: Upgrade k3dma driver to support hisi_asp_dma hardware Documentation: bindings: dma: Add binding for dma-channel-mask Documentation: bindings: k3dma: Extend the k3dma driver binding to support hisi-asp ...
2019-03-12Merge branch 'topic/imx' into for-linusVinod Koul1-7/+15
2019-02-25dmaengine: imx-sdma: fix consistent dma test failuresAngus Ainslie (Purism)1-0/+1
Without the copy being aligned sdma1 fails ~10% of the time Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-02-25dmaengine: imx-sdma: add a test for imx8mq multi sdma devicesAngus Ainslie (Purism)1-0/+6
On i.mx8mq, there are two sdma instances, and the common dma framework will get a channel dynamically from any available sdma instance whether it's the first sdma device or the second sdma device. Some IPs like SAI only work with sdma2 not sdma1. To make sure the sdma channel is from the correct sdma device, use the node pointer to match. Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-02-25dmaengine: imx-sdma: add clock ratio 1:1 checkAngus Ainslie (Purism)1-4/+14
On i.mx8 mscale B0 chip, AHB/SDMA clock ratio 2:1 can't be supportted, since SDMA clock ratio has to be increased to 250Mhz, AHB can't reach to 500Mhz, so use 1:1 instead. Based on NXP commit MLK-16841-1 by Robin Gong <yibin.gong@nxp.com> Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-01-20dmaengine: imx-sdma: pass ->dev to dma_alloc_coherent() APIAndy Duan1-7/+8
Pass ->dev to dma_alloc_coherent() API. We need this because dma_alloc_coherent() makes use of dev parameter and receiving NULL will result in a crash. Signed-off-by: Andy Duan <fugang.duan@nxp.com> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Robin Gong <yibin.gong@nxp.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-01-08dmaengine: imx-sdma: refine to load context only onceRobin Gong1-0/+7
The context loaded only one time before channel running,but currently sdma_config_channel() and dma_prep_* duplicated with sdma_load_context(), so refine it to load context only one time before channel running and reload after the channel terminated. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-01-08cross-tree: phase out dma_zalloc_coherent()Luis Chamberlain1-4/+4
We already need to zero out memory for dma_alloc_coherent(), as such using dma_zalloc_coherent() is superflous. Phase it out. This change was generated with the following Coccinelle SmPL patch: @ replace_dma_zalloc_coherent @ expression dev, size, data, handle, flags; @@ -dma_zalloc_coherent(dev, size, handle, flags) +dma_alloc_coherent(dev, size, handle, flags) Suggested-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Luis Chamberlain <mcgrof@kernel.org> [hch: re-ran the script on the latest tree] Signed-off-by: Christoph Hellwig <hch@lst.de>
2019-01-01Merge tag 'dmaengine-4.21-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds1-20/+40
Pull dmaengine updates from Vinod Koul: "This includes a new driver, removes R-Mobile APE6 as it is no longer used, sprd cyclic dma support, last batch of dma_slave_config direction removal and random updates to bunch of drivers. Summary: - New driver for UniPhier MIO DMA controller - Remove R-Mobile APE6 support - Sprd driver updates and support for cyclic link-list - Remove dma_slave_config direction usage from rest of drivers - Minor updates to dmatest, dw-dmac, zynqmp and bcm dma drivers" * tag 'dmaengine-4.21-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (48 commits) dmaengine: qcom_hidma: convert to DEFINE_SHOW_ATTRIBUTE dmaengine: pxa: remove DBGFS_FUNC_DECL() dmaengine: mic_x100_dma: convert to DEFINE_SHOW_ATTRIBUTE dmaengine: amba-pl08x: convert to DEFINE_SHOW_ATTRIBUTE dmaengine: Documentation: Add documentation for multi chan testing dmaengine: dmatest: Add transfer_size parameter dmaengine: dmatest: Add alignment parameter dmaengine: dmatest: Use fixed point div to calculate iops dmaengine: dmatest: Add support for multi channel testing dmaengine: rcar-dmac: Document R8A774C0 bindings dt-bindings: dmaengine: usb-dmac: Add binding for r8a774c0 dmaengine: zynqmp_dma: replace spin_lock_bh with spin_lock_irqsave dmaengine: sprd: Add me as one of the module authors dmaengine: sprd: Support DMA 2-stage transfer mode dmaengine: sprd: Support DMA link-list cyclic callback dmaengine: sprd: Set cur_desc as NULL when free or terminate one dma channel dmaengine: sprd: Fix the last link-list configuration dmaengine: sprd: Get transfer residue depending on the transfer direction dmaengine: sprd: Remove direction usage from struct dma_slave_config dmaengine: dmatest: fix a small memory leak in dmatest_func() ...
2018-12-31Merge branch 'topic/imx' into for-linusVinod Koul1-3/+1
2018-12-05dmaengine: imx-sdma: use GFP_NOWAIT for dma descriptor allocationsLucas Stach1-1/+1
DMA buffer descriptors aren't allocated from atomic context, so they can use the less heavyweigth GFP_NOWAIT. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Robin Gong <yibin.gong@nxp.com> Cc: stable <stable@vger.kernel.org> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-12-05dmaengine: imx-sdma: implement channel termination via workerLucas Stach1-13/+38
The dmaengine documentation states that device_terminate_all may be asynchronous and need not wait for the active transfers to stop. This allows us to move most of the functionality currently implemented in the sdma channel termination function to run in a worker, outside of any atomic context. Moving this out of atomic context has two benefits: we can now sleep while waiting for the channel to terminate, instead of busy waiting and the freeing of the dma descriptors happens with IRQs enabled, getting rid of a warning in the dma mapping code. As the termination is now async, we need to implement the device_synchronize dma engine function which simply waits for the worker to finish its execution. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Robin Gong <yibin.gong@nxp.com> Cc: stable <stable@vger.kernel.org> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-12-05Revert "dmaengine: imx-sdma: alloclate bd memory from dma pool"Lucas Stach1-12/+6
This reverts commit fe5b85c656bc. The SDMA engine needs the descriptors to be contiguous in memory. As the dma pool API is only able to provide a single descriptor per alloc invocation there is no guarantee that multiple descriptors satisfy this requirement. Also the code in question is broken as it only allocates memory for a single descriptor, without looking at the number of descriptors required for the transfer, leading to out-of-bounds accesses when the descriptors are written. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Robin Gong <yibin.gong@nxp.com> Cc: stable <stable@vger.kernel.org> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-12-05Revert "dmaengine: imx-sdma: Use GFP_NOWAIT for dma allocations"Lucas Stach1-2/+2
This reverts commit c1199875d327, as this depends on another commit that is going to be reverted. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Robin Gong <yibin.gong@nxp.com> Cc: stable <stable@vger.kernel.org> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-11-24dmaengine: imx-sdma: remove dma_slave_config direction usage and leave ↵Vinod Koul1-17/+39
sdma_event_enable() dma_slave_config direction was marked as deprecated quite some time back, remove the usage from this driver so that the field can be removed ENBLn bit should be set before any dma request triggered, please refer to the below information from i.mx6sololite RM. Otherwise, spi/uart test will be fail because there is dma request from tx fifo always before dmaengine_prep_slave_sg() in where ENBLn set and violate the below rule. https://www.nxp.com/docs/en/reference-manual/IMX6SLRM.pdf: 40.8.28 Channel Enable RAM (SDMAARM_CHNENBLn) "It is thus essential for the Arm platform to program them before any DMA request is triggered to the SDMA, otherwise an unpredictable combination of channels may be started". Signed-off-by: Robin Gong <yibin.gong@nxp.com> [vkoul: sqashed patch from Robin into direction change] Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-11-24dmaengine: imx-sdma: Use a single line for dma_alloc_coherent()Fabio Estevam1-3/+1
Make the call to dma_alloc_coherent() to fit into a single line, which helps readability. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-07-30dmaengine: imx-sdma: add memcpy interfaceRobin Gong1-3/+90
Add MEMCPY capability for imx-sdma driver. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-07-30dmaengine: imx-sdma: add SDMA_BD_MAX_CNT to replace '0xffff'Robin Gong1-5/+6
Add macro SDMA_BD_MAX_CNT to replace '0xffff'. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-07-06dmaengine: imx-sdma: add missing structure descriptionRobin Gong1-28/+57
Some member description or colons missing cause build warning with 'W=1' as below: drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'vd' not described in 'sdma_desc' drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'num_bd' not described in 'sdma_desc' drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'bd_phys' not described in 'sdma_desc' drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'buf_tail' not described in 'sdma_desc' drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'buf_ptail' not described in 'sdma_desc' drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'period_len' not described in 'sdma_desc' drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'chn_real_count' not described in 'sdma_desc' drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'chn_count' not described in 'sdma_desc Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reported-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-07-02dmaengine: imx-sdma: remove unused variableVinod Koul1-5/+2
The variable is no longer used, though it is set, so remove it drivers/dma/imx-sdma.c:1298:6: warning: variable ‘ret’ set but not used [-Wunused-but-set-variable] int ret, i, count; ^~~ Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-07-02dmaengine: imx-sdma: Use GFP_NOWAIT for dma allocationsVinod Koul1-2/+2
The memory allocation in DMA callbacks should use GFP_NOWAIT, so update this one and fix code alignment for this call while at it. Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-07-02dmaengine: imx-sdma: Fix some typosVinod Koul1-3/+3
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-07-02dmaengine: imx-sdma: alloclate bd memory from dma poolRobin Gong1-6/+12
dma_terminate_all maybe called in interrupt context which means WARN_ON() will be triggered as below when bd memory freed. Allocat bd memory from dma pool instead. [ 29.161079] WARNING: CPU: 1 PID: 533 at ./include/linux/dma-mapping.h:541 sdma_free_bd+0xa4/0xb4 [ 29.169883] Modules linked in: [ 29.172990] CPU: 1 PID: 533 Comm: mpegaudioparse0 Not tainted 4.18.0-rc1-next-20180618-00009-gf79f22c #20 [ 29.182597] Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree) [ 29.189163] Backtrace: [ 29.191685] [<c010d1e0>] (dump_backtrace) from [<c010d4a0>] (show_stack+0x18/0x1c) [ 29.199306] r7:00000000 r6:600f0093 r5:00000000 r4:c107db7c [ 29.205029] [<c010d488>] (show_stack) from [<c0a5bba0>] (dump_stack+0xb4/0xe8) [ 29.212312] [<c0a5baec>] (dump_stack) from [<c012703c>] (__warn+0x104/0x130) [ 29.219411] r9:ec3e817c r8:0000021d r7:00000009 r6:c0d1d440 r5:00000000 r4:00000000 [ 29.227204] [<c0126f38>] (__warn) from [<c0127180>] (warn_slowpath_null+0x44/0x50) [ 29.234821] r8:ed129dc4 r7:c0b01978 r6:c04d4e90 r5:0000021d r4:c0d1d440 [ 29.241574] [<c012713c>] (warn_slowpath_null) from [<c04d4e90>] (sdma_free_bd+0xa4/0xb4) [ 29.249706] r6:4c001000 r5:f082e000 r4:00000024 [ 29.254376] [<c04d4dec>] (sdma_free_bd) from [<c04d4eb4>] (sdma_desc_free+0x14/0x20) [ 29.262163] r7:ec3e8110 r6:00000100 r5:00000200 r4:ecf89a00 [ 29.267873] [<c04d4ea0>] (sdma_desc_free) from [<c04d229c>] (vchan_dma_desc_free_list+0xa4/0xac) [ 29.276697] r5:00000200 r4:ed129d9c [ 29.280326] [<c04d21f8>] (vchan_dma_desc_free_list) from [<c04d482c>] (sdma_disable_channel_with_delay+0x14c/0x188) [ 29.290808] r9:ecae560c r8:ec3e815c r7:00000000 r6:c1008908 r5:ed129dc4 r4:ec3e8110 [ 29.298605] [<c04d46e0>] (sdma_disable_channel_with_delay) from [<c07c5c84>] (snd_dmaengine_pcm_trigger+0x90/0x1b0) [ 29.309087] r8:ecae5000 r7:ec940800 r6:ed31bd80 r5:ecadb200 r4:ec26a700 [ 29.315855] [<c07c5bf4>] (snd_dmaengine_pcm_trigger) from [<c07dd800>] (soc_pcm_trigger+0xb4/0x130) [ 29.324953] r8:ecae5000 r7:ec940800 r6:00000000 r5:ecadb200 r4:ec26a700 [ 29.331716] [<c07dd74c>] (soc_pcm_trigger) from [<c07bc008>] (snd_pcm_do_stop+0x58/0x5c) [ 29.339859] r9:ecaed5a8 r8:ed31bdc0 r7:00000000 r6:00000001 r5:ecadb200 r4:c0b9c4d0 [ 29.347652] [<c07bbfb0>] (snd_pcm_do_stop) from [<c07bbde8>] (snd_pcm_action_single+0x40/0x80) [ 29.356315] [<c07bbda8>] (snd_pcm_action_single) from [<c07bbf1c>] (snd_pcm_action+0xf4/0xfc) [ 29.364883] r7:00000001 r6:c0b9c4d0 r5:ecadb2d4 r4:ecadb200 [ 29.370593] [<c07bbe28>] (snd_pcm_action) from [<c07bc8dc>] (snd_pcm_drop+0x58/0x9c) Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-07-02dmaengine: imx-sdma: add sdma_transfer_init to decrease code overlapRobin Gong1-46/+37
There are lot of codes overlap between prep_sg and prep_cyclic function. Add sdma_transfer_init() function to elimated the code overlap. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-07-02dmaengine: imx-sdma: remove the maximum limitation for bd numbersRobin Gong1-14/+0
No this limitation now after virtual dma used since bd is allocated dynamically instead of static. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-07-02dmaengine: imx-sdma: remove useless 'lock' and 'enabled' in 'struct ↵Robin Gong1-23/+0
sdma_channel' Since 'sdmac->vc.lock' and 'sdmac->desc' can be used as 'lock' and 'enabled' in 'struct sdma_channel sdmac', remove them. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-07-02dmaengine: imx-sdma: add virt-dma supportRobin Gong1-93/+170
The legacy sdma driver has below limitations or drawbacks: 1. Hardcode the max BDs number as "PAGE_SIZE / sizeof(*)", and alloc one page size for one channel regardless of only few BDs needed most time. But in few cases, the max PAGE_SIZE maybe not enough. 2. One SDMA channel can't stop immediatley once channel disabled which means SDMA interrupt may come in after this channel terminated.There are some patches for this corner case such as commit "2746e2c389f9", but not cover non-cyclic. The common virt-dma overcomes the above limitations. It can alloc bd dynamically and free bd once this tx transfer done. No memory wasted or maximum limititation here, only depends on how many memory can be requested from kernel. For No.2, such issue can be workaround by checking if there is available descript("sdmac->desc") now once the unwanted interrupt coming. At last the common virt-dma is easier for sdma driver maintain. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-07-02dmaengine: imx-sdma: factor out a struct sdma_desc from struct sdma_channelSascha Hauer1-54/+83
This is a preparation step to make the adding of virt-dma easier. We create a struct sdma_desc, move some fields from struct sdma_channel there and add a pointer from the former to the latter. For now we allocate the data statically in struct sdma_channel, but with virt-dma support it will be dynamically allocated. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-05-23dmaengine: imx-sdma: Switch to SPDX identifierFabio Estevam1-18/+11
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-03-05dmaengine: imx-sdma: fix pagefault when channel is disabled during interruptThierry Bultel1-0/+21
Add a spinlock and a 'enabled' boolean on channel descriptor, to avoid using buffer descriptors in the interrupt context, when sdma_disable_channel is called meanwhile. Signed-off-by: Thierry Bultel <tbultel@pixelsurmer.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-22dmaengine: imx-sdma: Add MODULE_FIRMWARENicolas Chauvet1-0/+6
This avoid the following error when using an initramfs on wandboard quad Direct firmware load for imx/sdma/sdma-imx6q.bin failed with error -2 Signed-off-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-21dmaengine: imx-sdma: Correct src_addr_widths and directionsNicolin Chen1-3/+11
The driver already supports DMA_DEV_TO_DEV in sdma_config(), DMA_SLAVE_BUSWIDTH_2_BYTES and DMA_SLAVE_BUSWIDTH_1_BYTE in sdma_prep_slave_sg(). So this patch adds them to the lists. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-05-30dmaengine: imx-sdma: Fix compilation warning.Arvind Yadav1-2/+2
Replace '%d' by '%zu' to fix the following compilation warning:- drivers/dma/imx-sdma.c: In function ‘sdma_prep_dma_cyclic’: drivers/dma/imx-sdma.c:1327:5: warning: format ‘%d’ expects argument of type ‘int’, but argument 4 has type ‘size_t’ [-Wformat=] channel, period_len, 0xffff); ^ drivers/dma/imx-sdma.c:1350:3: warning: format ‘%d’ expects argument of type ‘int’, but argument 5 has type ‘size_t’ [-Wformat=] dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-05-30dmaengine: imx-sdma: Handle return value of clk_prepare_enableArvind Yadav1-5/+18
clk_prepare_enable() can fail here and we must check its return value. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-03-27dmaengine: imx-sdma: add 1ms delay to ensure SDMA channel is stoppedJiada Wang1-1/+16
sdma_disable_channel() cannot ensure dma is stopped to access module's FIFOs. There is chance SDMA core is running and accessing BD when disable of corresponding channel, this may cause sometimes even after call of .sdma_disable_channel(), SDMA core still be running and accessing module's FIFOs. According to NXP R&D team a delay of one BD SDMA cost time (maximum is 1ms) should be added after disable of the channel bit, to ensure SDMA core has really been stopped after SDMA clients call .device_terminate_all. This patch introduces adds a new function sdma_disable_channel_with_delay() which simply adds 1ms delay after call sdma_disable_channel(), and set it as .device_terminate_all. Signed-off-by: Jiada Wang <jiada_wang@mentor.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-03-14dmaengine: imx-sdma: advertise correct residue granularityLucas Stach1-1/+1
The SDMA hardware/driver does not actually report the transfer residue at burst size granularity, but in fact is only able to report residue after each finished segment. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-11-25dmaengine: imx-sdma - correct the dma transfer residue calculationNandor Han1-4/+9
The residue calculation was taking in consideration that dma transaction status will be always retrieved in the dma callback used to inform that dma transfer is complete. However this is not the case for all subsystems that use dma. Some subsystems use a timer to check the dma status periodically. Therefore the calculation was updated and residue is calculated accordingly by a) update the residue calculation taking in consideration the last used buffer index by using *buf_ptail* variable and b) chn_real_count (number of bytes transferred) is initialized to zero, when dma channel is created, to avoid using an uninitialized value in residue calculation when dma status is checked without waiting dma complete event. Signed-off-by: Nandor Han <nandor.han@ge.com> Acked-by: Peter Senna Tschudin <peter.senna@collabora.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com> Tested-by: Marek Vasut <marex@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-10-06Merge tag 'dmaengine-4.9-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds1-5/+30
Pull dmaengine updates from Vinod Koul: "This is bit large pile of code which bring in some nice additions: - Error reporting: we have added a new mechanism for users of dmaenegine to register a callback_result which tells them the result of the dma transaction. Right now only one user (ntb) is using it. - As we discussed on KS mailing list and pointed out NO_IRQ has no place in kernel, this also remove NO_IRQ from dmaengine subsystem (both arm and ppc users) - Support for IOMMU slave transfers and its implementation for arm. - To get better build coverage, enable COMPILE_TEST for bunch of driver, and fix the warning and sparse complaints on these. - Apart from above, usual updates spread across drivers" * tag 'dmaengine-4.9-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (169 commits) async_pq_val: fix DMA memory leak dmaengine: virt-dma: move function declarations dmaengine: omap-dma: Enable burst and data pack for SG DT: dmaengine: rcar-dmac: document R8A7743/5 support dmaengine: fsldma: Unmap region obtained by of_iomap dmaengine: jz4780: fix resource leaks on error exit return dma-debug: fix ia64 build, use PHYS_PFN dmaengine: coh901318: fix integer overflow when shifting more than 32 places dmaengine: edma: avoid uninitialized variable use dma-mapping: fix m32r build warning dma-mapping: fix ia64 build, use PHYS_PFN dmaengine: ti-dma-crossbar: enable COMPILE_TEST dmaengine: omap-dma: enable COMPILE_TEST dmaengine: edma: enable COMPILE_TEST dmaengine: ti-dma-crossbar: Fix of_device_id data parameter usage dmaengine: ti-dma-crossbar: Correct type for of_find_property() third parameter dmaengine/ARM: omap-dma: Fix the DMAengine compile test on non OMAP configs dmaengine: edma: Rename set_bits and remove unused clear_bits helper dmaengine: edma: Use correct type for of_find_property() third parameter dmaengine: edma: Fix of_device_id data parameter usage (legacy vs TPCC) ...
2016-10-03Merge branch 'topic/imx' into for-linusVinod Koul1-1/+27
2016-08-31dmaengine: imx-sdma - update the residue calculation for cyclic channelsNandor Han1-2/+18
The calculation of the DMA transaction residue supports only fixed size data transfers. This implementation is not covering all operations (e.g. data receiving) when we need to know the exact amount of bytes transferred. The loop channels handling was changed to clear the buffer descriptor errors and use the bd->mode.count to calculate the residue. Tested-by: Peter Senna Tschudin <peter.senna@collabora.com> Acked-by: Peter Senna Tschudin <peter.senna@collabora.com> Reviewed-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Nandor Han <nandor.han@ge.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-08-31dmaengine: imx-sdma - reduce transfer latency for DMA cyclic clientsNandor Han1-20/+16
Having the SDMA driver use a tasklet for running the clients callback introduce some issues: - probability to have desynchronized data because of the race condition created since the DMA transaction status is retrieved only when the callback is executed, leaving plenty of time for transaction status to get altered. - inter-transfer latency which can leave channels idle. Move the callback execution, for cyclic channels, to SDMA interrupt (as advised in `Documentation/dmaengine/provider.txt`) to (a)reduce the inter-transfer latency and (b) eliminate the race condition possibility where DMA transaction status might be changed by the time is read. The responsibility of the SDMA interrupt latency is moved to the SDMA clients which case by case should defer the work to bottom-halves when needed. Tested-by: Peter Senna Tschudin <peter.senna@collabora.com> Acked-by: Peter Senna Tschudin <peter.senna@collabora.com> Reviewed-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Nandor Han <nandor.han@ge.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-08-31dmaengine: imx-sdma: Add i.MX7 supportFabio Estevam1-0/+26
Allow i.MX7 to work with the imx-sdma driver. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-08-10dmaengine: imx-sdma: (trivial) fix a typoMartin Kaiser1-1/+1
Signed-off-by: Martin Kaiser <martin@kaiser.cx> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-08-08dmaengine: imx-sdma: convert callback to helper functionDave Jiang1-4/+3
This is in preperation of moving to a callback that provides results to the callback for the transaction. The conversion will maintain current behavior and the driver must convert to new callback mechanism at a later time in order to receive results. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-23dmaengine: imx-sdma: remove assignment never usedVinod Koul1-2/+1
David reported: [drivers/dma/imx-sdma.c:769]: (style) Variable 'emi_2_emi' is assigned a value that is never used Since emi_2_emi is never used afterwards, remove thsi as well Reported-by: David Binderman <dcb314@hotmail.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-23dmaengine: imx-sdma: remove dummy assignmentVinod Koul1-2/+0
David reported: drivers/dma/imx-sdma.c:1003]: (style) Same expression on both sides of '|=' ORing with itself yields same result, So remove this Reported-by: David Binderman <dcb314@hotmail.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-16dmaengine: imx-sdma: explicitly freeup irqVinod Koul1-0/+4
dmaengine device should explicitly call devm_free_irq() when using devm_request_irq(). The irq is still ON when devices remove is executed and irq should be quiesced before remove is completed. Signed-off-by: Vinod Koul <vinod.koul@intel.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
2016-07-12dmaengine: imx-sdma: ack channel 0 IRQ in the interrupt handlerMichael Olbrich1-15/+8
Currently the handler ignores the channel 0 interrupt and thus doesn't ack it properly. This is done in order to allow sdma_run_channel0() to poll on the irq status bit, as this function may be called in atomic context, but needs to know when the channel has finished. This works mostly, as the polling happens under a spinlock, disabling IRQs on the local CPU, leaving only a very slight race window for a spurious IRQ to happen if the handler is executed on another CPU in an SMP system. Still this is clearly suboptimal. This behavior turns into a real problem on an RT system, where the spinlock doesn't disable IRQs on the local CPU. Not acking the IRQ in the handler in such a setup is very likely to drown the CPU in an IRQ storm, leaving it unable to make any progress in the polling loop, leading to the IRQ never being acked. Fix this by properly acknowledging the channel 0 IRQ in the handler. As the IRQ status bit can no longer be used to poll for the channel completion, switch over to using the SDMA_H_STATSTOP register for this purpose, where bit 0 is cleared by the hardware when the channel is done. Signed-off-by: Michael Olbrich <m.olbrich@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-11-16dmaengine: imx-sdma: remove __init annotation on sdma_event_remapJason Liu1-1/+1
The sdma_probe function will call sdma_event_remap, but sdma_event_remap marked with the __init annotation which make the kbuild complains as the following log: WARNING: drivers/dma/built-in.o(.text+0x56fc): Section mismatch in reference from the function sdma_probe() to the function .init.text:sdma_event_remap() The function sdma_probe() references the function __init sdma_event_remap(). This is often because sdma_probe lacks a __init annotation or the annotation of sdma_event_remap is wrong. Remove the __init annotation on sdma_event_remap to kill this build warning Signed-off-by: Jason Liu <r64343@freescale.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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