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2020-08-15Merge tag 'acpi-5.9-rc1-2' of ↵Linus Torvalds3-79/+102
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull more ACPI updates from Rafael Wysocki: "Add new hardware support to the ACPI driver for AMD SoCs, the x86 clk driver and the Designware i2c driver (changes from Akshu Agrawal and Pu Wen)" * tag 'acpi-5.9-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: clk: x86: Support RV architecture ACPI: APD: Add a fmw property is_raven clk: x86: Change name from ST to FCH ACPI: APD: Change name from ST to FCH i2c: designware: Add device HID for Hygon I2C controller
2020-08-14Merge tag 'pwm/for-5.9-rc1' of ↵Linus Torvalds1-1/+6
git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm Pull pwm updates from Thierry Reding: "The majority of this batch is conversion of the PWM period and duty cycle to 64-bit unsigned integers, which is required so that some types of hardware can generate the full range of signals that they're capable of. The remainder is mostly minor fixes and cleanups" * tag 'pwm/for-5.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: pwm: bcm-iproc: handle clk_get_rate() return pwm: Replace HTTP links with HTTPS ones pwm: omap-dmtimer: Repair pwm_omap_dmtimer_chip's broken kerneldoc header pwm: mediatek: Provide missing kerneldoc description for 'soc' arg pwm: bcm-kona: Remove impossible comparison when validating duty cycle pwm: bcm-iproc: Remove impossible comparison when validating duty cycle pwm: iqs620a: Use lowercase hexadecimal literals for consistency pwm: Convert period and duty cycle to u64 clk: pwm: Use 64-bit division function backlight: pwm_bl: Use 64-bit division function pwm: sun4i: Use nsecs_to_jiffies to avoid a division pwm: sifive: Use 64-bit division macro pwm: iqs620a: Use 64-bit division pwm: imx27: Use 64-bit division macro pwm: imx-tpm: Use 64-bit division macro pwm: clps711x: Use 64-bit division macro hwmon: pwm-fan: Use 64-bit division macro drm/i915: Use 64-bit division macro
2020-08-12Merge tag 'clk-for-linus' of ↵Linus Torvalds61-588/+4230
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull more clk updates from Stephen Boyd: "Here's some more updates that missed the last pull request because I happened to tag the tree at an earlier point in the history of clk-next. I must have fat fingered it and checked out an older version of clk-next on this second computer I'm using. This time it actually includes more code for Qualcomm SoCs, the AT91 major updates, and some Rockchip SoC clk driver updates as well. I've corrected this flow so this shouldn't happen again" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (83 commits) clk: bcm2835: Do not use prediv with bcm2711's PLLs clk: drop unused function __clk_get_flags clk: hsdk: Fix bad dependency on IOMEM dt-bindings: clock: Fix YAML schemas for LPASS clocks on SC7180 clk: mmp: avoid missing prototype warning clk: sparx5: Add Sparx5 SoC DPLL clock driver dt-bindings: clock: sparx5: Add bindings include file clk: qoriq: add LS1021A core pll mux options clk: clk-atlas6: fix return value check in atlas6_clk_init() clk: tegra: pll: Improve PLLM enable-state detection clk: X1000: Add support for calculat REFCLK of USB PHY. clk: JZ4780: Reformat the code to align it. clk: JZ4780: Add functions for enable and disable USB PHY. clk: Ingenic: Add RTC related clocks for Ingenic SoCs. dt-bindings: clock: Add tabs to align code. dt-bindings: clock: Add RTC related clocks for Ingenic SoCs. clk: davinci: Use fallthrough pseudo-keyword clk: imx: Use fallthrough pseudo-keyword clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clk clk: qcom: gcc-sdm660: Add missing modem reset ...
2020-08-07Merge tag 'clk-for-linus' of ↵Linus Torvalds47-330/+2719
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "It looks like a smaller batch of clk updates this time around. In the core framework we just have some minor tweaks and a debugfs feature, so not much to see there. The driver updates are fairly well split between AT91 and Qualcomm clk support. Adding those two drivers together equals about 50% of the diffstat. Otherwise, the big amount of work this time was on supporting Broadcom's Raspberry Pi firmware clks. Highlights: Core: - Document clk_hw_round_rate() so it gets some more use - Remove unused __clk_get_flags() - Add a prepare/enable debugfs feature similar to rate setting New Drivers: - Add support for SAMA7G5 SoC clks - Enable CPU clks on Qualcomm IPQ6018 SoCs - Enable CPU clks on Qualcomm MSM8996 SoCs - GPU clk support for Qualcomm SM8150 and SM8250 SoCs - Audio clks on Qualcomm SC7180 SoCs - Microchip Sparx5 DPLL clk - Add support for the new Renesas RZ/G2H (R8A774E1) SoC Updates: - Make defines for bcm63xx-gate clks to use in DT - Support BCM2711 SoC firmware clks - Add HDMI clks for BCM2711 SoCs - Add RTC related clks on Ingenic SoCs - Support USB PHY clks on Ingenic SoCs - Support gate clks on BCM6318 SoCs - RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs - Use poll_timeout functions in Rockchip clk driver - Support Rockchip rk3288w SoC variant - Mark mac_lbtest critical on Rockchip rk3188 - Add CAAM clock support for i.MX vf610 driver - Add MU root clock support for i.MX imx8mp driver - Amlogic g12: add neural network accelerator clock sources - Amlogic meson8: remove critical flag for main PLL divider - Amlogic meson8: add video decoder clock gates - Convert one more Renesas DT binding to json-schema - Enhance critical clock handling on Renesas platforms to only consider clocks that were enabled at boot time" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (79 commits) clk: qcom: gcc: Make disp gpll0 branch aon for sc7180/sdm845 ipq806x: gcc: add support for child probe clk: qcom: msm8996: Make symbol 'cpu_msm8996_clks' static clk: qcom: ipq8074: Add correct index for PCIe clocks clk: <linux/clk-provider.h>: drop a duplicated word clk: renesas: cpg-mssr: Add r8a774e1 support dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1 clk: Drop duplicate selection in Kconfig clk: qcom: smd: Add support for MSM8992/4 rpm clocks clk: qcom: ipq8074: Add missing clocks for pcie dt-bindings: clock: qcom: ipq8074: Add missing bindings for PCIe Replace HTTP links with HTTPS ones: Common CLK framework clk: qcom: Add CPU clock driver for msm8996 dt-bindings: clk: qcom: Add bindings for CPU clock for msm8996 soc: qcom: Separate kryo l2 accessors from PMU driver clk: meson: meson8b: add the vclk2_en gate clock clk: meson: meson8b: add the vclk_en gate clock clk: qcom: Fix return value check in apss_ipq6018_probe() clk: bcm: dvp: Add missing module informations clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2 ...
2020-08-07clk: x86: Support RV architectureAkshu Agrawal1-15/+38
There is minor difference between previous family of SoC and the current one. Which is the there is only 48Mh fixed clk. There is no mux and no option to select another freq as there in previous. Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2020-08-07clk: x86: Change name from ST to FCHAkshu Agrawal2-13/+13
AMD SoC general pupose clk is present in new platforms with minor differences. We can reuse the same clk driver for other platforms. Hence, changing name from ST(SoC) to FCH(IP) Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2020-08-07ACPI: APD: Change name from ST to FCHAkshu Agrawal1-2/+2
AMD SoC general pupose clk is present in new platforms with same MMIO mappings. We can reuse the same clk handler support for other platforms. Hence, changing name from ST(SoC) to FCH(IP) Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2020-08-04Merge tag 'uninit-macro-v5.9-rc1' of ↵Linus Torvalds3-3/+2
git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux Pull uninitialized_var() macro removal from Kees Cook: "This is long overdue, and has hidden too many bugs over the years. The series has several "by hand" fixes, and then a trivial treewide replacement. - Clean up non-trivial uses of uninitialized_var() - Update documentation and checkpatch for uninitialized_var() removal - Treewide removal of uninitialized_var()" * tag 'uninit-macro-v5.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux: compiler: Remove uninitialized_var() macro treewide: Remove uninitialized_var() usage checkpatch: Remove awareness of uninitialized_var() macro mm/debug_vm_pgtable: Remove uninitialized_var() usage f2fs: Eliminate usage of uninitialized_var() macro media: sur40: Remove uninitialized_var() usage KVM: PPC: Book3S PR: Remove uninitialized_var() usage clk: spear: Remove uninitialized_var() usage clk: st: Remove uninitialized_var() usage spi: davinci: Remove uninitialized_var() usage ide: Remove uninitialized_var() usage rtlwifi: rtl8192cu: Remove uninitialized_var() usage b43: Remove uninitialized_var() usage drbd: Remove uninitialized_var() usage x86/mm/numa: Remove uninitialized_var() usage docs: deprecated.rst: Add uninitialized_var()
2020-08-03Merge tag 'arm-drivers-5.9' of ↵Linus Torvalds1-3/+19
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "A couple of subsystems have their own subsystem maintainers but choose to have the code merged through the soc tree as upstream, as the code tends to be used across multiple SoCs or has SoC specific drivers itself: - memory controllers: Krzysztof Kozlowski takes ownership of the drivers/memory subsystem and its drivers, starting out with a set of cleanup patches. A larger driver for the Tegra memory controller that was accidentally missed for v5.8 is now added. - reset controllers: Only minor updates to drivers/reset this time - firmware: The "turris mox" firmware driver gains support for signed firmware blobs The tegra firmware driver gets extended to export some debug information Various updates to i.MX firmware drivers, mostly cosmetic - ARM SCMI/SCPI: A new mechanism for platform notifications is added, among a number of minor changes. - optee: Probing of the TEE bus is rewritten to better support detection of devices that depend on the tee-supplicant user space. A new firmware based trusted platform module (fTPM) driver is added based on OP-TEE - SoC attributes: A new driver is added to provide a generic soc_device for identifying a machine through the SMCCC ARCH_SOC_ID firmware interface rather than by probing SoC family specific registers. The series also contains some cleanups to the common soc_device code. There are also a number of updates to SoC specific drivers, the main ones are: - Mediatek cmdq driver gains a few in-kernel interfaces - Minor updates to Qualcomm RPMh, socinfo, rpm drivers, mostly adding support for additional SoC variants - The Qualcomm GENI core code gains interconnect path voting and performance level support, and integrating this into a number of device drivers. - A new driver for Samsung Exynos5800 voltage coupler for - Renesas RZ/G2H (R8A774E1) SoC support gets added to a couple of SoC specific device drivers - Updates to the TI K3 Ring Accelerator driver" * tag 'arm-drivers-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (164 commits) soc: qcom: geni: Fix unused label warning soc: qcom: smd-rpm: Fix kerneldoc memory: jz4780_nemc: Only request IO memory the driver will use soc: qcom: pdr: Reorder the PD state indication ack MAINTAINERS: Add Git repository for memory controller drivers memory: brcmstb_dpfe: Fix language typo memory: samsung: exynos5422-dmc: Correct white space issues memory: samsung: exynos-srom: Correct alignment memory: pl172: Enclose macro argument usage in parenthesis memory: of: Correct kerneldoc memory: omap-gpmc: Fix language typo memory: omap-gpmc: Correct white space issues memory: omap-gpmc: Use 'unsigned int' for consistency memory: omap-gpmc: Enclose macro argument usage in parenthesis memory: omap-gpmc: Correct kerneldoc memory: mvebu-devbus: Align with open parenthesis memory: mvebu-devbus: Add missing braces to all arms of if statement memory: bt1-l2-ctl: Add blank lines after declarations soc: TI knav_qmss: make symbol 'knav_acc_range_ops' static firmware: ti_sci: Replace HTTP links with HTTPS ones ...
2020-08-03Merge tag 'arm-dt-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2-0/+2
Pull ARM SoC DT updates from Arnd Bergmann: "As usual, there are many patches addressing minor issues in existing DTS files, such as DTC warnings, or adding support for additional peripherals. There are three added SoCs in existing product families: - Amazon: Alpine v3 is a 16-core Cortex-A72 SoC from Amazon's Annapurna Labs, otherwise known as AL73400 or first-generation Graviton, and following the already supported Cortex-A1`5 and Cortex-A57 based Alpine chips. This one is added together with the official Evaluation platform. - Qualcomm: The Snapdragon SDM630 platform is a family of mid-range mobile phone chips from 2017 based on Cortex-A53 or Kryo 260 CPUs. A total of five end-user products are added based on these, all Android phones from Sony: Xperia 10, 10 Plus, XA2, XA2 Plus and XA2 Ultra. - Renesas: RZ/G2H (r8a774e1) is currently the top model in the Renesas RZ/G family, and apparently closely related to the RZ/G2N and RZ/G2M models we already support but has a faster GPU and additional on-chip peripherals. It is added along with the HopeRun HiHope RZ/G2H development board A small number of new boards for already supported SoCs also debut: - Allwinner sunxi: Only one new machine, revision v1.2 of the Pine64 PinePhone (non-Android) smartphone, containing minor changes compared to earlier versions. - Amlogic Meson: WeTek Core2 is an Amlogic S912 (GXM) based Set-top-box - Aspeed: EthanolX is AMD's EPYC data center rerence platform, using an ASpeed AST2600 baseboard management controller. - Mediatek: Lenovo IdeaPad Duet 10.1" (kukui/krane) is a new Chromebook based on the MT8183 (Helio P60t) SoC. - Nvidia Tegra: ASUS Google Nexus 7 and Acer Iconia Tab A500 are two Android tablets from around 2012 using Tegra 3 and Tegra 2, respectively. Thanks to PostmarketOS, these can now run mainline kernels and become useful again. The Jetson Xavier NX Developer Kit uses a SoM and carrier board for the Tegra194, their latest 64-bit chip based on Carmel CPU cores and Volta graphics. - NXP i.MX: Five new boards based on the 32-bit i.MX6 series are added: The MYiR MYS-6ULX single-board computer, and four different models of industrial computers from Protonic. - Qualcomm: MikroTik RouterBoard 3011 is a rackmounted router based on the 32-bit IPQ8064 networking SoC Three older phones get added, the Snapdragon 808 (msm8992) based Xiaomi Libra (Mi 4C) and Microsoft Lumia 950, originally running Windows Phone, and the Snapdragon 810 (msm8994) based Sony Xperia Z5. - Renesas: In addition to the HiHope RZ/G2H board mentioned above, we gain support for board versions 3.0 and 4.0 of the earlier RZ/G2M and RZ/G2N reference boards. Beacon EmbeddedWorks adds another SoM+Carrier development board for RZ/G2M. - Rockchips: Radxa Rock Pi N8 development board and the VMARC RK3288 SoM it is based on, using the high-end 32-bit rk3288 SoC. Notable updates to existing platforms are usually for added on-chip peripherals, including: - ASpeed AST2xxx (various) - Allwinner (cpufreq, thermal, Pinephone touchscreen) - Amlogic Meson (audio, gpu dvdfs, board updates) - Arm Versatile - Broadcom (board updates for switch ports, Raspberry pi clock updates) - Hisilicon (various) - Intel/Altera SoCFPGA (various) - Marvell Armada 7xxx/8xxx (smmu) - Marvell MMP (GPU on mmp2/mmp3) - Mediatek mt8183 (USB, pericfg) - NXP Layerscape (VPU, thermal, DSPI) - NXP i.MX (VPU, bindings, board updates) - Nvidia Tegra194 (GPU) - Qualcomm (GPU, Interconnect, ...) - Renesas R-Car (SPI, IPMMU, board updates) - STMicroelectronics STM32 (various) - Samsung Exynos (various) - Socionext Uniphier (updates to serial, and pcie) - TI K3 (serdes, usb3, audio, sd, chipid) - TI OMAP (IPU/DSP remoteproc changes, dropping platform data)" * tag 'arm-dt-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (605 commits) arm64: dts: meson: odroid-n2: add jack audio output support arm64: dts: meson: odroid-n2: enable audio loopback ARM: dts: berlin: Align L2 cache-controller nodename with dtschema arm64: dts: qcom: Add Microsoft Lumia 950 (Talkman) device tree arm64: dts: qcom: Add Xiaomi Libra (Mi 4C) device tree arm64: dts: qcom: msm8992: Add RPMCC node arm64: dts: qcom: msm8992: Add PSCI support. arm64: dts: qcom: msm8992: Add PMU node arm64: dts: qcom: msm8992: Add BLSP2_UART2 and I2C nodes arm64: dts: qcom: msm8992: Add SPMI PMIC arbiter device arm64: dts: qcom: msm8992: Add a SCM node arm64: dts: qcom: msm8992: Add a proper CPU map arm64: dts: qcom: bullhead: Move UART pinctrl to SoC arm64: dts: qcom: bullhead: Add qcom,msm-id arm64: dts: qcom: msm8992: Fix SDHCI1 arm64: dts: qcom: msm8992: Modernize the DTS style arm64: dts: qcom: Add support for Sony Xperia Z5 (SoMC Sumire-RoW) arm64: dts: qcom: Move msm8994-smd-rpm contents to lg-bullhead. arm64: dts: qcom: msm8994: Add support for SMD RPM arm64: dts: qcom: msm8992: Add a label to rpm-requests ...
2020-08-03Merge branches 'clk-microchip', 'clk-mmp', 'clk-unused' and 'clk-at91' into ↵Stephen Boyd28-285/+2438
clk-next - Add support for SAMA7G5 SoC clks - Microchip Sparx5 DPLL clk * clk-microchip: clk: sparx5: Add Sparx5 SoC DPLL clock driver dt-bindings: clock: sparx5: Add bindings include file * clk-mmp: clk: mmp: avoid missing prototype warning * clk-unused: clk: drop unused function __clk_get_flags * clk-at91: clk: at91: sama7g5: add clock support for sama7g5 clk: at91: clk-utmi: add utmi support for sama7g5 clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs clk: at91: add macro for pll ids mask clk: at91: clk-programmable: add mux_table option clk: at91: clk-peripheral: add support for changeable parent rate clk: at91: clk-master: add master clock support for SAMA7G5 clk: at91: clk-generated: add mux_table option clk: at91: clk-generated: pass the id of changeable parent at registration clk: at91: replace conditional operator with double logical not clk: at91: sckc: register slow_rc with accuracy option clk: at91: sam9x60: fix main rc oscillator frequency clk: at91: sam9x60-pll: use frac when setting frequency clk: at91: sam9x60-pll: check fcore against ranges clk: at91: sam9x60-pll: use logical or for range check clk: at91: clk-sam9x60-pll: fix mul mask clk: at91: clk-generated: check best_rate against ranges clk: at91: clk-generated: continue if __clk_determine_rate() returns error clk: at91: fix possible dead lock in new drivers
2020-08-03Merge branches 'clk-fallthru', 'clk-ingenic', 'clk-tegra', 'clk-sirf' and ↵Stephen Boyd8-85/+228
'clk-qoriq' into clk-next - Add RTC related clks on Ingenic SoCs - Support USB PHY clks on Ingenic SoCs * clk-fallthru: clk: davinci: Use fallthrough pseudo-keyword clk: imx: Use fallthrough pseudo-keyword * clk-ingenic: clk: X1000: Add support for calculat REFCLK of USB PHY. clk: JZ4780: Reformat the code to align it. clk: JZ4780: Add functions for enable and disable USB PHY. clk: Ingenic: Add RTC related clocks for Ingenic SoCs. dt-bindings: clock: Add tabs to align code. dt-bindings: clock: Add RTC related clocks for Ingenic SoCs. * clk-tegra: clk: tegra: pll: Improve PLLM enable-state detection * clk-sirf: clk: clk-atlas6: fix return value check in atlas6_clk_init() * clk-qoriq: clk: qoriq: add LS1021A core pll mux options
2020-08-03Merge branches 'clk-actions', 'clk-rockchip', 'clk-iproc', 'clk-intel' and ↵Stephen Boyd9-60/+214
'clk-debugfs' into clk-next - RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs * clk-actions: MAINTAINERS: Add reset binding entry for Actions Semi Owl SoCs clk: actions: Add Actions S500 SoC Reset Management Unit support dt-bindings: reset: Add binding constants for Actions S500 RMU clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoC dt-bindings: clock: Add APB, DMAC, GPIO bindings for Actions S500 SoC clk: actions: Fix h_clk for Actions S500 SoC * clk-rockchip: clk: rockchip: add sclk_mac_lbtest to rk3188_critical_clocks clk: rockchip: Revert "fix wrong mmc sample phase shift for rk3328" clk: rockchip: use separate compatibles for rk3288w-cru dt-bindings: clocks: add rk3288w variant compatible clk: rockchip: Handle clock tree for rk3288w variant clk: rockchip: convert rk3036 pll type to use internal lock status clk: rockchip: convert basic pll lock_wait to use regmap_read_poll_timeout clk: rockchip: convert rk3399 pll type to use readl_relaxed_poll_timeout * clk-iproc: clk: iproc: round clock rate to the closest * clk-intel: clk: intel: Avoid unnecessary memset by improving code clk: intel: Improve locking in the driver clk: intel: Use devm_clk_hw_register() instead of clk_hw_register() * clk-debugfs: clk: Add support for enabling/disabling clocks from debugfs
2020-08-03Merge branches 'clk-https', 'clk-renesas', 'clk-kconfig', 'clk-amlogic' and ↵Stephen Boyd31-51/+613
'clk-imx' into clk-next * clk-https: Replace HTTP links with HTTPS ones: Common CLK framework * clk-renesas: clk: renesas: cpg-mssr: Add r8a774e1 support dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1 clk: renesas: Add r8a774e1 CPG Core Clock Definitions dt-bindings: power: Add r8a774e1 SYSC power domain definitions clk: renesas: rzg2: Mark RWDT clocks as critical clk: renesas: rcar-gen3: Mark RWDT clocks as critical clk: renesas: cpg-mssr: Mark clocks as critical only if on at boot dt-bindings: clock: renesas: cpg: Convert to json-schema * clk-kconfig: clk: hsdk: Fix bad dependency on IOMEM clk: Specify IOMEM dependency for HSDK pll driver clk: Drop duplicate selection in Kconfig clk: AST2600: Add mux for EMMC clock clk: mvebu: ARMADA_AP_CPU_CLK needs to select ARMADA_AP_CP_HELPER * clk-amlogic: clk: meson: meson8b: add the vclk2_en gate clock clk: meson: meson8b: add the vclk_en gate clock clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2 clk: meson: g12a: Add support for NNA CLK source clocks dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs * clk-imx: clk: imx: vf610: add CAAM clock clk: imx8mp: add mu root clk
2020-08-03Merge branches 'clk-socfpga', 'clk-doc', 'clk-qcom', 'clk-vc5' and 'clk-bcm' ↵Stephen Boyd29-433/+3485
into clk-next - Enable CPU clks on Qualcomm IPQ6018 SoCs - Enable CPU clks on Qualcomm MSM8996 SoCs - GPU clk support for Qualcomm SM8150 and SM8250 SoCs - Audio clks on Qualcomm SC7180 SoCs - Make defines for bcm63xx-gate clks to use in DT - Support gate clks on BCM6318 SoCs - Add HDMI clks for BCM2711 SoCs - Support BCM2711 SoC firmware clks * clk-socfpga: clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK * clk-doc: clk: Clean up kernel-doc errors clk: <linux/clk-provider.h>: drop a duplicated word clk: add function documentation for clk_hw_round_rate() * clk-qcom: (38 commits) dt-bindings: clock: Fix YAML schemas for LPASS clocks on SC7180 clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clk clk: qcom: gcc-sdm660: Add missing modem reset clk: qcom: lpass: Add support for LPASS clock controller for SC7180 clk: qcom: gcc: Add support for GCC LPASS clock for SC7180 dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180 clk: qcom: gdsc: Add support to enable retention of GSDCR clk: qcom: Export gdsc_gx_do_nothing_enable() to modules clk: qcom: Add graphics clock controller driver for SM8250 clk: qcom: Add graphics clock controller driver for SM8150 clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers dt-bindings: clock: add SM8250 QCOM Graphics clock bindings dt-bindings: clock: add SM8150 QCOM Graphics clock bindings dt-bindings: clock: combine qcom,sdm845-gpucc and qcom,sc7180-gpucc clk: qcom: gcc: remove unnecessary vco_table from SM8150 clk: qcom: clk-alpha-pll: use the right PCAL_DONE value for lucid pll clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VAL clk: qcom: gcc: fix sm8150 GPU and NPU clocks dt-bindings: clock: Fix qcom,msm8996-apcc yaml syntax ... * clk-vc5: clk: vc5: use a dedicated struct to describe the output drivers dt-bindings: clk: versaclock5: convert to yaml MAINTAINERS: take over IDT VersaClock 5 clock driver dt-bindings: clk: versaclock5: fix 'idt' prefix typos clk: vc5: Add memory check to prevent oops clk: vc5: fix use of memory after it has been kfree'd clk: vc5: Enable addition output configurations of the Versaclock dt: Add additional option bindings for IDT VersaClock clk: vc5: Allow Versaclock driver to support multiple instances * clk-bcm: (44 commits) clk: bcm2835: Do not use prediv with bcm2711's PLLs dt-bindings: arm: bcm: Add a select to the RPI Firmware binding clk: bcm: dvp: Add missing module informations clk: bcm: rpi: Remove the quirks for the CPU clock clk: bcm2835: Don't cache the PLLB rate clk: bcm2835: Allow custom CCF flags for the PLLs Revert "clk: bcm2835: remove pllb" clk: bcm: rpi: Give firmware clocks a name clk: bcm: rpi: Discover the firmware clocks clk: bcm: rpi: Add an enum for the firmware clocks clk: bcm: rpi: Add DT provider for the clocks clk: bcm: rpi: Make the PLLB registration function return a clk_hw clk: bcm: rpi: Split pllb clock hooks clk: bcm: rpi: Rename is_prepared function clk: bcm: rpi: Pass the clocks data to the firmware function clk: bcm: rpi: Add clock id to data clk: bcm: rpi: Create a data structure for the clocks clk: bcm: rpi: Use CCF boundaries instead of rolling our own clk: bcm: rpi: Make sure the clkdev lookup is removed clk: bcm: rpi: Switch to clk_hw_register_clkdev ...
2020-08-03clk: bcm2835: Do not use prediv with bcm2711's PLLsNicolas Saenz Julienne1-4/+21
Contrary to previous SoCs, bcm2711 doesn't have a prescaler in the PLL feedback loop. Bypass it by zeroing fb_prediv_mask when running on bcm2711. Note that, since the prediv configuration bits were re-purposed, this was triggering miscalculations on all clocks hanging from the VPU clock, notably the aux UART, making its output unintelligible. Fixes: 42de9ad400af ("clk: bcm2835: Add BCM2711_CLOCK_EMMC2 support") Reported-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Link: https://lore.kernel.org/r/20200730182619.23246-1-nsaenzjulienne@suse.de Tested-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-08-03clk: drop unused function __clk_get_flagsJulia Lawall1-6/+0
The function __clk_get_flags has not been used since the April 2019 commit a348f05361c9 ("ARM: omap2+: hwmod: drop CLK_IS_BASIC flag usage"). Other uses were removed in June 2015, eg by commit 98d8a60eccee ("clk: Convert __clk_get_flags() to clk_hw_get_flags()"), which shows how clk_hw_get_flags can easily be used instead. Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Link: https://lore.kernel.org/r/1596272022-14173-1-git-send-email-Julia.Lawall@inria.fr Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-08-03clk: hsdk: Fix bad dependency on IOMEMGeert Uytterhoeven1-1/+1
CONFIG_IOMEM does not exist. The correct symbol to depend on is CONFIG_HAS_IOMEM. Fixes: 1e7468bd9d30a21e ("clk: Specify IOMEM dependency for HSDK pll driver") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200803084835.21838-1-geert+renesas@glider.be Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-08-03Merge branch 'clk-fixes' into clk-kconfigStephen Boyd3-8/+43
Need to merge this up to get the IOMEM dependency patch on top that is broken and fixed in the next commit. * clk-fixes: clk: Specify IOMEM dependency for HSDK pll driver clk: AST2600: Add mux for EMMC clock clk: mvebu: ARMADA_AP_CPU_CLK needs to select ARMADA_AP_CP_HELPER
2020-07-29clk: mmp: avoid missing prototype warningArnd Bergmann2-0/+2
The kernel test robot points out two harmless warnings in the mmp clk drivers: drivers/clk/mmp/clk-pxa168.c:68:13: warning: no previous prototype for 'pxa168_clk_init' [-Wmissing-prototypes] drivers/clk/mmp/clk-pxa910.c:66:13: warning: no previous prototype for 'pxa910_clk_init' [-Wmissing-prototypes] Fix these by including corresponding header file. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20200729113456.4072290-1-arnd@arndb.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-28clk: sparx5: Add Sparx5 SoC DPLL clock driverLars Povlsen2-0/+296
This adds a device driver for the Sparx5 SoC DPLL clock Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200727084211.6632-9-lars.povlsen@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27clk: qoriq: add LS1021A core pll mux optionsMichael Krummsdorf1-1/+9
This allows to clock the cores with 1 GHz, 500 MHz and 250 MHz. Signed-off-by: Michael Krummsdorf <michael.krummsdorf@tq-group.com> Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Link: https://lore.kernel.org/r/20200610113837.27117-1-matthias.schiffer@ew.tq-group.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27clk: clk-atlas6: fix return value check in atlas6_clk_init()Xu Wang1-1/+1
In case of error, the function clk_register() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by: Xu Wang <vulab@iscas.ac.cn> Link: https://lore.kernel.org/r/20200713032143.21362-1-vulab@iscas.ac.cn Acked-by: Barry Song <baohua@kernel.org> Fixes: 7bf21bc81f28 ("clk: sirf: re-arch to make the codes support both prima2 and atlas6") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27clk: tegra: pll: Improve PLLM enable-state detectionDmitry Osipenko1-5/+15
Power Management Controller (PMC) can override the PLLM clock settings, including the enable-state. Although PMC could only act as a second level gate, meaning that PLLM needs to be enabled by the Clock and Reset Controller (CaR) anyways if we want it to be enabled. Hence, when PLLM is overridden by PMC, it needs to be enabled by CaR and ungated by PMC in order to be functional. Please note that this patch doesn't fix any known problem, and thus, it's merely a minor improvement. Link: https://lore.kernel.org/linux-arm-kernel/20191210120909.GA2703785@ulmo/T/ Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20200709172057.13951-1-digetx@gmail.com Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27clk: X1000: Add support for calculat REFCLK of USB PHY.周琰杰 (Zhou Yanjie)1-1/+83
Add functions for calculat the rate of REFCLK, which is needed by USB PHY in Ingenic X1000 SoC. Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20200630163852.47267-4-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27clk: JZ4780: Reformat the code to align it.周琰杰 (Zhou Yanjie)1-45/+45
Reformat the code (add one level of indentation before the values), to align the code in the macro definition section. Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20200630163852.47267-3-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27clk: JZ4780: Add functions for enable and disable USB PHY.周琰杰 (Zhou Yanjie)1-30/+35
Add new functions to "jz4780_otg_phy_ops" to enable or disable the USB PHY in the JZ4780 SoC. Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20200630163852.47267-2-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27clk: Ingenic: Add RTC related clocks for Ingenic SoCs.周琰杰 (Zhou Yanjie)3-0/+38
The RTC unit in the Ingenic SoCs has two clock sources, one is from an external 32.768kHz clock, and the other is from an external 24MHz/48MHz main clock that is divided by 512. The choice of these two clocks is controlled by the ERCS bit in the OPCR register. The RNG unit will also use this clock. Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20200725051136.58220-4-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27clk: davinci: Use fallthrough pseudo-keywordGustavo A. R. Silva1-1/+1
Replace the existing /* fall through */ comments and its variants with the new pseudo-keyword macro fallthrough[1]. [1] https://www.kernel.org/doc/html/v5.7/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Link: https://lore.kernel.org/r/20200727201122.GA2593@embeddedor Reviewed-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27clk: imx: Use fallthrough pseudo-keywordGustavo A. R. Silva1-2/+2
Replace the existing /* fall through */ comments and its variants with the new pseudo-keyword macro fallthrough[1]. [1] https://www.kernel.org/doc/html/v5.7/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Link: https://lore.kernel.org/r/20200727200922.GA2326@embeddedor Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clkKonrad Dybcio1-0/+3
Add missing halt_check, hwcg_reg and hwcg_bit properties. These were likely omitted when porting the driver upstream. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200726111215.22361-9-konradybcio@gmail.com Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27clk: qcom: gcc-sdm660: Add missing modem resetKonrad Dybcio1-0/+1
This will be required in order to support the modem upstream. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200726111215.22361-2-konradybcio@gmail.com Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24clk: qcom: lpass: Add support for LPASS clock controller for SC7180Taniya Das3-0/+486
The Low Power Audio subsystem clocks are required for Audio client to be able to request for the clocks and power domains. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1595606878-2664-5-git-send-email-tdas@codeaurora.org [sboyd@kernel.org: Drop unused ret in probe function] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24clk: qcom: gcc: Add support for GCC LPASS clock for SC7180Taniya Das1-0/+14
Add the GCC lpass clock which is required to access the LPASS core clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1595606878-2664-4-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24clk: qcom: gdsc: Add support to enable retention of GSDCRTaniya Das2-0/+13
Add support for the RETAIN_FF_ENABLE feature which enables the usage of retention registers. These registers maintain their state after disabling and re-enabling a GDSC. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1595606878-2664-2-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24clk: Clean up kernel-doc errorsStephen Boyd1-0/+3
Two things aren't documented causing kernel-doc to fail when checking the core clk.c file. Fix them so that this file is clean. Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200622090935.213833-1-sboyd@kernel.org
2020-07-24clk: qcom: Export gdsc_gx_do_nothing_enable() to modulesStephen Boyd1-0/+2
A clk driver can be a module but the gdsc code is in the common module. Export this symbol so that allmodconfig builds keep working. Cc: Jonathan Marek <jonathan@marek.ca> Fixes: 0638226dd095 ("clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers") Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200724094025.3261266-1-sboyd@kernel.org
2020-07-24clk: at91: sama7g5: add clock support for sama7g5Claudiu Beznea2-0/+1060
Add clock support for SAMA7G5. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1595403506-8209-19-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24clk: at91: clk-utmi: add utmi support for sama7g5Claudiu Beznea2-5/+102
Add UTMI support for SAMA7G5. SAMA7G5's UTMI control is done via XTALF register. Values written at bits 2..0 in this register correspond to the on board crystal oscillator frequency. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1595403506-8209-18-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputsClaudiu Beznea3-186/+433
Some of the SAMA7G5 PLLs support multiple outputs (e.g. AUDIO PLL). For these, split the PLL clock in two: fractional clock and divider clock. In case PLLs supports multiple outputs (since these outputs are dividers (with different settings) sharing the same fractional part), it will register one fractional clock and multiple divider clocks (dividers sharing the fractional clock). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1595403506-8209-17-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24clk: at91: clk-programmable: add mux_table optionClaudiu Beznea13-17/+38
Add mux table option. This is necessary for IP versions that has gaps in the range of available clock sources (e.g. SAMA7G5). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1595403506-8209-15-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24clk: at91: clk-peripheral: add support for changeable parent rateClaudiu Beznea9-16/+119
Some peripheral clocks on SAMA7G5 supports requesting parent to change its rate (image related clocks: csi, csi2dc, isc). Add support so that if registered with this option the clock rate to be requested from parent. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1595403506-8209-14-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24clk: at91: clk-master: add master clock support for SAMA7G5Claudiu Beznea2-5/+312
Add master clock support (MCK1..4) for SAMA7G5. SAMA7G5's PMC has multiple master clocks feeding different subsystems. One of them feeds image subsystem and is changeable based on image subsystem needs. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1595403506-8209-13-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24clk: at91: clk-generated: add mux_table optionClaudiu Beznea5-8/+16
Add mux table option. This is necessary for IP versions that has gaps in the range of available clock sources (e.g. SAMA7G5). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1595403506-8209-12-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24clk: at91: clk-generated: pass the id of changeable parent at registrationClaudiu Beznea5-35/+37
Pass the ID of changeable parent at registration. This will allow the scalability of this clock driver with regards to the changeable parent ID for versions of this IP where changeable parent is not the last one in the parents list (e.g. SAMA7G5). With this the clock flags are set to zero in case we have no changeable parent. Also in clk_generated_best_diff() the *best_diff variable is check against tmp_diff variable using ">=" operator instead of ">" so that in case the requested frequency could be obtained using fix parents + gck dividers but the clock also supports changeable parent to be able to force the usage of the changeable parent. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1595403506-8209-11-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24clk: at91: replace conditional operator with double logical notClaudiu Beznea5-8/+8
Replace conditional operator with double logical not as code may be simpler to read. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1595403506-8209-10-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24clk: at91: sckc: register slow_rc with accuracy optionClaudiu Beznea1-2/+3
Chapter 57.7.5 of SAM9X60 datasheet specifies that the maximum drift of this oscillator is +- 3KHz. Use that value and the formula at [1] or the calculator at [2] to compute the PPB value. [1] https://www.everythingrf.com/rf-calculators/ppm-to-hz-calculator [2] https://www.changpuak.ch/electronics/ppm_to_Hz_converter.php Fixes: 04bcc4275e601 ("clk: at91: sckc: add support for SAM9X60") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1595403506-8209-9-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24clk: at91: sam9x60: fix main rc oscillator frequencyClaudiu Beznea1-1/+1
Main RC oscillator frequency is 12MHz according to datasheet (chapter 27.2). Fixes: 01e2113de9a52 ("clk: at91: add sam9x60 pmc driver") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1595403506-8209-8-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24clk: at91: sam9x60-pll: use frac when setting frequencyClaudiu Beznea1-4/+8
In commit a436c2a447e59 ("clk: at91: add sam9x60 PLL driver") the fractional part of PLL wasn't set on registers but it was calculated and taken into account for determining div and mul (see sam9x60_pll_get_best_div_mul()). Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1595403506-8209-7-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24clk: at91: sam9x60-pll: check fcore against rangesClaudiu Beznea2-2/+12
According to datasheet the range of 600-1200MHz is for the frequency generated by the fractional part of the PLL (namely Fcorepllck according to datasheet). With this in mind the output range of the PLL itself (fractional + div), taking into account that the divider is 8 bits wide, is 600/256-1200Hz=2.3-1200MHz. Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1595403506-8209-6-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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