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path: root/drivers/clk/tegra/clk-tegra210.c
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2019-11-11clk: tegra: Fix build error without CONFIG_PM_SLEEPYueHaibing1-0/+2
2019-11-11clk: tegra: Add suspend and resume support on Tegra210Sowjanya Komatineni1-4/+92
2019-11-11clk: tegra: Use fence_udelay() during PLLU initSowjanya Komatineni1-4/+4
2019-11-11clk: tegra: Reimplement SOR clocks on Tegra210Thierry Reding1-16/+55
2019-11-11clk: tegra: Rename sor0_lvds to sor0_outThierry Reding1-1/+1
2019-11-11clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRCThierry Reding1-1/+1
2019-07-17Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds1-8/+12
2019-06-28Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds1-0/+2
2019-06-25clk: tegra: Do not enable PLL_RE_VCO on Tegra210Thierry Reding1-1/+0
2019-06-25clk: tegra: Warn if an enabled PLL is in IDDQThierry Reding1-1/+5
2019-06-25clk: tegra: Do not warn unnecessarilyThierry Reding1-2/+3
2019-06-25clk: tegra210: fix PLLU and PLLU_OUT1JC Kuo1-4/+4
2019-06-14clk: tegra210: Fix default rates for HDA clocksJon Hunter1-0/+2
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner1-12/+1
2019-04-23clk: core: replace clk_{readl,writel} with {readl,writel}Jonas Gorski1-3/+3
2018-12-14clk: tegra: Fix maximum audio sync clock for Tegra124/210Jon Hunter1-1/+8
2018-10-16clk: tegra210: Include size.h for compilation easeStephen Boyd1-0/+1
2018-10-16clk: tegra: Fixes for MBIST work aroundJoseph Lo1-3/+3
2018-07-25clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocksPeter De-Schrijver1-2/+12
2018-05-18clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko1-1/+1
2018-03-12clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko1-2/+1
2018-03-08clk: tegra: MBIST work around for Tegra210Peter De Schrijver1-2/+342
2018-03-08clk: tegra: Add la clock for Tegra210Peter De Schrijver1-0/+14
2017-11-01clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()Nicolin Chen1-2/+2
2017-10-19clk: tegra: Fix sor1_out clock implementationThierry Reding1-0/+47
2017-08-23clk: tegra: Fix Tegra210 PLLU initializationAlex Frid1-2/+4
2017-08-23clk: tegra: Correct Tegra210 UTMIPLL poweron delayAlex Frid1-3/+3
2017-08-23clk: tegra: Re-factor T210 PLLX registrationAlex Frid1-1/+1
2017-08-23clk: tegra: don't warn for pll_d2 defaults unnecessarilyPeter De Schrijver1-2/+4
2017-08-23clk: tegra: Fix T210 effective NDIV calculationAlex Frid1-4/+5
2017-08-23clk: tegra210: remove non-existing VFIR clockPeter De Schrijver1-1/+0
2017-08-23clk: tegra: disable SSC for PLL_D2Peter De Schrijver1-1/+1
2017-04-04clk: tegra: Don't reset PLL-CX if it is already enabledJon Hunter1-4/+4
2017-04-04clk: tegra: Add missing Tegra210 clocksPeter De Schrijver1-0/+7
2017-03-20clk: tegra: Mark TEGRA210_CLK_DBGAPB as always onPeter De Schrijver1-0/+2
2017-03-20clk: tegra: Add SATA seq input controlPeter De Schrijver1-0/+25
2017-03-20clk: tegra: Add Tegra210 special resetsPeter De Schrijver1-0/+85
2017-03-20clk: tegra: Rework pll_uPeter De Schrijver1-23/+272
2017-03-20clk: tegra: Handle UTMIPLL IDDQPeter De Schrijver1-0/+26
2017-03-20clk: tegra: Add aclkPeter De Schrijver1-0/+10
2017-03-20clk: tegra: Define Tegra210 DMIC clocksPeter De Schrijver1-0/+3
2017-03-20clk: tegra: Define Tegra210 DMIC sync clocksPeter De Schrijver1-0/+6
2017-03-20clk: tegra: Add CEC clockPeter De Schrijver1-0/+1
2017-03-20clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculationPeter De Schrijver1-1/+7
2017-03-20clk: tegra: Don't warn for PLL defaults unnecessarilyPeter De Schrijver1-6/+12
2017-03-20clk: tegra: Remove non-existing pll_m_out1 clockPeter De Schrijver1-5/+0
2017-03-20clk: tegra: Fix ISP clock modellingPeter De Schrijver1-0/+1
2017-03-20clk: tegra: Fix pll_a1 iddq register, add pll_a1Peter De Schrijver1-1/+2
2016-06-30clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker1-179/+3
2016-06-23clk: tegra: Micro-optimize Tegra210 clock setupThierry Reding1-4/+4