linux - Linux Kernel (branches are rebased on master from time to time)

Age	Commit message (Expand)	Author	Files	Lines
2022-03-11	clk: cleanup comments	Tom Rix	1	-1/+1
2021-09-23	clk: meson: meson8b: Make the video clock trees mutable	Martin Blumenstingl	1	-38/+38
2021-09-23	clk: meson: meson8b: Initialize the HDMI PLL registers	Martin Blumenstingl	1	-4/+36
2021-09-23	clk: meson: meson8b: Add the HDMI PLL M/N parameters	Martin Blumenstingl	1	-0/+22
2021-09-23	clk: meson: meson8b: Add the vid_pll_lvds_en gate clock	Martin Blumenstingl	1	-1/+22
2021-09-23	clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_sel	Martin Blumenstingl	1	-2/+2
2021-01-04	clk: meson: meson8b: remove compatibility code for old .dtbs	Martin Blumenstingl	1	-40/+5
2020-07-09	clk: meson: meson8b: add the vclk2_en gate clock	Martin Blumenstingl	1	-5/+25
2020-07-09	clk: meson: meson8b: add the vclk_en gate clock	Martin Blumenstingl	1	-5/+25
2020-06-24	clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2	Martin Blumenstingl	1	-7/+0
2020-05-02	clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers	Martin Blumenstingl	1	-0/+9
2020-04-29	clk: meson: meson8b: Make the CCF use the glitch-free VPU mux	Martin Blumenstingl	1	-3/+11
2020-04-29	clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits	Martin Blumenstingl	1	-5/+5
2020-04-29	clk: meson: meson8b: Fix the polarity of the RESET_N lines	Martin Blumenstingl	1	-23/+56
2020-04-29	clk: meson: meson8b: Fix the first parent of vid_pll_in_sel	Martin Blumenstingl	1	-1/+1
2020-04-14	clk: meson: meson8b: make the hdmi_sys clock tree mutable	Martin Blumenstingl	1	-3/+3
2020-02-21	clk: meson: meson8b: set audio output clock hierarchy	Martin Blumenstingl	1	-8/+13
2020-01-07	clk: meson: meson8b: make the CCF use the glitch-free mali mux	Martin Blumenstingl	1	-4/+7
2019-12-11	clk: meson: meson8b: use of_clk_hw_register to register the clocks	Martin Blumenstingl	1	-1/+1
2019-12-11	clk: meson: meson8b: don't register the XTAL clock when provided via OF	Martin Blumenstingl	1	-3/+9
2019-12-11	clk: meson: meson8b: change references to the XTAL clock to use [fw_]name	Martin Blumenstingl	1	-34/+44
2019-12-11	clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier	Martin Blumenstingl	1	-13/+8
2019-07-29	clk: meson: clk-regmap: migrate to new parent description method	Alexandre Mergnat	1	-0/+3
2019-07-29	clk: meson: meson8b: migrate to the new parent description method	Alexandre Mergnat	1	-211/+496
2019-06-11	clk: meson: meson8b: add the cts_i958 clock	Martin Blumenstingl	1	-0/+24
2019-06-11	clk: meson: meson8b: add the cts_mclk_i958 clocks	Martin Blumenstingl	1	-0/+65
2019-06-11	clk: meson: meson8b: add the cts_amclk clocks	Martin Blumenstingl	1	-0/+65
2019-05-20	clk: meson: meson8b: fix a typo in the VPU parent names array variable	Martin Blumenstingl	1	-5/+5
2019-04-01	clk: meson: meson8b: add the video decoder clock trees	Martin Blumenstingl	1	-0/+312
2019-04-01	clk: meson: meson8b: add the VPU clock trees	Martin Blumenstingl	1	-0/+167
2019-04-01	clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2	Martin Blumenstingl	1	-0/+62
2019-04-01	clk: meson: meson8b: use a separate clock table for Meson8m2	Martin Blumenstingl	1	-1/+192
2019-02-13	clk: meson: meson8b: fix the naming of the APB clocks	Martin Blumenstingl	1	-13/+13
2019-02-02	clk: meson: rework and clean drivers dependencies	Jerome Brunet	1	-1/+2
2019-01-07	clk: meson: meson8b: add the GPU clock tree	Martin Blumenstingl	1	-0/+146
2019-01-07	clk: meson: meson8b: use a separate clock table for Meson8	Martin Blumenstingl	1	-6/+197
2018-12-03	clk: meson: meson8b: add the read-only video clock trees	Martin Blumenstingl	1	-8/+731
2018-12-03	clk: meson: meson8b: add the fractional divider for vid_pll_dco	Martin Blumenstingl	1	-0/+5
2018-12-03	clk: meson: meson8b: fix the offset of vid_pll_dco's N value	Martin Blumenstingl	1	-1/+1
2018-11-23	clk: meson: meson8b: add the CPU clock post divider clocks	Martin Blumenstingl	1	-0/+244
2018-11-23	clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3	Martin Blumenstingl	1	-10/+10
2018-11-23	clk: meson: meson8b: allow changing the CPU clock tree	Martin Blumenstingl	1	-6/+6
2018-11-23	clk: meson: meson8b: run from the XTAL when changing the CPU frequency	Martin Blumenstingl	1	-0/+63
2018-11-23	clk: meson: meson8b: add support for more M/N values in sys_pll	Martin Blumenstingl	1	-0/+5
2018-11-23	clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICAL	Martin Blumenstingl	1	-1/+2
2018-11-23	clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel	Martin Blumenstingl	1	-2/+9
2018-11-23	clk: meson: meson8b: fix the width of the cpu_scale_div clock	Martin Blumenstingl	1	-1/+1
2018-11-23	clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_table	Martin Blumenstingl	1	-7/+8
2018-11-23	clk: meson: meson8b: use the HHI syscon if available	Martin Blumenstingl	1	-9/+15
2018-09-26	clk: meson: meson8b: use the regmap in the internal reset controller	Martin Blumenstingl	1	-7/+6