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-rw-r--r--drivers/video/via/hw.c630
1 files changed, 210 insertions, 420 deletions
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index dc4c778877ce..47b13535ed2b 100644
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -20,274 +20,84 @@
*/
#include <linux/via-core.h>
+#include <asm/olpc.h>
#include "global.h"
-
-static struct pll_config cle266_pll_config[] = {
- {19, 4, 0},
- {26, 5, 0},
- {28, 5, 0},
- {31, 5, 0},
- {33, 5, 0},
- {55, 5, 0},
- {102, 5, 0},
- {53, 6, 0},
- {92, 6, 0},
- {98, 6, 0},
- {112, 6, 0},
- {41, 7, 0},
- {60, 7, 0},
- {99, 7, 0},
- {100, 7, 0},
- {83, 8, 0},
- {86, 8, 0},
- {108, 8, 0},
- {87, 9, 0},
- {118, 9, 0},
- {95, 12, 0},
- {115, 12, 0},
- {108, 13, 0},
- {83, 17, 0},
- {67, 20, 0},
- {86, 20, 0},
- {98, 20, 0},
- {121, 24, 0},
- {99, 29, 0},
- {33, 3, 1},
- {15, 4, 1},
- {23, 4, 1},
- {37, 5, 1},
- {83, 5, 1},
- {85, 5, 1},
- {94, 5, 1},
- {103, 5, 1},
- {109, 5, 1},
- {113, 5, 1},
- {121, 5, 1},
- {82, 6, 1},
- {31, 7, 1},
- {55, 7, 1},
- {84, 7, 1},
- {83, 8, 1},
- {76, 9, 1},
- {127, 9, 1},
- {33, 4, 2},
- {75, 4, 2},
- {119, 4, 2},
- {121, 4, 2},
- {91, 5, 2},
- {118, 5, 2},
- {83, 6, 2},
- {109, 6, 2},
- {90, 7, 2},
- {93, 2, 3},
- {53, 3, 3},
- {73, 4, 3},
- {89, 4, 3},
- {105, 4, 3},
- {117, 4, 3},
- {101, 5, 3},
- {121, 5, 3},
- {127, 5, 3},
- {99, 7, 3}
+#include "via_clock.h"
+
+static struct pll_limit cle266_pll_limits[] = {
+ {19, 19, 4, 0},
+ {26, 102, 5, 0},
+ {53, 112, 6, 0},
+ {41, 100, 7, 0},
+ {83, 108, 8, 0},
+ {87, 118, 9, 0},
+ {95, 115, 12, 0},
+ {108, 108, 13, 0},
+ {83, 83, 17, 0},
+ {67, 98, 20, 0},
+ {121, 121, 24, 0},
+ {99, 99, 29, 0},
+ {33, 33, 3, 1},
+ {15, 23, 4, 1},
+ {37, 121, 5, 1},
+ {82, 82, 6, 1},
+ {31, 84, 7, 1},
+ {83, 83, 8, 1},
+ {76, 127, 9, 1},
+ {33, 121, 4, 2},
+ {91, 118, 5, 2},
+ {83, 109, 6, 2},
+ {90, 90, 7, 2},
+ {93, 93, 2, 3},
+ {53, 53, 3, 3},
+ {73, 117, 4, 3},
+ {101, 127, 5, 3},
+ {99, 99, 7, 3}
};
-static struct pll_config k800_pll_config[] = {
- {22, 2, 0},
- {28, 3, 0},
- {81, 3, 1},
- {85, 3, 1},
- {98, 3, 1},
- {112, 3, 1},
- {86, 4, 1},
- {166, 4, 1},
- {109, 5, 1},
- {113, 5, 1},
- {121, 5, 1},
- {131, 5, 1},
- {143, 5, 1},
- {153, 5, 1},
- {66, 3, 2},
- {68, 3, 2},
- {95, 3, 2},
- {106, 3, 2},
- {116, 3, 2},
- {93, 4, 2},
- {119, 4, 2},
- {121, 4, 2},
- {133, 4, 2},
- {137, 4, 2},
- {117, 5, 2},
- {118, 5, 2},
- {120, 5, 2},
- {124, 5, 2},
- {132, 5, 2},
- {137, 5, 2},
- {141, 5, 2},
- {166, 5, 2},
- {170, 5, 2},
- {191, 5, 2},
- {206, 5, 2},
- {208, 5, 2},
- {30, 2, 3},
- {69, 3, 3},
- {82, 3, 3},
- {83, 3, 3},
- {109, 3, 3},
- {114, 3, 3},
- {125, 3, 3},
- {89, 4, 3},
- {103, 4, 3},
- {117, 4, 3},
- {126, 4, 3},
- {150, 4, 3},
- {161, 4, 3},
- {121, 5, 3},
- {127, 5, 3},
- {131, 5, 3},
- {134, 5, 3},
- {148, 5, 3},
- {169, 5, 3},
- {172, 5, 3},
- {182, 5, 3},
- {195, 5, 3},
- {196, 5, 3},
- {208, 5, 3},
- {66, 2, 4},
- {85, 3, 4},
- {141, 4, 4},
- {146, 4, 4},
- {161, 4, 4},
- {177, 5, 4}
+static struct pll_limit k800_pll_limits[] = {
+ {22, 22, 2, 0},
+ {28, 28, 3, 0},
+ {81, 112, 3, 1},
+ {86, 166, 4, 1},
+ {109, 153, 5, 1},
+ {66, 116, 3, 2},
+ {93, 137, 4, 2},
+ {117, 208, 5, 2},
+ {30, 30, 2, 3},
+ {69, 125, 3, 3},
+ {89, 161, 4, 3},
+ {121, 208, 5, 3},
+ {66, 66, 2, 4},
+ {85, 85, 3, 4},
+ {141, 161, 4, 4},
+ {177, 177, 5, 4}
};
-static struct pll_config cx700_pll_config[] = {
- {98, 3, 1},
- {86, 4, 1},
- {109, 5, 1},
- {110, 5, 1},
- {113, 5, 1},
- {121, 5, 1},
- {131, 5, 1},
- {135, 5, 1},
- {142, 5, 1},
- {143, 5, 1},
- {153, 5, 1},
- {187, 5, 1},
- {208, 5, 1},
- {68, 2, 2},
- {95, 3, 2},
- {116, 3, 2},
- {93, 4, 2},
- {119, 4, 2},
- {133, 4, 2},
- {137, 4, 2},
- {151, 4, 2},
- {166, 4, 2},
- {110, 5, 2},
- {112, 5, 2},
- {117, 5, 2},
- {118, 5, 2},
- {120, 5, 2},
- {132, 5, 2},
- {137, 5, 2},
- {141, 5, 2},
- {151, 5, 2},
- {166, 5, 2},
- {175, 5, 2},
- {191, 5, 2},
- {206, 5, 2},
- {174, 7, 2},
- {82, 3, 3},
- {109, 3, 3},
- {117, 4, 3},
- {150, 4, 3},
- {161, 4, 3},
- {112, 5, 3},
- {115, 5, 3},
- {121, 5, 3},
- {127, 5, 3},
- {129, 5, 3},
- {131, 5, 3},
- {134, 5, 3},
- {138, 5, 3},
- {148, 5, 3},
- {157, 5, 3},
- {169, 5, 3},
- {172, 5, 3},
- {190, 5, 3},
- {195, 5, 3},
- {196, 5, 3},
- {208, 5, 3},
- {141, 5, 4},
- {150, 5, 4},
- {166, 5, 4},
- {176, 5, 4},
- {177, 5, 4},
- {183, 5, 4},
- {202, 5, 4}
+static struct pll_limit cx700_pll_limits[] = {
+ {98, 98, 3, 1},
+ {86, 86, 4, 1},
+ {109, 208, 5, 1},
+ {68, 68, 2, 2},
+ {95, 116, 3, 2},
+ {93, 166, 4, 2},
+ {110, 206, 5, 2},
+ {174, 174, 7, 2},
+ {82, 109, 3, 3},
+ {117, 161, 4, 3},
+ {112, 208, 5, 3},
+ {141, 202, 5, 4}
};
-static struct pll_config vx855_pll_config[] = {
- {86, 4, 1},
- {108, 5, 1},
- {110, 5, 1},
- {113, 5, 1},
- {121, 5, 1},
- {131, 5, 1},
- {135, 5, 1},
- {142, 5, 1},
- {143, 5, 1},
- {153, 5, 1},
- {164, 5, 1},
- {187, 5, 1},
- {208, 5, 1},
- {110, 5, 2},
- {112, 5, 2},
- {117, 5, 2},
- {118, 5, 2},
- {124, 5, 2},
- {132, 5, 2},
- {137, 5, 2},
- {141, 5, 2},
- {149, 5, 2},
- {151, 5, 2},
- {159, 5, 2},
- {166, 5, 2},
- {167, 5, 2},
- {172, 5, 2},
- {189, 5, 2},
- {191, 5, 2},
- {194, 5, 2},
- {206, 5, 2},
- {208, 5, 2},
- {83, 3, 3},
- {88, 3, 3},
- {109, 3, 3},
- {112, 3, 3},
- {103, 4, 3},
- {105, 4, 3},
- {161, 4, 3},
- {112, 5, 3},
- {115, 5, 3},
- {121, 5, 3},
- {127, 5, 3},
- {134, 5, 3},
- {137, 5, 3},
- {148, 5, 3},
- {157, 5, 3},
- {169, 5, 3},
- {172, 5, 3},
- {182, 5, 3},
- {191, 5, 3},
- {195, 5, 3},
- {209, 5, 3},
- {142, 4, 4},
- {146, 4, 4},
- {161, 4, 4},
- {141, 5, 4},
- {150, 5, 4},
- {165, 5, 4},
- {176, 5, 4}
+static struct pll_limit vx855_pll_limits[] = {
+ {86, 86, 4, 1},
+ {108, 208, 5, 1},
+ {110, 208, 5, 2},
+ {83, 112, 3, 3},
+ {103, 161, 4, 3},
+ {112, 209, 5, 3},
+ {142, 161, 4, 4},
+ {141, 176, 5, 4}
};
/* according to VIA Technologies these values are based on experiment */
@@ -308,6 +118,42 @@ static struct io_reg scaling_parameters[] = {
{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
};
+static struct io_reg common_vga[] = {
+ {VIACR, CR07, 0x10, 0x10}, /* [0] vertical total (bit 8)
+ [1] vertical display end (bit 8)
+ [2] vertical retrace start (bit 8)
+ [3] start vertical blanking (bit 8)
+ [4] line compare (bit 8)
+ [5] vertical total (bit 9)
+ [6] vertical display end (bit 9)
+ [7] vertical retrace start (bit 9) */
+ {VIACR, CR08, 0xFF, 0x00}, /* [0-4] preset row scan
+ [5-6] byte panning */
+ {VIACR, CR09, 0xDF, 0x40}, /* [0-4] max scan line
+ [5] start vertical blanking (bit 9)
+ [6] line compare (bit 9)
+ [7] scan doubling */
+ {VIACR, CR0A, 0xFF, 0x1E}, /* [0-4] cursor start
+ [5] cursor disable */
+ {VIACR, CR0B, 0xFF, 0x00}, /* [0-4] cursor end
+ [5-6] cursor skew */
+ {VIACR, CR0E, 0xFF, 0x00}, /* [0-7] cursor location (high) */
+ {VIACR, CR0F, 0xFF, 0x00}, /* [0-7] cursor location (low) */
+ {VIACR, CR11, 0xF0, 0x80}, /* [0-3] vertical retrace end
+ [6] memory refresh bandwidth
+ [7] CRTC register protect enable */
+ {VIACR, CR14, 0xFF, 0x00}, /* [0-4] underline location
+ [5] divide memory address clock by 4
+ [6] double word addressing */
+ {VIACR, CR17, 0xFF, 0x63}, /* [0-1] mapping of display address 13-14
+ [2] divide scan line clock by 2
+ [3] divide memory address clock by 2
+ [5] address wrap
+ [6] byte mode select
+ [7] sync enable */
+ {VIACR, CR18, 0xFF, 0xFF}, /* [0-7] line compare */
+};
+
static struct fifo_depth_select display_fifo_depth_reg = {
/* IGA1 FIFO Depth_Select */
{IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
@@ -676,6 +522,9 @@ static struct via_device_mapping device_mapping[] = {
{VIA_LVDS2, "LVDS2"}
};
+/* structure with function pointers to support clock control */
+static struct via_clock clock;
+
static void load_fix_bit_crtc_reg(void);
static void __devinit init_gfx_chip_info(int chip_type);
static void __devinit init_tmds_chip_info(void);
@@ -770,13 +619,14 @@ static u32 get_lcd_devices(int output_interface)
/*Set IGA path for each device*/
void viafb_set_iga_path(void)
{
+ int crt_iga_path = 0;
if (viafb_SAMM_ON == 1) {
if (viafb_CRT_ON) {
if (viafb_primary_dev == CRT_Device)
- viaparinfo->crt_setting_info->iga_path = IGA1;
+ crt_iga_path = IGA1;
else
- viaparinfo->crt_setting_info->iga_path = IGA2;
+ crt_iga_path = IGA2;
}
if (viafb_DVI_ON) {
@@ -793,8 +643,7 @@ void viafb_set_iga_path(void)
UNICHROME_CLE266)) {
viaparinfo->
lvds_setting_info->iga_path = IGA2;
- viaparinfo->
- crt_setting_info->iga_path = IGA1;
+ crt_iga_path = IGA1;
viaparinfo->
tmds_setting_info->iga_path = IGA1;
} else
@@ -814,10 +663,10 @@ void viafb_set_iga_path(void)
viafb_SAMM_ON = 0;
if (viafb_CRT_ON && viafb_LCD_ON) {
- viaparinfo->crt_setting_info->iga_path = IGA1;
+ crt_iga_path = IGA1;
viaparinfo->lvds_setting_info->iga_path = IGA2;
} else if (viafb_CRT_ON && viafb_DVI_ON) {
- viaparinfo->crt_setting_info->iga_path = IGA1;
+ crt_iga_path = IGA1;
viaparinfo->tmds_setting_info->iga_path = IGA2;
} else if (viafb_LCD_ON && viafb_DVI_ON) {
viaparinfo->tmds_setting_info->iga_path = IGA1;
@@ -826,7 +675,7 @@ void viafb_set_iga_path(void)
viaparinfo->lvds_setting_info->iga_path = IGA2;
viaparinfo->lvds_setting_info2->iga_path = IGA2;
} else if (viafb_CRT_ON) {
- viaparinfo->crt_setting_info->iga_path = IGA1;
+ crt_iga_path = IGA1;
} else if (viafb_LCD_ON) {
viaparinfo->lvds_setting_info->iga_path = IGA2;
} else if (viafb_DVI_ON) {
@@ -837,7 +686,7 @@ void viafb_set_iga_path(void)
viaparinfo->shared->iga1_devices = 0;
viaparinfo->shared->iga2_devices = 0;
if (viafb_CRT_ON) {
- if (viaparinfo->crt_setting_info->iga_path == IGA1)
+ if (crt_iga_path == IGA1)
viaparinfo->shared->iga1_devices |= VIA_CRT;
else
viaparinfo->shared->iga2_devices |= VIA_CRT;
@@ -875,6 +724,10 @@ void viafb_set_iga_path(void)
viaparinfo->chip_info->
lvds_chip_info2.output_interface);
}
+
+ /* looks like the OLPC has its display wired to DVP1 and LVDS2 */
+ if (machine_is_olpc())
+ viaparinfo->shared->iga2_devices = VIA_DVP1 | VIA_LVDS2;
}
static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
@@ -1162,25 +1015,17 @@ void via_odev_to_seq(struct seq_file *m, u32 odev)
static void load_fix_bit_crtc_reg(void)
{
+ viafb_unlock_crt();
+
/* always set to 1 */
viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
/* line compare should set all bits = 1 (extend modes) */
- viafb_write_reg(CR18, VIACR, 0xff);
- /* line compare should set all bits = 1 (extend modes) */
- viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
- /* line compare should set all bits = 1 (extend modes) */
- viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
- /* line compare should set all bits = 1 (extend modes) */
viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
/* line compare should set all bits = 1 (extend modes) */
viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
/*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
- /* extend mode always set to e3h */
- viafb_write_reg(CR17, VIACR, 0xe3);
- /* extend mode always set to 0h */
- viafb_write_reg(CR08, VIACR, 0x00);
- /* extend mode always set to 0h */
- viafb_write_reg(CR14, VIACR, 0x00);
+
+ viafb_lock_crt();
/* If K8M800, enable Prefetch Mode. */
if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
@@ -1601,69 +1446,54 @@ void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
}
-static u32 cle266_encode_pll(struct pll_config pll)
-{
- return (pll.multiplier << 8)
- | (pll.rshift << 6)
- | pll.divisor;
-}
-
-static u32 k800_encode_pll(struct pll_config pll)
-{
- return ((pll.divisor - 2) << 16)
- | (pll.rshift << 10)
- | (pll.multiplier - 2);
-}
-
-static u32 vx855_encode_pll(struct pll_config pll)
-{
- return (pll.divisor << 16)
- | (pll.rshift << 10)
- | pll.multiplier;
-}
-
-static inline u32 get_pll_internal_frequency(u32 ref_freq,
- struct pll_config pll)
-{
- return ref_freq / pll.divisor * pll.multiplier;
-}
-
-static inline u32 get_pll_output_frequency(u32 ref_freq, struct pll_config pll)
-{
- return get_pll_internal_frequency(ref_freq, pll)>>pll.rshift;
-}
-
-static struct pll_config get_pll_config(struct pll_config *config, int size,
+static struct via_pll_config get_pll_config(struct pll_limit *limits, int size,
int clk)
{
- struct pll_config best = config[0];
+ struct via_pll_config cur, up, down, best = {0, 1, 0};
const u32 f0 = 14318180; /* X1 frequency */
- int i;
-
- for (i = 1; i < size; i++) {
- if (abs(get_pll_output_frequency(f0, config[i]) - clk)
- < abs(get_pll_output_frequency(f0, best) - clk))
- best = config[i];
+ int i, f;
+
+ for (i = 0; i < size; i++) {
+ cur.rshift = limits[i].rshift;
+ cur.divisor = limits[i].divisor;
+ cur.multiplier = clk / ((f0 / cur.divisor)>>cur.rshift);
+ f = abs(get_pll_output_frequency(f0, cur) - clk);
+ up = down = cur;
+ up.multiplier++;
+ down.multiplier--;
+ if (abs(get_pll_output_frequency(f0, up) - clk) < f)
+ cur = up;
+ else if (abs(get_pll_output_frequency(f0, down) - clk) < f)
+ cur = down;
+
+ if (cur.multiplier < limits[i].multiplier_min)
+ cur.multiplier = limits[i].multiplier_min;
+ else if (cur.multiplier > limits[i].multiplier_max)
+ cur.multiplier = limits[i].multiplier_max;
+
+ f = abs(get_pll_output_frequency(f0, cur) - clk);
+ if (f < abs(get_pll_output_frequency(f0, best) - clk))
+ best = cur;
}
return best;
}
-u32 viafb_get_clk_value(int clk)
+static struct via_pll_config get_best_pll_config(int clk)
{
- u32 value = 0;
+ struct via_pll_config config;
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_CLE266:
case UNICHROME_K400:
- value = cle266_encode_pll(get_pll_config(cle266_pll_config,
- ARRAY_SIZE(cle266_pll_config), clk));
+ config = get_pll_config(cle266_pll_limits,
+ ARRAY_SIZE(cle266_pll_limits), clk);
break;
case UNICHROME_K800:
case UNICHROME_PM800:
case UNICHROME_CN700:
- value = k800_encode_pll(get_pll_config(k800_pll_config,
- ARRAY_SIZE(k800_pll_config), clk));
+ config = get_pll_config(k800_pll_limits,
+ ARRAY_SIZE(k800_pll_limits), clk);
break;
case UNICHROME_CX700:
case UNICHROME_CN750:
@@ -1671,92 +1501,28 @@ u32 viafb_get_clk_value(int clk)
case UNICHROME_P4M890:
case UNICHROME_P4M900:
case UNICHROME_VX800:
- value = k800_encode_pll(get_pll_config(cx700_pll_config,
- ARRAY_SIZE(cx700_pll_config), clk));
+ config = get_pll_config(cx700_pll_limits,
+ ARRAY_SIZE(cx700_pll_limits), clk);
break;
case UNICHROME_VX855:
case UNICHROME_VX900:
- value = vx855_encode_pll(get_pll_config(vx855_pll_config,
- ARRAY_SIZE(vx855_pll_config), clk));
+ config = get_pll_config(vx855_pll_limits,
+ ARRAY_SIZE(vx855_pll_limits), clk);
break;
}
- return value;
+ return config;
}
/* Set VCLK*/
void viafb_set_vclock(u32 clk, int set_iga)
{
- /* H.W. Reset : ON */
- viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
+ struct via_pll_config config = get_best_pll_config(clk);
- if (set_iga == IGA1) {
- /* Change D,N FOR VCLK */
- switch (viaparinfo->chip_info->gfx_chip_name) {
- case UNICHROME_CLE266:
- case UNICHROME_K400:
- via_write_reg(VIASR, SR46, (clk & 0x00FF));
- via_write_reg(VIASR, SR47, (clk & 0xFF00) >> 8);
- break;
-
- case UNICHROME_K800:
- case UNICHROME_PM800:
- case UNICHROME_CN700:
- case UNICHROME_CX700:
- case UNICHROME_CN750:
- case UNICHROME_K8M890:
- case UNICHROME_P4M890:
- case UNICHROME_P4M900:
- case UNICHROME_VX800:
- case UNICHROME_VX855:
- case UNICHROME_VX900:
- via_write_reg(VIASR, SR44, (clk & 0x0000FF));
- via_write_reg(VIASR, SR45, (clk & 0x00FF00) >> 8);
- via_write_reg(VIASR, SR46, (clk & 0xFF0000) >> 16);
- break;
- }
- }
-
- if (set_iga == IGA2) {
- /* Change D,N FOR LCK */
- switch (viaparinfo->chip_info->gfx_chip_name) {
- case UNICHROME_CLE266:
- case UNICHROME_K400:
- via_write_reg(VIASR, SR44, (clk & 0x00FF));
- via_write_reg(VIASR, SR45, (clk & 0xFF00) >> 8);
- break;
-
- case UNICHROME_K800:
- case UNICHROME_PM800:
- case UNICHROME_CN700:
- case UNICHROME_CX700:
- case UNICHROME_CN750:
- case UNICHROME_K8M890:
- case UNICHROME_P4M890:
- case UNICHROME_P4M900:
- case UNICHROME_VX800:
- case UNICHROME_VX855:
- case UNICHROME_VX900:
- via_write_reg(VIASR, SR4A, (clk & 0x0000FF));
- via_write_reg(VIASR, SR4B, (clk & 0x00FF00) >> 8);
- via_write_reg(VIASR, SR4C, (clk & 0xFF0000) >> 16);
- break;
- }
- }
-
- /* H.W. Reset : OFF */
- viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
-
- /* Reset PLL */
- if (set_iga == IGA1) {
- viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
- viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
- }
-
- if (set_iga == IGA2) {
- viafb_write_reg_mask(SR40, VIASR, 0x04, BIT2);
- viafb_write_reg_mask(SR40, VIASR, 0x00, BIT2);
- }
+ if (set_iga == IGA1)
+ clock.set_primary_pll(config);
+ if (set_iga == IGA2)
+ clock.set_secondary_pll(config);
/* Fire! */
via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
@@ -2002,7 +1768,7 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
int i;
int index = 0;
int h_addr, v_addr;
- u32 pll_D_N, clock, refresh = viafb_refresh;
+ u32 clock, refresh = viafb_refresh;
if (viafb_SAMM_ON && set_iga == IGA2)
refresh = viafb_refresh1;
@@ -2033,8 +1799,6 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
v_addr = crt_reg.ver_addr;
if (set_iga == IGA1) {
viafb_unlock_crt();
- viafb_write_reg(CR09, VIACR, 0x00); /*initial CR09=0 */
- viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
}
@@ -2047,7 +1811,6 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
break;
}
- load_fix_bit_crtc_reg();
viafb_lock_crt();
viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
@@ -2059,20 +1822,17 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
clock = crt_reg.hor_total * crt_reg.ver_total
* crt_table[index].refresh_rate;
- pll_D_N = viafb_get_clk_value(clock);
- DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
- viafb_set_vclock(pll_D_N, set_iga);
+ viafb_set_vclock(clock, set_iga);
}
void __devinit viafb_init_chip_info(int chip_type)
{
+ via_clock_init(&clock, chip_type);
init_gfx_chip_info(chip_type);
init_tmds_chip_info();
init_lvds_chip_info();
- viaparinfo->crt_setting_info->iga_path = IGA1;
-
/*Set IGA path for each device */
viafb_set_iga_path();
@@ -2354,6 +2114,7 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
outb(0x00, VIAAR);
/* Write Common Setting for Video Mode */
+ viafb_write_regx(common_vga, ARRAY_SIZE(common_vga));
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_CLE266:
viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
@@ -2400,9 +2161,6 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
- /* Write CRTC */
- viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
-
/* Write Graphic Controller */
for (i = 0; i < StdGR; i++)
via_write_reg(VIAGR, i, VPIT.GR[i]);
@@ -2432,6 +2190,7 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
}
}
+ load_fix_bit_crtc_reg();
via_set_primary_pitch(viafbinfo->fix.line_length);
via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
: viafbinfo->fix.line_length);
@@ -2451,15 +2210,15 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
/* CRT set mode */
if (viafb_CRT_ON) {
- if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
- IGA2)) {
+ if (viafb_SAMM_ON &&
+ viaparinfo->shared->iga2_devices & VIA_CRT) {
viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
- video_bpp1 / 8,
- viaparinfo->crt_setting_info->iga_path);
+ video_bpp1 / 8, IGA2);
} else {
viafb_fill_crtc_timing(crt_timing, vmode_tbl,
video_bpp / 8,
- viaparinfo->crt_setting_info->iga_path);
+ (viaparinfo->shared->iga1_devices & VIA_CRT)
+ ? IGA1 : IGA2);
}
/* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
@@ -2557,6 +2316,33 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
get_sync(viafbinfo1));
}
+ clock.set_engine_pll_state(VIA_STATE_ON);
+ clock.set_primary_clock_source(VIA_CLKSRC_X1, true);
+ clock.set_secondary_clock_source(VIA_CLKSRC_X1, true);
+
+#ifdef CONFIG_FB_VIA_X_COMPATIBILITY
+ clock.set_primary_pll_state(VIA_STATE_ON);
+ clock.set_primary_clock_state(VIA_STATE_ON);
+ clock.set_secondary_pll_state(VIA_STATE_ON);
+ clock.set_secondary_clock_state(VIA_STATE_ON);
+#else
+ if (viaparinfo->shared->iga1_devices) {
+ clock.set_primary_pll_state(VIA_STATE_ON);
+ clock.set_primary_clock_state(VIA_STATE_ON);
+ } else {
+ clock.set_primary_pll_state(VIA_STATE_OFF);
+ clock.set_primary_clock_state(VIA_STATE_OFF);
+ }
+
+ if (viaparinfo->shared->iga2_devices) {
+ clock.set_secondary_pll_state(VIA_STATE_ON);
+ clock.set_secondary_clock_state(VIA_STATE_ON);
+ } else {
+ clock.set_secondary_pll_state(VIA_STATE_OFF);
+ clock.set_secondary_clock_state(VIA_STATE_OFF);
+ }
+#endif /*CONFIG_FB_VIA_X_COMPATIBILITY*/
+
via_set_state(devices, VIA_STATE_ON);
device_screen_on();
return 1;
@@ -2598,8 +2384,12 @@ int viafb_get_refresh(int hres, int vres, u32 long_refresh)
best = &vmode->crtc[i];
}
- if (abs(best->refresh_rate - long_refresh) > 3)
- return 60;
+ if (abs(best->refresh_rate - long_refresh) > 3) {
+ if (hres == 1200 && vres == 900)
+ return 49; /* OLPC DCON only supports 50 Hz */
+ else
+ return 60;
+ }
return best->refresh_rate;
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-13 15:25:59 +0000