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path: root/drivers/gpu/drm/radeon/radeon_mode.h
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Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_mode.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h49
1 files changed, 37 insertions, 12 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 0c28ca3964b1..92c5f473cf08 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -251,8 +251,23 @@ struct radeon_mode_info {
/* pointer to fbdev info structure */
struct radeon_fbdev *rfbdev;
+ /* firmware flags */
+ u16 firmware_flags;
+ /* pointer to backlight encoder */
+ struct radeon_encoder *bl_encoder;
};
+#define RADEON_MAX_BL_LEVEL 0xFF
+
+#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
+
+struct radeon_backlight_privdata {
+ struct radeon_encoder *encoder;
+ uint8_t negative;
+};
+
+#endif
+
#define MAX_H_CODE_TIMING_LEN 32
#define MAX_V_CODE_TIMING_LEN 32
@@ -268,6 +283,18 @@ struct radeon_tv_regs {
uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
};
+struct radeon_atom_ss {
+ uint16_t percentage;
+ uint8_t type;
+ uint16_t step;
+ uint8_t delay;
+ uint8_t range;
+ uint8_t refdiv;
+ /* asic_ss */
+ uint16_t rate;
+ uint16_t amount;
+};
+
struct radeon_crtc {
struct drm_crtc base;
int crtc_id;
@@ -292,6 +319,16 @@ struct radeon_crtc {
/* page flipping */
struct radeon_unpin_work *unpin_work;
int deferred_flip_completion;
+ /* pll sharing */
+ struct radeon_atom_ss ss;
+ bool ss_enabled;
+ u32 adjusted_clock;
+ int bpc;
+ u32 pll_reference_div;
+ u32 pll_post_div;
+ u32 pll_flags;
+ struct drm_encoder *encoder;
+ struct drm_connector *connector;
};
struct radeon_encoder_primary_dac {
@@ -345,18 +382,6 @@ struct radeon_encoder_ext_tmds {
};
/* spread spectrum */
-struct radeon_atom_ss {
- uint16_t percentage;
- uint8_t type;
- uint16_t step;
- uint8_t delay;
- uint8_t range;
- uint8_t refdiv;
- /* asic_ss */
- uint16_t rate;
- uint16_t amount;
-};
-
struct radeon_encoder_atom_dig {
bool linkb;
/* atom dig */