diff options
Diffstat (limited to 'arch/mips/mm')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 2 | ||||
| -rw-r--r-- | arch/mips/mm/dma-default.c | 2 | ||||
| -rw-r--r-- | arch/mips/mm/page.c | 3 | ||||
| -rw-r--r-- | arch/mips/mm/tlbex.c | 1 |
4 files changed, 5 insertions, 3 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index c43f4b26a690..871e828bc62a 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -780,7 +780,7 @@ static void __cpuinit probe_pcache(void) c->dcache.ways = 2; c->dcache.waybit = 0; - c->options |= MIPS_CPU_CACHE_CDEX_P; + c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; break; case CPU_TX49XX: diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 546e6977d4ff..bed56f1ac837 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -225,7 +225,7 @@ void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, if (!plat_device_is_coherent(dev) && direction != DMA_TO_DEVICE) { unsigned long addr; - addr = plat_dma_addr_to_phys(dma_address); + addr = dma_addr_to_virt(dma_address); dma_cache_wback_inv(addr, size); } diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c index 1417c6494858..48060c635acd 100644 --- a/arch/mips/mm/page.c +++ b/arch/mips/mm/page.c @@ -172,8 +172,9 @@ static void __cpuinit set_prefetch_parameters(void) */ cache_line_size = cpu_dcache_line_size(); switch (current_cpu_type()) { + case CPU_R5500: case CPU_TX49XX: - /* TX49 supports only Pref_Load */ + /* These processors only support the Pref_Load. */ pref_bias_copy_load = 256; break; diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 42942038d0fd..f335cf6cdd78 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -318,6 +318,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_BCM4710: case CPU_LOONGSON2: case CPU_CAVIUM_OCTEON: + case CPU_R5500: if (m4kc_tlbp_war()) uasm_i_nop(p); tlbw(p); |