diff options
| -rw-r--r-- | arch/arm/include/asm/cputype.h | 22 | ||||
| -rw-r--r-- | arch/arm/kernel/xscale-cp0.c | 7 | ||||
| -rw-r--r-- | arch/arm/mm/idmap.c | 2 | ||||
| -rw-r--r-- | arch/arm/mm/mmu.c | 2 |
4 files changed, 28 insertions, 5 deletions
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index 85e374f873ac..b23c6c81c9ad 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -228,10 +228,26 @@ static inline int cpu_is_xsc3(void) } #endif -#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) -#define cpu_is_xscale() 0 +#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) && \ + !defined(CONFIG_CPU_MOHAWK) +#define cpu_is_xscale_family() 0 #else -#define cpu_is_xscale() 1 +static inline int cpu_is_xscale_family(void) +{ + unsigned int id; + id = read_cpuid_id() & 0xffffe000; + + switch (id) { + case 0x69052000: /* Intel XScale 1 */ + case 0x69054000: /* Intel XScale 2 */ + case 0x69056000: /* Intel XScale 3 */ + case 0x56056000: /* Marvell XScale 3 */ + case 0x56158000: /* Marvell Mohawk */ + return 1; + } + + return 0; +} #endif /* diff --git a/arch/arm/kernel/xscale-cp0.c b/arch/arm/kernel/xscale-cp0.c index bdbb8853a19b..77a2eef72115 100644 --- a/arch/arm/kernel/xscale-cp0.c +++ b/arch/arm/kernel/xscale-cp0.c @@ -15,6 +15,9 @@ #include <linux/init.h> #include <linux/io.h> #include <asm/thread_notify.h> +#include <asm/cputype.h> + +asm(" .arch armv5te\n"); static inline void dsp_save_state(u32 *state) { @@ -152,6 +155,10 @@ static int __init xscale_cp0_init(void) { u32 cp_access; + /* do not attempt to probe iwmmxt on non-xscale family CPUs */ + if (!cpu_is_xscale_family()) + return 0; + cp_access = xscale_cp_access_read() & ~3; xscale_cp_access_write(cp_access | 1); diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c index e7a81cebbb2e..d65909697165 100644 --- a/arch/arm/mm/idmap.c +++ b/arch/arm/mm/idmap.c @@ -86,7 +86,7 @@ static void identity_mapping_add(pgd_t *pgd, const char *text_start, prot |= PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AF; - if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) + if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale_family()) prot |= PMD_BIT4; pgd += pgd_index(addr); diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 4867f5daf82c..e0e911ea32e6 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -477,7 +477,7 @@ static void __init build_mem_type_table(void) * "update-able on write" bit on ARM610). However, Xscale and * Xscale3 require this bit to be cleared. */ - if (cpu_is_xscale() || cpu_is_xsc3()) { + if (cpu_is_xscale_family()) { for (i = 0; i < ARRAY_SIZE(mem_types); i++) { mem_types[i].prot_sect &= ~PMD_BIT4; mem_types[i].prot_l1 &= ~PMD_BIT4; |