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| author | Marc Zyngier <maz@kernel.org> | 2019-05-22 18:16:49 +0100 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2019-08-18 18:38:47 +0100 |
| commit | b4931afcde1ffccd4a406009aef33c14bc6c6cb8 (patch) | |
| tree | 21553adc2468e1657cc41404b053dd7e288071d7 /virt | |
| parent | 0c14484866194382c0631d6e9bb14cc2fe83e814 (diff) | |
| download | linux-b4931afcde1ffccd4a406009aef33c14bc6c6cb8.tar.bz2 | |
KVM: arm/arm64: vgic-its: Invalidate MSI-LPI translation cache on disabling LPIs
If a vcpu disables LPIs at its redistributor level, we need to make sure
we won't pend more interrupts. For this, we need to invalidate the LPI
translation cache.
Tested-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'virt')
| -rw-r--r-- | virt/kvm/arm/vgic/vgic-mmio-v3.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/virt/kvm/arm/vgic/vgic-mmio-v3.c b/virt/kvm/arm/vgic/vgic-mmio-v3.c index c45e2d7e942f..fdcfb7ae4491 100644 --- a/virt/kvm/arm/vgic/vgic-mmio-v3.c +++ b/virt/kvm/arm/vgic/vgic-mmio-v3.c @@ -192,8 +192,10 @@ static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu, vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS; - if (was_enabled && !vgic_cpu->lpis_enabled) + if (was_enabled && !vgic_cpu->lpis_enabled) { vgic_flush_pending_lpis(vcpu); + vgic_its_invalidate_cache(vcpu->kvm); + } if (!was_enabled && vgic_cpu->lpis_enabled) vgic_enable_lpis(vcpu); |