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authorMichael Turquette <mturquette@baylibre.com>2017-04-12 18:49:36 +0200
committerMichael Turquette <mturquette@baylibre.com>2017-04-12 18:49:36 +0200
commit0d4ae360629fa4d199ac4e6ccfc97c8c367fd503 (patch)
treeb8bfc42aa9b29f47b9a376a5276248cc42d940fd /scripts/extract-sys-certs.pl
parentf37753e2a361f0583c9999c571f1051699c19552 (diff)
parentbb1953067c05be30a605ee1d5b05a2677735bb37 (diff)
downloadlinux-0d4ae360629fa4d199ac4e6ccfc97c8c367fd503.tar.bz2
Merge tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Pull Renesas clk driver updates from Geert Uytterhoeven: - Add support for the Clock Pulse Generator / Module Standby and Software Reset module on revision ES2.0 of the R-Car H3 SoC, which differs from ES1.x in some areas. - Add IMR clocks for R-Car H3 and M3-W, - Add workaround for PLL0/2/4 errata on R-Car H3 ES1.0, - Small fixes and cleanups. * tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0 clk: renesas: r8a7795: Add support for R-Car H3 ES2.0 clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions clk: renesas: cpg-mssr: Add support for fixing up clock tables clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0 clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init() clk: renesas: r8a7796: Reformat core clock table clk: renesas: r8a7795: Reformat core clock table clk: renesas: r8a7796: Correct name of watchdog clock clk: renesas: r8a7795: Correct name of watchdog clock clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACs clk: renesas: r8a7796: Add IMR clocks clk: renesas: r8a7795: Add IMR clocks
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