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| author | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 23:46:05 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 23:46:05 +0100 |
| commit | 641e97f318870921d048154af6807e46e43c307a (patch) | |
| tree | 6e0984a1bc8932db848be3fdb104a92c97fe341a /include/asm-mips/cpu-features.h | |
| parent | 424b28ba4d25fc41abdb7e6fa90e132f0d9558fb (diff) | |
| download | linux-641e97f318870921d048154af6807e46e43c307a.tar.bz2 | |
[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.
It may not be perfect yet but the SB1 code is badly borken and has
horrible performance issues.
Downside: This seriously breaks support for pass 1 parts of the BCM1250
where indexed cacheops don't work quite reliable but I seem to be the
last one on the planet with a pass 1 part anyway.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/cpu-features.h')
| -rw-r--r-- | include/asm-mips/cpu-features.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index d95a83e3e1d7..81f19aebc0db 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h @@ -35,9 +35,6 @@ #ifndef cpu_has_tx39_cache #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) #endif -#ifndef cpu_has_sb1_cache -#define cpu_has_sb1_cache (cpu_data[0].options & MIPS_CPU_SB1_CACHE) -#endif #ifndef cpu_has_fpu #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) #define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) |