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| author | Horia Geant? <horia.geanta@freescale.com> | 2015-08-21 18:53:20 +0300 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2015-08-24 22:07:38 +0800 |
| commit | 9f587fa29f7e8ed6b8885cff51a51ace3ad85152 (patch) | |
| tree | aa4db25708fc827a2159d9f7c4e8e8dd2ed691c3 /drivers/crypto | |
| parent | d4421c54c45f643731c92daa8e268ce74dcdf5a2 (diff) | |
| download | linux-9f587fa29f7e8ed6b8885cff51a51ace3ad85152.tar.bz2 | |
crypto: caam - fix writing to JQCR_MS when using service interface
Most significant part of JQCR (Job Queue Control Register) contains
bits that control endianness: ILE - Immediate Little Endian,
DWS - Double Word Swap.
The bits are automatically set by the Job Queue Controller HW.
Unfortunately these bits are cleared in SW when submitting descriptors
via the register-based service interface.
>From LS1021A:
JQCR_MS = 08080100 - before writing: ILE | DWS | SRC (JR0)
JQCR_MS = 30000100 - after writing: WHL | FOUR | SRC (JR0)
This would cause problems on little endian caam for descriptors
containing immediata data or double-word pointers.
Currently there is no problem since the only descriptors ran through
this interface are the ones that (un)instantiate RNG.
Signed-off-by: Horia Geant? <horia.geanta@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto')
| -rw-r--r-- | drivers/crypto/caam/ctrl.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c index 81b552d1ad91..09c16f5ea97d 100644 --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c @@ -139,7 +139,7 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc, flags |= DECO_JQCR_FOUR; /* Instruct the DECO to execute it */ - wr_reg32(&deco->jr_ctl_hi, flags); + setbits32(&deco->jr_ctl_hi, flags); timeout = 10000000; do { |