diff options
| author | Stephen Boyd <sboyd@codeaurora.org> | 2014-07-15 14:48:41 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2014-07-15 16:39:02 -0700 |
| commit | d8c25d3a1a1d61cf433654f3632a03ddaee4f781 (patch) | |
| tree | f3073e5d22c2762ee28fa0c1fe1c1be29fefa468 /drivers/clk/qcom/clk-pll.c | |
| parent | f87dfcabc6f173cc811d185d33327f50a8c88399 (diff) | |
| download | linux-d8c25d3a1a1d61cf433654f3632a03ddaee4f781.tar.bz2 | |
clk: qcom: pll: Add support for configuring SR PLLs
Some SR type PLLs need to be configured for a certain rate when
linux boots. Add support for these types of PLLs so that we can
program PLL15's rate on apq8064.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom/clk-pll.c')
| -rw-r--r-- | drivers/clk/qcom/clk-pll.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/drivers/clk/qcom/clk-pll.c b/drivers/clk/qcom/clk-pll.c index 0f927c538613..9db03d3b1657 100644 --- a/drivers/clk/qcom/clk-pll.c +++ b/drivers/clk/qcom/clk-pll.c @@ -166,7 +166,7 @@ const struct clk_ops clk_pll_vote_ops = { EXPORT_SYMBOL_GPL(clk_pll_vote_ops); static void -clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap) +clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap, u8 lock_count) { u32 val; u32 mask; @@ -175,7 +175,7 @@ clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap) regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_RESET, 0); /* Program bias count and lock count */ - val = 1 << PLL_BIAS_COUNT_SHIFT; + val = 1 << PLL_BIAS_COUNT_SHIFT | lock_count << PLL_LOCK_COUNT_SHIFT; mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT; mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT; regmap_update_bits(regmap, pll->mode_reg, mask, val); @@ -212,11 +212,20 @@ static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap, regmap_update_bits(regmap, pll->config_reg, mask, val); } +void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap, + const struct pll_config *config, bool fsm_mode) +{ + clk_pll_configure(pll, regmap, config); + if (fsm_mode) + clk_pll_set_fsm_mode(pll, regmap, 8); +} +EXPORT_SYMBOL_GPL(clk_pll_configure_sr); + void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap, const struct pll_config *config, bool fsm_mode) { clk_pll_configure(pll, regmap, config); if (fsm_mode) - clk_pll_set_fsm_mode(pll, regmap); + clk_pll_set_fsm_mode(pll, regmap, 0); } EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp); |