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| author | Padmavathi Venna <padma.v@samsung.com> | 2012-12-19 09:49:29 -0800 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2012-12-19 09:49:29 -0800 |
| commit | fb0a20594787f8a1f10389eec46a2cd51fa6a533 (patch) | |
| tree | 0aea1cecd985b78aab88fcbd6dacad9966bf221f /arch | |
| parent | 1fa49e46972d76b2e7d80410d95aff7ab59a3d23 (diff) | |
| download | linux-fb0a20594787f8a1f10389eec46a2cd51fa6a533.tar.bz2 | |
ARM: EXYNOS: Avoid passing the clks through platform data
I2S controller has an internal mux for RCLK source clks. The list
of source clk names were passed through platform data in non-dt case.
The variable holding the list of RCLK source clk names is not
required, as the list of clks need to be registered with clkdev
using generic connection id. This is required as part of adding DT
support for I2S controller driver.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Acked-by: Sangbeom Kim <sbkim73@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-exynos/dev-audio.c | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c index a1cb42c39590..9d1a60951d7b 100644 --- a/arch/arm/mach-exynos/dev-audio.c +++ b/arch/arm/mach-exynos/dev-audio.c @@ -23,11 +23,6 @@ #include <mach/irqs.h> #include <mach/regs-audss.h> -static const char *rclksrc[] = { - [0] = "busclk", - [1] = "i2sclk", -}; - static int exynos4_cfg_i2s(struct platform_device *pdev) { /* configure GPIO for i2s port */ @@ -55,7 +50,6 @@ static struct s3c_audio_pdata i2sv5_pdata = { .i2s = { .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR, - .src_clk = rclksrc, .idma_addr = EXYNOS4_AUDSS_INT_MEM, }, }, @@ -78,17 +72,11 @@ struct platform_device exynos4_device_i2s0 = { }, }; -static const char *rclksrc_v3[] = { - [0] = "sclk_i2s", - [1] = "no_such_clock", -}; - static struct s3c_audio_pdata i2sv3_pdata = { .cfg_gpio = exynos4_cfg_i2s, .type = { .i2s = { .quirks = QUIRK_NO_MUXPSR, - .src_clk = rclksrc_v3, }, }, }; |