diff options
| author | Jongpill Lee <boyko.lee@samsung.com> | 2010-08-27 16:50:47 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2010-08-27 18:29:24 +0900 |
| commit | 5a847b4af8057f0297356824f793988d311d7aa0 (patch) | |
| tree | 2c6ec3ec319e1dccd7b724284c785592372bd59d /arch | |
| parent | 3ff310206db33e66c076b1f656e70e9080f5be50 (diff) | |
| download | linux-5a847b4af8057f0297356824f793988d311d7aa0.tar.bz2 | |
ARM: S5PV310: Fix missed uart clocks
This patch adds missed uart clocks for S5PV310/S5PC210.
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-s5pv310/clock.c | 44 |
1 files changed, 37 insertions, 7 deletions
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index b3f50426148d..165c8bf412b2 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c @@ -30,6 +30,11 @@ static struct clk clk_sclk_hdmi27m = { .rate = 27000000, }; +static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable); +} + /* Core list of CMU_CPU side */ static struct clksrc_clk clk_mout_apll = { @@ -329,11 +334,6 @@ static struct clksrc_clk clk_sclk_vpll = { .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, }; -static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable); -} - static struct clk init_clocks_disable[] = { { .name = "timers", @@ -345,7 +345,37 @@ static struct clk init_clocks_disable[] = { }; static struct clk init_clocks[] = { - /* Nothing here yet */ + { + .name = "uart", + .id = 0, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "uart", + .id = 1, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "uart", + .id = 2, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "uart", + .id = 3, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "uart", + .id = 4, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "uart", + .id = 5, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 5), + } }; static struct clk *clkset_group_list[] = { @@ -367,8 +397,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "uclk1", .id = 0, - .ctrlbit = (1 << 0), .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 0), }, .sources = &clkset_group, .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 }, |