diff options
| author | Markos Chandras <markos.chandras@imgtec.com> | 2014-07-21 14:35:56 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-08-19 18:24:41 +0200 |
| commit | 6521d9a436a62e83ce57d6be6e5484e1098c1380 (patch) | |
| tree | a5330080f04abd92d755dcb2a33d637498e340e6 /arch/mips | |
| parent | ca4d24f7954f3746742ba350c2276ff777f21173 (diff) | |
| download | linux-6521d9a436a62e83ce57d6be6e5484e1098c1380.tar.bz2 | |
MIPS: CPS: Initialize EVA before bringing up VPEs from secondary cores
The CPS code is doing several memory loads when configuring the VPEs
from secondary cores, so the segmentation control registers must be
initialized in time otherwise the kernel will crash with strange
TLB exceptions.
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: http://patchwork.linux-mips.org/patch/7424/
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/kernel/cps-vec.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index 6f4f739dad96..e6e97d2a5c9e 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -13,6 +13,7 @@ #include <asm/asm-offsets.h> #include <asm/asmmacro.h> #include <asm/cacheops.h> +#include <asm/eva.h> #include <asm/mipsregs.h> #include <asm/mipsmtregs.h> #include <asm/pm.h> @@ -166,6 +167,9 @@ dcache_done: 1: jal mips_cps_core_init nop + /* Do any EVA initialization if necessary */ + eva_init + /* * Boot any other VPEs within this core that should be online, and * deactivate this VPE if it should be offline. |