diff options
| author | Steven J. Hill <steven.hill@cavium.com> | 2018-07-03 16:44:21 -0500 |
|---|---|---|
| committer | Paul Burton <paul.burton@mips.com> | 2018-07-03 16:00:43 -0700 |
| commit | 769f4372b2887b7c758f67f4fae82bd5b8555b59 (patch) | |
| tree | c93e3c6eaff7253016be805137f661cdd2694936 /arch/mips/pci | |
| parent | 67701aea341e9e667eae816510523982137b12e6 (diff) | |
| download | linux-769f4372b2887b7c758f67f4fae82bd5b8555b59.tar.bz2 | |
MIPS: Octeon: Unify QLM data types in CIU header.
Data types 'cvmx_ciu_qlm0' and 'cvmx_ciu_qlm1' are identical in
their usage and structure. Combine them and update the PCIe code.
Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/19708/
Cc: linux-mips@linux-mips.org
Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
Diffstat (limited to 'arch/mips/pci')
| -rw-r--r-- | arch/mips/pci/pcie-octeon.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c index 9cc5905860ef..d919a0d813a1 100644 --- a/arch/mips/pci/pcie-octeon.c +++ b/arch/mips/pci/pcie-octeon.c @@ -1237,14 +1237,14 @@ static int __cvmx_pcie_rc_initialize_gen2(int pcie_port) /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */ if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0)) { if (pcie_port) { - union cvmx_ciu_qlm1 ciu_qlm; + union cvmx_ciu_qlm ciu_qlm; ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM1); ciu_qlm.s.txbypass = 1; ciu_qlm.s.txdeemph = 5; ciu_qlm.s.txmargin = 0x17; cvmx_write_csr(CVMX_CIU_QLM1, ciu_qlm.u64); } else { - union cvmx_ciu_qlm0 ciu_qlm; + union cvmx_ciu_qlm ciu_qlm; ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM0); ciu_qlm.s.txbypass = 1; ciu_qlm.s.txdeemph = 5; |