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authorPaul Burton <paul.burton@imgtec.com>2015-05-24 16:11:33 +0100
committerRalf Baechle <ralf@linux-mips.org>2015-06-21 21:53:12 +0200
commite06b86a33ad9a225d6336f2489cdd79aeaa9d59b (patch)
treead484b9facecd02ee2a9e800d978c41c67b64179 /arch/mips/jz4740
parent1f4b840983ffbd7053b5c2219deaf62b4b8a3c12 (diff)
downloadlinux-e06b86a33ad9a225d6336f2489cdd79aeaa9d59b.tar.bz2
MIPS: JZ4740: replace use of jz4740_clock_bdata
Replace uses of the jz4740_clock_bdata struct with calls to clk_get_rate for the appropriate clock. This is in preparation for migrating the clocks towards common clock framework & devicetree. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: Apelete Seketeli <apelete@seketeli.net> Patchwork: https://patchwork.linux-mips.org/patch/10149/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/jz4740')
-rw-r--r--arch/mips/jz4740/platform.c11
-rw-r--r--arch/mips/jz4740/reset.c13
-rw-r--r--arch/mips/jz4740/time.c9
3 files changed, 29 insertions, 4 deletions
diff --git a/arch/mips/jz4740/platform.c b/arch/mips/jz4740/platform.c
index 0b12f273cb2e..2a5c7c7d0735 100644
--- a/arch/mips/jz4740/platform.c
+++ b/arch/mips/jz4740/platform.c
@@ -13,6 +13,7 @@
*
*/
+#include <linux/clk.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
@@ -308,9 +309,17 @@ static struct platform_device jz4740_uart_device = {
void jz4740_serial_device_register(void)
{
struct plat_serial8250_port *p;
+ struct clk *ext_clk;
+ unsigned long ext_rate;
+
+ ext_clk = clk_get(NULL, "ext");
+ if (IS_ERR(ext_clk))
+ panic("unable to get ext clock");
+ ext_rate = clk_get_rate(ext_clk);
+ clk_put(ext_clk);
for (p = jz4740_uart_data; p->flags != 0; ++p)
- p->uartclk = jz4740_clock_bdata.ext_rate;
+ p->uartclk = ext_rate;
platform_device_register(&jz4740_uart_device);
}
diff --git a/arch/mips/jz4740/reset.c b/arch/mips/jz4740/reset.c
index b6c6343d2834..954e669c9e6b 100644
--- a/arch/mips/jz4740/reset.c
+++ b/arch/mips/jz4740/reset.c
@@ -12,6 +12,7 @@
*
*/
+#include <linux/clk.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/pm.h>
@@ -79,12 +80,20 @@ static void jz4740_power_off(void)
void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x38);
unsigned long wakeup_filter_ticks;
unsigned long reset_counter_ticks;
+ struct clk *rtc_clk;
+ unsigned long rtc_rate;
+
+ rtc_clk = clk_get(NULL, "rtc");
+ if (IS_ERR(rtc_clk))
+ panic("unable to get RTC clock");
+ rtc_rate = clk_get_rate(rtc_clk);
+ clk_put(rtc_clk);
/*
* Set minimum wakeup pin assertion time: 100 ms.
* Range is 0 to 2 sec if RTC is clocked at 32 kHz.
*/
- wakeup_filter_ticks = (100 * jz4740_clock_bdata.rtc_rate) / 1000;
+ wakeup_filter_ticks = (100 * rtc_rate) / 1000;
if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
else
@@ -96,7 +105,7 @@ static void jz4740_power_off(void)
* Set reset pin low-level assertion time after wakeup: 60 ms.
* Range is 0 to 125 ms if RTC is clocked at 32 kHz.
*/
- reset_counter_ticks = (60 * jz4740_clock_bdata.rtc_rate) / 1000;
+ reset_counter_ticks = (60 * rtc_rate) / 1000;
if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK)
reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK;
else
diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c
index 78ed7652ef67..f66f7f5bbe87 100644
--- a/arch/mips/jz4740/time.c
+++ b/arch/mips/jz4740/time.c
@@ -13,6 +13,7 @@
*
*/
+#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/time.h>
@@ -115,11 +116,17 @@ void __init plat_time_init(void)
int ret;
uint32_t clk_rate;
uint16_t ctrl;
+ struct clk *ext_clk;
jz4740_clock_init();
jz4740_timer_init();
- clk_rate = jz4740_clock_bdata.ext_rate >> 4;
+ ext_clk = clk_get(NULL, "ext");
+ if (IS_ERR(ext_clk))
+ panic("unable to get ext clock");
+ clk_rate = clk_get_rate(ext_clk) >> 4;
+ clk_put(ext_clk);
+
jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);
clockevent_set_clock(&jz4740_clockevent, clk_rate);