diff options
| author | David Daney <ddaney@caviumnetworks.com> | 2009-05-13 15:59:55 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-06-17 11:06:31 +0100 |
| commit | fbeda19f82aa07082d2e1607a9f5114141dae2ac (patch) | |
| tree | c631cfe8884cd72a4fd709baf72e857edbbac477 /arch/mips/include | |
| parent | 9cffd154cf6817b130762501b91e753524ba2cd4 (diff) | |
| download | linux-fbeda19f82aa07082d2e1607a9f5114141dae2ac.tar.bz2 | |
MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.
Some CPUs have implementation dependent rdhwr registers. Allow them
to be enabled on a per CPU basis.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/asm/cpu-features.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 1cba4b2ffd1e..8ab1d12ba7f4 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -234,4 +234,8 @@ #define cpu_scache_line_size() cpu_data[0].scache.linesz #endif +#ifndef cpu_hwrena_impl_bits +#define cpu_hwrena_impl_bits 0 +#endif + #endif /* __ASM_CPU_FEATURES_H */ |