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| author | Kefeng Wang <wangkefeng.wang@huawei.com> | 2020-05-07 23:04:45 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-05-12 16:21:46 -0700 |
| commit | 48084c3595cb7429f6ba734cfea1313573b9a7fa (patch) | |
| tree | 305785d6b4ee85ea3d3c640e306a9cee466dc9bf /arch/hexagon | |
| parent | e7b146a8bfba50e263745bbdefc11833c3766664 (diff) | |
| download | linux-48084c3595cb7429f6ba734cfea1313573b9a7fa.tar.bz2 | |
riscv: perf: RISCV_BASE_PMU should be independent
Selecting PERF_EVENTS without selecting RISCV_BASE_PMU results in a build
error.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
[Palmer: commit text]
Fixes: 178e9fc47aae("perf: riscv: preliminary RISC-V support")
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'arch/hexagon')
0 files changed, 0 insertions, 0 deletions