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| author | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2018-01-18 02:52:56 +0100 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2018-01-18 02:52:56 +0100 |
| commit | f31c376025b5b295908d4b8ec74811be7d7e15f8 (patch) | |
| tree | 766845cd39d7adfc192ce0b16d75d8a8e4f8be02 /arch/arm | |
| parent | bee344cb70e9bf5ad929e0a493c0f7aa3a587bfb (diff) | |
| parent | f06970f4b03dffeb9831a8ad605db3c85a55aca1 (diff) | |
| download | linux-f31c376025b5b295908d4b8ec74811be7d7e15f8.tar.bz2 | |
Merge branch 'pm-cpufreq'
* pm-cpufreq: (36 commits)
cpufreq: scpi: remove arm_big_little dependency
drivers: psci: remove cluster terminology and dependency on physical_package_id
cpufreq: powernv: Dont assume distinct pstate values for nominal and pmin
cpufreq: intel_pstate: Add Skylake servers support
cpufreq: intel_pstate: Replace bxt_funcs with core_funcs
cpufreq: imx6q: add 696MHz operating point for i.mx6ul
ARM: dts: imx6ul: add 696MHz operating point
cpufreq: stats: Change return type of cpufreq_stats_update() as void
powernv-cpufreq: Treat pstates as opaque 8-bit values
powernv-cpufreq: Fix pstate_to_idx() to handle non-continguous pstates
powernv-cpufreq: Add helper to extract pstate from PMSR
cpu_cooling: Remove static-power related documentation
cpufreq: imx6q: switch to Use clk_bulk_get() to refine clk operations
PM / OPP: Make local function ti_opp_supply_set_opp() static
PM / OPP: Add ti-opp-supply driver
dt-bindings: opp: Introduce ti-opp-supply bindings
cpufreq: ti-cpufreq: Add support for multiple regulators
cpufreq: ti-cpufreq: Convert to module_platform_driver
cpufreq: Add DVFS support for Armada 37xx
MAINTAINERS: add new entries for Armada 37xx cpufreq driver
...
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/imx6ul.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index d5181f85ca9c..963e1698fe1d 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -68,12 +68,14 @@ clock-latency = <61036>; /* two CLK32 periods */ operating-points = < /* kHz uV */ + 696000 1275000 528000 1175000 396000 1025000 198000 950000 >; fsl,soc-operating-points = < /* KHz uV */ + 696000 1275000 528000 1175000 396000 1175000 198000 1175000 |