arm64: dts: rockchip: Define values for the IPA governor for rock960

Currently the default thermal values for the rk3399-rock960 board is
inherited from the generic definition in rk3399.dtsi.

In order to ensure the rock960 has more room for througput before
being capped by the thermal framework and is correctly supported by
the IPA governor, let's define the power values and the right trip
points for better performances:

 - sustainable power is tested to be 1550mW

 - increase the first mitigation point to 75°C in order to get better
   performances

 - the first trip point is 65°C in order to let the IPA to collect
   enough data for the PID regulation when it reaches 75°C

 - restrict the cooling device to the big CPUs as the little CPUs
   contribution to the heating effect can be considered negligible

The intelligent power allocator PID coefficient to be set in sysfs
are:

    k_d: 0
    k_po: 79
    k_i: 10
    k_pu: 50

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

1 files changed, 39 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
index c624b4e73129..437a75f31ad4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
@@ -124,6 +124,45 @@
 	status = "okay";
 };
 
+&thermal_zones {
+	cpu_thermal: cpu {
+		polling-delay-passive = <100>;
+		polling-delay = <1000>;
+		thermal-sensors = <&tsadc 0>;
+		sustainable-power = <1550>;
+
+		trips {
+			cpu_alert0: cpu_alert0 {
+				    temperature = <65000>;
+				    hysteresis = <2000>;
+				    type = "passive";
+			};
+
+			cpu_alert1: cpu_alert1 {
+				    temperature = <75000>;
+				    hysteresis = <2000>;
+				    type = "passive";
+			};
+
+			cpu_crit: cpu_crit {
+				  temperature = <95000>;
+				  hysteresis = <2000>;
+				  type = "critical";
+			};
+		};
+
+		cooling-maps {
+			     map0 {
+
+			     trip = <&cpu_alert1>;
+			     cooling-device =
+					<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+};
+
 &usbdrd_dwc3_0 {
 	dr_mode = "otg";
 };