summaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-exynos/platsmp.c
diff options
context:
space:
mode:
authorBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>2015-03-18 14:09:57 +0100
committerKukjin Kim <kgene@kernel.org>2015-06-06 02:17:57 +0900
commitaf9971144dde808338919cb4f3849ea2ac60739f (patch)
tree99b42bff1f28ecdf201a547bbd0a2dc996a95583 /arch/arm/mach-exynos/platsmp.c
parent1225ad72866b440574a22372b9edceb035632f2b (diff)
downloadlinux-af9971144dde808338919cb4f3849ea2ac60739f.tar.bz2
ARM: EXYNOS: add coupled cpuidle support for Exynos3250
The following patch adds coupled cpuidle support for Exynos3250 to an existing cpuidle-exynos driver. As a result it enables AFTR mode to be used by default on Exynos3250 without the need to hot unplug CPU1 first. The detailed changelog: - use exynos_[get,set]_boot_addr() in cpuidle-exynos.c and then make cpu_boot_reg_base() static - use exynos_core_restart() in exynos_cpu0_enter_aftr() - add missing smp_rmb() to exynos_cpu0_enter_aftr() (to make the code in-sync with the platform SMP code) - add call_firmware_op(cpu_boot, 1) to exynos_cpu0_enter_aftr() - use dsb_sev() instead of IPI wakeup for Exynos3250 in exynos_cpu0_enter_aftr() - add CPU0 vs CPU1 synchronization based on S5P_PMU_SPARE2 register for Exynos3250 to cpuidle-exynos.c - add flush_cache_all() for CPU1/0 before powerdown/AFTR for Exynos3250 to exynos_wfi_finisher()/exynos_do_idle() Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
Diffstat (limited to 'arch/arm/mach-exynos/platsmp.c')
-rw-r--r--arch/arm/mach-exynos/platsmp.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 449edd1121e4..58e05a2eae57 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -169,7 +169,7 @@ int exynos_cluster_power_state(int cluster)
S5P_CORE_LOCAL_PWR_EN);
}
-void __iomem *cpu_boot_reg_base(void)
+static void __iomem *cpu_boot_reg_base(void)
{
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
return pmu_base_addr + S5P_INFORM5;
@@ -195,7 +195,7 @@ static inline void __iomem *cpu_boot_reg(int cpu)
*
* Currently this is needed only when booting secondary CPU on Exynos3250.
*/
-static void exynos_core_restart(u32 core_id)
+void exynos_core_restart(u32 core_id)
{
u32 val;
@@ -247,7 +247,7 @@ static void exynos_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
-static int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr)
+int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr)
{
int ret;
@@ -272,7 +272,7 @@ fail:
return ret;
}
-static int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr)
+int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr)
{
int ret;