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| author | Linus Walleij <linus.walleij@linaro.org> | 2019-09-15 15:54:44 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2019-09-16 16:31:17 +0200 |
| commit | 2a7326caab479ca257c4b9bd67db42d1d49079bf (patch) | |
| tree | e3823a754a32b0132c51b65eaee37da3579e5513 /arch/arm/boot | |
| parent | 375a7baddbdd62c61a41b6c25437b425d7aeeea6 (diff) | |
| download | linux-2a7326caab479ca257c4b9bd67db42d1d49079bf.tar.bz2 | |
ARM: dts: dir685: Drop spi-cpol from the display
The D-Link DIR-685 had its clock polarity set as active
low using the special SPI "spi-cpol" property.
This is not correct: the datasheet clearly states:
"Fix SCL to GND level when not in use" which is
indicative that this line is active high.
After a recent fix making the GPIO-based SPI driver
force the clock line de-asserted at the beginning of
each SPI transaction this reared its ugly head: now
de-asserted was taken to mean the line should be
driven high, but it should be driven low.
Fix this up in the DTS file and the display works again.
Link: https://lore.kernel.org/r/20190915135444.11066-1-linus.walleij@linaro.org
Cc: Mark Brown <broonie@kernel.org>
Fixes: 2922d1cc1696 ("spi: gpio: Add SPI_MASTER_GPIO_SS flag")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/gemini-dlink-dir-685.dts | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts index bfaa2de63a10..e2030ba16512 100644 --- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts +++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts @@ -72,7 +72,6 @@ reg = <0>; /* 50 ns min period = 20 MHz */ spi-max-frequency = <20000000>; - spi-cpol; /* Clock active low */ vcc-supply = <&vdisp>; iovcc-supply = <&vdisp>; vci-supply = <&vdisp>; |