diff options
| author | Linus Walleij <linus.walleij@linaro.org> | 2017-10-20 14:57:37 +0200 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2017-10-25 11:25:38 +0200 |
| commit | 5c7b0c4e7d5cd9850a93b8a1ea092baf4c8b3cd0 (patch) | |
| tree | 877809c15b39bb8c2b33f94e8219f2d6b656a1f3 | |
| parent | fe29416b5ca2f80b43622ac3023ed9cd0c1ce777 (diff) | |
| download | linux-5c7b0c4e7d5cd9850a93b8a1ea092baf4c8b3cd0.tar.bz2 | |
gpio: grgpio: Do not use gc->pin2mask()
The pin2mask() accessor only shuffles BIT ORDER in big endian systems,
i.e. the bitstuffing is swizzled big endian so "bit 0" is bit 7 or
bit 15 or bit 31 or so.
The grgpio only uses big endian BYTE ORDER which will be taken car of
by the ->write_reg() callback.
Just use BIT(offset) to assign the bit.
Acked-by: Andreas Larsson <andreas@gaisler.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| -rw-r--r-- | drivers/gpio/gpio-grgpio.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpio/gpio-grgpio.c b/drivers/gpio/gpio-grgpio.c index 6544a16ab02e..e2fc561f4315 100644 --- a/drivers/gpio/gpio-grgpio.c +++ b/drivers/gpio/gpio-grgpio.c @@ -35,6 +35,7 @@ #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/irqdomain.h> +#include <linux/bitops.h> #define GRGPIO_MAX_NGPIO 32 @@ -96,12 +97,11 @@ static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset, int val) { struct gpio_chip *gc = &priv->gc; - unsigned long mask = gc->pin2mask(gc, offset); if (val) - priv->imask |= mask; + priv->imask |= BIT(offset); else - priv->imask &= ~mask; + priv->imask &= ~BIT(offset); gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask); } |