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authorJon Hunter <jonathanh@nvidia.com>2016-02-26 15:48:40 +0000
committerThierry Reding <treding@nvidia.com>2016-04-05 15:22:53 +0200
commit0a2d87e0473fc5eea3f8168f5a24a35e4cf3f29c (patch)
treee6bacbecb33dd2123fca41a991b17459edda6269
parentbc9af23d314f5c846e66e9425b31df2815ef1763 (diff)
downloadlinux-0a2d87e0473fc5eea3f8168f5a24a35e4cf3f29c.tar.bz2
soc/tegra: pmc: Wait for powergate state to change
Currently, the function tegra_powergate_set() simply sets the desired powergate state but does not wait for the state to change. In most cases we should wait for the state to change before proceeding. Currently, there is a case for Tegra114 and Tegra124 devices where we do not wait when starting the secondary CPU as this is not necessary. However, this is only done at boot time and so waiting here will only have a small impact on boot time. Therefore, update tegra_powergate_set() to wait when setting the powergate. By adding this feature, we can also eliminate the polling loop from tegra30_boot_secondary(). A function has been added for checking the status of the powergate and so update the tegra_powergate_is_powered() to use this macro as well. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/platsmp.c16
-rw-r--r--drivers/soc/tegra/pmc.c9
2 files changed, 11 insertions, 14 deletions
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index f3f61dbbda97..75620ae73913 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -108,19 +108,9 @@ static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle)
* be un-gated by un-toggling the power gate register
* manually.
*/
- if (!tegra_pmc_cpu_is_powered(cpu)) {
- ret = tegra_pmc_cpu_power_on(cpu);
- if (ret)
- return ret;
-
- /* Wait for the power to come up. */
- timeout = jiffies + msecs_to_jiffies(100);
- while (!tegra_pmc_cpu_is_powered(cpu)) {
- if (time_after(jiffies, timeout))
- return -ETIMEDOUT;
- udelay(10);
- }
- }
+ ret = tegra_pmc_cpu_power_on(cpu);
+ if (ret)
+ return ret;
remove_clamps:
/* CPU partition is powered. Enable the CPU clock. */
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index e4fd40fa27e8..08966c26d65c 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -28,6 +28,7 @@
#include <linux/export.h>
#include <linux/init.h>
#include <linux/io.h>
+#include <linux/iopoll.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
@@ -194,6 +195,9 @@ static inline bool tegra_powergate_is_valid(int id)
*/
static int tegra_powergate_set(unsigned int id, bool new_state)
{
+ bool status;
+ int err;
+
if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
return -EINVAL;
@@ -206,9 +210,12 @@ static int tegra_powergate_set(unsigned int id, bool new_state)
tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
+ err = readx_poll_timeout(tegra_powergate_state, id, status,
+ status == new_state, 10, 100000);
+
mutex_unlock(&pmc->powergates_lock);
- return 0;
+ return err;
}
/**