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| author | Kevin Cernekee <cernekee@gmail.com> | 2014-10-20 21:27:52 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-11-24 07:45:10 +0100 |
| commit | bdb2e05c900d0c2a14605411dc054f284241d42e (patch) | |
| tree | de867f32032648094369d30993955cf5c760e9ef /.gitignore | |
| parent | 3526f74fa925e44335b94ed0c9f93648e26058ef (diff) | |
| download | linux-bdb2e05c900d0c2a14605411dc054f284241d42e.tar.bz2 | |
MIPS: BMIPS: Align secondary boot sequence with latest firmware releases
On some older BMIPS5200 (dual core / quad thread) platforms, the
PROM code set up CPU2/CPU3 so they would be started through an NMI
instead of through the ACTION register. But this was incompatible with
some power management features that were later added, so the scheme was
changed so that Linux is fully responsible for booting CPU2/CPU3.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8157/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to '.gitignore')
0 files changed, 0 insertions, 0 deletions