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<title>linux/include/asm-powerpc/reg_booke.h, branch v5.3</title>
<subtitle>Linux Kernel (branches are rebased on master from time to time)</subtitle>
<id>https://sre.ring0.de/linux/atom?h=v5.3</id>
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<updated>2008-08-04T02:02:00Z</updated>
<entry>
<title>powerpc: Move include files to arch/powerpc/include/asm</title>
<updated>2008-08-04T02:02:00Z</updated>
<author>
<name>Stephen Rothwell</name>
<email>sfr@canb.auug.org.au</email>
</author>
<published>2008-08-01T05:20:30Z</published>
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<id>urn:sha1:b8b572e1015f81b4e748417be2629dfe51ab99f9</id>
<content type='text'>
from include/asm-powerpc.  This is the result of a

mkdir arch/powerpc/include/asm
git mv include/asm-powerpc/* arch/powerpc/include/asm

Followed by a few documentation/comment fixups and a couple of places
where &lt;asm-powepc/...&gt; was being used explicitly.  Of the latter only
one was outside the arch code and it is a driver only built for powerpc.

Signed-off-by: Stephen Rothwell &lt;sfr@canb.auug.org.au&gt;
Signed-off-by: Paul Mackerras &lt;paulus@samba.org&gt;
</content>
</entry>
<entry>
<title>powerpc/e500mc: flush L2 on NAP for e500mc</title>
<updated>2008-06-26T06:49:03Z</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2008-06-19T14:40:31Z</published>
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<id>urn:sha1:aba11fc50c925bbd6fb25d54eae2f86277a3b107</id>
<content type='text'>
If we have an L2CSR register (e500mc) we need to flush the L2 before going
to nap.  We use the HW flush mechanism provided in that register.

The code reuses the CPU_FTR_604_PERF_MON bit as it is no longer used by
any code in the kernel.  Additionally we didn't reuse the exist L2CR
feature bit as this is intended for the 7xxx L2CR register and L2CSR
is part of the new Freescale "Book-E" registers.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>powerpc/85xx: add DOZE/NAP support for e500 core</title>
<updated>2008-06-26T06:48:56Z</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2008-06-18T21:26:52Z</published>
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<id>urn:sha1:fc4033b2f8b1482022bff3d05505a1b1631bb6de</id>
<content type='text'>
The e500 core enter DOZE/NAP power-saving modes when the core go to
cpu_idle routine.

The power management default running mode is DOZE, If the user

echo 1 &gt; /proc/sys/kernel/powersave-nap

the system will change to NAP running mode.

Signed-off-by: Dave Liu &lt;daveliu@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>powerpc/booke: Fix definitions for dbcr[1-2] and dbsr registers</title>
<updated>2008-06-16T14:56:18Z</updated>
<author>
<name>Jerone Young</name>
<email>jyoung5@us.ibm.com</email>
</author>
<published>2008-06-06T19:09:05Z</published>
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<id>urn:sha1:bccaea8fe287454d70f5b2546910561e9f884053</id>
<content type='text'>
This takes values from the PowerPC ISA BookIII-E specifications that are
for DBCR0. Many of these values are different from those currently
specified, which are for the ppc405. Also added some bookE definitions
for DBCR1 &amp; DBCR2.

[ galak@kernel.crashing.org: Added aliases to 40x DBCR0 to match Book-E,
  Added enhanced debug DBCR0/DBSR _CIRPT and _CRET defines and DBSR
  IRPT and RET. ]

Signed-off-by: Jerone Young &lt;jyoung5@us.ibm.com&gt;
Acked-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>[POWERPC] Made FSL Book-E PMC support more generic</title>
<updated>2008-02-06T05:34:14Z</updated>
<author>
<name>Andy Fleming</name>
<email>afleming@freescale.com</email>
</author>
<published>2008-02-05T00:27:55Z</published>
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<id>urn:sha1:39aef685af431c032ffd2763ec8782b13c32520c</id>
<content type='text'>
Some of the more recent e300 cores have the same performance monitor
implementation as the e500.  e300 isn't book-e, so the name isn't
really appropriate.  In preparation for e300 support, rename a bunch
of fsl_booke things to say fsl_emb (Freescale Embedded Performance Monitors).

Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>[POWERPC] Reworking machine check handling and Fix 440/440A</title>
<updated>2007-12-23T19:11:59Z</updated>
<author>
<name>Benjamin Herrenschmidt</name>
<email>benh@kernel.crashing.org</email>
</author>
<published>2007-12-21T04:39:21Z</published>
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<id>urn:sha1:47c0bd1ae24c34e851cf0f2b02ef2a6847d7ae15</id>
<content type='text'>
This adds a cputable function pointer for the CPU-side machine
check handling. The semantic is still the same as the old one,
the one in ppc_md. overrides the one in cputable, though
ultimately we'll want to change that so the CPU gets first.

This removes CONFIG_440A which was a problem for multiplatform
kernels and instead fixes up the IVOR at runtime from a setup_cpu
function. The "A" version of the machine check also tweaks the
regs-&gt;trap value to differenciate the 2 versions at the C level.

Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</content>
</entry>
<entry>
<title>[POWERPC] include/asm-powerpc/: Spelling fixes</title>
<updated>2007-12-20T05:17:44Z</updated>
<author>
<name>joe@perches.com</name>
<email>joe@perches.com</email>
</author>
<published>2007-12-17T19:30:13Z</published>
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<id>urn:sha1:567e9fdd49bcfa7e15ebc0005853ac5529c81856</id>
<content type='text'>
Signed-off-by: Joe Perches &lt;joe@perches.com&gt;
Signed-off-by: Paul Mackerras &lt;paulus@samba.org&gt;
</content>
</entry>
<entry>
<title>[POWERPC] Add SPRN for Embedded registers specified in PowerISA 2.04</title>
<updated>2007-12-11T19:57:16Z</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2007-11-16T19:57:57Z</published>
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<id>urn:sha1:fd351b89205bc14f79af2e0d69f4198bcea1cf6a</id>
<content type='text'>
* Added SPRN for new architectural features added for embedded:
	- Alternate Time Base (ATB, ATBL, ATBU)
	- Doorbell Interrupts (IVOR36, IVOR37)
	- SPRG8/9
	- External Proxy (EPR)
	- External PID load/store (EPLC, EPSC)

* Added BUCSR for Freescale Embedded Processors
* Moved around MAS7 so its in numeric order

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>[POWERPC] Fix FSL BookE machine check reporting</title>
<updated>2007-08-17T18:22:28Z</updated>
<author>
<name>Becky Bruce</name>
<email>becky.bruce@freescale.com</email>
</author>
<published>2007-08-02T20:37:15Z</published>
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<id>urn:sha1:86d7a9a9c4775f864e6bc5f5da66ef9ea3715734</id>
<content type='text'>
Reserved MCSR bits on FSL BookE parts may have spurious values
when mcheck occurs.  Mask these off when printing the MCSR to
avoid confusion.  Also, get rid of the MCSR_GL_CI bit defined
for e500 - this bit doesn't actually have any meaning.

Signed-off-by: Becky Bruce &lt;becky.bruce@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>[POWERPC] Move reg_booke.h to include/asm-powerpc</title>
<updated>2007-05-10T04:00:37Z</updated>
<author>
<name>Becky Bruce</name>
<email>becky.bruce@freescale.com</email>
</author>
<published>2007-05-09T19:31:19Z</published>
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<id>urn:sha1:828765269efaafbf8973bb6e41d10970ee4effc3</id>
<content type='text'>
This patch moves a copy of reg_booke.h to include/asm-powerpc and fixes
up the ifdef protection.

Signed-off-by: Becky Bruce &lt;becky.bruce@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
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