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<title>linux/drivers/pci/dwc/pci-exynos.c, branch v4.15</title>
<subtitle>Linux Kernel (branches are rebased on master from time to time)</subtitle>
<id>https://sre.ring0.de/linux/atom?h=v4.15</id>
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<updated>2017-09-07T18:23:56Z</updated>
<entry>
<title>Merge branch 'pci/host-exynos' into next</title>
<updated>2017-09-07T18:23:56Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2017-09-07T18:23:56Z</published>
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<id>urn:sha1:0dd9636f97daa346b514402782a782c979b0a454</id>
<content type='text'>
* pci/host-exynos:
  PCI: exynos: Fix platform_get_irq() error handling
</content>
</entry>
<entry>
<title>PCI: exynos: Fix platform_get_irq() error handling</title>
<updated>2017-09-05T18:28:24Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@nxp.com</email>
</author>
<published>2017-08-31T17:52:01Z</published>
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<id>urn:sha1:1df5a487c8b338105930310eb9a876d9ad1646cb</id>
<content type='text'>
platform_get_irq() returns a negative number on failure, so adjust the
logic to detect such condition and propagate the real error value on
failure.

Reported-by: Bjorn Helgaas &lt;helgaas@kernel.org&gt;
Signed-off-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Acked-by: Jingoo Han &lt;jingoohan1@gmail.com&gt;</content>
</entry>
<entry>
<title>PCI: dwc: designware: Handle -&gt;host_init() failures</title>
<updated>2017-08-03T21:14:32Z</updated>
<author>
<name>Bjorn Andersson</name>
<email>bjorn.andersson@linaro.org</email>
</author>
<published>2017-07-16T06:39:45Z</published>
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<id>urn:sha1:4a301766f5263dd94c1b95d1b1bbdf338afb1a37</id>
<content type='text'>
In several dwc-based drivers, -&gt;host_init() can fail, so make sure to
propagate and handle this to avoid continuing operation of a driver or
hardware in an invalid state.

Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Acked-by: Joao Pinto &lt;jpinto@synopsys.com&gt;
Acked-by: Jingoo Han &lt;jingoohan1@gmail.com&gt;</content>
</entry>
<entry>
<title>PCI: dwc: Constify dw_pcie_host_ops structures</title>
<updated>2017-07-02T23:38:50Z</updated>
<author>
<name>Jisheng Zhang</name>
<email>jszhang@marvell.com</email>
</author>
<published>2017-06-05T08:53:46Z</published>
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<id>urn:sha1:4ab2e7c0df6b8bbc6c8ea1617b737d33c2510012</id>
<content type='text'>
The dw_pcie_host_ops structures are never modified.  Constify these
structures such that these can be write-protected.

Signed-off-by: Jisheng Zhang &lt;jszhang@marvell.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Acked-by: Jingoo Han &lt;jingoohan1@gmail.com&gt;
Acked-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;</content>
</entry>
<entry>
<title>PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes</title>
<updated>2017-04-04T13:40:55Z</updated>
<author>
<name>Kishon Vijay Abraham I</name>
<email>kishon@ti.com</email>
</author>
<published>2017-03-13T13:43:26Z</published>
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<id>urn:sha1:a509d7d9af5ebf86ffbefa98e49761d813fb1d40</id>
<content type='text'>
Previously dbi accessors can be used to access data of size 4 bytes. But
there might be situations (like accessing MSI_MESSAGE_CONTROL in order to
set/get the number of required MSI interrupts in EP mode) where dbi
accessors must be used to access data of size 2. This is in preparation
for adding endpoint mode support to designware driver.

Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Acked-by: Niklas Cassel &lt;niklas.cassel@axis.com&gt;
Cc: Jingoo Han &lt;jingoohan1@gmail.com&gt;
Cc: Joao Pinto &lt;Joao.Pinto@synopsys.com&gt;</content>
</entry>
<entry>
<title>PCI: dwc: all: Modify dbi accessors to take dbi_base as argument</title>
<updated>2017-04-04T13:40:12Z</updated>
<author>
<name>Kishon Vijay Abraham I</name>
<email>kishon@ti.com</email>
</author>
<published>2017-03-13T13:43:25Z</published>
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<id>urn:sha1:b50b2db266d8a8c303e8d88590c6416dfe576c6c</id>
<content type='text'>
dwc has 2 dbi address space labeled dbics and dbics2. The existing helper
to access dbi address space can access only dbics. However dbics2 has to
be accessed for programming the BAR registers in the case of EP mode. This
is in preparation for adding EP mode support to dwc driver.

Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Acked-by: Niklas Cassel &lt;niklas.cassel@axis.com&gt;
Cc: Jingoo Han &lt;jingoohan1@gmail.com&gt;
Cc: Joao Pinto &lt;Joao.Pinto@synopsys.com&gt;</content>
</entry>
<entry>
<title>PCI: exynos: Initialize elbi_base even when using PHY framework</title>
<updated>2017-03-07T18:46:38Z</updated>
<author>
<name>Jaehoon Chung</name>
<email>jh80.chung@samsung.com</email>
</author>
<published>2017-03-07T10:54:05Z</published>
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<id>urn:sha1:544714d8e17c33822319d5a1a00e5ddc4db502b6</id>
<content type='text'>
Even when using the PHY framework, we need the elbi_base.  Before this
patch, we didn't initialize elbi_base, which caused NULL pointer
dereferences later.

Fixes: e7cd7ef58e1f ("PCI: exynos: Support the PHY generic framework")
Signed-off-by: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</content>
</entry>
<entry>
<title>PCI: dwc: Fix crashes seen due to missing assignments</title>
<updated>2017-02-25T15:06:02Z</updated>
<author>
<name>Guenter Roeck</name>
<email>linux@roeck-us.net</email>
</author>
<published>2017-02-25T10:08:12Z</published>
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<id>urn:sha1:c0464062bfea9cd2ef6643d93429eafe8f6c2a4a</id>
<content type='text'>
Fix the following crash, seen in dwc/pci-imx6.

  Unable to handle kernel NULL pointer dereference at virtual address 00000070
  pgd = c0004000
  [00000070] *pgd=00000000
  Internal error: Oops: 805 [#1] SMP ARM
  Modules linked in:
  CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.10.0-09686-g9e31489 #1
  Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
  task: cb850000 task.stack: cb84e000
  PC is at imx6_pcie_probe+0x2f4/0x414
  ...

While at it, fix the same problem in various drivers instead of waiting for
individual crash reports.

The change in the imx6 driver was tested with qemu. The changes in other
drivers are based on code inspection and have been compile tested only.

Fixes: 442ec4c04d12 ("PCI: dwc: all: Split struct pcie_port into host-only and core structures")
Signed-off-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
Signed-off-by: Vivek Gautam &lt;vivek.gautam@codeaurora.org&gt;  # designware-plat
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Acked-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;</content>
</entry>
<entry>
<title>Merge branch 'pci/host-exynos' into next</title>
<updated>2017-02-21T21:13:30Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2017-02-21T21:13:30Z</published>
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<id>urn:sha1:b2e6d3055d5545b97533d4e8376fa848639d9951</id>
<content type='text'>
* pci/host-exynos:
  PCI: exynos: Support the PHY generic framework
  Documentation: binding: Modify the exynos5440 PCIe binding
  phy: phy-exynos-pcie: Add support for Exynos PCIe PHY
  Documentation: samsung-phy: Add exynos-pcie-phy binding
  PCI: exynos: Refactor to make it easier to support other SoCs
  PCI: exynos: Remove duplicated code
  PCI: exynos: Use the bitops BIT() macro to build bitmasks
  PCI: exynos: Remove unnecessary local variables
  PCI: exynos: Replace the *_blk/*_phy/*_elb accessors
  PCI: exynos: Rename all pointer names from "exynos_pcie" to "ep"

Conflicts:
	drivers/pci/dwc/pci-exynos.c
</content>
</entry>
<entry>
<title>PCI: dwc: all: Split struct pcie_port into host-only and core structures</title>
<updated>2017-02-21T21:00:26Z</updated>
<author>
<name>Kishon Vijay Abraham I</name>
<email>kishon@ti.com</email>
</author>
<published>2017-02-15T13:18:14Z</published>
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<id>urn:sha1:442ec4c04d1235f8c664a74004dae54a7a574d18</id>
<content type='text'>
Keep only the host-specific members in struct pcie_port and move the common
members (i.e common to both host and endpoint) to struct dw_pcie.  This is
in preparation for adding endpoint mode support to designware driver.

While at that also fix checkpatch warnings.

Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
CC: Jingoo Han &lt;jingoohan1@gmail.com&gt;
CC: Richard Zhu &lt;hongxing.zhu@nxp.com&gt;
CC: Lucas Stach &lt;l.stach@pengutronix.de&gt;
CC: Murali Karicheri &lt;m-karicheri2@ti.com&gt;
CC: Minghuan Lian &lt;minghuan.Lian@freescale.com&gt;
CC: Mingkai Hu &lt;mingkai.hu@freescale.com&gt;
CC: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
CC: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
CC: Niklas Cassel &lt;niklas.cassel@axis.com&gt;
CC: Jesper Nilsson &lt;jesper.nilsson@axis.com&gt;
CC: Joao Pinto &lt;Joao.Pinto@synopsys.com&gt;
CC: Zhou Wang &lt;wangzhou1@hisilicon.com&gt;
CC: Gabriele Paoloni &lt;gabriele.paoloni@huawei.com&gt;
CC: Stanimir Varbanov &lt;svarbanov@mm-sol.com&gt;
CC: Pratyush Anand &lt;pratyush.anand@gmail.com&gt;</content>
</entry>
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