<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/display/dc/inc/hw, branch master</title>
<subtitle>Linux Kernel (branches are rebased on master from time to time)</subtitle>
<id>https://sre.ring0.de/linux/atom?h=master</id>
<link rel='self' href='https://sre.ring0.de/linux/atom?h=master'/>
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<updated>2022-12-09T21:50:30Z</updated>
<entry>
<title>drm/amd/display: Fix spelling mistake: "dram_clk_chanage" -&gt; "dram_clk_change"</title>
<updated>2022-12-09T21:50:30Z</updated>
<author>
<name>Colin Ian King</name>
<email>colin.i.king@gmail.com</email>
</author>
<published>2022-12-08T12:18:54Z</published>
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<id>urn:sha1:2165359b7ed4e0b93fc23f49ede38d76e91fffe1</id>
<content type='text'>
There is a spelling mistake in the struct field dram_clk_chanage. Fix it.

Signed-off-by: Colin Ian King &lt;colin.i.king@gmail.com&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add YCBCR2020 coefficients to CSC matrix</title>
<updated>2022-11-23T14:47:14Z</updated>
<author>
<name>Rodrigo Siqueira</name>
<email>Rodrigo.Siqueira@amd.com</email>
</author>
<published>2022-11-03T13:38:14Z</published>
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<id>urn:sha1:7ce24a3606855f656f30c174e3078a1c642f1e41</id>
<content type='text'>
When some of the IGT tests are executed in DCN31, it is possible to see
multiple occurrences of this warning:

 WARNING: CPU: 9 PID: 3482 at
 drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dcn30/dcn30_dpp.c:154
 dpp3_program_post_csc+0x196/0x220 [amdgpu]
 [..]
 PU: 9 PID: 3482 Comm: amd_hdr Tainted: G       W        5.18.0+ #3
 IP: 0010:dpp3_program_post_csc+0x196/0x220 [amdgpu]
 [..]
 all Trace:
 &lt;TASK&gt;
 dpp3_cnv_setup+0x5d9/0x5f0 [amdgpu]
 ? dcn20_blank_pixel_data+0x30a/0x330 [amdgpu]
 dcn20_program_pipe+0x259/0xb40 [amdgpu]
 ? offset_to_id+0x1b0/0x1c0 [amdgpu]
 dcn20_program_front_end_for_ctx+0x36a/0x450 [amdgpu]
 commit_planes_for_stream+0x8eb/0x13e0 [amdgpu]

This commit fix the above issue by adding YCBCR2020 coefficients to the
DPP Color Space Converter (CSC) matrix.

Reviewed-by: Nawwar Ali &lt;nawwar.ali@amd.com&gt;
Acked-by: Brian Chang &lt;Brian.Chang@amd.com&gt;
Signed-off-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix the build when DRM_AMD_DC_DCN is not set</title>
<updated>2022-11-17T05:17:43Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2022-11-16T16:54:27Z</published>
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<id>urn:sha1:5ca9b33ece9aa048b6ec9411f054e1b781662327</id>
<content type='text'>
Move the new callback outside of the guard.

Fixes: dc55b106ad47 ("drm/amd/display: Disable phantom OTG after enable for plane disable")
CC: Alvin Lee &lt;Alvin.Lee2@amd.com&gt;
CC: Alan Liu &lt;HaoPing.Liu@amd.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: enable dchub request limit for DCN 3.2.x</title>
<updated>2022-11-15T18:34:42Z</updated>
<author>
<name>Jun Lei</name>
<email>jun.lei@amd.com</email>
</author>
<published>2022-11-02T19:19:37Z</published>
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<id>urn:sha1:d97fd7a07b34d3671ae09d64f102adabdbd80ffe</id>
<content type='text'>
[why]
HW recommend we enable this for better DF QoS for DCN 3.2.x

[how]
Add interfaces to hubbub to program register
Add initialization as part of init_hw
Add default settings for DCN 3.2.x
Add registry override for debug/tuning

Reviewed-by: Alvin Lee &lt;Alvin.Lee2@amd.com&gt;
Acked-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Signed-off-by: Jun Lei &lt;jun.lei@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Disable phantom OTG after enable for plane disable</title>
<updated>2022-11-09T22:25:45Z</updated>
<author>
<name>Alvin Lee</name>
<email>Alvin.Lee2@amd.com</email>
</author>
<published>2022-10-27T14:51:15Z</published>
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<id>urn:sha1:dc55b106ad477c67f969f3432d9070c6846fb557</id>
<content type='text'>
[Description]
- Need to disable phantom OTG after it's enabled
  in order to restore it to it's original state.
- If it's enabled and then an MCLK switch comes in
  we may not prefetch the correct data since the phantom
  OTG could already be in the middle of the frame.

Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Alan Liu &lt;HaoPing.Liu@amd.com&gt;
Signed-off-by: Alvin Lee &lt;Alvin.Lee2@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add basic ODM description</title>
<updated>2022-10-27T18:45:45Z</updated>
<author>
<name>Rodrigo Siqueira</name>
<email>Rodrigo.Siqueira@amd.com</email>
</author>
<published>2022-10-20T15:46:59Z</published>
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<id>urn:sha1:a6126e14cfb200ecb915c66bccbfc077c704c1fa</id>
<content type='text'>
Add kernel-doc to some of the ODM-related functions.

Tested-by: Mark Broadworth &lt;mark.broadworth@amd.com&gt;
Reviewed-by: Aurabindo Pillai &lt;Aurabindo.Pillai@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add DEC/CRB basic doc</title>
<updated>2022-10-27T18:45:39Z</updated>
<author>
<name>Rodrigo Siqueira</name>
<email>Rodrigo.Siqueira@amd.com</email>
</author>
<published>2022-10-20T15:46:58Z</published>
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<id>urn:sha1:61708a47e84bc458fae9fbc8a9070fb62a9bcf6d</id>
<content type='text'>
Add a kernel-doc to the DE-Tile function hook.

Tested-by: Mark Broadworth &lt;mark.broadworth@amd.com&gt;
Reviewed-by: Aurabindo Pillai &lt;Aurabindo.Pillai@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Expand kernel doc for DC</title>
<updated>2022-10-27T18:45:29Z</updated>
<author>
<name>Rodrigo Siqueira</name>
<email>Rodrigo.Siqueira@amd.com</email>
</author>
<published>2022-10-20T15:46:57Z</published>
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<id>urn:sha1:1682bd1a6b5fb094e914d9b73b711821fd84dcbd</id>
<content type='text'>
This commit adds extra documentation for elements related to FAMs.

Tested-by: Mark Broadworth &lt;mark.broadworth@amd.com&gt;
Reviewed-by: Aurabindo Pillai &lt;Aurabindo.Pillai@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Drop struct crc_region and reuse struct rect</title>
<updated>2022-10-27T18:42:40Z</updated>
<author>
<name>Alan Liu</name>
<email>HaoPing.Liu@amd.com</email>
</author>
<published>2022-10-20T15:46:43Z</published>
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<id>urn:sha1:62fa035b5605a993fa3b4526af8b6ed145e3ce1b</id>
<content type='text'>
[Why]
reuse struct rect rather than adding a new struct.

[How]
- Userspace keeps inputting x_start, y_start, x_end, y_end
- We translate data to x, y, width, height in code flow to store
- translate back to x_start, y_start, x_end, y_end before programming HW

Tested-by: Mark Broadworth &lt;mark.broadworth@amd.com&gt;
Reviewed-by: Wayne Lin &lt;Wayne.Lin@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alan Liu &lt;HaoPing.Liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Implement secure display on DCN21</title>
<updated>2022-10-27T18:42:32Z</updated>
<author>
<name>Alan Liu</name>
<email>HaoPing.Liu@amd.com</email>
</author>
<published>2022-10-20T15:46:42Z</published>
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<id>urn:sha1:c0459bddd1955df35c9331757671e64e3ea0a77a</id>
<content type='text'>
[Why]
Porting secure display feature from DCN10 to DCN21. Support single
display for now and will extend to multiple displays.

[How]
- use workqueue to offload works for dmub or dmcu firmware
- after receiving ROI update from userspace, set skip_frame_cnt to 1
- refactor amdgpu_dm_crtc_handle_crc_window_irq()
- disable PSR before activating secure_display on a crtc
- check if secure_display is activated before enabling psr
- only work for single display for now.

Tested-by: Mark Broadworth &lt;mark.broadworth@amd.com&gt;
Reviewed-by: Wayne Lin &lt;Wayne.Lin@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alan Liu &lt;HaoPing.Liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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